1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2011 - 2014 Xilinx 4 */ 5 6/ { 7 #address-cells = <1>; 8 #size-cells = <1>; 9 compatible = "xlnx,zynq-7000"; 10 11 options { 12 u-boot { 13 compatible = "u-boot,config"; 14 bootscr-address = /bits/ 64 <0x3000000>; 15 }; 16 }; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a9"; 24 device_type = "cpu"; 25 reg = <0>; 26 clocks = <&clkc 3>; 27 clock-latency = <1000>; 28 cpu0-supply = <®ulator_vccpint>; 29 operating-points = < 30 /* kHz uV */ 31 666667 1000000 32 333334 1000000 33 >; 34 }; 35 36 cpu1: cpu@1 { 37 compatible = "arm,cortex-a9"; 38 device_type = "cpu"; 39 reg = <1>; 40 clocks = <&clkc 3>; 41 }; 42 }; 43 44 fpga_full: fpga-region { 45 compatible = "fpga-region"; 46 fpga-mgr = <&devcfg>; 47 #address-cells = <1>; 48 #size-cells = <1>; 49 ranges; 50 }; 51 52 pmu@f8891000 { 53 compatible = "arm,cortex-a9-pmu"; 54 interrupts = <0 5 4>, <0 6 4>; 55 interrupt-parent = <&intc>; 56 reg = <0xf8891000 0x1000>, 57 <0xf8893000 0x1000>; 58 }; 59 60 regulator_vccpint: fixedregulator { 61 compatible = "regulator-fixed"; 62 regulator-name = "VCCPINT"; 63 regulator-min-microvolt = <1000000>; 64 regulator-max-microvolt = <1000000>; 65 regulator-boot-on; 66 regulator-always-on; 67 }; 68 69 replicator { 70 compatible = "arm,coresight-static-replicator"; 71 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 72 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 73 74 out-ports { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 /* replicator output ports */ 79 port@0 { 80 reg = <0>; 81 replicator_out_port0: endpoint { 82 remote-endpoint = <&tpiu_in_port>; 83 }; 84 }; 85 port@1 { 86 reg = <1>; 87 replicator_out_port1: endpoint { 88 remote-endpoint = <&etb_in_port>; 89 }; 90 }; 91 }; 92 in-ports { 93 /* replicator input port */ 94 port { 95 replicator_in_port0: endpoint { 96 remote-endpoint = <&funnel_out_port>; 97 }; 98 }; 99 }; 100 }; 101 102 amba: axi { 103 bootph-all; 104 compatible = "simple-bus"; 105 #address-cells = <1>; 106 #size-cells = <1>; 107 interrupt-parent = <&intc>; 108 ranges; 109 110 adc: adc@f8007100 { 111 compatible = "xlnx,zynq-xadc-1.00.a"; 112 reg = <0xf8007100 0x20>; 113 interrupts = <0 7 4>; 114 interrupt-parent = <&intc>; 115 clocks = <&clkc 12>; 116 }; 117 118 can0: can@e0008000 { 119 compatible = "xlnx,zynq-can-1.0"; 120 status = "disabled"; 121 clocks = <&clkc 19>, <&clkc 36>; 122 clock-names = "can_clk", "pclk"; 123 reg = <0xe0008000 0x1000>; 124 interrupts = <0 28 4>; 125 interrupt-parent = <&intc>; 126 tx-fifo-depth = <0x40>; 127 rx-fifo-depth = <0x40>; 128 }; 129 130 can1: can@e0009000 { 131 compatible = "xlnx,zynq-can-1.0"; 132 status = "disabled"; 133 clocks = <&clkc 20>, <&clkc 37>; 134 clock-names = "can_clk", "pclk"; 135 reg = <0xe0009000 0x1000>; 136 interrupts = <0 51 4>; 137 interrupt-parent = <&intc>; 138 tx-fifo-depth = <0x40>; 139 rx-fifo-depth = <0x40>; 140 }; 141 142 gpio0: gpio@e000a000 { 143 compatible = "xlnx,zynq-gpio-1.0"; 144 #gpio-cells = <2>; 145 clocks = <&clkc 42>; 146 gpio-controller; 147 interrupt-controller; 148 #interrupt-cells = <2>; 149 interrupt-parent = <&intc>; 150 interrupts = <0 20 4>; 151 reg = <0xe000a000 0x1000>; 152 }; 153 154 i2c0: i2c@e0004000 { 155 compatible = "cdns,i2c-r1p10"; 156 status = "disabled"; 157 clocks = <&clkc 38>; 158 interrupt-parent = <&intc>; 159 interrupts = <0 25 4>; 160 clock-frequency = <400000>; 161 reg = <0xe0004000 0x1000>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 }; 165 166 i2c1: i2c@e0005000 { 167 compatible = "cdns,i2c-r1p10"; 168 status = "disabled"; 169 clocks = <&clkc 39>; 170 interrupt-parent = <&intc>; 171 interrupts = <0 48 4>; 172 clock-frequency = <400000>; 173 reg = <0xe0005000 0x1000>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 }; 177 178 intc: interrupt-controller@f8f01000 { 179 compatible = "arm,cortex-a9-gic"; 180 #interrupt-cells = <3>; 181 interrupt-controller; 182 reg = <0xF8F01000 0x1000>, 183 <0xF8F00100 0x100>; 184 }; 185 186 L2: cache-controller@f8f02000 { 187 compatible = "arm,pl310-cache"; 188 reg = <0xF8F02000 0x1000>; 189 interrupts = <0 2 4>; 190 arm,data-latency = <3 2 2>; 191 arm,tag-latency = <2 2 2>; 192 cache-unified; 193 cache-level = <2>; 194 }; 195 196 mc: memory-controller@f8006000 { 197 compatible = "xlnx,zynq-ddrc-a05"; 198 reg = <0xf8006000 0x1000>; 199 }; 200 201 ocm: sram@fffc0000 { 202 compatible = "mmio-sram"; 203 reg = <0xfffc0000 0x10000>; 204 #address-cells = <1>; 205 #size-cells = <1>; 206 ranges = <0 0xfffc0000 0x10000>; 207 ocm-sram@0 { 208 reg = <0x0 0x10000>; 209 }; 210 }; 211 212 uart0: serial@e0000000 { 213 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 214 status = "disabled"; 215 clocks = <&clkc 23>, <&clkc 40>; 216 clock-names = "uart_clk", "pclk"; 217 reg = <0xE0000000 0x1000>; 218 interrupts = <0 27 4>; 219 }; 220 221 uart1: serial@e0001000 { 222 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 223 status = "disabled"; 224 clocks = <&clkc 24>, <&clkc 41>; 225 clock-names = "uart_clk", "pclk"; 226 reg = <0xE0001000 0x1000>; 227 interrupts = <0 50 4>; 228 }; 229 230 spi0: spi@e0006000 { 231 compatible = "xlnx,zynq-spi-r1p6"; 232 reg = <0xe0006000 0x1000>; 233 status = "disabled"; 234 interrupt-parent = <&intc>; 235 interrupts = <0 26 4>; 236 clocks = <&clkc 25>, <&clkc 34>; 237 clock-names = "ref_clk", "pclk"; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 }; 241 242 spi1: spi@e0007000 { 243 compatible = "xlnx,zynq-spi-r1p6"; 244 reg = <0xe0007000 0x1000>; 245 status = "disabled"; 246 interrupt-parent = <&intc>; 247 interrupts = <0 49 4>; 248 clocks = <&clkc 26>, <&clkc 35>; 249 clock-names = "ref_clk", "pclk"; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 }; 253 254 qspi: spi@e000d000 { 255 compatible = "xlnx,zynq-qspi-1.0"; 256 reg = <0xe000d000 0x1000>; 257 interrupt-parent = <&intc>; 258 interrupts = <0 19 4>; 259 clocks = <&clkc 10>, <&clkc 43>; 260 clock-names = "ref_clk", "pclk"; 261 status = "disabled"; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 }; 265 266 gem0: ethernet@e000b000 { 267 compatible = "xlnx,zynq-gem", "cdns,gem"; 268 reg = <0xe000b000 0x1000>; 269 status = "disabled"; 270 interrupts = <0 22 4>; 271 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 272 clock-names = "pclk", "hclk", "tx_clk"; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 }; 276 277 gem1: ethernet@e000c000 { 278 compatible = "xlnx,zynq-gem", "cdns,gem"; 279 reg = <0xe000c000 0x1000>; 280 status = "disabled"; 281 interrupts = <0 45 4>; 282 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 283 clock-names = "pclk", "hclk", "tx_clk"; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 }; 287 288 smcc: memory-controller@e000e000 { 289 compatible = "arm,pl353-smc-r2p1", "arm,primecell"; 290 reg = <0xe000e000 0x0001000>; 291 status = "disabled"; 292 clock-names = "memclk", "apb_pclk"; 293 clocks = <&clkc 11>, <&clkc 44>; 294 ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ 295 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ 296 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ 297 #address-cells = <2>; 298 #size-cells = <1>; 299 interrupt-parent = <&intc>; 300 interrupts = <0 18 4>; 301 302 nfc0: nand-controller@0,0 { 303 compatible = "arm,pl353-nand-r2p1"; 304 reg = <0 0 0x1000000>; 305 status = "disabled"; 306 }; 307 nor0: flash@1,0 { 308 status = "disabled"; 309 compatible = "cfi-flash"; 310 reg = <1 0 0x2000000>; 311 }; 312 }; 313 314 sdhci0: mmc@e0100000 { 315 compatible = "arasan,sdhci-8.9a"; 316 status = "disabled"; 317 clock-names = "clk_xin", "clk_ahb"; 318 clocks = <&clkc 21>, <&clkc 32>; 319 interrupt-parent = <&intc>; 320 interrupts = <0 24 4>; 321 reg = <0xe0100000 0x1000>; 322 }; 323 324 sdhci1: mmc@e0101000 { 325 compatible = "arasan,sdhci-8.9a"; 326 status = "disabled"; 327 clock-names = "clk_xin", "clk_ahb"; 328 clocks = <&clkc 22>, <&clkc 33>; 329 interrupt-parent = <&intc>; 330 interrupts = <0 47 4>; 331 reg = <0xe0101000 0x1000>; 332 }; 333 334 slcr: slcr@f8000000 { 335 bootph-all; 336 #address-cells = <1>; 337 #size-cells = <1>; 338 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 339 reg = <0xF8000000 0x1000>; 340 ranges; 341 clkc: clkc@100 { 342 bootph-all; 343 #clock-cells = <1>; 344 compatible = "xlnx,ps7-clkc"; 345 fclk-enable = <0>; 346 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 347 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 348 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 349 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 350 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 351 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 352 "gem1_aper", "sdio0_aper", "sdio1_aper", 353 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 354 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 355 "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 356 "dbg_trc", "dbg_apb"; 357 reg = <0x100 0x100>; 358 }; 359 360 rstc: rstc@200 { 361 compatible = "xlnx,zynq-reset"; 362 reg = <0x200 0x48>; 363 #reset-cells = <1>; 364 syscon = <&slcr>; 365 }; 366 367 pinctrl0: pinctrl@700 { 368 compatible = "xlnx,pinctrl-zynq"; 369 reg = <0x700 0x200>; 370 syscon = <&slcr>; 371 }; 372 }; 373 374 dmac_s: dma-controller@f8003000 { 375 compatible = "arm,pl330", "arm,primecell"; 376 reg = <0xf8003000 0x1000>; 377 interrupt-parent = <&intc>; 378 /* 379 * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 380 * "dma4", "dma5", "dma6", "dma7"; 381 */ 382 interrupts = <0 13 4>, 383 <0 14 4>, <0 15 4>, 384 <0 16 4>, <0 17 4>, 385 <0 40 4>, <0 41 4>, 386 <0 42 4>, <0 43 4>; 387 #dma-cells = <1>; 388 clocks = <&clkc 27>; 389 clock-names = "apb_pclk"; 390 }; 391 392 devcfg: devcfg@f8007000 { 393 compatible = "xlnx,zynq-devcfg-1.0"; 394 reg = <0xf8007000 0x100>; 395 interrupt-parent = <&intc>; 396 interrupts = <0 8 4>; 397 clocks = <&clkc 12>; 398 clock-names = "ref_clk"; 399 syscon = <&slcr>; 400 }; 401 402 global_timer: timer@f8f00200 { 403 compatible = "arm,cortex-a9-global-timer"; 404 reg = <0xf8f00200 0x20>; 405 interrupts = <1 11 0x301>; 406 interrupt-parent = <&intc>; 407 clocks = <&clkc 4>; 408 }; 409 410 ttc0: timer@f8001000 { 411 interrupt-parent = <&intc>; 412 interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 413 compatible = "cdns,ttc"; 414 clocks = <&clkc 6>; 415 reg = <0xF8001000 0x1000>; 416 }; 417 418 ttc1: timer@f8002000 { 419 interrupt-parent = <&intc>; 420 interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 421 compatible = "cdns,ttc"; 422 clocks = <&clkc 6>; 423 reg = <0xF8002000 0x1000>; 424 }; 425 426 scutimer: timer@f8f00600 { 427 bootph-all; 428 interrupt-parent = <&intc>; 429 interrupts = <1 13 0x301>; 430 compatible = "arm,cortex-a9-twd-timer"; 431 reg = <0xf8f00600 0x20>; 432 clocks = <&clkc 4>; 433 }; 434 435 usb0: usb@e0002000 { 436 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 437 status = "disabled"; 438 clocks = <&clkc 28>; 439 interrupt-parent = <&intc>; 440 interrupts = <0 21 4>; 441 reg = <0xe0002000 0x1000>; 442 phy_type = "ulpi"; 443 }; 444 445 usb1: usb@e0003000 { 446 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 447 status = "disabled"; 448 clocks = <&clkc 29>; 449 interrupt-parent = <&intc>; 450 interrupts = <0 44 4>; 451 reg = <0xe0003000 0x1000>; 452 phy_type = "ulpi"; 453 }; 454 455 watchdog0: watchdog@f8005000 { 456 clocks = <&clkc 45>; 457 compatible = "cdns,wdt-r1p2"; 458 interrupt-parent = <&intc>; 459 interrupts = <0 9 1>; 460 reg = <0xf8005000 0x1000>; 461 timeout-sec = <10>; 462 }; 463 464 etb@f8801000 { 465 compatible = "arm,coresight-etb10", "arm,primecell"; 466 reg = <0xf8801000 0x1000>; 467 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 468 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 469 in-ports { 470 port { 471 etb_in_port: endpoint { 472 remote-endpoint = <&replicator_out_port1>; 473 }; 474 }; 475 }; 476 }; 477 478 tpiu@f8803000 { 479 compatible = "arm,coresight-tpiu", "arm,primecell"; 480 reg = <0xf8803000 0x1000>; 481 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 482 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 483 in-ports { 484 port { 485 tpiu_in_port: endpoint { 486 remote-endpoint = <&replicator_out_port0>; 487 }; 488 }; 489 }; 490 }; 491 492 funnel@f8804000 { 493 compatible = "arm,coresight-static-funnel", "arm,primecell"; 494 reg = <0xf8804000 0x1000>; 495 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 496 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 497 498 /* funnel output ports */ 499 out-ports { 500 port { 501 funnel_out_port: endpoint { 502 remote-endpoint = 503 <&replicator_in_port0>; 504 }; 505 }; 506 }; 507 508 in-ports { 509 #address-cells = <1>; 510 #size-cells = <0>; 511 512 /* funnel input ports */ 513 port@0 { 514 reg = <0>; 515 funnel0_in_port0: endpoint { 516 remote-endpoint = <&ptm0_out_port>; 517 }; 518 }; 519 520 port@1 { 521 reg = <1>; 522 funnel0_in_port1: endpoint { 523 remote-endpoint = <&ptm1_out_port>; 524 }; 525 }; 526 527 port@2 { 528 reg = <2>; 529 funnel0_in_port2: endpoint { 530 }; 531 }; 532 /* The other input ports are not connect to anything */ 533 }; 534 }; 535 536 ptm@f889c000 { 537 compatible = "arm,coresight-etm3x", "arm,primecell"; 538 reg = <0xf889c000 0x1000>; 539 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 540 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 541 cpu = <&cpu0>; 542 out-ports { 543 port { 544 ptm0_out_port: endpoint { 545 remote-endpoint = <&funnel0_in_port0>; 546 }; 547 }; 548 }; 549 }; 550 551 ptm@f889d000 { 552 compatible = "arm,coresight-etm3x", "arm,primecell"; 553 reg = <0xf889d000 0x1000>; 554 clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>; 555 clock-names = "apb_pclk", "dbg_trc", "dbg_apb"; 556 cpu = <&cpu1>; 557 out-ports { 558 port { 559 ptm1_out_port: endpoint { 560 remote-endpoint = <&funnel0_in_port1>; 561 }; 562 }; 563 }; 564 }; 565 }; 566}; 567