1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 8#include <dt-bindings/clock/qcom,x1e80100-dispcc.h> 9#include <dt-bindings/clock/qcom,x1e80100-gcc.h> 10#include <dt-bindings/clock/qcom,x1e80100-gpucc.h> 11#include <dt-bindings/clock/qcom,x1e80100-tcsr.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/interconnect/qcom,icc.h> 14#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,gpr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 clock-frequency = <76800000>; 36 #clock-cells = <0>; 37 }; 38 39 sleep_clk: sleep-clk { 40 compatible = "fixed-clock"; 41 clock-frequency = <32764>; 42 #clock-cells = <0>; 43 }; 44 45 bi_tcxo_div2: bi-tcxo-div2-clk { 46 compatible = "fixed-factor-clock"; 47 #clock-cells = <0>; 48 49 clocks = <&rpmhcc RPMH_CXO_CLK>; 50 clock-mult = <1>; 51 clock-div = <2>; 52 }; 53 54 bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { 55 compatible = "fixed-factor-clock"; 56 #clock-cells = <0>; 57 58 clocks = <&rpmhcc RPMH_CXO_CLK_A>; 59 clock-mult = <1>; 60 clock-div = <2>; 61 }; 62 }; 63 64 cpus { 65 #address-cells = <2>; 66 #size-cells = <0>; 67 68 cpu0: cpu@0 { 69 device_type = "cpu"; 70 compatible = "qcom,oryon"; 71 reg = <0x0 0x0>; 72 enable-method = "psci"; 73 next-level-cache = <&l2_0>; 74 power-domains = <&cpu_pd0>; 75 power-domain-names = "psci"; 76 cpu-idle-states = <&cluster_c4>; 77 78 l2_0: l2-cache { 79 compatible = "cache"; 80 cache-level = <2>; 81 cache-unified; 82 }; 83 }; 84 85 cpu1: cpu@100 { 86 device_type = "cpu"; 87 compatible = "qcom,oryon"; 88 reg = <0x0 0x100>; 89 enable-method = "psci"; 90 next-level-cache = <&l2_0>; 91 power-domains = <&cpu_pd1>; 92 power-domain-names = "psci"; 93 cpu-idle-states = <&cluster_c4>; 94 }; 95 96 cpu2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "qcom,oryon"; 99 reg = <0x0 0x200>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_0>; 102 power-domains = <&cpu_pd2>; 103 power-domain-names = "psci"; 104 cpu-idle-states = <&cluster_c4>; 105 }; 106 107 cpu3: cpu@300 { 108 device_type = "cpu"; 109 compatible = "qcom,oryon"; 110 reg = <0x0 0x300>; 111 enable-method = "psci"; 112 next-level-cache = <&l2_0>; 113 power-domains = <&cpu_pd3>; 114 power-domain-names = "psci"; 115 cpu-idle-states = <&cluster_c4>; 116 }; 117 118 cpu4: cpu@10000 { 119 device_type = "cpu"; 120 compatible = "qcom,oryon"; 121 reg = <0x0 0x10000>; 122 enable-method = "psci"; 123 next-level-cache = <&l2_1>; 124 power-domains = <&cpu_pd4>; 125 power-domain-names = "psci"; 126 cpu-idle-states = <&cluster_c4>; 127 128 l2_1: l2-cache { 129 compatible = "cache"; 130 cache-level = <2>; 131 cache-unified; 132 }; 133 }; 134 135 cpu5: cpu@10100 { 136 device_type = "cpu"; 137 compatible = "qcom,oryon"; 138 reg = <0x0 0x10100>; 139 enable-method = "psci"; 140 next-level-cache = <&l2_1>; 141 power-domains = <&cpu_pd5>; 142 power-domain-names = "psci"; 143 cpu-idle-states = <&cluster_c4>; 144 }; 145 146 cpu6: cpu@10200 { 147 device_type = "cpu"; 148 compatible = "qcom,oryon"; 149 reg = <0x0 0x10200>; 150 enable-method = "psci"; 151 next-level-cache = <&l2_1>; 152 power-domains = <&cpu_pd6>; 153 power-domain-names = "psci"; 154 cpu-idle-states = <&cluster_c4>; 155 }; 156 157 cpu7: cpu@10300 { 158 device_type = "cpu"; 159 compatible = "qcom,oryon"; 160 reg = <0x0 0x10300>; 161 enable-method = "psci"; 162 next-level-cache = <&l2_1>; 163 power-domains = <&cpu_pd7>; 164 power-domain-names = "psci"; 165 cpu-idle-states = <&cluster_c4>; 166 }; 167 168 cpu8: cpu@20000 { 169 device_type = "cpu"; 170 compatible = "qcom,oryon"; 171 reg = <0x0 0x20000>; 172 enable-method = "psci"; 173 next-level-cache = <&l2_2>; 174 power-domains = <&cpu_pd8>; 175 power-domain-names = "psci"; 176 cpu-idle-states = <&cluster_c4>; 177 178 l2_2: l2-cache { 179 compatible = "cache"; 180 cache-level = <2>; 181 cache-unified; 182 }; 183 }; 184 185 cpu9: cpu@20100 { 186 device_type = "cpu"; 187 compatible = "qcom,oryon"; 188 reg = <0x0 0x20100>; 189 enable-method = "psci"; 190 next-level-cache = <&l2_2>; 191 power-domains = <&cpu_pd9>; 192 power-domain-names = "psci"; 193 cpu-idle-states = <&cluster_c4>; 194 }; 195 196 cpu10: cpu@20200 { 197 device_type = "cpu"; 198 compatible = "qcom,oryon"; 199 reg = <0x0 0x20200>; 200 enable-method = "psci"; 201 next-level-cache = <&l2_2>; 202 power-domains = <&cpu_pd10>; 203 power-domain-names = "psci"; 204 cpu-idle-states = <&cluster_c4>; 205 }; 206 207 cpu11: cpu@20300 { 208 device_type = "cpu"; 209 compatible = "qcom,oryon"; 210 reg = <0x0 0x20300>; 211 enable-method = "psci"; 212 next-level-cache = <&l2_2>; 213 power-domains = <&cpu_pd11>; 214 power-domain-names = "psci"; 215 cpu-idle-states = <&cluster_c4>; 216 }; 217 218 cpu-map { 219 cluster0 { 220 core0 { 221 cpu = <&cpu0>; 222 }; 223 224 core1 { 225 cpu = <&cpu1>; 226 }; 227 228 core2 { 229 cpu = <&cpu2>; 230 }; 231 232 core3 { 233 cpu = <&cpu3>; 234 }; 235 }; 236 237 cluster1 { 238 core0 { 239 cpu = <&cpu4>; 240 }; 241 242 core1 { 243 cpu = <&cpu5>; 244 }; 245 246 core2 { 247 cpu = <&cpu6>; 248 }; 249 250 core3 { 251 cpu = <&cpu7>; 252 }; 253 }; 254 255 cluster2 { 256 core0 { 257 cpu = <&cpu8>; 258 }; 259 260 core1 { 261 cpu = <&cpu9>; 262 }; 263 264 core2 { 265 cpu = <&cpu10>; 266 }; 267 268 core3 { 269 cpu = <&cpu11>; 270 }; 271 }; 272 }; 273 274 idle-states { 275 entry-method = "psci"; 276 277 cluster_c4: cpu-sleep-0 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "ret"; 280 arm,psci-suspend-param = <0x00000004>; 281 entry-latency-us = <180>; 282 exit-latency-us = <500>; 283 min-residency-us = <600>; 284 }; 285 }; 286 287 domain-idle-states { 288 cluster_cl4: cluster-sleep-0 { 289 compatible = "domain-idle-state"; 290 arm,psci-suspend-param = <0x01000044>; 291 entry-latency-us = <350>; 292 exit-latency-us = <500>; 293 min-residency-us = <2500>; 294 }; 295 296 cluster_cl5: cluster-sleep-1 { 297 compatible = "domain-idle-state"; 298 arm,psci-suspend-param = <0x01000054>; 299 entry-latency-us = <2200>; 300 exit-latency-us = <4000>; 301 min-residency-us = <7000>; 302 }; 303 }; 304 }; 305 306 dummy-sink { 307 compatible = "arm,coresight-dummy-sink"; 308 309 in-ports { 310 port { 311 eud_in: endpoint { 312 remote-endpoint = <&swao_rep_out1>; 313 }; 314 }; 315 }; 316 }; 317 318 firmware { 319 scm: scm { 320 compatible = "qcom,scm-x1e80100", "qcom,scm"; 321 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 322 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 323 qcom,dload-mode = <&tcsr 0x19000>; 324 }; 325 }; 326 327 clk_virt: interconnect-0 { 328 compatible = "qcom,x1e80100-clk-virt"; 329 #interconnect-cells = <2>; 330 qcom,bcm-voters = <&apps_bcm_voter>; 331 }; 332 333 mc_virt: interconnect-1 { 334 compatible = "qcom,x1e80100-mc-virt"; 335 #interconnect-cells = <2>; 336 qcom,bcm-voters = <&apps_bcm_voter>; 337 }; 338 339 memory@80000000 { 340 device_type = "memory"; 341 /* We expect the bootloader to fill in the size */ 342 reg = <0 0x80000000 0 0>; 343 }; 344 345 pmu { 346 compatible = "arm,armv8-pmuv3"; 347 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 348 }; 349 350 psci { 351 compatible = "arm,psci-1.0"; 352 method = "smc"; 353 354 cpu_pd0: power-domain-cpu0 { 355 #power-domain-cells = <0>; 356 power-domains = <&cluster_pd0>; 357 }; 358 359 cpu_pd1: power-domain-cpu1 { 360 #power-domain-cells = <0>; 361 power-domains = <&cluster_pd0>; 362 }; 363 364 cpu_pd2: power-domain-cpu2 { 365 #power-domain-cells = <0>; 366 power-domains = <&cluster_pd0>; 367 }; 368 369 cpu_pd3: power-domain-cpu3 { 370 #power-domain-cells = <0>; 371 power-domains = <&cluster_pd0>; 372 }; 373 374 cpu_pd4: power-domain-cpu4 { 375 #power-domain-cells = <0>; 376 power-domains = <&cluster_pd1>; 377 }; 378 379 cpu_pd5: power-domain-cpu5 { 380 #power-domain-cells = <0>; 381 power-domains = <&cluster_pd1>; 382 }; 383 384 cpu_pd6: power-domain-cpu6 { 385 #power-domain-cells = <0>; 386 power-domains = <&cluster_pd1>; 387 }; 388 389 cpu_pd7: power-domain-cpu7 { 390 #power-domain-cells = <0>; 391 power-domains = <&cluster_pd1>; 392 }; 393 394 cpu_pd8: power-domain-cpu8 { 395 #power-domain-cells = <0>; 396 power-domains = <&cluster_pd2>; 397 }; 398 399 cpu_pd9: power-domain-cpu9 { 400 #power-domain-cells = <0>; 401 power-domains = <&cluster_pd2>; 402 }; 403 404 cpu_pd10: power-domain-cpu10 { 405 #power-domain-cells = <0>; 406 power-domains = <&cluster_pd2>; 407 }; 408 409 cpu_pd11: power-domain-cpu11 { 410 #power-domain-cells = <0>; 411 power-domains = <&cluster_pd2>; 412 }; 413 414 cluster_pd0: power-domain-cpu-cluster0 { 415 #power-domain-cells = <0>; 416 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 417 power-domains = <&system_pd>; 418 }; 419 420 cluster_pd1: power-domain-cpu-cluster1 { 421 #power-domain-cells = <0>; 422 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 423 power-domains = <&system_pd>; 424 }; 425 426 cluster_pd2: power-domain-cpu-cluster2 { 427 #power-domain-cells = <0>; 428 domain-idle-states = <&cluster_cl4>, <&cluster_cl5>; 429 power-domains = <&system_pd>; 430 }; 431 432 system_pd: power-domain-system { 433 #power-domain-cells = <0>; 434 /* TODO: system-wide idle states */ 435 }; 436 }; 437 438 reserved-memory { 439 #address-cells = <2>; 440 #size-cells = <2>; 441 ranges; 442 443 gunyah_hyp_mem: gunyah-hyp@80000000 { 444 reg = <0x0 0x80000000 0x0 0x800000>; 445 no-map; 446 }; 447 448 hyp_elf_package_mem: hyp-elf-package@80800000 { 449 reg = <0x0 0x80800000 0x0 0x200000>; 450 no-map; 451 }; 452 453 ncc_mem: ncc@80a00000 { 454 reg = <0x0 0x80a00000 0x0 0x400000>; 455 no-map; 456 }; 457 458 cpucp_log_mem: cpucp-log@80e00000 { 459 reg = <0x0 0x80e00000 0x0 0x40000>; 460 no-map; 461 }; 462 463 cpucp_mem: cpucp@80e40000 { 464 reg = <0x0 0x80e40000 0x0 0x540000>; 465 no-map; 466 }; 467 468 reserved-region@81380000 { 469 reg = <0x0 0x81380000 0x0 0x80000>; 470 no-map; 471 }; 472 473 tags_mem: tags-region@81400000 { 474 reg = <0x0 0x81400000 0x0 0x1a0000>; 475 no-map; 476 }; 477 478 xbl_dtlog_mem: xbl-dtlog@81a00000 { 479 reg = <0x0 0x81a00000 0x0 0x40000>; 480 no-map; 481 }; 482 483 xbl_ramdump_mem: xbl-ramdump@81a40000 { 484 reg = <0x0 0x81a40000 0x0 0x1c0000>; 485 no-map; 486 }; 487 488 aop_image_mem: aop-image@81c00000 { 489 reg = <0x0 0x81c00000 0x0 0x60000>; 490 no-map; 491 }; 492 493 aop_cmd_db_mem: aop-cmd-db@81c60000 { 494 compatible = "qcom,cmd-db"; 495 reg = <0x0 0x81c60000 0x0 0x20000>; 496 no-map; 497 }; 498 499 aop_config_mem: aop-config@81c80000 { 500 reg = <0x0 0x81c80000 0x0 0x20000>; 501 no-map; 502 }; 503 504 tme_crash_dump_mem: tme-crash-dump@81ca0000 { 505 reg = <0x0 0x81ca0000 0x0 0x40000>; 506 no-map; 507 }; 508 509 tme_log_mem: tme-log@81ce0000 { 510 reg = <0x0 0x81ce0000 0x0 0x4000>; 511 no-map; 512 }; 513 514 uefi_log_mem: uefi-log@81ce4000 { 515 reg = <0x0 0x81ce4000 0x0 0x10000>; 516 no-map; 517 }; 518 519 secdata_apss_mem: secdata-apss@81cff000 { 520 reg = <0x0 0x81cff000 0x0 0x1000>; 521 no-map; 522 }; 523 524 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 525 reg = <0x0 0x81e00000 0x0 0x100000>; 526 no-map; 527 }; 528 529 gpu_prr_mem: gpu-prr@81f00000 { 530 reg = <0x0 0x81f00000 0x0 0x10000>; 531 no-map; 532 }; 533 534 tpm_control_mem: tpm-control@81f10000 { 535 reg = <0x0 0x81f10000 0x0 0x10000>; 536 no-map; 537 }; 538 539 usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 { 540 reg = <0x0 0x81f20000 0x0 0x10000>; 541 no-map; 542 }; 543 544 pld_pep_mem: pld-pep@81f30000 { 545 reg = <0x0 0x81f30000 0x0 0x6000>; 546 no-map; 547 }; 548 549 pld_gmu_mem: pld-gmu@81f36000 { 550 reg = <0x0 0x81f36000 0x0 0x1000>; 551 no-map; 552 }; 553 554 pld_pdp_mem: pld-pdp@81f37000 { 555 reg = <0x0 0x81f37000 0x0 0x1000>; 556 no-map; 557 }; 558 559 tz_stat_mem: tz-stat@82700000 { 560 reg = <0x0 0x82700000 0x0 0x100000>; 561 no-map; 562 }; 563 564 xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 { 565 reg = <0x0 0x82800000 0x0 0xc00000>; 566 no-map; 567 }; 568 569 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 { 570 reg = <0x0 0x84b00000 0x0 0x800000>; 571 no-map; 572 }; 573 574 spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 { 575 reg = <0x0 0x85300000 0x0 0x80000>; 576 no-map; 577 }; 578 579 adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 { 580 reg = <0x0 0x866c0000 0x0 0x40000>; 581 no-map; 582 }; 583 584 spss_region_mem: spss-region@86700000 { 585 reg = <0x0 0x86700000 0x0 0x400000>; 586 no-map; 587 }; 588 589 adsp_boot_mem: adsp-boot@86b00000 { 590 reg = <0x0 0x86b00000 0x0 0xc00000>; 591 no-map; 592 }; 593 594 video_mem: video@87700000 { 595 reg = <0x0 0x87700000 0x0 0x700000>; 596 no-map; 597 }; 598 599 adspslpi_mem: adspslpi@87e00000 { 600 reg = <0x0 0x87e00000 0x0 0x3a00000>; 601 no-map; 602 }; 603 604 q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 { 605 reg = <0x0 0x8b800000 0x0 0x80000>; 606 no-map; 607 }; 608 609 cdsp_mem: cdsp@8b900000 { 610 reg = <0x0 0x8b900000 0x0 0x2000000>; 611 no-map; 612 }; 613 614 q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 { 615 reg = <0x0 0x8d900000 0x0 0x80000>; 616 no-map; 617 }; 618 619 gpu_microcode_mem: gpu-microcode@8d9fe000 { 620 reg = <0x0 0x8d9fe000 0x0 0x2000>; 621 no-map; 622 }; 623 624 cvp_mem: cvp@8da00000 { 625 reg = <0x0 0x8da00000 0x0 0x700000>; 626 no-map; 627 }; 628 629 camera_mem: camera@8e100000 { 630 reg = <0x0 0x8e100000 0x0 0x800000>; 631 no-map; 632 }; 633 634 av1_encoder_mem: av1-encoder@8e900000 { 635 reg = <0x0 0x8e900000 0x0 0x700000>; 636 no-map; 637 }; 638 639 reserved-region@8f000000 { 640 reg = <0x0 0x8f000000 0x0 0xa00000>; 641 no-map; 642 }; 643 644 wpss_mem: wpss@8fa00000 { 645 reg = <0x0 0x8fa00000 0x0 0x1900000>; 646 no-map; 647 }; 648 649 q6_wpss_dtb_mem: q6-wpss-dtb@91300000 { 650 reg = <0x0 0x91300000 0x0 0x80000>; 651 no-map; 652 }; 653 654 xbl_sc_mem: xbl-sc@d8000000 { 655 reg = <0x0 0xd8000000 0x0 0x40000>; 656 no-map; 657 }; 658 659 reserved-region@d8040000 { 660 reg = <0x0 0xd8040000 0x0 0xa0000>; 661 no-map; 662 }; 663 664 qtee_mem: qtee@d80e0000 { 665 reg = <0x0 0xd80e0000 0x0 0x520000>; 666 no-map; 667 }; 668 669 ta_mem: ta@d8600000 { 670 reg = <0x0 0xd8600000 0x0 0x8a00000>; 671 no-map; 672 }; 673 674 tags_mem1: tags@e1000000 { 675 reg = <0x0 0xe1000000 0x0 0x26a0000>; 676 no-map; 677 }; 678 679 llcc_lpi_mem: llcc-lpi@ff800000 { 680 reg = <0x0 0xff800000 0x0 0x600000>; 681 no-map; 682 }; 683 684 smem_mem: smem@ffe00000 { 685 compatible = "qcom,smem"; 686 reg = <0x0 0xffe00000 0x0 0x200000>; 687 hwlocks = <&tcsr_mutex 3>; 688 no-map; 689 }; 690 }; 691 692 qup_opp_table_100mhz: opp-table-qup100mhz { 693 compatible = "operating-points-v2"; 694 695 opp-75000000 { 696 opp-hz = /bits/ 64 <75000000>; 697 required-opps = <&rpmhpd_opp_low_svs>; 698 }; 699 700 opp-100000000 { 701 opp-hz = /bits/ 64 <100000000>; 702 required-opps = <&rpmhpd_opp_svs>; 703 }; 704 }; 705 706 qup_opp_table_120mhz: opp-table-qup120mhz { 707 compatible = "operating-points-v2"; 708 709 opp-75000000 { 710 opp-hz = /bits/ 64 <75000000>; 711 required-opps = <&rpmhpd_opp_low_svs>; 712 }; 713 714 opp-120000000 { 715 opp-hz = /bits/ 64 <120000000>; 716 required-opps = <&rpmhpd_opp_svs>; 717 }; 718 }; 719 720 smp2p-adsp { 721 compatible = "qcom,smp2p"; 722 723 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 724 IPCC_MPROC_SIGNAL_SMP2P 725 IRQ_TYPE_EDGE_RISING>; 726 727 mboxes = <&ipcc IPCC_CLIENT_LPASS 728 IPCC_MPROC_SIGNAL_SMP2P>; 729 730 qcom,smem = <443>, <429>; 731 qcom,local-pid = <0>; 732 qcom,remote-pid = <2>; 733 734 smp2p_adsp_out: master-kernel { 735 qcom,entry-name = "master-kernel"; 736 #qcom,smem-state-cells = <1>; 737 }; 738 739 smp2p_adsp_in: slave-kernel { 740 qcom,entry-name = "slave-kernel"; 741 interrupt-controller; 742 #interrupt-cells = <2>; 743 }; 744 }; 745 746 smp2p-cdsp { 747 compatible = "qcom,smp2p"; 748 749 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 750 IPCC_MPROC_SIGNAL_SMP2P 751 IRQ_TYPE_EDGE_RISING>; 752 753 mboxes = <&ipcc IPCC_CLIENT_CDSP 754 IPCC_MPROC_SIGNAL_SMP2P>; 755 756 qcom,smem = <94>, <432>; 757 qcom,local-pid = <0>; 758 qcom,remote-pid = <5>; 759 760 smp2p_cdsp_out: master-kernel { 761 qcom,entry-name = "master-kernel"; 762 #qcom,smem-state-cells = <1>; 763 }; 764 765 smp2p_cdsp_in: slave-kernel { 766 qcom,entry-name = "slave-kernel"; 767 interrupt-controller; 768 #interrupt-cells = <2>; 769 }; 770 }; 771 772 soc: soc@0 { 773 compatible = "simple-bus"; 774 775 #address-cells = <2>; 776 #size-cells = <2>; 777 dma-ranges = <0 0 0 0 0x10 0>; 778 ranges = <0 0 0 0 0x10 0>; 779 780 gcc: clock-controller@100000 { 781 compatible = "qcom,x1e80100-gcc"; 782 reg = <0 0x00100000 0 0x200000>; 783 784 clocks = <&bi_tcxo_div2>, 785 <&sleep_clk>, 786 <&pcie3_phy>, 787 <&pcie4_phy>, 788 <&pcie5_phy>, 789 <&pcie6a_phy>, 790 <0>, 791 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 792 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 793 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 794 795 power-domains = <&rpmhpd RPMHPD_CX>; 796 #clock-cells = <1>; 797 #reset-cells = <1>; 798 #power-domain-cells = <1>; 799 }; 800 801 ipcc: mailbox@408000 { 802 compatible = "qcom,x1e80100-ipcc", "qcom,ipcc"; 803 reg = <0 0x00408000 0 0x1000>; 804 805 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 806 interrupt-controller; 807 #interrupt-cells = <3>; 808 809 #mbox-cells = <2>; 810 }; 811 812 gpi_dma2: dma-controller@800000 { 813 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 814 reg = <0 0x00800000 0 0x60000>; 815 816 interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; 828 829 dma-channels = <12>; 830 dma-channel-mask = <0x3e>; 831 #dma-cells = <3>; 832 833 iommus = <&apps_smmu 0x436 0x0>; 834 835 status = "disabled"; 836 }; 837 838 qupv3_2: geniqup@8c0000 { 839 compatible = "qcom,geni-se-qup"; 840 reg = <0 0x008c0000 0 0x2000>; 841 842 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 843 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 844 clock-names = "m-ahb", 845 "s-ahb"; 846 847 iommus = <&apps_smmu 0x423 0x0>; 848 849 #address-cells = <2>; 850 #size-cells = <2>; 851 ranges; 852 853 status = "disabled"; 854 855 i2c16: i2c@880000 { 856 compatible = "qcom,geni-i2c"; 857 reg = <0 0x00880000 0 0x4000>; 858 859 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 860 861 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 862 clock-names = "se"; 863 864 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 865 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 866 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 867 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 868 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 869 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 870 interconnect-names = "qup-core", 871 "qup-config", 872 "qup-memory"; 873 874 power-domains = <&rpmhpd RPMHPD_CX>; 875 required-opps = <&rpmhpd_opp_low_svs>; 876 877 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 878 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 879 dma-names = "tx", 880 "rx"; 881 882 pinctrl-0 = <&qup_i2c16_data_clk>; 883 pinctrl-names = "default"; 884 885 #address-cells = <1>; 886 #size-cells = <0>; 887 888 status = "disabled"; 889 }; 890 891 spi16: spi@880000 { 892 compatible = "qcom,geni-spi"; 893 reg = <0 0x00880000 0 0x4000>; 894 895 interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>; 896 897 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 898 clock-names = "se"; 899 900 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 901 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 902 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 903 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 904 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 905 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 906 interconnect-names = "qup-core", 907 "qup-config", 908 "qup-memory"; 909 910 power-domains = <&rpmhpd RPMHPD_CX>; 911 operating-points-v2 = <&qup_opp_table_120mhz>; 912 913 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 914 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 915 dma-names = "tx", 916 "rx"; 917 918 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 919 pinctrl-names = "default"; 920 921 #address-cells = <1>; 922 #size-cells = <0>; 923 924 status = "disabled"; 925 }; 926 927 i2c17: i2c@884000 { 928 compatible = "qcom,geni-i2c"; 929 reg = <0 0x00884000 0 0x4000>; 930 931 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 932 933 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 934 clock-names = "se"; 935 936 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 937 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 938 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 939 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 940 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 941 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 942 interconnect-names = "qup-core", 943 "qup-config", 944 "qup-memory"; 945 946 power-domains = <&rpmhpd RPMHPD_CX>; 947 required-opps = <&rpmhpd_opp_low_svs>; 948 949 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 950 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 951 dma-names = "tx", 952 "rx"; 953 954 pinctrl-0 = <&qup_i2c17_data_clk>; 955 pinctrl-names = "default"; 956 957 #address-cells = <1>; 958 #size-cells = <0>; 959 960 status = "disabled"; 961 }; 962 963 spi17: spi@884000 { 964 compatible = "qcom,geni-spi"; 965 reg = <0 0x00884000 0 0x4000>; 966 967 interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>; 968 969 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 970 clock-names = "se"; 971 972 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 973 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 974 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 975 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 976 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 977 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 978 interconnect-names = "qup-core", 979 "qup-config", 980 "qup-memory"; 981 982 power-domains = <&rpmhpd RPMHPD_CX>; 983 operating-points-v2 = <&qup_opp_table_120mhz>; 984 985 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 986 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 987 dma-names = "tx", 988 "rx"; 989 990 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 991 pinctrl-names = "default"; 992 993 #address-cells = <1>; 994 #size-cells = <0>; 995 996 status = "disabled"; 997 }; 998 999 i2c18: i2c@888000 { 1000 compatible = "qcom,geni-i2c"; 1001 reg = <0 0x00888000 0 0x4000>; 1002 1003 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1004 1005 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1006 clock-names = "se"; 1007 1008 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1009 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1010 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1011 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1012 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1013 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1014 interconnect-names = "qup-core", 1015 "qup-config", 1016 "qup-memory"; 1017 1018 power-domains = <&rpmhpd RPMHPD_CX>; 1019 required-opps = <&rpmhpd_opp_low_svs>; 1020 1021 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1022 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1023 dma-names = "tx", 1024 "rx"; 1025 1026 pinctrl-0 = <&qup_i2c18_data_clk>; 1027 pinctrl-names = "default"; 1028 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 1032 status = "disabled"; 1033 }; 1034 1035 spi18: spi@888000 { 1036 compatible = "qcom,geni-spi"; 1037 reg = <0 0x00888000 0 0x4000>; 1038 1039 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 1040 1041 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1042 clock-names = "se"; 1043 1044 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1045 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1046 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1047 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1048 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1049 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1050 interconnect-names = "qup-core", 1051 "qup-config", 1052 "qup-memory"; 1053 1054 power-domains = <&rpmhpd RPMHPD_CX>; 1055 operating-points-v2 = <&qup_opp_table_100mhz>; 1056 1057 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1058 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1059 dma-names = "tx", 1060 "rx"; 1061 1062 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1063 pinctrl-names = "default"; 1064 1065 #address-cells = <1>; 1066 #size-cells = <0>; 1067 1068 status = "disabled"; 1069 }; 1070 1071 i2c19: i2c@88c000 { 1072 compatible = "qcom,geni-i2c"; 1073 reg = <0 0x0088c000 0 0x4000>; 1074 1075 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1076 1077 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1078 clock-names = "se"; 1079 1080 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1081 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1082 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1083 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1084 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1085 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1086 interconnect-names = "qup-core", 1087 "qup-config", 1088 "qup-memory"; 1089 1090 power-domains = <&rpmhpd RPMHPD_CX>; 1091 required-opps = <&rpmhpd_opp_low_svs>; 1092 1093 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1094 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1095 dma-names = "tx", 1096 "rx"; 1097 1098 pinctrl-0 = <&qup_i2c19_data_clk>; 1099 pinctrl-names = "default"; 1100 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 1104 status = "disabled"; 1105 }; 1106 1107 spi19: spi@88c000 { 1108 compatible = "qcom,geni-spi"; 1109 reg = <0 0x0088c000 0 0x4000>; 1110 1111 interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>; 1112 1113 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1114 clock-names = "se"; 1115 1116 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1117 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1118 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1119 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1120 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1121 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1122 interconnect-names = "qup-core", 1123 "qup-config", 1124 "qup-memory"; 1125 1126 power-domains = <&rpmhpd RPMHPD_CX>; 1127 operating-points-v2 = <&qup_opp_table_100mhz>; 1128 1129 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1130 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1131 dma-names = "tx", 1132 "rx"; 1133 1134 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1135 pinctrl-names = "default"; 1136 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 1140 status = "disabled"; 1141 }; 1142 1143 i2c20: i2c@890000 { 1144 compatible = "qcom,geni-i2c"; 1145 reg = <0 0x00890000 0 0x4000>; 1146 1147 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1148 1149 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1150 clock-names = "se"; 1151 1152 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1153 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1154 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1155 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1156 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1157 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1158 interconnect-names = "qup-core", 1159 "qup-config", 1160 "qup-memory"; 1161 1162 power-domains = <&rpmhpd RPMHPD_CX>; 1163 required-opps = <&rpmhpd_opp_low_svs>; 1164 1165 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1166 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1167 dma-names = "tx", 1168 "rx"; 1169 1170 pinctrl-0 = <&qup_i2c20_data_clk>; 1171 pinctrl-names = "default"; 1172 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 1176 status = "disabled"; 1177 }; 1178 1179 spi20: spi@890000 { 1180 compatible = "qcom,geni-spi"; 1181 reg = <0 0x00890000 0 0x4000>; 1182 1183 interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>; 1184 1185 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1186 clock-names = "se"; 1187 1188 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1189 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1190 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1191 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1192 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1193 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1194 interconnect-names = "qup-core", 1195 "qup-config", 1196 "qup-memory"; 1197 1198 power-domains = <&rpmhpd RPMHPD_CX>; 1199 operating-points-v2 = <&qup_opp_table_100mhz>; 1200 1201 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1202 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1203 dma-names = "tx", 1204 "rx"; 1205 1206 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1207 pinctrl-names = "default"; 1208 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 1212 status = "disabled"; 1213 }; 1214 1215 i2c21: i2c@894000 { 1216 compatible = "qcom,geni-i2c"; 1217 reg = <0 0x00894000 0 0x4000>; 1218 1219 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1220 1221 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1222 clock-names = "se"; 1223 1224 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1225 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1226 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1227 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1228 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1229 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1230 interconnect-names = "qup-core", 1231 "qup-config", 1232 "qup-memory"; 1233 1234 power-domains = <&rpmhpd RPMHPD_CX>; 1235 required-opps = <&rpmhpd_opp_low_svs>; 1236 1237 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1238 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1239 dma-names = "tx", 1240 "rx"; 1241 1242 pinctrl-0 = <&qup_i2c21_data_clk>; 1243 pinctrl-names = "default"; 1244 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 1248 status = "disabled"; 1249 }; 1250 1251 spi21: spi@894000 { 1252 compatible = "qcom,geni-spi"; 1253 reg = <0 0x00894000 0 0x4000>; 1254 1255 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1256 1257 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1258 clock-names = "se"; 1259 1260 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1261 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1262 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1263 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1264 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1265 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1266 interconnect-names = "qup-core", 1267 "qup-config", 1268 "qup-memory"; 1269 1270 power-domains = <&rpmhpd RPMHPD_CX>; 1271 operating-points-v2 = <&qup_opp_table_100mhz>; 1272 1273 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1274 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1275 dma-names = "tx", 1276 "rx"; 1277 1278 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1279 pinctrl-names = "default"; 1280 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 1284 status = "disabled"; 1285 }; 1286 1287 uart21: serial@894000 { 1288 compatible = "qcom,geni-uart"; 1289 reg = <0 0x00894000 0 0x4000>; 1290 1291 interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>; 1292 1293 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1294 clock-names = "se"; 1295 1296 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1297 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1298 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1299 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1300 interconnect-names = "qup-core", 1301 "qup-config"; 1302 1303 power-domains = <&rpmhpd RPMHPD_CX>; 1304 operating-points-v2 = <&qup_opp_table_100mhz>; 1305 1306 pinctrl-0 = <&qup_uart21_default>; 1307 pinctrl-names = "default"; 1308 1309 status = "disabled"; 1310 }; 1311 1312 i2c22: i2c@898000 { 1313 compatible = "qcom,geni-i2c"; 1314 reg = <0 0x00898000 0 0x4000>; 1315 1316 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1317 1318 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1319 clock-names = "se"; 1320 1321 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1322 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1323 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1324 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1325 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1326 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1327 interconnect-names = "qup-core", 1328 "qup-config", 1329 "qup-memory"; 1330 1331 power-domains = <&rpmhpd RPMHPD_CX>; 1332 required-opps = <&rpmhpd_opp_low_svs>; 1333 1334 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1335 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1336 dma-names = "tx", 1337 "rx"; 1338 1339 pinctrl-0 = <&qup_i2c22_data_clk>; 1340 pinctrl-names = "default"; 1341 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 1345 status = "disabled"; 1346 }; 1347 1348 spi22: spi@898000 { 1349 compatible = "qcom,geni-spi"; 1350 reg = <0 0x00898000 0 0x4000>; 1351 1352 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1353 1354 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1355 clock-names = "se"; 1356 1357 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1358 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1359 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1360 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1361 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1362 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1363 interconnect-names = "qup-core", 1364 "qup-config", 1365 "qup-memory"; 1366 1367 power-domains = <&rpmhpd RPMHPD_CX>; 1368 operating-points-v2 = <&qup_opp_table_100mhz>; 1369 1370 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1371 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1372 dma-names = "tx", 1373 "rx"; 1374 1375 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1376 pinctrl-names = "default"; 1377 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 1381 status = "disabled"; 1382 }; 1383 1384 i2c23: i2c@89c000 { 1385 compatible = "qcom,geni-i2c"; 1386 reg = <0 0x0089c000 0 0x4000>; 1387 1388 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1389 1390 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1391 clock-names = "se"; 1392 1393 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1394 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1395 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1396 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1397 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1398 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1399 interconnect-names = "qup-core", 1400 "qup-config", 1401 "qup-memory"; 1402 1403 power-domains = <&rpmhpd RPMHPD_CX>; 1404 required-opps = <&rpmhpd_opp_low_svs>; 1405 1406 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1407 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1408 dma-names = "tx", 1409 "rx"; 1410 1411 pinctrl-0 = <&qup_i2c23_data_clk>; 1412 pinctrl-names = "default"; 1413 1414 #address-cells = <1>; 1415 #size-cells = <0>; 1416 1417 status = "disabled"; 1418 }; 1419 1420 spi23: spi@89c000 { 1421 compatible = "qcom,geni-spi"; 1422 reg = <0 0x0089c000 0 0x4000>; 1423 1424 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1425 1426 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1427 clock-names = "se"; 1428 1429 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1430 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1431 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1432 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1433 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1434 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1435 interconnect-names = "qup-core", 1436 "qup-config", 1437 "qup-memory"; 1438 1439 power-domains = <&rpmhpd RPMHPD_CX>; 1440 operating-points-v2 = <&qup_opp_table_100mhz>; 1441 1442 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1443 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1444 dma-names = "tx", 1445 "rx"; 1446 1447 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1448 pinctrl-names = "default"; 1449 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 1453 status = "disabled"; 1454 }; 1455 }; 1456 1457 gpi_dma1: dma-controller@a00000 { 1458 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 1459 reg = <0 0x00a00000 0 0x60000>; 1460 1461 interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>; 1473 1474 dma-channels = <12>; 1475 dma-channel-mask = <0x3e>; 1476 #dma-cells = <3>; 1477 1478 iommus = <&apps_smmu 0x136 0x0>; 1479 1480 status = "disabled"; 1481 }; 1482 1483 qupv3_1: geniqup@ac0000 { 1484 compatible = "qcom,geni-se-qup"; 1485 reg = <0 0x00ac0000 0 0x2000>; 1486 1487 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1488 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1489 clock-names = "m-ahb", 1490 "s-ahb"; 1491 1492 iommus = <&apps_smmu 0x123 0x0>; 1493 1494 #address-cells = <2>; 1495 #size-cells = <2>; 1496 ranges; 1497 1498 status = "disabled"; 1499 1500 i2c8: i2c@a80000 { 1501 compatible = "qcom,geni-i2c"; 1502 reg = <0 0x00a80000 0 0x4000>; 1503 1504 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1505 1506 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1507 clock-names = "se"; 1508 1509 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1510 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1511 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1512 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1513 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1514 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1515 interconnect-names = "qup-core", 1516 "qup-config", 1517 "qup-memory"; 1518 1519 power-domains = <&rpmhpd RPMHPD_CX>; 1520 required-opps = <&rpmhpd_opp_low_svs>; 1521 1522 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1523 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1524 dma-names = "tx", 1525 "rx"; 1526 1527 pinctrl-0 = <&qup_i2c8_data_clk>; 1528 pinctrl-names = "default"; 1529 1530 #address-cells = <1>; 1531 #size-cells = <0>; 1532 1533 status = "disabled"; 1534 }; 1535 1536 spi8: spi@a80000 { 1537 compatible = "qcom,geni-spi"; 1538 reg = <0 0x00a80000 0 0x4000>; 1539 1540 interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>; 1541 1542 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1543 clock-names = "se"; 1544 1545 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1546 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1547 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1548 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1549 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1550 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1551 interconnect-names = "qup-core", 1552 "qup-config", 1553 "qup-memory"; 1554 1555 power-domains = <&rpmhpd RPMHPD_CX>; 1556 operating-points-v2 = <&qup_opp_table_120mhz>; 1557 1558 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1559 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1560 dma-names = "tx", 1561 "rx"; 1562 1563 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1564 pinctrl-names = "default"; 1565 1566 #address-cells = <1>; 1567 #size-cells = <0>; 1568 1569 status = "disabled"; 1570 }; 1571 1572 i2c9: i2c@a84000 { 1573 compatible = "qcom,geni-i2c"; 1574 reg = <0 0x00a84000 0 0x4000>; 1575 1576 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1577 1578 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1579 clock-names = "se"; 1580 1581 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1582 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1583 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1584 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1585 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1586 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1587 interconnect-names = "qup-core", 1588 "qup-config", 1589 "qup-memory"; 1590 1591 power-domains = <&rpmhpd RPMHPD_CX>; 1592 required-opps = <&rpmhpd_opp_low_svs>; 1593 1594 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1595 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1596 dma-names = "tx", 1597 "rx"; 1598 1599 pinctrl-0 = <&qup_i2c9_data_clk>; 1600 pinctrl-names = "default"; 1601 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 1605 status = "disabled"; 1606 }; 1607 1608 spi9: spi@a84000 { 1609 compatible = "qcom,geni-spi"; 1610 reg = <0 0x00a84000 0 0x4000>; 1611 1612 interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>; 1613 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1615 clock-names = "se"; 1616 1617 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1618 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1619 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1620 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1621 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1622 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1623 interconnect-names = "qup-core", 1624 "qup-config", 1625 "qup-memory"; 1626 1627 power-domains = <&rpmhpd RPMHPD_CX>; 1628 operating-points-v2 = <&qup_opp_table_120mhz>; 1629 1630 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1631 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1632 dma-names = "tx", 1633 "rx"; 1634 1635 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1636 pinctrl-names = "default"; 1637 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 1641 status = "disabled"; 1642 }; 1643 1644 i2c10: i2c@a88000 { 1645 compatible = "qcom,geni-i2c"; 1646 reg = <0 0x00a88000 0 0x4000>; 1647 1648 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1649 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1651 clock-names = "se"; 1652 1653 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1654 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1655 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1656 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1657 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1658 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1659 interconnect-names = "qup-core", 1660 "qup-config", 1661 "qup-memory"; 1662 1663 power-domains = <&rpmhpd RPMHPD_CX>; 1664 required-opps = <&rpmhpd_opp_low_svs>; 1665 1666 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1667 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1668 dma-names = "tx", 1669 "rx"; 1670 1671 pinctrl-0 = <&qup_i2c10_data_clk>; 1672 pinctrl-names = "default"; 1673 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 1677 status = "disabled"; 1678 }; 1679 1680 spi10: spi@a88000 { 1681 compatible = "qcom,geni-spi"; 1682 reg = <0 0x00a88000 0 0x4000>; 1683 1684 interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>; 1685 1686 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1687 clock-names = "se"; 1688 1689 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1690 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1691 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1692 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1693 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1694 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1695 interconnect-names = "qup-core", 1696 "qup-config", 1697 "qup-memory"; 1698 1699 power-domains = <&rpmhpd RPMHPD_CX>; 1700 operating-points-v2 = <&qup_opp_table_100mhz>; 1701 1702 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1703 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1704 dma-names = "tx", 1705 "rx"; 1706 1707 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1708 pinctrl-names = "default"; 1709 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 1713 status = "disabled"; 1714 }; 1715 1716 i2c11: i2c@a8c000 { 1717 compatible = "qcom,geni-i2c"; 1718 reg = <0 0x00a8c000 0 0x4000>; 1719 1720 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1721 1722 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1723 clock-names = "se"; 1724 1725 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1726 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1727 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1728 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1729 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1730 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1731 interconnect-names = "qup-core", 1732 "qup-config", 1733 "qup-memory"; 1734 1735 power-domains = <&rpmhpd RPMHPD_CX>; 1736 required-opps = <&rpmhpd_opp_low_svs>; 1737 1738 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1739 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1740 dma-names = "tx", 1741 "rx"; 1742 1743 pinctrl-0 = <&qup_i2c11_data_clk>; 1744 pinctrl-names = "default"; 1745 1746 #address-cells = <1>; 1747 #size-cells = <0>; 1748 1749 status = "disabled"; 1750 }; 1751 1752 spi11: spi@a8c000 { 1753 compatible = "qcom,geni-spi"; 1754 reg = <0 0x00a8c000 0 0x4000>; 1755 1756 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 1757 1758 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1759 clock-names = "se"; 1760 1761 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1762 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1763 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1764 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1765 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1766 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1767 interconnect-names = "qup-core", 1768 "qup-config", 1769 "qup-memory"; 1770 1771 power-domains = <&rpmhpd RPMHPD_CX>; 1772 operating-points-v2 = <&qup_opp_table_100mhz>; 1773 1774 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1775 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1776 dma-names = "tx", 1777 "rx"; 1778 1779 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1780 pinctrl-names = "default"; 1781 1782 #address-cells = <1>; 1783 #size-cells = <0>; 1784 1785 status = "disabled"; 1786 }; 1787 1788 i2c12: i2c@a90000 { 1789 compatible = "qcom,geni-i2c"; 1790 reg = <0 0x00a90000 0 0x4000>; 1791 1792 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1793 1794 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1795 clock-names = "se"; 1796 1797 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1798 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1799 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1800 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1801 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1802 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1803 interconnect-names = "qup-core", 1804 "qup-config", 1805 "qup-memory"; 1806 1807 power-domains = <&rpmhpd RPMHPD_CX>; 1808 required-opps = <&rpmhpd_opp_low_svs>; 1809 1810 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1811 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1812 dma-names = "tx", 1813 "rx"; 1814 1815 pinctrl-0 = <&qup_i2c12_data_clk>; 1816 pinctrl-names = "default"; 1817 1818 #address-cells = <1>; 1819 #size-cells = <0>; 1820 1821 status = "disabled"; 1822 }; 1823 1824 spi12: spi@a90000 { 1825 compatible = "qcom,geni-spi"; 1826 reg = <0 0x00a90000 0 0x4000>; 1827 1828 interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>; 1829 1830 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1831 clock-names = "se"; 1832 1833 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1834 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1835 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1836 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1837 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1838 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1839 interconnect-names = "qup-core", 1840 "qup-config", 1841 "qup-memory"; 1842 1843 power-domains = <&rpmhpd RPMHPD_CX>; 1844 operating-points-v2 = <&qup_opp_table_100mhz>; 1845 1846 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1847 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1848 dma-names = "tx", 1849 "rx"; 1850 1851 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1852 pinctrl-names = "default"; 1853 1854 #address-cells = <1>; 1855 #size-cells = <0>; 1856 1857 status = "disabled"; 1858 }; 1859 1860 i2c13: i2c@a94000 { 1861 compatible = "qcom,geni-i2c"; 1862 reg = <0 0x00a94000 0 0x4000>; 1863 1864 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1865 1866 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1867 clock-names = "se"; 1868 1869 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1870 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1871 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1872 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1873 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1874 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1875 interconnect-names = "qup-core", 1876 "qup-config", 1877 "qup-memory"; 1878 1879 power-domains = <&rpmhpd RPMHPD_CX>; 1880 required-opps = <&rpmhpd_opp_low_svs>; 1881 1882 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1883 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1884 dma-names = "tx", 1885 "rx"; 1886 1887 pinctrl-0 = <&qup_i2c13_data_clk>; 1888 pinctrl-names = "default"; 1889 1890 #address-cells = <1>; 1891 #size-cells = <0>; 1892 1893 status = "disabled"; 1894 }; 1895 1896 spi13: spi@a94000 { 1897 compatible = "qcom,geni-spi"; 1898 reg = <0 0x00a94000 0 0x4000>; 1899 1900 interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>; 1901 1902 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1903 clock-names = "se"; 1904 1905 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1906 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1907 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1908 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1909 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1910 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1911 interconnect-names = "qup-core", 1912 "qup-config", 1913 "qup-memory"; 1914 1915 power-domains = <&rpmhpd RPMHPD_CX>; 1916 operating-points-v2 = <&qup_opp_table_100mhz>; 1917 1918 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1919 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1920 dma-names = "tx", 1921 "rx"; 1922 1923 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1924 pinctrl-names = "default"; 1925 1926 #address-cells = <1>; 1927 #size-cells = <0>; 1928 1929 status = "disabled"; 1930 }; 1931 1932 i2c14: i2c@a98000 { 1933 compatible = "qcom,geni-i2c"; 1934 reg = <0 0x00a98000 0 0x4000>; 1935 1936 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1937 1938 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1939 clock-names = "se"; 1940 1941 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1942 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1943 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1944 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1945 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1946 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1947 interconnect-names = "qup-core", 1948 "qup-config", 1949 "qup-memory"; 1950 1951 power-domains = <&rpmhpd RPMHPD_CX>; 1952 required-opps = <&rpmhpd_opp_low_svs>; 1953 1954 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1955 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1956 dma-names = "tx", 1957 "rx"; 1958 1959 pinctrl-0 = <&qup_i2c14_data_clk>; 1960 pinctrl-names = "default"; 1961 1962 #address-cells = <1>; 1963 #size-cells = <0>; 1964 1965 status = "disabled"; 1966 }; 1967 1968 spi14: spi@a98000 { 1969 compatible = "qcom,geni-spi"; 1970 reg = <0 0x00a98000 0 0x4000>; 1971 1972 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 1973 1974 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1975 clock-names = "se"; 1976 1977 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1978 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1979 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1980 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1981 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1982 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1983 interconnect-names = "qup-core", 1984 "qup-config", 1985 "qup-memory"; 1986 1987 power-domains = <&rpmhpd RPMHPD_CX>; 1988 operating-points-v2 = <&qup_opp_table_100mhz>; 1989 1990 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1991 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1992 dma-names = "tx", 1993 "rx"; 1994 1995 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1996 pinctrl-names = "default"; 1997 1998 #address-cells = <1>; 1999 #size-cells = <0>; 2000 2001 status = "disabled"; 2002 }; 2003 2004 uart14: serial@a98000 { 2005 compatible = "qcom,geni-uart"; 2006 reg = <0 0x00a98000 0 0x4000>; 2007 2008 interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>; 2009 2010 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2011 clock-names = "se"; 2012 2013 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2014 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2015 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2016 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2017 interconnect-names = "qup-core", 2018 "qup-config"; 2019 2020 power-domains = <&rpmhpd RPMHPD_CX>; 2021 operating-points-v2 = <&qup_opp_table_100mhz>; 2022 2023 pinctrl-0 = <&qup_uart14_default>; 2024 pinctrl-names = "default"; 2025 2026 status = "disabled"; 2027 }; 2028 2029 i2c15: i2c@a9c000 { 2030 compatible = "qcom,geni-i2c"; 2031 reg = <0 0x00a9c000 0 0x4000>; 2032 2033 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2034 2035 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2036 clock-names = "se"; 2037 2038 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2039 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2040 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2041 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2042 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2043 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2044 interconnect-names = "qup-core", 2045 "qup-config", 2046 "qup-memory"; 2047 2048 power-domains = <&rpmhpd RPMHPD_CX>; 2049 required-opps = <&rpmhpd_opp_low_svs>; 2050 2051 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2052 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2053 dma-names = "tx", 2054 "rx"; 2055 2056 pinctrl-0 = <&qup_i2c15_data_clk>; 2057 pinctrl-names = "default"; 2058 2059 #address-cells = <1>; 2060 #size-cells = <0>; 2061 2062 status = "disabled"; 2063 }; 2064 2065 spi15: spi@a9c000 { 2066 compatible = "qcom,geni-spi"; 2067 reg = <0 0x00a9c000 0 0x4000>; 2068 2069 interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>; 2070 2071 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2072 clock-names = "se"; 2073 2074 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2075 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2076 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2077 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2078 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2079 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2080 interconnect-names = "qup-core", 2081 "qup-config", 2082 "qup-memory"; 2083 2084 power-domains = <&rpmhpd RPMHPD_CX>; 2085 operating-points-v2 = <&qup_opp_table_100mhz>; 2086 2087 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2088 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2089 dma-names = "tx", 2090 "rx"; 2091 2092 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2093 pinctrl-names = "default"; 2094 2095 #address-cells = <1>; 2096 #size-cells = <0>; 2097 2098 status = "disabled"; 2099 }; 2100 }; 2101 2102 gpi_dma0: dma-controller@b00000 { 2103 compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma"; 2104 reg = <0 0x00b00000 0 0x60000>; 2105 2106 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 2118 2119 dma-channels = <12>; 2120 dma-channel-mask = <0x3e>; 2121 #dma-cells = <3>; 2122 2123 iommus = <&apps_smmu 0x456 0x0>; 2124 2125 status = "disabled"; 2126 }; 2127 2128 qupv3_0: geniqup@bc0000 { 2129 compatible = "qcom,geni-se-qup"; 2130 reg = <0 0x00bc0000 0 0x2000>; 2131 2132 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 2133 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 2134 clock-names = "m-ahb", 2135 "s-ahb"; 2136 2137 iommus = <&apps_smmu 0x443 0x0>; 2138 #address-cells = <2>; 2139 #size-cells = <2>; 2140 ranges; 2141 2142 status = "disabled"; 2143 2144 i2c0: i2c@b80000 { 2145 compatible = "qcom,geni-i2c"; 2146 reg = <0 0x00b80000 0 0x4000>; 2147 2148 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2149 2150 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2151 clock-names = "se"; 2152 2153 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2154 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2155 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2156 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2157 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2158 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2159 interconnect-names = "qup-core", 2160 "qup-config", 2161 "qup-memory"; 2162 2163 power-domains = <&rpmhpd RPMHPD_CX>; 2164 required-opps = <&rpmhpd_opp_low_svs>; 2165 2166 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 2167 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 2168 dma-names = "tx", 2169 "rx"; 2170 2171 pinctrl-0 = <&qup_i2c0_data_clk>; 2172 pinctrl-names = "default"; 2173 2174 #address-cells = <1>; 2175 #size-cells = <0>; 2176 2177 status = "disabled"; 2178 }; 2179 2180 spi0: spi@b80000 { 2181 compatible = "qcom,geni-spi"; 2182 reg = <0 0x00b80000 0 0x4000>; 2183 2184 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2185 2186 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 2187 clock-names = "se"; 2188 2189 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2190 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2191 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2192 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2193 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2194 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2195 interconnect-names = "qup-core", 2196 "qup-config", 2197 "qup-memory"; 2198 2199 power-domains = <&rpmhpd RPMHPD_CX>; 2200 operating-points-v2 = <&qup_opp_table_120mhz>; 2201 2202 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 2203 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 2204 dma-names = "tx", 2205 "rx"; 2206 2207 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 2208 pinctrl-names = "default"; 2209 2210 #address-cells = <1>; 2211 #size-cells = <0>; 2212 2213 status = "disabled"; 2214 }; 2215 2216 i2c1: i2c@b84000 { 2217 compatible = "qcom,geni-i2c"; 2218 reg = <0 0x00b84000 0 0x4000>; 2219 2220 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2221 2222 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2223 clock-names = "se"; 2224 2225 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2226 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2227 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2228 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2229 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2230 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2231 interconnect-names = "qup-core", 2232 "qup-config", 2233 "qup-memory"; 2234 2235 power-domains = <&rpmhpd RPMHPD_CX>; 2236 required-opps = <&rpmhpd_opp_low_svs>; 2237 2238 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 2239 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 2240 dma-names = "tx", 2241 "rx"; 2242 2243 pinctrl-0 = <&qup_i2c1_data_clk>; 2244 pinctrl-names = "default"; 2245 2246 #address-cells = <1>; 2247 #size-cells = <0>; 2248 2249 status = "disabled"; 2250 }; 2251 2252 spi1: spi@b84000 { 2253 compatible = "qcom,geni-spi"; 2254 reg = <0 0x00b84000 0 0x4000>; 2255 2256 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 2257 2258 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 2259 clock-names = "se"; 2260 2261 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2262 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2263 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2264 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2265 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2266 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2267 interconnect-names = "qup-core", 2268 "qup-config", 2269 "qup-memory"; 2270 2271 power-domains = <&rpmhpd RPMHPD_CX>; 2272 operating-points-v2 = <&qup_opp_table_120mhz>; 2273 2274 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 2275 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 2276 dma-names = "tx", 2277 "rx"; 2278 2279 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 2280 pinctrl-names = "default"; 2281 2282 #address-cells = <1>; 2283 #size-cells = <0>; 2284 2285 status = "disabled"; 2286 }; 2287 2288 i2c2: i2c@b88000 { 2289 compatible = "qcom,geni-i2c"; 2290 reg = <0 0x00b88000 0 0x4000>; 2291 2292 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2293 2294 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2295 clock-names = "se"; 2296 2297 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2298 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2299 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2300 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2301 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2302 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2303 interconnect-names = "qup-core", 2304 "qup-config", 2305 "qup-memory"; 2306 2307 power-domains = <&rpmhpd RPMHPD_CX>; 2308 required-opps = <&rpmhpd_opp_low_svs>; 2309 2310 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2311 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2312 dma-names = "tx", 2313 "rx"; 2314 2315 pinctrl-0 = <&qup_i2c2_data_clk>; 2316 pinctrl-names = "default"; 2317 2318 #address-cells = <1>; 2319 #size-cells = <0>; 2320 2321 status = "disabled"; 2322 }; 2323 2324 uart2: serial@b88000 { 2325 compatible = "qcom,geni-uart"; 2326 reg = <0 0x00b88000 0 0x4000>; 2327 2328 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2329 2330 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2331 clock-names = "se"; 2332 2333 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2334 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2335 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2336 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2337 interconnect-names = "qup-core", 2338 "qup-config"; 2339 2340 power-domains = <&rpmhpd RPMHPD_CX>; 2341 operating-points-v2 = <&qup_opp_table_100mhz>; 2342 2343 pinctrl-0 = <&qup_uart2_default>; 2344 pinctrl-names = "default"; 2345 2346 status = "disabled"; 2347 }; 2348 2349 spi2: spi@b88000 { 2350 compatible = "qcom,geni-spi"; 2351 reg = <0 0x00b88000 0 0x4000>; 2352 2353 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 2354 2355 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2356 clock-names = "se"; 2357 2358 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2359 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2360 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2361 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2362 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2363 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2364 interconnect-names = "qup-core", 2365 "qup-config", 2366 "qup-memory"; 2367 2368 power-domains = <&rpmhpd RPMHPD_CX>; 2369 operating-points-v2 = <&qup_opp_table_100mhz>; 2370 2371 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2372 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2373 dma-names = "tx", 2374 "rx"; 2375 2376 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2377 pinctrl-names = "default"; 2378 2379 #address-cells = <1>; 2380 #size-cells = <0>; 2381 2382 status = "disabled"; 2383 }; 2384 2385 i2c3: i2c@b8c000 { 2386 compatible = "qcom,geni-i2c"; 2387 reg = <0 0x00b8c000 0 0x4000>; 2388 2389 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2390 2391 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2392 clock-names = "se"; 2393 2394 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2395 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2396 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2397 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2398 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2399 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2400 interconnect-names = "qup-core", 2401 "qup-config", 2402 "qup-memory"; 2403 2404 power-domains = <&rpmhpd RPMHPD_CX>; 2405 required-opps = <&rpmhpd_opp_low_svs>; 2406 2407 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2408 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2409 dma-names = "tx", 2410 "rx"; 2411 2412 pinctrl-0 = <&qup_i2c3_data_clk>; 2413 pinctrl-names = "default"; 2414 2415 #address-cells = <1>; 2416 #size-cells = <0>; 2417 2418 status = "disabled"; 2419 }; 2420 2421 spi3: spi@b8c000 { 2422 compatible = "qcom,geni-spi"; 2423 reg = <0 0x00b8c000 0 0x4000>; 2424 2425 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 2426 2427 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2428 clock-names = "se"; 2429 2430 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2431 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2432 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2433 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2434 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2435 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2436 interconnect-names = "qup-core", 2437 "qup-config", 2438 "qup-memory"; 2439 2440 power-domains = <&rpmhpd RPMHPD_CX>; 2441 operating-points-v2 = <&qup_opp_table_100mhz>; 2442 2443 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2444 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2445 dma-names = "tx", 2446 "rx"; 2447 2448 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2449 pinctrl-names = "default"; 2450 2451 #address-cells = <1>; 2452 #size-cells = <0>; 2453 2454 status = "disabled"; 2455 }; 2456 2457 i2c4: i2c@b90000 { 2458 compatible = "qcom,geni-i2c"; 2459 reg = <0 0x00b90000 0 0x4000>; 2460 2461 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2462 2463 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2464 clock-names = "se"; 2465 2466 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2467 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2468 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2469 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2470 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2471 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2472 interconnect-names = "qup-core", 2473 "qup-config", 2474 "qup-memory"; 2475 2476 power-domains = <&rpmhpd RPMHPD_CX>; 2477 required-opps = <&rpmhpd_opp_low_svs>; 2478 2479 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2480 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2481 dma-names = "tx", 2482 "rx"; 2483 2484 pinctrl-0 = <&qup_i2c4_data_clk>; 2485 pinctrl-names = "default"; 2486 2487 #address-cells = <1>; 2488 #size-cells = <0>; 2489 2490 status = "disabled"; 2491 }; 2492 2493 spi4: spi@b90000 { 2494 compatible = "qcom,geni-spi"; 2495 reg = <0 0x00b90000 0 0x4000>; 2496 2497 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 2498 2499 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2500 clock-names = "se"; 2501 2502 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2503 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2504 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2505 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2506 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2507 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2508 interconnect-names = "qup-core", 2509 "qup-config", 2510 "qup-memory"; 2511 2512 power-domains = <&rpmhpd RPMHPD_CX>; 2513 operating-points-v2 = <&qup_opp_table_100mhz>; 2514 2515 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2516 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2517 dma-names = "tx", 2518 "rx"; 2519 2520 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2521 pinctrl-names = "default"; 2522 2523 #address-cells = <1>; 2524 #size-cells = <0>; 2525 2526 status = "disabled"; 2527 }; 2528 2529 i2c5: i2c@b94000 { 2530 compatible = "qcom,geni-i2c"; 2531 reg = <0 0x00b94000 0 0x4000>; 2532 2533 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2534 2535 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2536 clock-names = "se"; 2537 2538 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2539 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2540 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2541 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2542 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2543 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2544 interconnect-names = "qup-core", 2545 "qup-config", 2546 "qup-memory"; 2547 2548 power-domains = <&rpmhpd RPMHPD_CX>; 2549 required-opps = <&rpmhpd_opp_low_svs>; 2550 2551 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2552 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2553 dma-names = "tx", 2554 "rx"; 2555 2556 pinctrl-0 = <&qup_i2c5_data_clk>; 2557 pinctrl-names = "default"; 2558 2559 #address-cells = <1>; 2560 #size-cells = <0>; 2561 2562 status = "disabled"; 2563 }; 2564 2565 spi5: spi@b94000 { 2566 compatible = "qcom,geni-spi"; 2567 reg = <0 0x00b94000 0 0x4000>; 2568 2569 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 2570 2571 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2572 clock-names = "se"; 2573 2574 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2575 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2576 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2577 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2578 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2579 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2580 interconnect-names = "qup-core", 2581 "qup-config", 2582 "qup-memory"; 2583 2584 power-domains = <&rpmhpd RPMHPD_CX>; 2585 operating-points-v2 = <&qup_opp_table_100mhz>; 2586 2587 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2588 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2589 dma-names = "tx", 2590 "rx"; 2591 2592 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2593 pinctrl-names = "default"; 2594 2595 #address-cells = <1>; 2596 #size-cells = <0>; 2597 2598 status = "disabled"; 2599 }; 2600 2601 i2c6: i2c@b98000 { 2602 compatible = "qcom,geni-i2c"; 2603 reg = <0 0x00b98000 0 0x4000>; 2604 2605 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2606 2607 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2608 clock-names = "se"; 2609 2610 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2611 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2612 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2613 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2614 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2615 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2616 interconnect-names = "qup-core", 2617 "qup-config", 2618 "qup-memory"; 2619 2620 power-domains = <&rpmhpd RPMHPD_CX>; 2621 required-opps = <&rpmhpd_opp_low_svs>; 2622 2623 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2624 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2625 dma-names = "tx", 2626 "rx"; 2627 2628 pinctrl-0 = <&qup_i2c6_data_clk>; 2629 pinctrl-names = "default"; 2630 2631 #address-cells = <1>; 2632 #size-cells = <0>; 2633 2634 status = "disabled"; 2635 }; 2636 2637 spi6: spi@b98000 { 2638 compatible = "qcom,geni-spi"; 2639 reg = <0 0x00b98000 0 0x4000>; 2640 2641 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 2642 2643 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2644 clock-names = "se"; 2645 2646 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2647 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2648 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2649 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2650 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2651 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2652 interconnect-names = "qup-core", 2653 "qup-config", 2654 "qup-memory"; 2655 2656 power-domains = <&rpmhpd RPMHPD_CX>; 2657 operating-points-v2 = <&qup_opp_table_100mhz>; 2658 2659 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2660 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2661 dma-names = "tx", 2662 "rx"; 2663 2664 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2665 pinctrl-names = "default"; 2666 2667 #address-cells = <1>; 2668 #size-cells = <0>; 2669 2670 status = "disabled"; 2671 }; 2672 2673 i2c7: i2c@b9c000 { 2674 compatible = "qcom,geni-i2c"; 2675 reg = <0 0x00b9c000 0 0x4000>; 2676 2677 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2678 2679 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2680 clock-names = "se"; 2681 2682 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2683 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2684 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2685 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2686 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2687 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2688 interconnect-names = "qup-core", 2689 "qup-config", 2690 "qup-memory"; 2691 2692 power-domains = <&rpmhpd RPMHPD_CX>; 2693 required-opps = <&rpmhpd_opp_low_svs>; 2694 2695 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2696 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2697 dma-names = "tx", 2698 "rx"; 2699 2700 pinctrl-0 = <&qup_i2c7_data_clk>; 2701 pinctrl-names = "default"; 2702 2703 #address-cells = <1>; 2704 #size-cells = <0>; 2705 2706 status = "disabled"; 2707 }; 2708 2709 spi7: spi@b9c000 { 2710 compatible = "qcom,geni-spi"; 2711 reg = <0 0x00b9c000 0 0x4000>; 2712 2713 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 2714 2715 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2716 clock-names = "se"; 2717 2718 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2719 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2720 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2721 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2722 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2723 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2724 interconnect-names = "qup-core", 2725 "qup-config", 2726 "qup-memory"; 2727 2728 power-domains = <&rpmhpd RPMHPD_CX>; 2729 operating-points-v2 = <&qup_opp_table_100mhz>; 2730 2731 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2732 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2733 dma-names = "tx", 2734 "rx"; 2735 2736 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2737 pinctrl-names = "default"; 2738 2739 #address-cells = <1>; 2740 #size-cells = <0>; 2741 2742 status = "disabled"; 2743 }; 2744 }; 2745 2746 tsens0: thermal-sensor@c271000 { 2747 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2748 reg = <0 0x0c271000 0 0x1000>, 2749 <0 0x0c222000 0 0x1000>; 2750 2751 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2752 <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; 2753 interrupt-names = "uplow", 2754 "critical"; 2755 2756 #qcom,sensors = <16>; 2757 2758 #thermal-sensor-cells = <1>; 2759 }; 2760 2761 tsens1: thermal-sensor@c272000 { 2762 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2763 reg = <0 0x0c272000 0 0x1000>, 2764 <0 0x0c223000 0 0x1000>; 2765 2766 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2767 <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; 2768 interrupt-names = "uplow", 2769 "critical"; 2770 2771 #qcom,sensors = <16>; 2772 2773 #thermal-sensor-cells = <1>; 2774 }; 2775 2776 tsens2: thermal-sensor@c273000 { 2777 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2778 reg = <0 0x0c273000 0 0x1000>, 2779 <0 0x0c224000 0 0x1000>; 2780 2781 interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>, 2782 <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 2783 interrupt-names = "uplow", 2784 "critical"; 2785 2786 #qcom,sensors = <16>; 2787 2788 #thermal-sensor-cells = <1>; 2789 }; 2790 2791 tsens3: thermal-sensor@c274000 { 2792 compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2"; 2793 reg = <0 0x0c274000 0 0x1000>, 2794 <0 0x0c225000 0 0x1000>; 2795 2796 interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>, 2797 <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>; 2798 interrupt-names = "uplow", 2799 "critical"; 2800 2801 #qcom,sensors = <16>; 2802 2803 #thermal-sensor-cells = <1>; 2804 }; 2805 2806 usb_1_ss0_hsphy: phy@fd3000 { 2807 compatible = "qcom,x1e80100-snps-eusb2-phy", 2808 "qcom,sm8550-snps-eusb2-phy"; 2809 reg = <0 0x00fd3000 0 0x154>; 2810 #phy-cells = <0>; 2811 2812 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2813 clock-names = "ref"; 2814 2815 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2816 2817 status = "disabled"; 2818 }; 2819 2820 usb_1_ss0_qmpphy: phy@fd5000 { 2821 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2822 reg = <0 0x00fd5000 0 0x4000>; 2823 2824 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2825 <&rpmhcc RPMH_CXO_CLK>, 2826 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2827 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2828 clock-names = "aux", 2829 "ref", 2830 "com_aux", 2831 "usb3_pipe"; 2832 2833 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2834 2835 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2836 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>; 2837 reset-names = "phy", 2838 "common"; 2839 2840 #clock-cells = <1>; 2841 #phy-cells = <1>; 2842 2843 orientation-switch; 2844 2845 status = "disabled"; 2846 2847 ports { 2848 #address-cells = <1>; 2849 #size-cells = <0>; 2850 2851 port@0 { 2852 reg = <0>; 2853 2854 usb_1_ss0_qmpphy_out: endpoint { 2855 }; 2856 }; 2857 2858 port@1 { 2859 reg = <1>; 2860 2861 usb_1_ss0_qmpphy_usb_ss_in: endpoint { 2862 remote-endpoint = <&usb_1_ss0_dwc3_ss>; 2863 }; 2864 }; 2865 2866 port@2 { 2867 reg = <2>; 2868 2869 usb_1_ss0_qmpphy_dp_in: endpoint { 2870 remote-endpoint = <&mdss_dp0_out>; 2871 }; 2872 }; 2873 }; 2874 }; 2875 2876 usb_1_ss1_hsphy: phy@fd9000 { 2877 compatible = "qcom,x1e80100-snps-eusb2-phy", 2878 "qcom,sm8550-snps-eusb2-phy"; 2879 reg = <0 0x00fd9000 0 0x154>; 2880 #phy-cells = <0>; 2881 2882 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2883 clock-names = "ref"; 2884 2885 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2886 2887 status = "disabled"; 2888 }; 2889 2890 usb_1_ss1_qmpphy: phy@fda000 { 2891 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2892 reg = <0 0x00fda000 0 0x4000>; 2893 2894 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2895 <&rpmhcc RPMH_CXO_CLK>, 2896 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2897 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2898 clock-names = "aux", 2899 "ref", 2900 "com_aux", 2901 "usb3_pipe"; 2902 2903 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2904 2905 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2906 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>; 2907 reset-names = "phy", 2908 "common"; 2909 2910 #clock-cells = <1>; 2911 #phy-cells = <1>; 2912 2913 orientation-switch; 2914 2915 status = "disabled"; 2916 2917 ports { 2918 #address-cells = <1>; 2919 #size-cells = <0>; 2920 2921 port@0 { 2922 reg = <0>; 2923 2924 usb_1_ss1_qmpphy_out: endpoint { 2925 }; 2926 }; 2927 2928 port@1 { 2929 reg = <1>; 2930 2931 usb_1_ss1_qmpphy_usb_ss_in: endpoint { 2932 remote-endpoint = <&usb_1_ss1_dwc3_ss>; 2933 }; 2934 }; 2935 2936 port@2 { 2937 reg = <2>; 2938 2939 usb_1_ss1_qmpphy_dp_in: endpoint { 2940 remote-endpoint = <&mdss_dp1_out>; 2941 }; 2942 }; 2943 }; 2944 }; 2945 2946 usb_1_ss2_hsphy: phy@fde000 { 2947 compatible = "qcom,x1e80100-snps-eusb2-phy", 2948 "qcom,sm8550-snps-eusb2-phy"; 2949 reg = <0 0x00fde000 0 0x154>; 2950 #phy-cells = <0>; 2951 2952 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2953 clock-names = "ref"; 2954 2955 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 2956 2957 status = "disabled"; 2958 }; 2959 2960 usb_1_ss2_qmpphy: phy@fdf000 { 2961 compatible = "qcom,x1e80100-qmp-usb3-dp-phy"; 2962 reg = <0 0x00fdf000 0 0x4000>; 2963 2964 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 2965 <&rpmhcc RPMH_CXO_CLK>, 2966 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 2967 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 2968 clock-names = "aux", 2969 "ref", 2970 "com_aux", 2971 "usb3_pipe"; 2972 2973 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 2974 2975 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 2976 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>; 2977 reset-names = "phy", 2978 "common"; 2979 2980 #clock-cells = <1>; 2981 #phy-cells = <1>; 2982 2983 orientation-switch; 2984 2985 status = "disabled"; 2986 2987 ports { 2988 #address-cells = <1>; 2989 #size-cells = <0>; 2990 2991 port@0 { 2992 reg = <0>; 2993 2994 usb_1_ss2_qmpphy_out: endpoint { 2995 }; 2996 }; 2997 2998 port@1 { 2999 reg = <1>; 3000 3001 usb_1_ss2_qmpphy_usb_ss_in: endpoint { 3002 remote-endpoint = <&usb_1_ss2_dwc3_ss>; 3003 }; 3004 }; 3005 3006 port@2 { 3007 reg = <2>; 3008 3009 usb_1_ss2_qmpphy_dp_in: endpoint { 3010 remote-endpoint = <&mdss_dp2_out>; 3011 }; 3012 }; 3013 }; 3014 }; 3015 3016 cnoc_main: interconnect@1500000 { 3017 compatible = "qcom,x1e80100-cnoc-main"; 3018 reg = <0 0x01500000 0 0x14400>; 3019 3020 qcom,bcm-voters = <&apps_bcm_voter>; 3021 3022 #interconnect-cells = <2>; 3023 }; 3024 3025 config_noc: interconnect@1600000 { 3026 compatible = "qcom,x1e80100-cnoc-cfg"; 3027 reg = <0 0x01600000 0 0x6600>; 3028 3029 qcom,bcm-voters = <&apps_bcm_voter>; 3030 3031 #interconnect-cells = <2>; 3032 }; 3033 3034 system_noc: interconnect@1680000 { 3035 compatible = "qcom,x1e80100-system-noc"; 3036 reg = <0 0x01680000 0 0x1c080>; 3037 3038 qcom,bcm-voters = <&apps_bcm_voter>; 3039 3040 #interconnect-cells = <2>; 3041 }; 3042 3043 pcie_south_anoc: interconnect@16c0000 { 3044 compatible = "qcom,x1e80100-pcie-south-anoc"; 3045 reg = <0 0x016c0000 0 0xd080>; 3046 3047 qcom,bcm-voters = <&apps_bcm_voter>; 3048 3049 #interconnect-cells = <2>; 3050 }; 3051 3052 pcie_center_anoc: interconnect@16d0000 { 3053 compatible = "qcom,x1e80100-pcie-center-anoc"; 3054 reg = <0 0x016d0000 0 0x7000>; 3055 3056 qcom,bcm-voters = <&apps_bcm_voter>; 3057 3058 #interconnect-cells = <2>; 3059 }; 3060 3061 aggre1_noc: interconnect@16e0000 { 3062 compatible = "qcom,x1e80100-aggre1-noc"; 3063 reg = <0 0x016e0000 0 0x14400>; 3064 3065 qcom,bcm-voters = <&apps_bcm_voter>; 3066 3067 #interconnect-cells = <2>; 3068 }; 3069 3070 aggre2_noc: interconnect@1700000 { 3071 compatible = "qcom,x1e80100-aggre2-noc"; 3072 reg = <0 0x01700000 0 0x1c400>; 3073 3074 qcom,bcm-voters = <&apps_bcm_voter>; 3075 3076 #interconnect-cells = <2>; 3077 }; 3078 3079 pcie_north_anoc: interconnect@1740000 { 3080 compatible = "qcom,x1e80100-pcie-north-anoc"; 3081 reg = <0 0x01740000 0 0x9080>; 3082 3083 qcom,bcm-voters = <&apps_bcm_voter>; 3084 3085 #interconnect-cells = <2>; 3086 }; 3087 3088 usb_center_anoc: interconnect@1750000 { 3089 compatible = "qcom,x1e80100-usb-center-anoc"; 3090 reg = <0 0x01750000 0 0x8800>; 3091 3092 qcom,bcm-voters = <&apps_bcm_voter>; 3093 3094 #interconnect-cells = <2>; 3095 }; 3096 3097 usb_north_anoc: interconnect@1760000 { 3098 compatible = "qcom,x1e80100-usb-north-anoc"; 3099 reg = <0 0x01760000 0 0x7080>; 3100 3101 qcom,bcm-voters = <&apps_bcm_voter>; 3102 3103 #interconnect-cells = <2>; 3104 }; 3105 3106 usb_south_anoc: interconnect@1770000 { 3107 compatible = "qcom,x1e80100-usb-south-anoc"; 3108 reg = <0 0x01770000 0 0xf080>; 3109 3110 qcom,bcm-voters = <&apps_bcm_voter>; 3111 3112 #interconnect-cells = <2>; 3113 }; 3114 3115 mmss_noc: interconnect@1780000 { 3116 compatible = "qcom,x1e80100-mmss-noc"; 3117 reg = <0 0x01780000 0 0x5B800>; 3118 3119 qcom,bcm-voters = <&apps_bcm_voter>; 3120 3121 #interconnect-cells = <2>; 3122 }; 3123 3124 pcie3: pcie@1bd0000 { 3125 device_type = "pci"; 3126 compatible = "qcom,pcie-x1e80100"; 3127 reg = <0x0 0x01bd0000 0x0 0x3000>, 3128 <0x0 0x78000000 0x0 0xf1d>, 3129 <0x0 0x78000f40 0x0 0xa8>, 3130 <0x0 0x78001000 0x0 0x1000>, 3131 <0x0 0x78100000 0x0 0x100000>, 3132 <0x0 0x01bd3000 0x0 0x1000>; 3133 reg-names = "parf", 3134 "dbi", 3135 "elbi", 3136 "atu", 3137 "config", 3138 "mhi"; 3139 #address-cells = <3>; 3140 #size-cells = <2>; 3141 ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>, 3142 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>, 3143 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3144 bus-range = <0x00 0xff>; 3145 3146 dma-coherent; 3147 3148 linux,pci-domain = <3>; 3149 num-lanes = <8>; 3150 3151 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 3160 interrupt-names = "msi0", 3161 "msi1", 3162 "msi2", 3163 "msi3", 3164 "msi4", 3165 "msi5", 3166 "msi6", 3167 "msi7", 3168 "global"; 3169 3170 #interrupt-cells = <1>; 3171 interrupt-map-mask = <0 0 0 0x7>; 3172 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 3173 <0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 3174 <0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 3175 <0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3176 3177 clocks = <&gcc GCC_PCIE_3_AUX_CLK>, 3178 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3179 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 3180 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 3181 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 3182 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3183 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3184 clock-names = "aux", 3185 "cfg", 3186 "bus_master", 3187 "bus_slave", 3188 "slave_q2a", 3189 "noc_aggr", 3190 "cnoc_sf_axi"; 3191 3192 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 3193 assigned-clock-rates = <19200000>; 3194 3195 interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS 3196 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3197 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3198 &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>; 3199 interconnect-names = "pcie-mem", 3200 "cpu-pcie"; 3201 3202 resets = <&gcc GCC_PCIE_3_BCR>, 3203 <&gcc GCC_PCIE_3_LINK_DOWN_BCR>; 3204 reset-names = "pci", 3205 "link_down"; 3206 3207 power-domains = <&gcc GCC_PCIE_3_GDSC>; 3208 3209 phys = <&pcie3_phy>; 3210 phy-names = "pciephy"; 3211 3212 operating-points-v2 = <&pcie3_opp_table>; 3213 3214 status = "disabled"; 3215 3216 pcie3_opp_table: opp-table { 3217 compatible = "operating-points-v2"; 3218 3219 /* GEN 1 x1 */ 3220 opp-2500000 { 3221 opp-hz = /bits/ 64 <2500000>; 3222 required-opps = <&rpmhpd_opp_low_svs>; 3223 opp-peak-kBps = <250000 1>; 3224 }; 3225 3226 /* GEN 1 x2 and GEN 2 x1 */ 3227 opp-5000000 { 3228 opp-hz = /bits/ 64 <5000000>; 3229 required-opps = <&rpmhpd_opp_low_svs>; 3230 opp-peak-kBps = <500000 1>; 3231 }; 3232 3233 /* GEN 1 x4 and GEN 2 x2 */ 3234 opp-10000000 { 3235 opp-hz = /bits/ 64 <10000000>; 3236 required-opps = <&rpmhpd_opp_low_svs>; 3237 opp-peak-kBps = <1000000 1>; 3238 }; 3239 3240 /* GEN 1 x8 and GEN 2 x4 */ 3241 opp-20000000 { 3242 opp-hz = /bits/ 64 <20000000>; 3243 required-opps = <&rpmhpd_opp_low_svs>; 3244 opp-peak-kBps = <2000000 1>; 3245 }; 3246 3247 /* GEN 2 x8 */ 3248 opp-40000000 { 3249 opp-hz = /bits/ 64 <40000000>; 3250 required-opps = <&rpmhpd_opp_low_svs>; 3251 opp-peak-kBps = <4000000 1>; 3252 }; 3253 3254 /* GEN 3 x1 */ 3255 opp-8000000 { 3256 opp-hz = /bits/ 64 <8000000>; 3257 required-opps = <&rpmhpd_opp_svs>; 3258 opp-peak-kBps = <984500 1>; 3259 }; 3260 3261 /* GEN 3 x2 and GEN 4 x1 */ 3262 opp-16000000 { 3263 opp-hz = /bits/ 64 <16000000>; 3264 required-opps = <&rpmhpd_opp_svs>; 3265 opp-peak-kBps = <1969000 1>; 3266 }; 3267 3268 /* GEN 3 x4 and GEN 4 x2 */ 3269 opp-32000000 { 3270 opp-hz = /bits/ 64 <32000000>; 3271 required-opps = <&rpmhpd_opp_svs>; 3272 opp-peak-kBps = <3938000 1>; 3273 }; 3274 3275 /* GEN 3 x8 and GEN 4 x4 */ 3276 opp-64000000 { 3277 opp-hz = /bits/ 64 <64000000>; 3278 required-opps = <&rpmhpd_opp_svs>; 3279 opp-peak-kBps = <7876000 1>; 3280 }; 3281 3282 /* GEN 4 x8 */ 3283 opp-128000000 { 3284 opp-hz = /bits/ 64 <128000000>; 3285 required-opps = <&rpmhpd_opp_svs>; 3286 opp-peak-kBps = <15753000 1>; 3287 }; 3288 }; 3289 }; 3290 3291 pcie3_phy: phy@1be0000 { 3292 compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy"; 3293 reg = <0 0x01be0000 0 0x10000>; 3294 3295 clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, 3296 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 3297 <&tcsr TCSR_PCIE_8L_CLKREF_EN>, 3298 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, 3299 <&gcc GCC_PCIE_3_PIPE_CLK>, 3300 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; 3301 clock-names = "aux", 3302 "cfg_ahb", 3303 "ref", 3304 "rchng", 3305 "pipe", 3306 "pipediv2"; 3307 3308 resets = <&gcc GCC_PCIE_3_PHY_BCR>, 3309 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; 3310 reset-names = "phy", 3311 "phy_nocsr"; 3312 3313 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; 3314 assigned-clock-rates = <100000000>; 3315 3316 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>; 3317 3318 #clock-cells = <0>; 3319 clock-output-names = "pcie3_pipe_clk"; 3320 3321 #phy-cells = <0>; 3322 3323 status = "disabled"; 3324 }; 3325 3326 pcie6a: pci@1bf8000 { 3327 device_type = "pci"; 3328 compatible = "qcom,pcie-x1e80100"; 3329 reg = <0 0x01bf8000 0 0x3000>, 3330 <0 0x70000000 0 0xf20>, 3331 <0 0x70000f40 0 0xa8>, 3332 <0 0x70001000 0 0x1000>, 3333 <0 0x70100000 0 0x100000>, 3334 <0 0x01bfb000 0 0x1000>; 3335 reg-names = "parf", 3336 "dbi", 3337 "elbi", 3338 "atu", 3339 "config", 3340 "mhi"; 3341 #address-cells = <3>; 3342 #size-cells = <2>; 3343 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, 3344 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 3345 bus-range = <0x00 0xff>; 3346 3347 dma-coherent; 3348 3349 linux,pci-domain = <6>; 3350 num-lanes = <4>; 3351 3352 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3353 3354 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; 3362 interrupt-names = "msi0", 3363 "msi1", 3364 "msi2", 3365 "msi3", 3366 "msi4", 3367 "msi5", 3368 "msi6", 3369 "msi7"; 3370 3371 #interrupt-cells = <1>; 3372 interrupt-map-mask = <0 0 0 0x7>; 3373 interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>, 3374 <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>, 3375 <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>, 3376 <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>; 3377 3378 clocks = <&gcc GCC_PCIE_6A_AUX_CLK>, 3379 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3380 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>, 3381 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>, 3382 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>, 3383 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>, 3384 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>; 3385 clock-names = "aux", 3386 "cfg", 3387 "bus_master", 3388 "bus_slave", 3389 "slave_q2a", 3390 "noc_aggr", 3391 "cnoc_sf_axi"; 3392 3393 assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>; 3394 assigned-clock-rates = <19200000>; 3395 3396 interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS 3397 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3398 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3399 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>; 3400 interconnect-names = "pcie-mem", 3401 "cpu-pcie"; 3402 3403 resets = <&gcc GCC_PCIE_6A_BCR>, 3404 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>; 3405 reset-names = "pci", 3406 "link_down"; 3407 3408 power-domains = <&gcc GCC_PCIE_6A_GDSC>; 3409 required-opps = <&rpmhpd_opp_nom>; 3410 3411 phys = <&pcie6a_phy>; 3412 phy-names = "pciephy"; 3413 3414 status = "disabled"; 3415 }; 3416 3417 pcie6a_phy: phy@1bfc000 { 3418 compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy"; 3419 reg = <0 0x01bfc000 0 0x2000>, 3420 <0 0x01bfe000 0 0x2000>; 3421 3422 clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>, 3423 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>, 3424 <&tcsr TCSR_PCIE_4L_CLKREF_EN>, 3425 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>, 3426 <&gcc GCC_PCIE_6A_PIPE_CLK>, 3427 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>; 3428 clock-names = "aux", 3429 "cfg_ahb", 3430 "ref", 3431 "rchng", 3432 "pipe", 3433 "pipediv2"; 3434 3435 resets = <&gcc GCC_PCIE_6A_PHY_BCR>, 3436 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>; 3437 reset-names = "phy", 3438 "phy_nocsr"; 3439 3440 assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>; 3441 assigned-clock-rates = <100000000>; 3442 3443 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3444 3445 qcom,4ln-config-sel = <&tcsr 0x1a000 0>; 3446 3447 #clock-cells = <0>; 3448 clock-output-names = "pcie6a_pipe_clk"; 3449 3450 #phy-cells = <0>; 3451 3452 status = "disabled"; 3453 }; 3454 3455 pcie5: pci@1c00000 { 3456 device_type = "pci"; 3457 compatible = "qcom,pcie-x1e80100"; 3458 reg = <0 0x01c00000 0 0x3000>, 3459 <0 0x7e000000 0 0xf1d>, 3460 <0 0x7e000f40 0 0xa8>, 3461 <0 0x7e001000 0 0x1000>, 3462 <0 0x7e100000 0 0x100000>, 3463 <0 0x01c03000 0 0x1000>; 3464 reg-names = "parf", 3465 "dbi", 3466 "elbi", 3467 "atu", 3468 "config", 3469 "mhi"; 3470 #address-cells = <3>; 3471 #size-cells = <2>; 3472 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3473 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>; 3474 bus-range = <0x00 0xff>; 3475 3476 dma-coherent; 3477 3478 linux,pci-domain = <5>; 3479 num-lanes = <2>; 3480 3481 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 3489 interrupt-names = "msi0", 3490 "msi1", 3491 "msi2", 3492 "msi3", 3493 "msi4", 3494 "msi5", 3495 "msi6", 3496 "msi7"; 3497 3498 #interrupt-cells = <1>; 3499 interrupt-map-mask = <0 0 0 0x7>; 3500 interrupt-map = <0 0 0 1 &intc 0 0 0 70 IRQ_TYPE_LEVEL_HIGH>, 3501 <0 0 0 2 &intc 0 0 0 71 IRQ_TYPE_LEVEL_HIGH>, 3502 <0 0 0 3 &intc 0 0 0 72 IRQ_TYPE_LEVEL_HIGH>, 3503 <0 0 0 4 &intc 0 0 0 73 IRQ_TYPE_LEVEL_HIGH>; 3504 3505 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3506 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3507 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3508 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3509 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3510 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3511 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3512 clock-names = "aux", 3513 "cfg", 3514 "bus_master", 3515 "bus_slave", 3516 "slave_q2a", 3517 "noc_aggr", 3518 "cnoc_sf_axi"; 3519 3520 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3521 assigned-clock-rates = <19200000>; 3522 3523 interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3524 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3525 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3526 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; 3527 interconnect-names = "pcie-mem", 3528 "cpu-pcie"; 3529 3530 resets = <&gcc GCC_PCIE_5_BCR>, 3531 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3532 reset-names = "pci", 3533 "link_down"; 3534 3535 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3536 required-opps = <&rpmhpd_opp_nom>; 3537 3538 phys = <&pcie5_phy>; 3539 phy-names = "pciephy"; 3540 3541 status = "disabled"; 3542 }; 3543 3544 pcie5_phy: phy@1c06000 { 3545 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3546 reg = <0 0x01c06000 0 0x2000>; 3547 3548 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3549 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3550 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>, 3551 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3552 <&gcc GCC_PCIE_5_PIPE_CLK>, 3553 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>; 3554 clock-names = "aux", 3555 "cfg_ahb", 3556 "ref", 3557 "rchng", 3558 "pipe", 3559 "pipediv2"; 3560 3561 resets = <&gcc GCC_PCIE_5_PHY_BCR>; 3562 reset-names = "phy"; 3563 3564 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3565 assigned-clock-rates = <100000000>; 3566 3567 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3568 3569 #clock-cells = <0>; 3570 clock-output-names = "pcie5_pipe_clk"; 3571 3572 #phy-cells = <0>; 3573 3574 status = "disabled"; 3575 }; 3576 3577 pcie4: pci@1c08000 { 3578 device_type = "pci"; 3579 compatible = "qcom,pcie-x1e80100"; 3580 reg = <0 0x01c08000 0 0x3000>, 3581 <0 0x7c000000 0 0xf1d>, 3582 <0 0x7c000f40 0 0xa8>, 3583 <0 0x7c001000 0 0x1000>, 3584 <0 0x7c100000 0 0x100000>, 3585 <0 0x01c0b000 0 0x1000>; 3586 reg-names = "parf", 3587 "dbi", 3588 "elbi", 3589 "atu", 3590 "config", 3591 "mhi"; 3592 #address-cells = <3>; 3593 #size-cells = <2>; 3594 ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>, 3595 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>; 3596 bus-range = <0x00 0xff>; 3597 3598 dma-coherent; 3599 3600 linux,pci-domain = <4>; 3601 num-lanes = <2>; 3602 3603 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 3604 3605 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 3613 interrupt-names = "msi0", 3614 "msi1", 3615 "msi2", 3616 "msi3", 3617 "msi4", 3618 "msi5", 3619 "msi6", 3620 "msi7"; 3621 3622 #interrupt-cells = <1>; 3623 interrupt-map-mask = <0 0 0 0x7>; 3624 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 3625 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 3626 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 3627 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 3628 3629 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3630 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3631 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 3632 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 3633 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 3634 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 3635 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 3636 clock-names = "aux", 3637 "cfg", 3638 "bus_master", 3639 "bus_slave", 3640 "slave_q2a", 3641 "noc_aggr", 3642 "cnoc_sf_axi"; 3643 3644 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 3645 assigned-clock-rates = <19200000>; 3646 3647 interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 3648 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3649 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3650 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 3651 interconnect-names = "pcie-mem", 3652 "cpu-pcie"; 3653 3654 resets = <&gcc GCC_PCIE_4_BCR>, 3655 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 3656 reset-names = "pci", 3657 "link_down"; 3658 3659 power-domains = <&gcc GCC_PCIE_4_GDSC>; 3660 required-opps = <&rpmhpd_opp_nom>; 3661 3662 phys = <&pcie4_phy>; 3663 phy-names = "pciephy"; 3664 3665 status = "disabled"; 3666 3667 pcie4_port0: pcie@0 { 3668 device_type = "pci"; 3669 reg = <0x0 0x0 0x0 0x0 0x0>; 3670 bus-range = <0x01 0xff>; 3671 3672 #address-cells = <3>; 3673 #size-cells = <2>; 3674 ranges; 3675 }; 3676 }; 3677 3678 pcie4_phy: phy@1c0e000 { 3679 compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy"; 3680 reg = <0 0x01c0e000 0 0x2000>; 3681 3682 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 3683 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3684 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>, 3685 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 3686 <&gcc GCC_PCIE_4_PIPE_CLK>, 3687 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 3688 clock-names = "aux", 3689 "cfg_ahb", 3690 "ref", 3691 "rchng", 3692 "pipe", 3693 "pipediv2"; 3694 3695 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 3696 reset-names = "phy"; 3697 3698 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 3699 assigned-clock-rates = <100000000>; 3700 3701 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 3702 3703 #clock-cells = <0>; 3704 clock-output-names = "pcie4_pipe_clk"; 3705 3706 #phy-cells = <0>; 3707 3708 status = "disabled"; 3709 }; 3710 3711 tcsr_mutex: hwlock@1f40000 { 3712 compatible = "qcom,tcsr-mutex"; 3713 reg = <0 0x01f40000 0 0x20000>; 3714 #hwlock-cells = <1>; 3715 }; 3716 3717 tcsr: clock-controller@1fc0000 { 3718 compatible = "qcom,x1e80100-tcsr", "syscon"; 3719 reg = <0 0x01fc0000 0 0x30000>; 3720 clocks = <&rpmhcc RPMH_CXO_CLK>; 3721 #clock-cells = <1>; 3722 #reset-cells = <1>; 3723 }; 3724 3725 gpu: gpu@3d00000 { 3726 compatible = "qcom,adreno-43050c01", "qcom,adreno"; 3727 reg = <0x0 0x03d00000 0x0 0x40000>, 3728 <0x0 0x03d9e000 0x0 0x1000>, 3729 <0x0 0x03d61000 0x0 0x800>; 3730 3731 reg-names = "kgsl_3d0_reg_memory", 3732 "cx_mem", 3733 "cx_dbgc"; 3734 3735 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3736 3737 iommus = <&adreno_smmu 0 0x0>, 3738 <&adreno_smmu 1 0x0>; 3739 3740 operating-points-v2 = <&gpu_opp_table>; 3741 3742 qcom,gmu = <&gmu>; 3743 #cooling-cells = <2>; 3744 3745 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3746 interconnect-names = "gfx-mem"; 3747 3748 status = "disabled"; 3749 3750 zap-shader { 3751 memory-region = <&gpu_microcode_mem>; 3752 }; 3753 3754 gpu_opp_table: opp-table { 3755 compatible = "operating-points-v2"; 3756 3757 opp-1100000000 { 3758 opp-hz = /bits/ 64 <1100000000>; 3759 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3760 opp-peak-kBps = <16500000>; 3761 }; 3762 3763 opp-1000000000 { 3764 opp-hz = /bits/ 64 <1000000000>; 3765 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3766 opp-peak-kBps = <14398438>; 3767 }; 3768 3769 opp-925000000 { 3770 opp-hz = /bits/ 64 <925000000>; 3771 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3772 opp-peak-kBps = <14398438>; 3773 }; 3774 3775 opp-800000000 { 3776 opp-hz = /bits/ 64 <800000000>; 3777 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3778 opp-peak-kBps = <12449219>; 3779 }; 3780 3781 opp-744000000 { 3782 opp-hz = /bits/ 64 <744000000>; 3783 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3784 opp-peak-kBps = <10687500>; 3785 }; 3786 3787 opp-687000000 { 3788 opp-hz = /bits/ 64 <687000000>; 3789 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3790 opp-peak-kBps = <8171875>; 3791 }; 3792 3793 opp-550000000 { 3794 opp-hz = /bits/ 64 <550000000>; 3795 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3796 opp-peak-kBps = <6074219>; 3797 }; 3798 3799 opp-390000000 { 3800 opp-hz = /bits/ 64 <390000000>; 3801 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3802 opp-peak-kBps = <3000000>; 3803 }; 3804 3805 opp-300000000 { 3806 opp-hz = /bits/ 64 <300000000>; 3807 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3808 opp-peak-kBps = <2136719>; 3809 }; 3810 }; 3811 }; 3812 3813 gmu: gmu@3d6a000 { 3814 compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu"; 3815 reg = <0x0 0x03d6a000 0x0 0x35000>, 3816 <0x0 0x03d50000 0x0 0x10000>, 3817 <0x0 0x0b280000 0x0 0x10000>; 3818 reg-names = "gmu", "rscc", "gmu_pdc"; 3819 3820 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3821 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3822 interrupt-names = "hfi", "gmu"; 3823 3824 clocks = <&gpucc GPU_CC_AHB_CLK>, 3825 <&gpucc GPU_CC_CX_GMU_CLK>, 3826 <&gpucc GPU_CC_CXO_CLK>, 3827 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3828 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3829 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3830 <&gpucc GPU_CC_DEMET_CLK>; 3831 clock-names = "ahb", 3832 "gmu", 3833 "cxo", 3834 "axi", 3835 "memnoc", 3836 "hub", 3837 "demet"; 3838 3839 power-domains = <&gpucc GPU_CX_GDSC>, 3840 <&gpucc GPU_GX_GDSC>; 3841 power-domain-names = "cx", 3842 "gx"; 3843 3844 iommus = <&adreno_smmu 5 0x0>; 3845 3846 qcom,qmp = <&aoss_qmp>; 3847 3848 operating-points-v2 = <&gmu_opp_table>; 3849 3850 gmu_opp_table: opp-table { 3851 compatible = "operating-points-v2"; 3852 3853 opp-550000000 { 3854 opp-hz = /bits/ 64 <550000000>; 3855 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3856 }; 3857 3858 opp-220000000 { 3859 opp-hz = /bits/ 64 <220000000>; 3860 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3861 }; 3862 }; 3863 }; 3864 3865 gpucc: clock-controller@3d90000 { 3866 compatible = "qcom,x1e80100-gpucc"; 3867 reg = <0 0x03d90000 0 0xa000>; 3868 clocks = <&bi_tcxo_div2>, 3869 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, 3870 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; 3871 #clock-cells = <1>; 3872 #reset-cells = <1>; 3873 #power-domain-cells = <1>; 3874 }; 3875 3876 adreno_smmu: iommu@3da0000 { 3877 compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu", 3878 "qcom,smmu-500", "arm,mmu-500"; 3879 reg = <0x0 0x03da0000 0x0 0x40000>; 3880 #iommu-cells = <2>; 3881 #global-interrupts = <1>; 3882 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 3883 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3884 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3886 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3887 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3888 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3889 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3890 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3891 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3892 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 3893 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 3894 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3895 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 3896 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 3897 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 3898 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 3899 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 3900 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, 3901 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 3902 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 3903 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 3904 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 3905 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 3907 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 3908 clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3909 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3910 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3911 <&gpucc GPU_CC_AHB_CLK>; 3912 clock-names = "hlos", 3913 "bus", 3914 "iface", 3915 "ahb"; 3916 power-domains = <&gpucc GPU_CX_GDSC>; 3917 dma-coherent; 3918 }; 3919 3920 gem_noc: interconnect@26400000 { 3921 compatible = "qcom,x1e80100-gem-noc"; 3922 reg = <0 0x26400000 0 0x311200>; 3923 3924 qcom,bcm-voters = <&apps_bcm_voter>; 3925 3926 #interconnect-cells = <2>; 3927 }; 3928 3929 nsp_noc: interconnect@320c0000 { 3930 compatible = "qcom,x1e80100-nsp-noc"; 3931 reg = <0 0x320C0000 0 0xe080>; 3932 3933 qcom,bcm-voters = <&apps_bcm_voter>; 3934 3935 #interconnect-cells = <2>; 3936 }; 3937 3938 remoteproc_adsp: remoteproc@6800000 { 3939 compatible = "qcom,x1e80100-adsp-pas"; 3940 reg = <0x0 0x06800000 0x0 0x10000>; 3941 3942 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3943 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3944 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3945 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3946 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3947 interrupt-names = "wdog", 3948 "fatal", 3949 "ready", 3950 "handover", 3951 "stop-ack"; 3952 3953 clocks = <&rpmhcc RPMH_CXO_CLK>; 3954 clock-names = "xo"; 3955 3956 power-domains = <&rpmhpd RPMHPD_LCX>, 3957 <&rpmhpd RPMHPD_LMX>; 3958 power-domain-names = "lcx", 3959 "lmx"; 3960 3961 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 3962 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3963 3964 memory-region = <&adspslpi_mem>, 3965 <&q6_adsp_dtb_mem>; 3966 3967 qcom,qmp = <&aoss_qmp>; 3968 3969 qcom,smem-states = <&smp2p_adsp_out 0>; 3970 qcom,smem-state-names = "stop"; 3971 3972 status = "disabled"; 3973 3974 glink-edge { 3975 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3976 IPCC_MPROC_SIGNAL_GLINK_QMP 3977 IRQ_TYPE_EDGE_RISING>; 3978 mboxes = <&ipcc IPCC_CLIENT_LPASS 3979 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3980 3981 label = "lpass"; 3982 qcom,remote-pid = <2>; 3983 3984 fastrpc { 3985 compatible = "qcom,fastrpc"; 3986 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3987 label = "adsp"; 3988 qcom,non-secure-domain; 3989 #address-cells = <1>; 3990 #size-cells = <0>; 3991 3992 compute-cb@3 { 3993 compatible = "qcom,fastrpc-compute-cb"; 3994 reg = <3>; 3995 iommus = <&apps_smmu 0x1003 0x80>, 3996 <&apps_smmu 0x1063 0x0>; 3997 dma-coherent; 3998 }; 3999 4000 compute-cb@4 { 4001 compatible = "qcom,fastrpc-compute-cb"; 4002 reg = <4>; 4003 iommus = <&apps_smmu 0x1004 0x80>, 4004 <&apps_smmu 0x1064 0x0>; 4005 dma-coherent; 4006 }; 4007 4008 compute-cb@5 { 4009 compatible = "qcom,fastrpc-compute-cb"; 4010 reg = <5>; 4011 iommus = <&apps_smmu 0x1005 0x80>, 4012 <&apps_smmu 0x1065 0x0>; 4013 dma-coherent; 4014 }; 4015 4016 compute-cb@6 { 4017 compatible = "qcom,fastrpc-compute-cb"; 4018 reg = <6>; 4019 iommus = <&apps_smmu 0x1006 0x80>, 4020 <&apps_smmu 0x1066 0x0>; 4021 dma-coherent; 4022 }; 4023 4024 compute-cb@7 { 4025 compatible = "qcom,fastrpc-compute-cb"; 4026 reg = <7>; 4027 iommus = <&apps_smmu 0x1007 0x80>, 4028 <&apps_smmu 0x1067 0x0>; 4029 dma-coherent; 4030 }; 4031 }; 4032 4033 gpr { 4034 compatible = "qcom,gpr"; 4035 qcom,glink-channels = "adsp_apps"; 4036 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4037 qcom,intents = <512 20>; 4038 #address-cells = <1>; 4039 #size-cells = <0>; 4040 4041 q6apm: service@1 { 4042 compatible = "qcom,q6apm"; 4043 reg = <GPR_APM_MODULE_IID>; 4044 #sound-dai-cells = <0>; 4045 qcom,protection-domain = "avs/audio", 4046 "msm/adsp/audio_pd"; 4047 4048 q6apmbedai: bedais { 4049 compatible = "qcom,q6apm-lpass-dais"; 4050 #sound-dai-cells = <1>; 4051 }; 4052 4053 q6apmdai: dais { 4054 compatible = "qcom,q6apm-dais"; 4055 iommus = <&apps_smmu 0x1001 0x80>, 4056 <&apps_smmu 0x1061 0x0>; 4057 }; 4058 }; 4059 4060 q6prm: service@2 { 4061 compatible = "qcom,q6prm"; 4062 reg = <GPR_PRM_MODULE_IID>; 4063 qcom,protection-domain = "avs/audio", 4064 "msm/adsp/audio_pd"; 4065 4066 q6prmcc: clock-controller { 4067 compatible = "qcom,q6prm-lpass-clocks"; 4068 #clock-cells = <2>; 4069 }; 4070 }; 4071 }; 4072 }; 4073 }; 4074 4075 lpass_wsa2macro: codec@6aa0000 { 4076 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4077 reg = <0 0x06aa0000 0 0x1000>; 4078 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4079 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4080 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4081 <&lpass_vamacro>; 4082 clock-names = "mclk", 4083 "macro", 4084 "dcodec", 4085 "fsgen"; 4086 4087 #clock-cells = <0>; 4088 clock-output-names = "wsa2-mclk"; 4089 #sound-dai-cells = <1>; 4090 sound-name-prefix = "WSA2"; 4091 }; 4092 4093 swr3: soundwire@6ab0000 { 4094 compatible = "qcom,soundwire-v2.0.0"; 4095 reg = <0 0x06ab0000 0 0x10000>; 4096 clocks = <&lpass_wsa2macro>; 4097 clock-names = "iface"; 4098 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 4099 label = "WSA2"; 4100 4101 pinctrl-0 = <&wsa2_swr_active>; 4102 pinctrl-names = "default"; 4103 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>; 4104 reset-names = "swr_audio_cgcr"; 4105 4106 qcom,din-ports = <4>; 4107 qcom,dout-ports = <9>; 4108 4109 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4110 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4111 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4112 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4113 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4114 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4115 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4116 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4117 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4118 4119 #address-cells = <2>; 4120 #size-cells = <0>; 4121 #sound-dai-cells = <1>; 4122 status = "disabled"; 4123 }; 4124 4125 lpass_rxmacro: codec@6ac0000 { 4126 compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 4127 reg = <0 0x06ac0000 0 0x1000>; 4128 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4129 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4130 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4131 <&lpass_vamacro>; 4132 clock-names = "mclk", 4133 "macro", 4134 "dcodec", 4135 "fsgen"; 4136 4137 #clock-cells = <0>; 4138 clock-output-names = "mclk"; 4139 #sound-dai-cells = <1>; 4140 }; 4141 4142 swr1: soundwire@6ad0000 { 4143 compatible = "qcom,soundwire-v2.0.0"; 4144 reg = <0 0x06ad0000 0 0x10000>; 4145 clocks = <&lpass_rxmacro>; 4146 clock-names = "iface"; 4147 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 4148 label = "RX"; 4149 4150 pinctrl-0 = <&rx_swr_active>; 4151 pinctrl-names = "default"; 4152 4153 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 4154 reset-names = "swr_audio_cgcr"; 4155 qcom,din-ports = <1>; 4156 qcom,dout-ports = <11>; 4157 4158 qcom,ports-sinterval = /bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4159 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4160 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4161 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4162 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4163 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4164 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4165 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4166 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4167 4168 #address-cells = <2>; 4169 #size-cells = <0>; 4170 #sound-dai-cells = <1>; 4171 status = "disabled"; 4172 }; 4173 4174 lpass_txmacro: codec@6ae0000 { 4175 compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 4176 reg = <0 0x06ae0000 0 0x1000>; 4177 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4178 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4179 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4180 <&lpass_vamacro>; 4181 clock-names = "mclk", 4182 "macro", 4183 "dcodec", 4184 "fsgen"; 4185 4186 #clock-cells = <0>; 4187 clock-output-names = "mclk"; 4188 #sound-dai-cells = <1>; 4189 }; 4190 4191 lpass_wsamacro: codec@6b00000 { 4192 compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4193 reg = <0 0x06b00000 0 0x1000>; 4194 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4195 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4196 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4197 <&lpass_vamacro>; 4198 clock-names = "mclk", 4199 "macro", 4200 "dcodec", 4201 "fsgen"; 4202 4203 #clock-cells = <0>; 4204 clock-output-names = "mclk"; 4205 #sound-dai-cells = <1>; 4206 sound-name-prefix = "WSA"; 4207 }; 4208 4209 swr0: soundwire@6b10000 { 4210 compatible = "qcom,soundwire-v2.0.0"; 4211 reg = <0 0x06b10000 0 0x10000>; 4212 clocks = <&lpass_wsamacro>; 4213 clock-names = "iface"; 4214 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 4215 label = "WSA"; 4216 4217 pinctrl-0 = <&wsa_swr_active>; 4218 pinctrl-names = "default"; 4219 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 4220 reset-names = "swr_audio_cgcr"; 4221 4222 qcom,din-ports = <4>; 4223 qcom,dout-ports = <9>; 4224 4225 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 4226 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 4227 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4228 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4229 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 4230 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 4231 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 4232 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4233 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4234 4235 #address-cells = <2>; 4236 #size-cells = <0>; 4237 #sound-dai-cells = <1>; 4238 status = "disabled"; 4239 }; 4240 4241 lpass_audiocc: clock-controller@6b6c000 { 4242 compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc"; 4243 reg = <0 0x06b6c000 0 0x1000>; 4244 #clock-cells = <1>; 4245 #reset-cells = <1>; 4246 }; 4247 4248 swr2: soundwire@6d30000 { 4249 compatible = "qcom,soundwire-v2.0.0"; 4250 reg = <0 0x06d30000 0 0x10000>; 4251 clocks = <&lpass_txmacro>; 4252 clock-names = "iface"; 4253 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 4254 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 4255 interrupt-names = "core", "wakeup"; 4256 label = "TX"; 4257 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 4258 reset-names = "swr_audio_cgcr"; 4259 4260 pinctrl-0 = <&tx_swr_active>; 4261 pinctrl-names = "default"; 4262 4263 qcom,din-ports = <4>; 4264 qcom,dout-ports = <1>; 4265 4266 qcom,ports-sinterval-low = /bits/ 8 <0x00 0x01 0x03 0x03 0x00>; 4267 qcom,ports-offset1 = /bits/ 8 <0x00 0x01 0x02 0x00 0x00>; 4268 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00 0xff>; 4269 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4270 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4271 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4272 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4273 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 4274 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x00 0x01 0xff>; 4275 4276 #address-cells = <2>; 4277 #size-cells = <0>; 4278 #sound-dai-cells = <1>; 4279 status = "disabled"; 4280 }; 4281 4282 lpass_vamacro: codec@6d44000 { 4283 compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4284 reg = <0 0x06d44000 0 0x1000>; 4285 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4286 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4287 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4288 clock-names = "mclk", 4289 "macro", 4290 "dcodec"; 4291 4292 #clock-cells = <0>; 4293 clock-output-names = "fsgen"; 4294 #sound-dai-cells = <1>; 4295 }; 4296 4297 lpass_tlmm: pinctrl@6e80000 { 4298 compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl"; 4299 reg = <0 0x06e80000 0 0x20000>, 4300 <0 0x07250000 0 0x10000>; 4301 4302 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4303 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4304 clock-names = "core", "audio"; 4305 4306 gpio-controller; 4307 #gpio-cells = <2>; 4308 gpio-ranges = <&lpass_tlmm 0 0 23>; 4309 4310 tx_swr_active: tx-swr-active-state { 4311 clk-pins { 4312 pins = "gpio0"; 4313 function = "swr_tx_clk"; 4314 drive-strength = <2>; 4315 slew-rate = <1>; 4316 bias-disable; 4317 }; 4318 4319 data-pins { 4320 pins = "gpio1", "gpio2"; 4321 function = "swr_tx_data"; 4322 drive-strength = <2>; 4323 slew-rate = <1>; 4324 bias-bus-hold; 4325 }; 4326 }; 4327 4328 rx_swr_active: rx-swr-active-state { 4329 clk-pins { 4330 pins = "gpio3"; 4331 function = "swr_rx_clk"; 4332 drive-strength = <2>; 4333 slew-rate = <1>; 4334 bias-disable; 4335 }; 4336 4337 data-pins { 4338 pins = "gpio4", "gpio5"; 4339 function = "swr_rx_data"; 4340 drive-strength = <2>; 4341 slew-rate = <1>; 4342 bias-bus-hold; 4343 }; 4344 }; 4345 4346 dmic01_default: dmic01-default-state { 4347 clk-pins { 4348 pins = "gpio6"; 4349 function = "dmic1_clk"; 4350 drive-strength = <8>; 4351 output-high; 4352 }; 4353 4354 data-pins { 4355 pins = "gpio7"; 4356 function = "dmic1_data"; 4357 drive-strength = <8>; 4358 input-enable; 4359 }; 4360 }; 4361 4362 dmic23_default: dmic23-default-state { 4363 clk-pins { 4364 pins = "gpio8"; 4365 function = "dmic2_clk"; 4366 drive-strength = <8>; 4367 output-high; 4368 }; 4369 4370 data-pins { 4371 pins = "gpio9"; 4372 function = "dmic2_data"; 4373 drive-strength = <8>; 4374 input-enable; 4375 }; 4376 }; 4377 4378 wsa_swr_active: wsa-swr-active-state { 4379 clk-pins { 4380 pins = "gpio10"; 4381 function = "wsa_swr_clk"; 4382 drive-strength = <2>; 4383 slew-rate = <1>; 4384 bias-disable; 4385 }; 4386 4387 data-pins { 4388 pins = "gpio11"; 4389 function = "wsa_swr_data"; 4390 drive-strength = <2>; 4391 slew-rate = <1>; 4392 bias-bus-hold; 4393 }; 4394 }; 4395 4396 wsa2_swr_active: wsa2-swr-active-state { 4397 clk-pins { 4398 pins = "gpio15"; 4399 function = "wsa2_swr_clk"; 4400 drive-strength = <2>; 4401 slew-rate = <1>; 4402 bias-disable; 4403 }; 4404 4405 data-pins { 4406 pins = "gpio16"; 4407 function = "wsa2_swr_data"; 4408 drive-strength = <2>; 4409 slew-rate = <1>; 4410 bias-bus-hold; 4411 }; 4412 }; 4413 }; 4414 4415 lpasscc: clock-controller@6ea0000 { 4416 compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc"; 4417 reg = <0 0x06ea0000 0 0x12000>; 4418 #clock-cells = <1>; 4419 #reset-cells = <1>; 4420 }; 4421 4422 lpass_ag_noc: interconnect@7e40000 { 4423 compatible = "qcom,x1e80100-lpass-ag-noc"; 4424 reg = <0 0x07e40000 0 0xe080>; 4425 4426 qcom,bcm-voters = <&apps_bcm_voter>; 4427 4428 #interconnect-cells = <2>; 4429 }; 4430 4431 lpass_lpiaon_noc: interconnect@7400000 { 4432 compatible = "qcom,x1e80100-lpass-lpiaon-noc"; 4433 reg = <0 0x07400000 0 0x19080>; 4434 4435 qcom,bcm-voters = <&apps_bcm_voter>; 4436 4437 #interconnect-cells = <2>; 4438 }; 4439 4440 lpass_lpicx_noc: interconnect@7430000 { 4441 compatible = "qcom,x1e80100-lpass-lpicx-noc"; 4442 reg = <0 0x07430000 0 0x3A200>; 4443 4444 qcom,bcm-voters = <&apps_bcm_voter>; 4445 4446 #interconnect-cells = <2>; 4447 }; 4448 4449 sdhc_2: mmc@8804000 { 4450 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4451 reg = <0 0x08804000 0 0x1000>; 4452 4453 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4454 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4455 interrupt-names = "hc_irq", "pwr_irq"; 4456 4457 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4458 <&gcc GCC_SDCC2_APPS_CLK>, 4459 <&rpmhcc RPMH_CXO_CLK>; 4460 clock-names = "iface", "core", "xo"; 4461 iommus = <&apps_smmu 0x520 0>; 4462 qcom,dll-config = <0x0007642c>; 4463 qcom,ddr-config = <0x80040868>; 4464 power-domains = <&rpmhpd RPMHPD_CX>; 4465 operating-points-v2 = <&sdhc2_opp_table>; 4466 4467 interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 4468 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4469 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4470 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4471 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4472 bus-width = <4>; 4473 dma-coherent; 4474 4475 status = "disabled"; 4476 4477 sdhc2_opp_table: opp-table { 4478 compatible = "operating-points-v2"; 4479 4480 opp-19200000 { 4481 opp-hz = /bits/ 64 <19200000>; 4482 required-opps = <&rpmhpd_opp_min_svs>; 4483 }; 4484 4485 opp-50000000 { 4486 opp-hz = /bits/ 64 <50000000>; 4487 required-opps = <&rpmhpd_opp_low_svs>; 4488 }; 4489 4490 opp-100000000 { 4491 opp-hz = /bits/ 64 <100000000>; 4492 required-opps = <&rpmhpd_opp_svs>; 4493 }; 4494 4495 opp-202000000 { 4496 opp-hz = /bits/ 64 <202000000>; 4497 required-opps = <&rpmhpd_opp_svs_l1>; 4498 }; 4499 }; 4500 }; 4501 4502 sdhc_4: mmc@8844000 { 4503 compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5"; 4504 reg = <0 0x08844000 0 0x1000>; 4505 4506 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4507 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 4508 interrupt-names = "hc_irq", "pwr_irq"; 4509 4510 clocks = <&gcc GCC_SDCC4_AHB_CLK>, 4511 <&gcc GCC_SDCC4_APPS_CLK>, 4512 <&rpmhcc RPMH_CXO_CLK>; 4513 clock-names = "iface", "core", "xo"; 4514 iommus = <&apps_smmu 0x160 0>; 4515 qcom,dll-config = <0x0007642c>; 4516 qcom,ddr-config = <0x80040868>; 4517 power-domains = <&rpmhpd RPMHPD_CX>; 4518 operating-points-v2 = <&sdhc4_opp_table>; 4519 4520 interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS 4521 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4522 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4523 &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 4524 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 4525 bus-width = <4>; 4526 dma-coherent; 4527 4528 status = "disabled"; 4529 4530 sdhc4_opp_table: opp-table { 4531 compatible = "operating-points-v2"; 4532 4533 opp-19200000 { 4534 opp-hz = /bits/ 64 <19200000>; 4535 required-opps = <&rpmhpd_opp_min_svs>; 4536 }; 4537 4538 opp-50000000 { 4539 opp-hz = /bits/ 64 <50000000>; 4540 required-opps = <&rpmhpd_opp_low_svs>; 4541 }; 4542 4543 opp-100000000 { 4544 opp-hz = /bits/ 64 <100000000>; 4545 required-opps = <&rpmhpd_opp_svs>; 4546 }; 4547 4548 opp-202000000 { 4549 opp-hz = /bits/ 64 <202000000>; 4550 required-opps = <&rpmhpd_opp_svs_l1>; 4551 }; 4552 }; 4553 }; 4554 4555 usb_2_hsphy: phy@88e0000 { 4556 compatible = "qcom,x1e80100-snps-eusb2-phy", 4557 "qcom,sm8550-snps-eusb2-phy"; 4558 reg = <0 0x088e0000 0 0x154>; 4559 #phy-cells = <0>; 4560 4561 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 4562 clock-names = "ref"; 4563 4564 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 4565 4566 status = "disabled"; 4567 }; 4568 4569 usb_mp_hsphy0: phy@88e1000 { 4570 compatible = "qcom,x1e80100-snps-eusb2-phy", 4571 "qcom,sm8550-snps-eusb2-phy"; 4572 reg = <0 0x088e1000 0 0x154>; 4573 #phy-cells = <0>; 4574 4575 clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>; 4576 clock-names = "ref"; 4577 4578 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 4579 4580 status = "disabled"; 4581 }; 4582 4583 usb_mp_hsphy1: phy@88e2000 { 4584 compatible = "qcom,x1e80100-snps-eusb2-phy", 4585 "qcom,sm8550-snps-eusb2-phy"; 4586 reg = <0 0x088e2000 0 0x154>; 4587 #phy-cells = <0>; 4588 4589 clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>; 4590 clock-names = "ref"; 4591 4592 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 4593 4594 status = "disabled"; 4595 }; 4596 4597 usb_mp_qmpphy0: phy@88e3000 { 4598 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4599 reg = <0 0x088e3000 0 0x2000>; 4600 4601 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4602 <&rpmhcc RPMH_CXO_CLK>, 4603 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4604 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 4605 clock-names = "aux", 4606 "ref", 4607 "com_aux", 4608 "pipe"; 4609 4610 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 4611 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 4612 reset-names = "phy", 4613 "phy_phy"; 4614 4615 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 4616 4617 #clock-cells = <0>; 4618 clock-output-names = "usb_mp_phy0_pipe_clk"; 4619 4620 #phy-cells = <0>; 4621 4622 status = "disabled"; 4623 }; 4624 4625 usb_mp_qmpphy1: phy@88e5000 { 4626 compatible = "qcom,x1e80100-qmp-usb3-uni-phy"; 4627 reg = <0 0x088e5000 0 0x2000>; 4628 4629 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 4630 <&rpmhcc RPMH_CXO_CLK>, 4631 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 4632 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 4633 clock-names = "aux", 4634 "ref", 4635 "com_aux", 4636 "pipe"; 4637 4638 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 4639 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 4640 reset-names = "phy", 4641 "phy_phy"; 4642 4643 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 4644 4645 #clock-cells = <0>; 4646 clock-output-names = "usb_mp_phy1_pipe_clk"; 4647 4648 #phy-cells = <0>; 4649 4650 status = "disabled"; 4651 }; 4652 4653 usb_1_ss2: usb@a0f8800 { 4654 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4655 reg = <0 0x0a0f8800 0 0x400>; 4656 4657 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 4658 <&gcc GCC_USB30_TERT_MASTER_CLK>, 4659 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 4660 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 4661 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4662 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4663 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4664 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4665 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4666 clock-names = "cfg_noc", 4667 "core", 4668 "iface", 4669 "sleep", 4670 "mock_utmi", 4671 "noc_aggr", 4672 "noc_aggr_north", 4673 "noc_aggr_south", 4674 "noc_sys"; 4675 4676 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4677 <&gcc GCC_USB30_TERT_MASTER_CLK>; 4678 assigned-clock-rates = <19200000>, 4679 <200000000>; 4680 4681 interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 4682 <&pdc 58 IRQ_TYPE_EDGE_BOTH>, 4683 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4684 <&pdc 10 IRQ_TYPE_LEVEL_HIGH>; 4685 interrupt-names = "pwr_event", 4686 "dp_hs_phy_irq", 4687 "dm_hs_phy_irq", 4688 "ss_phy_irq"; 4689 4690 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 4691 required-opps = <&rpmhpd_opp_nom>; 4692 4693 resets = <&gcc GCC_USB30_TERT_BCR>; 4694 4695 interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS 4696 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4697 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4698 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>; 4699 interconnect-names = "usb-ddr", 4700 "apps-usb"; 4701 4702 wakeup-source; 4703 4704 #address-cells = <2>; 4705 #size-cells = <2>; 4706 ranges; 4707 4708 status = "disabled"; 4709 4710 usb_1_ss2_dwc3: usb@a000000 { 4711 compatible = "snps,dwc3"; 4712 reg = <0 0x0a000000 0 0xcd00>; 4713 4714 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 4715 4716 iommus = <&apps_smmu 0x14a0 0x0>; 4717 4718 phys = <&usb_1_ss2_hsphy>, 4719 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>; 4720 phy-names = "usb2-phy", 4721 "usb3-phy"; 4722 4723 snps,dis_u2_susphy_quirk; 4724 snps,dis_enblslpm_quirk; 4725 snps,usb3_lpm_capable; 4726 snps,dis-u1-entry-quirk; 4727 snps,dis-u2-entry-quirk; 4728 4729 dma-coherent; 4730 4731 ports { 4732 #address-cells = <1>; 4733 #size-cells = <0>; 4734 4735 port@0 { 4736 reg = <0>; 4737 4738 usb_1_ss2_dwc3_hs: endpoint { 4739 }; 4740 }; 4741 4742 port@1 { 4743 reg = <1>; 4744 4745 usb_1_ss2_dwc3_ss: endpoint { 4746 remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>; 4747 }; 4748 }; 4749 }; 4750 }; 4751 }; 4752 4753 usb_2: usb@a2f8800 { 4754 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4755 reg = <0 0x0a2f8800 0 0x400>; 4756 #address-cells = <2>; 4757 #size-cells = <2>; 4758 ranges; 4759 4760 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4761 <&gcc GCC_USB20_MASTER_CLK>, 4762 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4763 <&gcc GCC_USB20_SLEEP_CLK>, 4764 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4765 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4766 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4767 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4768 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4769 clock-names = "cfg_noc", 4770 "core", 4771 "iface", 4772 "sleep", 4773 "mock_utmi", 4774 "noc_aggr", 4775 "noc_aggr_north", 4776 "noc_aggr_south", 4777 "noc_sys"; 4778 4779 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4780 <&gcc GCC_USB20_MASTER_CLK>; 4781 assigned-clock-rates = <19200000>, <200000000>; 4782 4783 interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 4784 <&pdc 50 IRQ_TYPE_EDGE_BOTH>, 4785 <&pdc 49 IRQ_TYPE_EDGE_BOTH>; 4786 interrupt-names = "pwr_event", 4787 "dp_hs_phy_irq", 4788 "dm_hs_phy_irq"; 4789 4790 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4791 required-opps = <&rpmhpd_opp_nom>; 4792 4793 resets = <&gcc GCC_USB20_PRIM_BCR>; 4794 4795 interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4796 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4797 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4798 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 4799 interconnect-names = "usb-ddr", 4800 "apps-usb"; 4801 4802 wakeup-source; 4803 4804 status = "disabled"; 4805 4806 usb_2_dwc3: usb@a200000 { 4807 compatible = "snps,dwc3"; 4808 reg = <0 0x0a200000 0 0xcd00>; 4809 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 4810 iommus = <&apps_smmu 0x14e0 0x0>; 4811 phys = <&usb_2_hsphy>; 4812 phy-names = "usb2-phy"; 4813 maximum-speed = "high-speed"; 4814 snps,dis-u1-entry-quirk; 4815 snps,dis-u2-entry-quirk; 4816 4817 ports { 4818 #address-cells = <1>; 4819 #size-cells = <0>; 4820 4821 port@0 { 4822 reg = <0>; 4823 4824 usb_2_dwc3_hs: endpoint { 4825 }; 4826 }; 4827 }; 4828 }; 4829 }; 4830 4831 usb_mp: usb@a4f8800 { 4832 compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3"; 4833 reg = <0 0x0a4f8800 0 0x400>; 4834 4835 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4836 <&gcc GCC_USB30_MP_MASTER_CLK>, 4837 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4838 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4839 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4840 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4841 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 4842 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 4843 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4844 clock-names = "cfg_noc", 4845 "core", 4846 "iface", 4847 "sleep", 4848 "mock_utmi", 4849 "noc_aggr", 4850 "noc_aggr_north", 4851 "noc_aggr_south", 4852 "noc_sys"; 4853 4854 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4855 <&gcc GCC_USB30_MP_MASTER_CLK>; 4856 assigned-clock-rates = <19200000>, 4857 <200000000>; 4858 4859 interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 4860 <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 4861 <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 4862 <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 4863 <&pdc 52 IRQ_TYPE_EDGE_BOTH>, 4864 <&pdc 51 IRQ_TYPE_EDGE_BOTH>, 4865 <&pdc 54 IRQ_TYPE_EDGE_BOTH>, 4866 <&pdc 53 IRQ_TYPE_EDGE_BOTH>, 4867 <&pdc 55 IRQ_TYPE_LEVEL_HIGH>, 4868 <&pdc 56 IRQ_TYPE_LEVEL_HIGH>; 4869 interrupt-names = "pwr_event_1", "pwr_event_2", 4870 "hs_phy_1", "hs_phy_2", 4871 "dp_hs_phy_1", "dm_hs_phy_1", 4872 "dp_hs_phy_2", "dm_hs_phy_2", 4873 "ss_phy_1", "ss_phy_2"; 4874 4875 power-domains = <&gcc GCC_USB30_MP_GDSC>; 4876 required-opps = <&rpmhpd_opp_nom>; 4877 4878 resets = <&gcc GCC_USB30_MP_BCR>; 4879 4880 interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS 4881 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4882 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4883 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ALWAYS>; 4884 interconnect-names = "usb-ddr", 4885 "apps-usb"; 4886 4887 wakeup-source; 4888 4889 #address-cells = <2>; 4890 #size-cells = <2>; 4891 ranges; 4892 4893 status = "disabled"; 4894 4895 usb_mp_dwc3: usb@a400000 { 4896 compatible = "snps,dwc3"; 4897 reg = <0 0x0a400000 0 0xcd00>; 4898 4899 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 4900 4901 iommus = <&apps_smmu 0x1400 0x0>; 4902 4903 phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>, 4904 <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>; 4905 phy-names = "usb2-0", "usb3-0", 4906 "usb2-1", "usb3-1"; 4907 dr_mode = "host"; 4908 4909 snps,dis_u2_susphy_quirk; 4910 snps,dis_enblslpm_quirk; 4911 snps,usb3_lpm_capable; 4912 snps,dis-u1-entry-quirk; 4913 snps,dis-u2-entry-quirk; 4914 4915 dma-coherent; 4916 }; 4917 }; 4918 4919 usb_1_ss0: usb@a6f8800 { 4920 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 4921 reg = <0 0x0a6f8800 0 0x400>; 4922 4923 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4924 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4925 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4926 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4927 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4928 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4929 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>, 4930 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>, 4931 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4932 clock-names = "cfg_noc", 4933 "core", 4934 "iface", 4935 "sleep", 4936 "mock_utmi", 4937 "noc_aggr", 4938 "noc_aggr_north", 4939 "noc_aggr_south", 4940 "noc_sys"; 4941 4942 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4943 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4944 assigned-clock-rates = <19200000>, 4945 <200000000>; 4946 4947 interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 4948 <&pdc 61 IRQ_TYPE_EDGE_BOTH>, 4949 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4950 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4951 interrupt-names = "pwr_event", 4952 "dp_hs_phy_irq", 4953 "dm_hs_phy_irq", 4954 "ss_phy_irq"; 4955 4956 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4957 required-opps = <&rpmhpd_opp_nom>; 4958 4959 resets = <&gcc GCC_USB30_PRIM_BCR>; 4960 4961 wakeup-source; 4962 4963 #address-cells = <2>; 4964 #size-cells = <2>; 4965 ranges; 4966 4967 status = "disabled"; 4968 4969 usb_1_ss0_dwc3: usb@a600000 { 4970 compatible = "snps,dwc3"; 4971 reg = <0 0x0a600000 0 0xcd00>; 4972 4973 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 4974 4975 iommus = <&apps_smmu 0x1420 0x0>; 4976 4977 phys = <&usb_1_ss0_hsphy>, 4978 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>; 4979 phy-names = "usb2-phy", 4980 "usb3-phy"; 4981 4982 snps,dis_u2_susphy_quirk; 4983 snps,dis_enblslpm_quirk; 4984 snps,usb3_lpm_capable; 4985 snps,dis-u1-entry-quirk; 4986 snps,dis-u2-entry-quirk; 4987 4988 dma-coherent; 4989 4990 ports { 4991 #address-cells = <1>; 4992 #size-cells = <0>; 4993 4994 port@0 { 4995 reg = <0>; 4996 4997 usb_1_ss0_dwc3_hs: endpoint { 4998 }; 4999 }; 5000 5001 port@1 { 5002 reg = <1>; 5003 5004 usb_1_ss0_dwc3_ss: endpoint { 5005 remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>; 5006 }; 5007 }; 5008 }; 5009 }; 5010 }; 5011 5012 usb_1_ss1: usb@a8f8800 { 5013 compatible = "qcom,x1e80100-dwc3", "qcom,dwc3"; 5014 reg = <0 0x0a8f8800 0 0x400>; 5015 5016 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 5017 <&gcc GCC_USB30_SEC_MASTER_CLK>, 5018 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 5019 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 5020 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5021 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 5022 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>, 5023 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>, 5024 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 5025 clock-names = "cfg_noc", 5026 "core", 5027 "iface", 5028 "sleep", 5029 "mock_utmi", 5030 "noc_aggr", 5031 "noc_aggr_north", 5032 "noc_aggr_south", 5033 "noc_sys"; 5034 5035 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5036 <&gcc GCC_USB30_SEC_MASTER_CLK>; 5037 assigned-clock-rates = <19200000>, 5038 <200000000>; 5039 5040 interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 5041 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 5042 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 5043 <&pdc 47 IRQ_TYPE_LEVEL_HIGH>; 5044 interrupt-names = "pwr_event", 5045 "dp_hs_phy_irq", 5046 "dm_hs_phy_irq", 5047 "ss_phy_irq"; 5048 5049 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 5050 required-opps = <&rpmhpd_opp_nom>; 5051 5052 resets = <&gcc GCC_USB30_SEC_BCR>; 5053 5054 interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS 5055 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5056 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5057 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>; 5058 interconnect-names = "usb-ddr", 5059 "apps-usb"; 5060 5061 wakeup-source; 5062 5063 #address-cells = <2>; 5064 #size-cells = <2>; 5065 ranges; 5066 5067 status = "disabled"; 5068 5069 usb_1_ss1_dwc3: usb@a800000 { 5070 compatible = "snps,dwc3"; 5071 reg = <0 0x0a800000 0 0xcd00>; 5072 5073 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 5074 5075 iommus = <&apps_smmu 0x1460 0x0>; 5076 5077 phys = <&usb_1_ss1_hsphy>, 5078 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>; 5079 phy-names = "usb2-phy", 5080 "usb3-phy"; 5081 5082 snps,dis_u2_susphy_quirk; 5083 snps,dis_enblslpm_quirk; 5084 snps,usb3_lpm_capable; 5085 snps,dis-u1-entry-quirk; 5086 snps,dis-u2-entry-quirk; 5087 5088 dma-coherent; 5089 5090 ports { 5091 #address-cells = <1>; 5092 #size-cells = <0>; 5093 5094 port@0 { 5095 reg = <0>; 5096 5097 usb_1_ss1_dwc3_hs: endpoint { 5098 }; 5099 }; 5100 5101 port@1 { 5102 reg = <1>; 5103 5104 usb_1_ss1_dwc3_ss: endpoint { 5105 remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>; 5106 }; 5107 }; 5108 }; 5109 }; 5110 }; 5111 5112 mdss: display-subsystem@ae00000 { 5113 compatible = "qcom,x1e80100-mdss"; 5114 reg = <0 0x0ae00000 0 0x1000>; 5115 reg-names = "mdss"; 5116 5117 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 5118 5119 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5120 <&gcc GCC_DISP_HF_AXI_CLK>, 5121 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5122 5123 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5124 5125 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 5126 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, 5127 <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 5128 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5129 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5130 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5131 interconnect-names = "mdp0-mem", 5132 "mdp1-mem", 5133 "cpu-cfg"; 5134 5135 power-domains = <&dispcc MDSS_GDSC>; 5136 5137 iommus = <&apps_smmu 0x1c00 0x2>; 5138 5139 interrupt-controller; 5140 #interrupt-cells = <1>; 5141 5142 #address-cells = <2>; 5143 #size-cells = <2>; 5144 ranges; 5145 5146 status = "disabled"; 5147 5148 mdss_mdp: display-controller@ae01000 { 5149 compatible = "qcom,x1e80100-dpu"; 5150 reg = <0 0x0ae01000 0 0x8f000>, 5151 <0 0x0aeb0000 0 0x2008>; 5152 reg-names = "mdp", 5153 "vbif"; 5154 5155 interrupts-extended = <&mdss 0>; 5156 5157 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5158 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5159 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5160 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5161 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5162 clock-names = "nrt_bus", 5163 "iface", 5164 "lut", 5165 "core", 5166 "vsync"; 5167 5168 operating-points-v2 = <&mdp_opp_table>; 5169 5170 power-domains = <&rpmhpd RPMHPD_MMCX>; 5171 5172 ports { 5173 #address-cells = <1>; 5174 #size-cells = <0>; 5175 5176 port@0 { 5177 reg = <0>; 5178 5179 mdss_intf0_out: endpoint { 5180 remote-endpoint = <&mdss_dp0_in>; 5181 }; 5182 }; 5183 5184 port@4 { 5185 reg = <4>; 5186 5187 mdss_intf4_out: endpoint { 5188 remote-endpoint = <&mdss_dp1_in>; 5189 }; 5190 }; 5191 5192 port@5 { 5193 reg = <5>; 5194 5195 mdss_intf5_out: endpoint { 5196 remote-endpoint = <&mdss_dp3_in>; 5197 }; 5198 }; 5199 5200 port@6 { 5201 reg = <6>; 5202 5203 mdss_intf6_out: endpoint { 5204 remote-endpoint = <&mdss_dp2_in>; 5205 }; 5206 }; 5207 }; 5208 5209 mdp_opp_table: opp-table { 5210 compatible = "operating-points-v2"; 5211 5212 opp-200000000 { 5213 opp-hz = /bits/ 64 <200000000>; 5214 required-opps = <&rpmhpd_opp_low_svs>; 5215 }; 5216 5217 opp-325000000 { 5218 opp-hz = /bits/ 64 <325000000>; 5219 required-opps = <&rpmhpd_opp_svs>; 5220 }; 5221 5222 opp-375000000 { 5223 opp-hz = /bits/ 64 <375000000>; 5224 required-opps = <&rpmhpd_opp_svs_l1>; 5225 }; 5226 5227 opp-514000000 { 5228 opp-hz = /bits/ 64 <514000000>; 5229 required-opps = <&rpmhpd_opp_nom>; 5230 }; 5231 5232 opp-575000000 { 5233 opp-hz = /bits/ 64 <575000000>; 5234 required-opps = <&rpmhpd_opp_nom_l1>; 5235 }; 5236 }; 5237 }; 5238 5239 mdss_dp0: displayport-controller@ae90000 { 5240 compatible = "qcom,x1e80100-dp"; 5241 reg = <0 0x0ae90000 0 0x200>, 5242 <0 0x0ae90200 0 0x200>, 5243 <0 0x0ae90400 0 0x600>, 5244 <0 0x0ae91000 0 0x400>, 5245 <0 0x0ae91400 0 0x400>; 5246 5247 interrupts-extended = <&mdss 12>; 5248 5249 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5250 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5251 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5252 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5253 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 5254 clock-names = "core_iface", 5255 "core_aux", 5256 "ctrl_link", 5257 "ctrl_link_iface", 5258 "stream_pixel"; 5259 5260 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5261 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 5262 assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5263 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5264 5265 operating-points-v2 = <&mdss_dp0_opp_table>; 5266 5267 power-domains = <&rpmhpd RPMHPD_MMCX>; 5268 5269 phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>; 5270 phy-names = "dp"; 5271 5272 #sound-dai-cells = <0>; 5273 5274 status = "disabled"; 5275 5276 ports { 5277 #address-cells = <1>; 5278 #size-cells = <0>; 5279 5280 port@0 { 5281 reg = <0>; 5282 5283 mdss_dp0_in: endpoint { 5284 remote-endpoint = <&mdss_intf0_out>; 5285 }; 5286 }; 5287 5288 port@1 { 5289 reg = <1>; 5290 5291 mdss_dp0_out: endpoint { 5292 remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>; 5293 }; 5294 }; 5295 }; 5296 5297 mdss_dp0_opp_table: opp-table { 5298 compatible = "operating-points-v2"; 5299 5300 opp-160000000 { 5301 opp-hz = /bits/ 64 <160000000>; 5302 required-opps = <&rpmhpd_opp_low_svs>; 5303 }; 5304 5305 opp-270000000 { 5306 opp-hz = /bits/ 64 <270000000>; 5307 required-opps = <&rpmhpd_opp_svs>; 5308 }; 5309 5310 opp-540000000 { 5311 opp-hz = /bits/ 64 <540000000>; 5312 required-opps = <&rpmhpd_opp_svs_l1>; 5313 }; 5314 5315 opp-810000000 { 5316 opp-hz = /bits/ 64 <810000000>; 5317 required-opps = <&rpmhpd_opp_nom>; 5318 }; 5319 }; 5320 }; 5321 5322 mdss_dp1: displayport-controller@ae98000 { 5323 compatible = "qcom,x1e80100-dp"; 5324 reg = <0 0x0ae98000 0 0x200>, 5325 <0 0x0ae98200 0 0x200>, 5326 <0 0x0ae98400 0 0x600>, 5327 <0 0x0ae99000 0 0x400>, 5328 <0 0x0ae99400 0 0x400>; 5329 5330 interrupts-extended = <&mdss 13>; 5331 5332 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5333 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 5334 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 5335 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5336 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 5337 clock-names = "core_iface", 5338 "core_aux", 5339 "ctrl_link", 5340 "ctrl_link_iface", 5341 "stream_pixel"; 5342 5343 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5344 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 5345 assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5346 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5347 5348 operating-points-v2 = <&mdss_dp1_opp_table>; 5349 5350 power-domains = <&rpmhpd RPMHPD_MMCX>; 5351 5352 phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>; 5353 phy-names = "dp"; 5354 5355 #sound-dai-cells = <0>; 5356 5357 status = "disabled"; 5358 5359 ports { 5360 #address-cells = <1>; 5361 #size-cells = <0>; 5362 5363 port@0 { 5364 reg = <0>; 5365 5366 mdss_dp1_in: endpoint { 5367 remote-endpoint = <&mdss_intf4_out>; 5368 }; 5369 }; 5370 5371 port@1 { 5372 reg = <1>; 5373 5374 mdss_dp1_out: endpoint { 5375 remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>; 5376 }; 5377 }; 5378 }; 5379 5380 mdss_dp1_opp_table: opp-table { 5381 compatible = "operating-points-v2"; 5382 5383 opp-160000000 { 5384 opp-hz = /bits/ 64 <160000000>; 5385 required-opps = <&rpmhpd_opp_low_svs>; 5386 }; 5387 5388 opp-270000000 { 5389 opp-hz = /bits/ 64 <270000000>; 5390 required-opps = <&rpmhpd_opp_svs>; 5391 }; 5392 5393 opp-540000000 { 5394 opp-hz = /bits/ 64 <540000000>; 5395 required-opps = <&rpmhpd_opp_svs_l1>; 5396 }; 5397 5398 opp-810000000 { 5399 opp-hz = /bits/ 64 <810000000>; 5400 required-opps = <&rpmhpd_opp_nom>; 5401 }; 5402 }; 5403 }; 5404 5405 mdss_dp2: displayport-controller@ae9a000 { 5406 compatible = "qcom,x1e80100-dp"; 5407 reg = <0 0x0ae9a000 0 0x200>, 5408 <0 0x0ae9a200 0 0x200>, 5409 <0 0x0ae9a400 0 0x600>, 5410 <0 0x0ae9b000 0 0x400>, 5411 <0 0x0ae9b400 0 0x400>; 5412 5413 interrupts-extended = <&mdss 14>; 5414 5415 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5416 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5417 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 5418 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5419 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 5420 clock-names = "core_iface", 5421 "core_aux", 5422 "ctrl_link", 5423 "ctrl_link_iface", 5424 "stream_pixel"; 5425 5426 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5427 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 5428 assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5429 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5430 5431 operating-points-v2 = <&mdss_dp2_opp_table>; 5432 5433 power-domains = <&rpmhpd RPMHPD_MMCX>; 5434 5435 phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>; 5436 phy-names = "dp"; 5437 5438 #sound-dai-cells = <0>; 5439 5440 status = "disabled"; 5441 5442 ports { 5443 #address-cells = <1>; 5444 #size-cells = <0>; 5445 5446 port@0 { 5447 reg = <0>; 5448 mdss_dp2_in: endpoint { 5449 remote-endpoint = <&mdss_intf6_out>; 5450 }; 5451 }; 5452 5453 port@1 { 5454 reg = <1>; 5455 5456 mdss_dp2_out: endpoint { 5457 remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>; 5458 }; 5459 }; 5460 }; 5461 5462 mdss_dp2_opp_table: opp-table { 5463 compatible = "operating-points-v2"; 5464 5465 opp-160000000 { 5466 opp-hz = /bits/ 64 <160000000>; 5467 required-opps = <&rpmhpd_opp_low_svs>; 5468 }; 5469 5470 opp-270000000 { 5471 opp-hz = /bits/ 64 <270000000>; 5472 required-opps = <&rpmhpd_opp_svs>; 5473 }; 5474 5475 opp-540000000 { 5476 opp-hz = /bits/ 64 <540000000>; 5477 required-opps = <&rpmhpd_opp_svs_l1>; 5478 }; 5479 5480 opp-810000000 { 5481 opp-hz = /bits/ 64 <810000000>; 5482 required-opps = <&rpmhpd_opp_nom>; 5483 }; 5484 }; 5485 }; 5486 5487 mdss_dp3: displayport-controller@aea0000 { 5488 compatible = "qcom,x1e80100-dp"; 5489 reg = <0 0x0aea0000 0 0x200>, 5490 <0 0x0aea0200 0 0x200>, 5491 <0 0x0aea0400 0 0x600>, 5492 <0 0x0aea1000 0 0x400>, 5493 <0 0x0aea1400 0 0x400>; 5494 5495 interrupts-extended = <&mdss 15>; 5496 5497 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5498 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5499 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 5500 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5501 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5502 clock-names = "core_iface", 5503 "core_aux", 5504 "ctrl_link", 5505 "ctrl_link_iface", 5506 "stream_pixel"; 5507 5508 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5509 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5510 assigned-clock-parents = <&mdss_dp3_phy 0>, 5511 <&mdss_dp3_phy 1>; 5512 5513 operating-points-v2 = <&mdss_dp3_opp_table>; 5514 5515 power-domains = <&rpmhpd RPMHPD_MMCX>; 5516 5517 phys = <&mdss_dp3_phy>; 5518 phy-names = "dp"; 5519 5520 #sound-dai-cells = <0>; 5521 5522 status = "disabled"; 5523 5524 ports { 5525 #address-cells = <1>; 5526 #size-cells = <0>; 5527 5528 port@0 { 5529 reg = <0>; 5530 5531 mdss_dp3_in: endpoint { 5532 remote-endpoint = <&mdss_intf5_out>; 5533 }; 5534 }; 5535 5536 port@1 { 5537 reg = <1>; 5538 }; 5539 }; 5540 5541 mdss_dp3_opp_table: opp-table { 5542 compatible = "operating-points-v2"; 5543 5544 opp-160000000 { 5545 opp-hz = /bits/ 64 <160000000>; 5546 required-opps = <&rpmhpd_opp_low_svs>; 5547 }; 5548 5549 opp-270000000 { 5550 opp-hz = /bits/ 64 <270000000>; 5551 required-opps = <&rpmhpd_opp_svs>; 5552 }; 5553 5554 opp-540000000 { 5555 opp-hz = /bits/ 64 <540000000>; 5556 required-opps = <&rpmhpd_opp_svs_l1>; 5557 }; 5558 5559 opp-810000000 { 5560 opp-hz = /bits/ 64 <810000000>; 5561 required-opps = <&rpmhpd_opp_nom>; 5562 }; 5563 }; 5564 }; 5565 5566 }; 5567 5568 mdss_dp2_phy: phy@aec2a00 { 5569 compatible = "qcom,x1e80100-dp-phy"; 5570 reg = <0 0x0aec2a00 0 0x19c>, 5571 <0 0x0aec2200 0 0xec>, 5572 <0 0x0aec2600 0 0xec>, 5573 <0 0x0aec2000 0 0x1c8>; 5574 5575 clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5576 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5577 clock-names = "aux", 5578 "cfg_ahb"; 5579 5580 power-domains = <&rpmhpd RPMHPD_MX>; 5581 5582 #clock-cells = <1>; 5583 #phy-cells = <0>; 5584 5585 status = "disabled"; 5586 }; 5587 5588 mdss_dp3_phy: phy@aec5a00 { 5589 compatible = "qcom,x1e80100-dp-phy"; 5590 reg = <0 0x0aec5a00 0 0x19c>, 5591 <0 0x0aec5200 0 0xec>, 5592 <0 0x0aec5600 0 0xec>, 5593 <0 0x0aec5000 0 0x1c8>; 5594 5595 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5596 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5597 clock-names = "aux", 5598 "cfg_ahb"; 5599 5600 power-domains = <&rpmhpd RPMHPD_MX>; 5601 5602 #clock-cells = <1>; 5603 #phy-cells = <0>; 5604 5605 status = "disabled"; 5606 }; 5607 5608 dispcc: clock-controller@af00000 { 5609 compatible = "qcom,x1e80100-dispcc"; 5610 reg = <0 0x0af00000 0 0x20000>; 5611 clocks = <&bi_tcxo_div2>, 5612 <&bi_tcxo_ao_div2>, 5613 <&gcc GCC_DISP_AHB_CLK>, 5614 <&sleep_clk>, 5615 <0>, /* dsi0 */ 5616 <0>, 5617 <0>, /* dsi1 */ 5618 <0>, 5619 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 5620 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5621 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 5622 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5623 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 5624 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5625 <&mdss_dp3_phy 0>, /* dp3 */ 5626 <&mdss_dp3_phy 1>; 5627 power-domains = <&rpmhpd RPMHPD_MMCX>; 5628 required-opps = <&rpmhpd_opp_low_svs>; 5629 #clock-cells = <1>; 5630 #reset-cells = <1>; 5631 #power-domain-cells = <1>; 5632 }; 5633 5634 pdc: interrupt-controller@b220000 { 5635 compatible = "qcom,x1e80100-pdc", "qcom,pdc"; 5636 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 5637 5638 qcom,pdc-ranges = <0 480 42>, <42 251 5>, 5639 <47 522 52>, <99 609 32>, 5640 <131 717 12>, <143 816 19>; 5641 #interrupt-cells = <2>; 5642 interrupt-parent = <&intc>; 5643 interrupt-controller; 5644 }; 5645 5646 aoss_qmp: power-management@c300000 { 5647 compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp"; 5648 reg = <0 0x0c300000 0 0x400>; 5649 interrupt-parent = <&ipcc>; 5650 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 5651 IRQ_TYPE_EDGE_RISING>; 5652 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5653 5654 #clock-cells = <0>; 5655 }; 5656 5657 sram@c3f0000 { 5658 compatible = "qcom,rpmh-stats"; 5659 reg = <0 0x0c3f0000 0 0x400>; 5660 }; 5661 5662 spmi: arbiter@c400000 { 5663 compatible = "qcom,x1e80100-spmi-pmic-arb"; 5664 reg = <0 0x0c400000 0 0x3000>, 5665 <0 0x0c500000 0 0x400000>, 5666 <0 0x0c440000 0 0x80000>; 5667 reg-names = "core", "chnls", "obsrvr"; 5668 5669 qcom,ee = <0>; 5670 qcom,channel = <0>; 5671 5672 #address-cells = <2>; 5673 #size-cells = <2>; 5674 ranges; 5675 5676 spmi_bus0: spmi@c42d000 { 5677 reg = <0 0x0c42d000 0 0x4000>, 5678 <0 0x0c4c0000 0 0x10000>; 5679 reg-names = "cnfg", "intr"; 5680 5681 interrupt-names = "periph_irq"; 5682 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5683 interrupt-controller; 5684 #interrupt-cells = <4>; 5685 5686 #address-cells = <2>; 5687 #size-cells = <0>; 5688 }; 5689 5690 spmi_bus1: spmi@c432000 { 5691 reg = <0 0x0c432000 0 0x4000>, 5692 <0 0x0c4d0000 0 0x10000>; 5693 reg-names = "cnfg", "intr"; 5694 5695 interrupt-names = "periph_irq"; 5696 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 5697 interrupt-controller; 5698 #interrupt-cells = <4>; 5699 5700 #address-cells = <2>; 5701 #size-cells = <0>; 5702 }; 5703 }; 5704 5705 tlmm: pinctrl@f100000 { 5706 compatible = "qcom,x1e80100-tlmm"; 5707 reg = <0 0x0f100000 0 0xf00000>; 5708 5709 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5710 5711 gpio-controller; 5712 #gpio-cells = <2>; 5713 5714 interrupt-controller; 5715 #interrupt-cells = <2>; 5716 5717 gpio-ranges = <&tlmm 0 0 239>; 5718 wakeup-parent = <&pdc>; 5719 5720 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5721 /* SDA, SCL */ 5722 pins = "gpio0", "gpio1"; 5723 function = "qup0_se0"; 5724 drive-strength = <2>; 5725 bias-pull-up = <2200>; 5726 }; 5727 5728 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5729 /* SDA, SCL */ 5730 pins = "gpio4", "gpio5"; 5731 function = "qup0_se1"; 5732 drive-strength = <2>; 5733 bias-pull-up = <2200>; 5734 }; 5735 5736 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5737 /* SDA, SCL */ 5738 pins = "gpio8", "gpio9"; 5739 function = "qup0_se2"; 5740 drive-strength = <2>; 5741 bias-pull-up = <2200>; 5742 }; 5743 5744 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5745 /* SDA, SCL */ 5746 pins = "gpio12", "gpio13"; 5747 function = "qup0_se3"; 5748 drive-strength = <2>; 5749 bias-pull-up = <2200>; 5750 }; 5751 5752 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5753 /* SDA, SCL */ 5754 pins = "gpio16", "gpio17"; 5755 function = "qup0_se4"; 5756 drive-strength = <2>; 5757 bias-pull-up = <2200>; 5758 }; 5759 5760 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5761 /* SDA, SCL */ 5762 pins = "gpio20", "gpio21"; 5763 function = "qup0_se5"; 5764 drive-strength = <2>; 5765 bias-pull-up = <2200>; 5766 }; 5767 5768 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5769 /* SDA, SCL */ 5770 pins = "gpio24", "gpio25"; 5771 function = "qup0_se6"; 5772 drive-strength = <2>; 5773 bias-pull-up = <2200>; 5774 }; 5775 5776 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5777 /* SDA, SCL */ 5778 pins = "gpio14", "gpio15"; 5779 function = "qup0_se7"; 5780 drive-strength = <2>; 5781 bias-pull-up = <2200>; 5782 }; 5783 5784 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5785 /* SDA, SCL */ 5786 pins = "gpio32", "gpio33"; 5787 function = "qup1_se0"; 5788 drive-strength = <2>; 5789 bias-pull-up = <2200>; 5790 }; 5791 5792 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5793 /* SDA, SCL */ 5794 pins = "gpio36", "gpio37"; 5795 function = "qup1_se1"; 5796 drive-strength = <2>; 5797 bias-pull-up = <2200>; 5798 }; 5799 5800 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5801 /* SDA, SCL */ 5802 pins = "gpio40", "gpio41"; 5803 function = "qup1_se2"; 5804 drive-strength = <2>; 5805 bias-pull-up = <2200>; 5806 }; 5807 5808 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5809 /* SDA, SCL */ 5810 pins = "gpio44", "gpio45"; 5811 function = "qup1_se3"; 5812 drive-strength = <2>; 5813 bias-pull-up = <2200>; 5814 }; 5815 5816 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5817 /* SDA, SCL */ 5818 pins = "gpio48", "gpio49"; 5819 function = "qup1_se4"; 5820 drive-strength = <2>; 5821 bias-pull-up = <2200>; 5822 }; 5823 5824 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5825 /* SDA, SCL */ 5826 pins = "gpio52", "gpio53"; 5827 function = "qup1_se5"; 5828 drive-strength = <2>; 5829 bias-pull-up = <2200>; 5830 }; 5831 5832 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5833 /* SDA, SCL */ 5834 pins = "gpio56", "gpio57"; 5835 function = "qup1_se6"; 5836 drive-strength = <2>; 5837 bias-pull-up = <2200>; 5838 }; 5839 5840 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5841 /* SDA, SCL */ 5842 pins = "gpio54", "gpio55"; 5843 function = "qup1_se7"; 5844 drive-strength = <2>; 5845 bias-pull-up = <2200>; 5846 }; 5847 5848 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 5849 /* SDA, SCL */ 5850 pins = "gpio64", "gpio65"; 5851 function = "qup2_se0"; 5852 drive-strength = <2>; 5853 bias-pull-up = <2200>; 5854 }; 5855 5856 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 5857 /* SDA, SCL */ 5858 pins = "gpio68", "gpio69"; 5859 function = "qup2_se1"; 5860 drive-strength = <2>; 5861 bias-pull-up = <2200>; 5862 }; 5863 5864 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 5865 /* SDA, SCL */ 5866 pins = "gpio72", "gpio73"; 5867 function = "qup2_se2"; 5868 drive-strength = <2>; 5869 bias-pull-up = <2200>; 5870 }; 5871 5872 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 5873 /* SDA, SCL */ 5874 pins = "gpio76", "gpio77"; 5875 function = "qup2_se3"; 5876 drive-strength = <2>; 5877 bias-pull-up = <2200>; 5878 }; 5879 5880 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 5881 /* SDA, SCL */ 5882 pins = "gpio80", "gpio81"; 5883 function = "qup2_se4"; 5884 drive-strength = <2>; 5885 bias-pull-up = <2200>; 5886 }; 5887 5888 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 5889 /* SDA, SCL */ 5890 pins = "gpio84", "gpio85"; 5891 function = "qup2_se5"; 5892 drive-strength = <2>; 5893 bias-pull-up = <2200>; 5894 }; 5895 5896 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 5897 /* SDA, SCL */ 5898 pins = "gpio88", "gpio89"; 5899 function = "qup2_se6"; 5900 drive-strength = <2>; 5901 bias-pull-up = <2200>; 5902 }; 5903 5904 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 5905 /* SDA, SCL */ 5906 pins = "gpio86", "gpio87"; 5907 function = "qup2_se7"; 5908 drive-strength = <2>; 5909 bias-pull-up = <2200>; 5910 }; 5911 5912 qup_spi0_cs: qup-spi0-cs-state { 5913 pins = "gpio3"; 5914 function = "qup0_se0"; 5915 drive-strength = <6>; 5916 bias-disable; 5917 }; 5918 5919 qup_spi0_data_clk: qup-spi0-data-clk-state { 5920 /* MISO, MOSI, CLK */ 5921 pins = "gpio0", "gpio1", "gpio2"; 5922 function = "qup0_se0"; 5923 drive-strength = <6>; 5924 bias-disable; 5925 }; 5926 5927 qup_spi1_cs: qup-spi1-cs-state { 5928 pins = "gpio7"; 5929 function = "qup0_se1"; 5930 drive-strength = <6>; 5931 bias-disable; 5932 }; 5933 5934 qup_spi1_data_clk: qup-spi1-data-clk-state { 5935 /* MISO, MOSI, CLK */ 5936 pins = "gpio4", "gpio5", "gpio6"; 5937 function = "qup0_se1"; 5938 drive-strength = <6>; 5939 bias-disable; 5940 }; 5941 5942 qup_spi2_cs: qup-spi2-cs-state { 5943 pins = "gpio11"; 5944 function = "qup0_se2"; 5945 drive-strength = <6>; 5946 bias-disable; 5947 }; 5948 5949 qup_spi2_data_clk: qup-spi2-data-clk-state { 5950 /* MISO, MOSI, CLK */ 5951 pins = "gpio8", "gpio9", "gpio10"; 5952 function = "qup0_se2"; 5953 drive-strength = <6>; 5954 bias-disable; 5955 }; 5956 5957 qup_spi3_cs: qup-spi3-cs-state { 5958 pins = "gpio15"; 5959 function = "qup0_se3"; 5960 drive-strength = <6>; 5961 bias-disable; 5962 }; 5963 5964 qup_spi3_data_clk: qup-spi3-data-clk-state { 5965 /* MISO, MOSI, CLK */ 5966 pins = "gpio12", "gpio13", "gpio14"; 5967 function = "qup0_se3"; 5968 drive-strength = <6>; 5969 bias-disable; 5970 }; 5971 5972 qup_spi4_cs: qup-spi4-cs-state { 5973 pins = "gpio19"; 5974 function = "qup0_se4"; 5975 drive-strength = <6>; 5976 bias-disable; 5977 }; 5978 5979 qup_spi4_data_clk: qup-spi4-data-clk-state { 5980 /* MISO, MOSI, CLK */ 5981 pins = "gpio16", "gpio17", "gpio18"; 5982 function = "qup0_se4"; 5983 drive-strength = <6>; 5984 bias-disable; 5985 }; 5986 5987 qup_spi5_cs: qup-spi5-cs-state { 5988 pins = "gpio23"; 5989 function = "qup0_se5"; 5990 drive-strength = <6>; 5991 bias-disable; 5992 }; 5993 5994 qup_spi5_data_clk: qup-spi5-data-clk-state { 5995 /* MISO, MOSI, CLK */ 5996 pins = "gpio20", "gpio21", "gpio22"; 5997 function = "qup0_se5"; 5998 drive-strength = <6>; 5999 bias-disable; 6000 }; 6001 6002 qup_spi6_cs: qup-spi6-cs-state { 6003 pins = "gpio27"; 6004 function = "qup0_se6"; 6005 drive-strength = <6>; 6006 bias-disable; 6007 }; 6008 6009 qup_spi6_data_clk: qup-spi6-data-clk-state { 6010 /* MISO, MOSI, CLK */ 6011 pins = "gpio24", "gpio25", "gpio26"; 6012 function = "qup0_se6"; 6013 drive-strength = <6>; 6014 bias-disable; 6015 }; 6016 6017 qup_spi7_cs: qup-spi7-cs-state { 6018 pins = "gpio13"; 6019 function = "qup0_se7"; 6020 drive-strength = <6>; 6021 bias-disable; 6022 }; 6023 6024 qup_spi7_data_clk: qup-spi7-data-clk-state { 6025 /* MISO, MOSI, CLK */ 6026 pins = "gpio14", "gpio15", "gpio12"; 6027 function = "qup0_se7"; 6028 drive-strength = <6>; 6029 bias-disable; 6030 }; 6031 6032 qup_spi8_cs: qup-spi8-cs-state { 6033 pins = "gpio35"; 6034 function = "qup1_se0"; 6035 drive-strength = <6>; 6036 bias-disable; 6037 }; 6038 6039 qup_spi8_data_clk: qup-spi8-data-clk-state { 6040 /* MISO, MOSI, CLK */ 6041 pins = "gpio32", "gpio33", "gpio34"; 6042 function = "qup1_se0"; 6043 drive-strength = <6>; 6044 bias-disable; 6045 }; 6046 6047 qup_spi9_cs: qup-spi9-cs-state { 6048 pins = "gpio39"; 6049 function = "qup1_se1"; 6050 drive-strength = <6>; 6051 bias-disable; 6052 }; 6053 6054 qup_spi9_data_clk: qup-spi9-data-clk-state { 6055 /* MISO, MOSI, CLK */ 6056 pins = "gpio36", "gpio37", "gpio38"; 6057 function = "qup1_se1"; 6058 drive-strength = <6>; 6059 bias-disable; 6060 }; 6061 6062 qup_spi10_cs: qup-spi10-cs-state { 6063 pins = "gpio43"; 6064 function = "qup1_se2"; 6065 drive-strength = <6>; 6066 bias-disable; 6067 }; 6068 6069 qup_spi10_data_clk: qup-spi10-data-clk-state { 6070 /* MISO, MOSI, CLK */ 6071 pins = "gpio40", "gpio41", "gpio42"; 6072 function = "qup1_se2"; 6073 drive-strength = <6>; 6074 bias-disable; 6075 }; 6076 6077 qup_spi11_cs: qup-spi11-cs-state { 6078 pins = "gpio47"; 6079 function = "qup1_se3"; 6080 drive-strength = <6>; 6081 bias-disable; 6082 }; 6083 6084 qup_spi11_data_clk: qup-spi11-data-clk-state { 6085 /* MISO, MOSI, CLK */ 6086 pins = "gpio44", "gpio45", "gpio46"; 6087 function = "qup1_se3"; 6088 drive-strength = <6>; 6089 bias-disable; 6090 }; 6091 6092 qup_spi12_cs: qup-spi12-cs-state { 6093 pins = "gpio51"; 6094 function = "qup1_se4"; 6095 drive-strength = <6>; 6096 bias-disable; 6097 }; 6098 6099 qup_spi12_data_clk: qup-spi12-data-clk-state { 6100 /* MISO, MOSI, CLK */ 6101 pins = "gpio48", "gpio49", "gpio50"; 6102 function = "qup1_se4"; 6103 drive-strength = <6>; 6104 bias-disable; 6105 }; 6106 6107 qup_spi13_cs: qup-spi13-cs-state { 6108 pins = "gpio55"; 6109 function = "qup1_se5"; 6110 drive-strength = <6>; 6111 bias-disable; 6112 }; 6113 6114 qup_spi13_data_clk: qup-spi13-data-clk-state { 6115 /* MISO, MOSI, CLK */ 6116 pins = "gpio52", "gpio53", "gpio54"; 6117 function = "qup1_se5"; 6118 drive-strength = <6>; 6119 bias-disable; 6120 }; 6121 6122 qup_spi14_cs: qup-spi14-cs-state { 6123 pins = "gpio59"; 6124 function = "qup1_se6"; 6125 drive-strength = <6>; 6126 bias-disable; 6127 }; 6128 6129 qup_spi14_data_clk: qup-spi14-data-clk-state { 6130 /* MISO, MOSI, CLK */ 6131 pins = "gpio56", "gpio57", "gpio58"; 6132 function = "qup1_se6"; 6133 drive-strength = <6>; 6134 bias-disable; 6135 }; 6136 6137 qup_spi15_cs: qup-spi15-cs-state { 6138 pins = "gpio53"; 6139 function = "qup1_se7"; 6140 drive-strength = <6>; 6141 bias-disable; 6142 }; 6143 6144 qup_spi15_data_clk: qup-spi15-data-clk-state { 6145 /* MISO, MOSI, CLK */ 6146 pins = "gpio54", "gpio55", "gpio52"; 6147 function = "qup1_se7"; 6148 drive-strength = <6>; 6149 bias-disable; 6150 }; 6151 6152 qup_spi16_cs: qup-spi16-cs-state { 6153 pins = "gpio67"; 6154 function = "qup2_se0"; 6155 drive-strength = <6>; 6156 bias-disable; 6157 }; 6158 6159 qup_spi16_data_clk: qup-spi16-data-clk-state { 6160 /* MISO, MOSI, CLK */ 6161 pins = "gpio64", "gpio65", "gpio66"; 6162 function = "qup2_se0"; 6163 drive-strength = <6>; 6164 bias-disable; 6165 }; 6166 6167 qup_spi17_cs: qup-spi17-cs-state { 6168 pins = "gpio71"; 6169 function = "qup2_se1"; 6170 drive-strength = <6>; 6171 bias-disable; 6172 }; 6173 6174 qup_spi17_data_clk: qup-spi17-data-clk-state { 6175 /* MISO, MOSI, CLK */ 6176 pins = "gpio68", "gpio69", "gpio70"; 6177 function = "qup2_se1"; 6178 drive-strength = <6>; 6179 bias-disable; 6180 }; 6181 6182 qup_spi18_cs: qup-spi18-cs-state { 6183 pins = "gpio75"; 6184 function = "qup2_se2"; 6185 drive-strength = <6>; 6186 bias-disable; 6187 }; 6188 6189 qup_spi18_data_clk: qup-spi18-data-clk-state { 6190 /* MISO, MOSI, CLK */ 6191 pins = "gpio72", "gpio73", "gpio74"; 6192 function = "qup2_se2"; 6193 drive-strength = <6>; 6194 bias-disable; 6195 }; 6196 6197 qup_spi19_cs: qup-spi19-cs-state { 6198 pins = "gpio79"; 6199 function = "qup2_se3"; 6200 drive-strength = <6>; 6201 bias-disable; 6202 }; 6203 6204 qup_spi19_data_clk: qup-spi19-data-clk-state { 6205 /* MISO, MOSI, CLK */ 6206 pins = "gpio76", "gpio77", "gpio78"; 6207 function = "qup2_se3"; 6208 drive-strength = <6>; 6209 bias-disable; 6210 }; 6211 6212 qup_spi20_cs: qup-spi20-cs-state { 6213 pins = "gpio83"; 6214 function = "qup2_se4"; 6215 drive-strength = <6>; 6216 bias-disable; 6217 }; 6218 6219 qup_spi20_data_clk: qup-spi20-data-clk-state { 6220 /* MISO, MOSI, CLK */ 6221 pins = "gpio80", "gpio81", "gpio82"; 6222 function = "qup2_se4"; 6223 drive-strength = <6>; 6224 bias-disable; 6225 }; 6226 6227 qup_spi21_cs: qup-spi21-cs-state { 6228 pins = "gpio87"; 6229 function = "qup2_se5"; 6230 drive-strength = <6>; 6231 bias-disable; 6232 }; 6233 6234 qup_spi21_data_clk: qup-spi21-data-clk-state { 6235 /* MISO, MOSI, CLK */ 6236 pins = "gpio84", "gpio85", "gpio86"; 6237 function = "qup2_se5"; 6238 drive-strength = <6>; 6239 bias-disable; 6240 }; 6241 6242 qup_spi22_cs: qup-spi22-cs-state { 6243 pins = "gpio91"; 6244 function = "qup2_se6"; 6245 drive-strength = <6>; 6246 bias-disable; 6247 }; 6248 6249 qup_spi22_data_clk: qup-spi22-data-clk-state { 6250 /* MISO, MOSI, CLK */ 6251 pins = "gpio88", "gpio89", "gpio90"; 6252 function = "qup2_se6"; 6253 drive-strength = <6>; 6254 bias-disable; 6255 }; 6256 6257 qup_spi23_cs: qup-spi23-cs-state { 6258 pins = "gpio85"; 6259 function = "qup2_se7"; 6260 drive-strength = <6>; 6261 bias-disable; 6262 }; 6263 6264 qup_spi23_data_clk: qup-spi23-data-clk-state { 6265 /* MISO, MOSI, CLK */ 6266 pins = "gpio86", "gpio87", "gpio84"; 6267 function = "qup2_se7"; 6268 drive-strength = <6>; 6269 bias-disable; 6270 }; 6271 6272 qup_uart2_default: qup-uart2-default-state { 6273 cts-pins { 6274 pins = "gpio8"; 6275 function = "qup0_se2"; 6276 drive-strength = <2>; 6277 bias-disable; 6278 }; 6279 6280 rts-pins { 6281 pins = "gpio9"; 6282 function = "qup0_se2"; 6283 drive-strength = <2>; 6284 bias-disable; 6285 }; 6286 6287 tx-pins { 6288 pins = "gpio10"; 6289 function = "qup0_se2"; 6290 drive-strength = <2>; 6291 bias-disable; 6292 }; 6293 6294 rx-pins { 6295 pins = "gpio11"; 6296 function = "qup0_se2"; 6297 drive-strength = <2>; 6298 bias-disable; 6299 }; 6300 }; 6301 6302 qup_uart14_default: qup-uart14-default-state { 6303 cts-pins { 6304 pins = "gpio56"; 6305 function = "qup1_se6"; 6306 bias-bus-hold; 6307 }; 6308 6309 rts-pins { 6310 pins = "gpio57"; 6311 function = "qup1_se6"; 6312 drive-strength = <2>; 6313 bias-disable; 6314 }; 6315 6316 tx-pins { 6317 pins = "gpio58"; 6318 function = "qup1_se6"; 6319 drive-strength = <2>; 6320 bias-disable; 6321 }; 6322 6323 rx-pins { 6324 pins = "gpio59"; 6325 function = "qup1_se6"; 6326 bias-pull-up; 6327 }; 6328 }; 6329 6330 qup_uart21_default: qup-uart21-default-state { 6331 tx-pins { 6332 pins = "gpio86"; 6333 function = "qup2_se5"; 6334 drive-strength = <2>; 6335 bias-disable; 6336 }; 6337 6338 rx-pins { 6339 pins = "gpio87"; 6340 function = "qup2_se5"; 6341 drive-strength = <2>; 6342 bias-disable; 6343 }; 6344 }; 6345 6346 sdc2_default: sdc2-default-state { 6347 clk-pins { 6348 pins = "sdc2_clk"; 6349 drive-strength = <16>; 6350 bias-disable; 6351 }; 6352 6353 cmd-pins { 6354 pins = "sdc2_cmd"; 6355 drive-strength = <10>; 6356 bias-pull-up; 6357 }; 6358 6359 data-pins { 6360 pins = "sdc2_data"; 6361 drive-strength = <10>; 6362 bias-pull-up; 6363 }; 6364 }; 6365 6366 sdc2_sleep: sdc2-sleep-state { 6367 clk-pins { 6368 pins = "sdc2_clk"; 6369 drive-strength = <2>; 6370 bias-disable; 6371 }; 6372 6373 cmd-pins { 6374 pins = "sdc2_cmd"; 6375 drive-strength = <2>; 6376 bias-pull-up; 6377 }; 6378 6379 data-pins { 6380 pins = "sdc2_data"; 6381 drive-strength = <2>; 6382 bias-pull-up; 6383 }; 6384 }; 6385 }; 6386 6387 stm@10002000 { 6388 compatible = "arm,coresight-stm", "arm,primecell"; 6389 reg = <0x0 0x10002000 0x0 0x1000>, 6390 <0x0 0x16280000 0x0 0x180000>; 6391 reg-names = "stm-base", 6392 "stm-stimulus-base"; 6393 6394 clocks = <&aoss_qmp>; 6395 clock-names = "apb_pclk"; 6396 6397 out-ports { 6398 port { 6399 stm_out: endpoint { 6400 remote-endpoint = <&funnel0_in7>; 6401 }; 6402 }; 6403 }; 6404 }; 6405 6406 tpdm@10003000 { 6407 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6408 reg = <0x0 0x10003000 0x0 0x1000>; 6409 6410 clocks = <&aoss_qmp>; 6411 clock-names = "apb_pclk"; 6412 6413 qcom,cmb-element-bits = <32>; 6414 qcom,cmb-msrs-num = <32>; 6415 status = "disabled"; 6416 6417 out-ports { 6418 port { 6419 dcc_tpdm_out: endpoint { 6420 remote-endpoint = <&qdss_tpda_in0>; 6421 }; 6422 }; 6423 }; 6424 }; 6425 6426 tpda@10004000 { 6427 compatible = "qcom,coresight-tpda", "arm,primecell"; 6428 reg = <0x0 0x10004000 0x0 0x1000>; 6429 6430 clocks = <&aoss_qmp>; 6431 clock-names = "apb_pclk"; 6432 6433 in-ports { 6434 #address-cells = <1>; 6435 #size-cells = <0>; 6436 6437 port@0 { 6438 reg = <0>; 6439 6440 qdss_tpda_in0: endpoint { 6441 remote-endpoint = <&dcc_tpdm_out>; 6442 }; 6443 }; 6444 6445 port@1 { 6446 reg = <1>; 6447 6448 qdss_tpda_in1: endpoint { 6449 remote-endpoint = <&qdss_tpdm_out>; 6450 }; 6451 }; 6452 }; 6453 6454 out-ports { 6455 port { 6456 qdss_tpda_out: endpoint { 6457 remote-endpoint = <&funnel0_in6>; 6458 }; 6459 }; 6460 }; 6461 }; 6462 6463 tpdm@1000f000 { 6464 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6465 reg = <0x0 0x1000f000 0x0 0x1000>; 6466 6467 clocks = <&aoss_qmp>; 6468 clock-names = "apb_pclk"; 6469 6470 qcom,cmb-element-bits = <32>; 6471 qcom,cmb-msrs-num = <32>; 6472 6473 out-ports { 6474 port { 6475 qdss_tpdm_out: endpoint { 6476 remote-endpoint = <&qdss_tpda_in1>; 6477 }; 6478 }; 6479 }; 6480 }; 6481 6482 funnel@10041000 { 6483 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6484 reg = <0x0 0x10041000 0x0 0x1000>; 6485 6486 clocks = <&aoss_qmp>; 6487 clock-names = "apb_pclk"; 6488 6489 in-ports { 6490 #address-cells = <1>; 6491 #size-cells = <0>; 6492 6493 port@6 { 6494 reg = <6>; 6495 6496 funnel0_in6: endpoint { 6497 remote-endpoint = <&qdss_tpda_out>; 6498 }; 6499 }; 6500 6501 port@7 { 6502 reg = <7>; 6503 6504 funnel0_in7: endpoint { 6505 remote-endpoint = <&stm_out>; 6506 }; 6507 }; 6508 }; 6509 6510 out-ports { 6511 port { 6512 funnel0_out: endpoint { 6513 remote-endpoint = <&qdss_funnel_in0>; 6514 }; 6515 }; 6516 }; 6517 }; 6518 6519 funnel@10042000 { 6520 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6521 reg = <0x0 0x10042000 0x0 0x1000>; 6522 6523 clocks = <&aoss_qmp>; 6524 clock-names = "apb_pclk"; 6525 6526 in-ports { 6527 #address-cells = <1>; 6528 #size-cells = <0>; 6529 6530 port@2 { 6531 reg = <2>; 6532 6533 funnel1_in2: endpoint { 6534 remote-endpoint = <&tmess_funnel_out>; 6535 }; 6536 }; 6537 6538 port@5 { 6539 reg = <5>; 6540 6541 funnel1_in5: endpoint { 6542 remote-endpoint = <&dlst_funnel_out>; 6543 }; 6544 }; 6545 6546 port@6 { 6547 reg = <6>; 6548 6549 funnel1_in6: endpoint { 6550 remote-endpoint = <&dlct1_funnel_out>; 6551 }; 6552 }; 6553 }; 6554 6555 out-ports { 6556 port { 6557 funnel1_out: endpoint { 6558 remote-endpoint = <&qdss_funnel_in1>; 6559 }; 6560 }; 6561 }; 6562 }; 6563 6564 funnel@10045000 { 6565 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6566 reg = <0x0 0x10045000 0x0 0x1000>; 6567 6568 clocks = <&aoss_qmp>; 6569 clock-names = "apb_pclk"; 6570 6571 in-ports { 6572 #address-cells = <1>; 6573 #size-cells = <0>; 6574 6575 port@0 { 6576 reg = <0>; 6577 6578 qdss_funnel_in0: endpoint { 6579 remote-endpoint = <&funnel0_out>; 6580 }; 6581 }; 6582 6583 port@1 { 6584 reg = <1>; 6585 6586 qdss_funnel_in1: endpoint { 6587 remote-endpoint = <&funnel1_out>; 6588 }; 6589 }; 6590 }; 6591 6592 out-ports { 6593 port { 6594 qdss_funnel_out: endpoint { 6595 remote-endpoint = <&aoss_funnel_in7>; 6596 }; 6597 }; 6598 }; 6599 }; 6600 6601 tpdm@10800000 { 6602 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6603 reg = <0x0 0x10800000 0x0 0x1000>; 6604 6605 clocks = <&aoss_qmp>; 6606 clock-names = "apb_pclk"; 6607 6608 qcom,cmb-element-bits = <64>; 6609 qcom,cmb-msrs-num = <32>; 6610 6611 out-ports { 6612 port { 6613 mxa_tpdm_out: endpoint { 6614 remote-endpoint = <&dlct2_tpda_in15>; 6615 }; 6616 }; 6617 }; 6618 }; 6619 6620 tpdm@1082c000 { 6621 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6622 reg = <0x0 0x1082c000 0x0 0x1000>; 6623 6624 clocks = <&aoss_qmp>; 6625 clock-names = "apb_pclk"; 6626 6627 qcom,dsb-element-bits = <32>; 6628 qcom,dsb-msrs-num = <32>; 6629 6630 out-ports { 6631 port { 6632 gcc_tpdm_out: endpoint { 6633 remote-endpoint = <&dlct1_tpda_in21>; 6634 }; 6635 }; 6636 }; 6637 }; 6638 6639 tpdm@10841000 { 6640 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6641 reg = <0x0 0x10841000 0x0 0x1000>; 6642 6643 clocks = <&aoss_qmp>; 6644 clock-names = "apb_pclk"; 6645 6646 qcom,cmb-element-bits = <32>; 6647 qcom,cmb-msrs-num = <32>; 6648 6649 out-ports { 6650 port { 6651 prng_tpdm_out: endpoint { 6652 remote-endpoint = <&dlct1_tpda_in19>; 6653 }; 6654 }; 6655 }; 6656 }; 6657 6658 tpdm@10844000 { 6659 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6660 reg = <0x0 0x10844000 0x0 0x1000>; 6661 6662 clocks = <&aoss_qmp>; 6663 clock-names = "apb_pclk"; 6664 6665 qcom,dsb-element-bits = <32>; 6666 qcom,dsb-msrs-num = <32>; 6667 6668 out-ports { 6669 port { 6670 lpass_cx_tpdm_out: endpoint { 6671 remote-endpoint = <&lpass_cx_funnel_in0>; 6672 }; 6673 }; 6674 }; 6675 }; 6676 6677 funnel@10846000 { 6678 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6679 reg = <0x0 0x10846000 0x0 0x1000>; 6680 6681 clocks = <&aoss_qmp>; 6682 clock-names = "apb_pclk"; 6683 6684 in-ports { 6685 port { 6686 lpass_cx_funnel_in0: endpoint { 6687 remote-endpoint = <&lpass_cx_tpdm_out>; 6688 }; 6689 }; 6690 }; 6691 6692 out-ports { 6693 port { 6694 lpass_cx_funnel_out: endpoint { 6695 remote-endpoint = <&dlct1_tpda_in4>; 6696 }; 6697 }; 6698 }; 6699 }; 6700 6701 cti@1098b000 { 6702 compatible = "arm,coresight-cti", "arm,primecell"; 6703 reg = <0x0 0x1098b000 0x0 0x1000>; 6704 6705 clocks = <&aoss_qmp>; 6706 clock-names = "apb_pclk"; 6707 }; 6708 6709 tpdm@109d0000 { 6710 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6711 reg = <0x0 0x109d0000 0x0 0x1000>; 6712 6713 clocks = <&aoss_qmp>; 6714 clock-names = "apb_pclk"; 6715 6716 qcom,dsb-element-bits = <32>; 6717 qcom,dsb-msrs-num = <32>; 6718 status = "disabled"; 6719 6720 out-ports { 6721 port { 6722 qm_tpdm_out: endpoint { 6723 remote-endpoint = <&dlct1_tpda_in20>; 6724 }; 6725 }; 6726 }; 6727 }; 6728 6729 tpdm@10ac0000 { 6730 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6731 reg = <0x0 0x10ac0000 0x0 0x1000>; 6732 6733 clocks = <&aoss_qmp>; 6734 clock-names = "apb_pclk"; 6735 6736 qcom,dsb-element-bits = <32>; 6737 qcom,dsb-msrs-num = <32>; 6738 status = "disabled"; 6739 6740 out-ports { 6741 port { 6742 dlst_tpdm0_out: endpoint { 6743 remote-endpoint = <&dlst_tpda_in8>; 6744 }; 6745 }; 6746 }; 6747 }; 6748 6749 tpdm@10ac1000 { 6750 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6751 reg = <0x0 0x10ac1000 0x0 0x1000>; 6752 6753 clocks = <&aoss_qmp>; 6754 clock-names = "apb_pclk"; 6755 6756 qcom,cmb-element-bits = <64>; 6757 qcom,cmb-msrs-num = <32>; 6758 6759 out-ports { 6760 port { 6761 dlst_tpdm1_out: endpoint { 6762 remote-endpoint = <&dlst_tpda_in9>; 6763 }; 6764 }; 6765 }; 6766 }; 6767 6768 tpda@10ac4000 { 6769 compatible = "qcom,coresight-tpda", "arm,primecell"; 6770 reg = <0x0 0x10ac4000 0x0 0x1000>; 6771 6772 clocks = <&aoss_qmp>; 6773 clock-names = "apb_pclk"; 6774 6775 in-ports { 6776 #address-cells = <1>; 6777 #size-cells = <0>; 6778 6779 port@8 { 6780 reg = <8>; 6781 6782 dlst_tpda_in8: endpoint { 6783 remote-endpoint = <&dlst_tpdm0_out>; 6784 }; 6785 }; 6786 6787 port@9 { 6788 reg = <9>; 6789 6790 dlst_tpda_in9: endpoint { 6791 remote-endpoint = <&dlst_tpdm1_out>; 6792 }; 6793 }; 6794 }; 6795 6796 out-ports { 6797 port { 6798 dlst_tpda_out: endpoint { 6799 remote-endpoint = <&dlst_funnel_in0>; 6800 }; 6801 }; 6802 }; 6803 }; 6804 6805 funnel@10ac5000 { 6806 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6807 reg = <0x0 0x10ac5000 0x0 0x1000>; 6808 6809 clocks = <&aoss_qmp>; 6810 clock-names = "apb_pclk"; 6811 6812 in-ports { 6813 port { 6814 dlst_funnel_in0: endpoint { 6815 remote-endpoint = <&dlst_tpda_out>; 6816 }; 6817 }; 6818 }; 6819 6820 out-ports { 6821 port { 6822 dlst_funnel_out: endpoint { 6823 remote-endpoint = <&funnel1_in5>; 6824 }; 6825 }; 6826 }; 6827 }; 6828 6829 funnel@10b04000 { 6830 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6831 reg = <0x0 0x10b04000 0x0 0x1000>; 6832 6833 clocks = <&aoss_qmp>; 6834 clock-names = "apb_pclk"; 6835 6836 in-ports { 6837 #address-cells = <1>; 6838 #size-cells = <0>; 6839 6840 port@3 { 6841 reg = <3>; 6842 6843 aoss_funnel_in3: endpoint { 6844 remote-endpoint = <&ddr_lpi_funnel_out>; 6845 }; 6846 }; 6847 6848 port@6 { 6849 reg = <6>; 6850 6851 aoss_funnel_in6: endpoint { 6852 remote-endpoint = <&aoss_tpda_out>; 6853 }; 6854 }; 6855 6856 port@7 { 6857 reg = <7>; 6858 6859 aoss_funnel_in7: endpoint { 6860 remote-endpoint = <&qdss_funnel_out>; 6861 }; 6862 }; 6863 }; 6864 6865 out-ports { 6866 port { 6867 aoss_funnel_out: endpoint { 6868 remote-endpoint = <&etf0_in>; 6869 }; 6870 }; 6871 }; 6872 }; 6873 6874 etf0: tmc@10b05000 { 6875 compatible = "arm,coresight-tmc", "arm,primecell"; 6876 reg = <0x0 0x10b05000 0x0 0x1000>; 6877 6878 clocks = <&aoss_qmp>; 6879 clock-names = "apb_pclk"; 6880 6881 in-ports { 6882 port { 6883 etf0_in: endpoint { 6884 remote-endpoint = <&aoss_funnel_out>; 6885 }; 6886 }; 6887 }; 6888 6889 out-ports { 6890 port { 6891 etf0_out: endpoint { 6892 remote-endpoint = <&swao_rep_in>; 6893 }; 6894 }; 6895 }; 6896 }; 6897 6898 replicator@10b06000 { 6899 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 6900 reg = <0x0 0x10b06000 0x0 0x1000>; 6901 6902 clocks = <&aoss_qmp>; 6903 clock-names = "apb_pclk"; 6904 6905 in-ports { 6906 port { 6907 swao_rep_in: endpoint { 6908 remote-endpoint = <&etf0_out>; 6909 }; 6910 }; 6911 }; 6912 6913 out-ports { 6914 port { 6915 swao_rep_out1: endpoint { 6916 remote-endpoint = <&eud_in>; 6917 }; 6918 }; 6919 }; 6920 }; 6921 6922 tpda@10b08000 { 6923 compatible = "qcom,coresight-tpda", "arm,primecell"; 6924 reg = <0x0 0x10b08000 0x0 0x1000>; 6925 6926 clocks = <&aoss_qmp>; 6927 clock-names = "apb_pclk"; 6928 6929 in-ports { 6930 #address-cells = <1>; 6931 #size-cells = <0>; 6932 6933 port@0 { 6934 reg = <0>; 6935 6936 aoss_tpda_in0: endpoint { 6937 remote-endpoint = <&aoss_tpdm0_out>; 6938 }; 6939 }; 6940 6941 port@1 { 6942 reg = <1>; 6943 6944 aoss_tpda_in1: endpoint { 6945 remote-endpoint = <&aoss_tpdm1_out>; 6946 }; 6947 }; 6948 6949 port@2 { 6950 reg = <2>; 6951 6952 aoss_tpda_in2: endpoint { 6953 remote-endpoint = <&aoss_tpdm2_out>; 6954 }; 6955 }; 6956 6957 port@3 { 6958 reg = <3>; 6959 6960 aoss_tpda_in3: endpoint { 6961 remote-endpoint = <&aoss_tpdm3_out>; 6962 }; 6963 }; 6964 6965 port@4 { 6966 reg = <4>; 6967 6968 aoss_tpda_in4: endpoint { 6969 remote-endpoint = <&aoss_tpdm4_out>; 6970 }; 6971 }; 6972 }; 6973 6974 out-ports { 6975 port { 6976 aoss_tpda_out: endpoint { 6977 remote-endpoint = <&aoss_funnel_in6>; 6978 }; 6979 }; 6980 }; 6981 }; 6982 6983 tpdm@10b09000 { 6984 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6985 reg = <0x0 0x10b09000 0x0 0x1000>; 6986 6987 clocks = <&aoss_qmp>; 6988 clock-names = "apb_pclk"; 6989 6990 qcom,cmb-element-bits = <64>; 6991 qcom,cmb-msrs-num = <32>; 6992 6993 out-ports { 6994 port { 6995 aoss_tpdm0_out: endpoint { 6996 remote-endpoint = <&aoss_tpda_in0>; 6997 }; 6998 }; 6999 }; 7000 }; 7001 7002 tpdm@10b0a000 { 7003 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7004 reg = <0x0 0x10b0a000 0x0 0x1000>; 7005 7006 clocks = <&aoss_qmp>; 7007 clock-names = "apb_pclk"; 7008 7009 qcom,cmb-element-bits = <64>; 7010 qcom,cmb-msrs-num = <32>; 7011 7012 out-ports { 7013 port { 7014 aoss_tpdm1_out: endpoint { 7015 remote-endpoint = <&aoss_tpda_in1>; 7016 }; 7017 }; 7018 }; 7019 }; 7020 7021 tpdm@10b0b000 { 7022 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7023 reg = <0x0 0x10b0b000 0x0 0x1000>; 7024 7025 clocks = <&aoss_qmp>; 7026 clock-names = "apb_pclk"; 7027 7028 qcom,cmb-element-bits = <64>; 7029 qcom,cmb-msrs-num = <32>; 7030 7031 out-ports { 7032 port { 7033 aoss_tpdm2_out: endpoint { 7034 remote-endpoint = <&aoss_tpda_in2>; 7035 }; 7036 }; 7037 }; 7038 }; 7039 7040 tpdm@10b0c000 { 7041 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7042 reg = <0x0 0x10b0c000 0x0 0x1000>; 7043 7044 clocks = <&aoss_qmp>; 7045 clock-names = "apb_pclk"; 7046 7047 qcom,cmb-element-bits = <64>; 7048 qcom,cmb-msrs-num = <32>; 7049 7050 out-ports { 7051 port { 7052 aoss_tpdm3_out: endpoint { 7053 remote-endpoint = <&aoss_tpda_in3>; 7054 }; 7055 }; 7056 }; 7057 }; 7058 7059 tpdm@10b0d000 { 7060 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7061 reg = <0x0 0x10b0d000 0x0 0x1000>; 7062 7063 clocks = <&aoss_qmp>; 7064 clock-names = "apb_pclk"; 7065 7066 qcom,dsb-element-bits = <32>; 7067 qcom,dsb-msrs-num = <32>; 7068 7069 out-ports { 7070 port { 7071 aoss_tpdm4_out: endpoint { 7072 remote-endpoint = <&aoss_tpda_in4>; 7073 }; 7074 }; 7075 }; 7076 }; 7077 7078 tpdm@10b20000 { 7079 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7080 reg = <0x0 0x10b20000 0x0 0x1000>; 7081 7082 clocks = <&aoss_qmp>; 7083 clock-names = "apb_pclk"; 7084 7085 qcom,dsb-element-bits = <32>; 7086 qcom,dsb-msrs-num = <32>; 7087 status = "disabled"; 7088 7089 out-ports { 7090 port { 7091 lpicc_tpdm_out: endpoint { 7092 remote-endpoint = <&ddr_lpi_tpda_in>; 7093 }; 7094 }; 7095 }; 7096 }; 7097 7098 tpda@10b23000 { 7099 compatible = "qcom,coresight-tpda", "arm,primecell"; 7100 reg = <0x0 0x10b23000 0x0 0x1000>; 7101 7102 clocks = <&aoss_qmp>; 7103 clock-names = "apb_pclk"; 7104 status = "disabled"; 7105 7106 in-ports { 7107 port { 7108 ddr_lpi_tpda_in: endpoint { 7109 remote-endpoint = <&lpicc_tpdm_out>; 7110 }; 7111 }; 7112 }; 7113 7114 out-ports { 7115 port { 7116 ddr_lpi_tpda_out: endpoint { 7117 remote-endpoint = <&ddr_lpi_funnel_in0>; 7118 }; 7119 }; 7120 }; 7121 }; 7122 7123 funnel@10b24000 { 7124 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7125 reg = <0x0 0x10b24000 0x0 0x1000>; 7126 7127 clocks = <&aoss_qmp>; 7128 clock-names = "apb_pclk"; 7129 status = "disabled"; 7130 7131 in-ports { 7132 port { 7133 ddr_lpi_funnel_in0: endpoint { 7134 remote-endpoint = <&ddr_lpi_tpda_out>; 7135 }; 7136 }; 7137 }; 7138 7139 out-ports { 7140 port { 7141 ddr_lpi_funnel_out: endpoint { 7142 remote-endpoint = <&aoss_funnel_in3>; 7143 }; 7144 }; 7145 }; 7146 }; 7147 7148 tpdm@10c08000 { 7149 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7150 reg = <0x0 0x10c08000 0x0 0x1000>; 7151 7152 clocks = <&aoss_qmp>; 7153 clock-names = "apb_pclk"; 7154 7155 qcom,dsb-element-bits = <32>; 7156 qcom,dsb-msrs-num = <32>; 7157 7158 out-ports { 7159 port { 7160 mm_tpdm_out: endpoint { 7161 remote-endpoint = <&mm_funnel_in4>; 7162 }; 7163 }; 7164 }; 7165 }; 7166 7167 funnel@10c0b000 { 7168 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7169 reg = <0x0 0x10c0b000 0x0 0x1000>; 7170 7171 clocks = <&aoss_qmp>; 7172 clock-names = "apb_pclk"; 7173 7174 in-ports { 7175 #address-cells = <1>; 7176 #size-cells = <0>; 7177 7178 port@4 { 7179 reg = <4>; 7180 7181 mm_funnel_in4: endpoint { 7182 remote-endpoint = <&mm_tpdm_out>; 7183 }; 7184 }; 7185 }; 7186 7187 out-ports { 7188 port { 7189 mm_funnel_out: endpoint { 7190 remote-endpoint = <&dlct2_tpda_in4>; 7191 }; 7192 }; 7193 }; 7194 }; 7195 7196 tpdm@10c28000 { 7197 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7198 reg = <0x0 0x10c28000 0x0 0x1000>; 7199 7200 clocks = <&aoss_qmp>; 7201 clock-names = "apb_pclk"; 7202 7203 qcom,dsb-element-bits = <32>; 7204 qcom,dsb-msrs-num = <32>; 7205 7206 out-ports { 7207 port { 7208 dlct1_tpdm_out: endpoint { 7209 remote-endpoint = <&dlct1_tpda_in26>; 7210 }; 7211 }; 7212 }; 7213 }; 7214 7215 tpdm@10c29000 { 7216 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7217 reg = <0x0 0x10c29000 0x0 0x1000>; 7218 7219 clocks = <&aoss_qmp>; 7220 clock-names = "apb_pclk"; 7221 7222 qcom,cmb-element-bits = <64>; 7223 qcom,cmb-msrs-num = <32>; 7224 7225 out-ports { 7226 port { 7227 ipcc_tpdm_out: endpoint { 7228 remote-endpoint = <&dlct1_tpda_in27>; 7229 }; 7230 }; 7231 }; 7232 }; 7233 7234 tpda@10c2b000 { 7235 compatible = "qcom,coresight-tpda", "arm,primecell"; 7236 reg = <0x0 0x10c2b000 0x0 0x1000>; 7237 7238 clocks = <&aoss_qmp>; 7239 clock-names = "apb_pclk"; 7240 7241 in-ports { 7242 #address-cells = <1>; 7243 #size-cells = <0>; 7244 7245 port@4 { 7246 reg = <4>; 7247 7248 dlct1_tpda_in4: endpoint { 7249 remote-endpoint = <&lpass_cx_funnel_out>; 7250 }; 7251 }; 7252 7253 port@13 { 7254 reg = <19>; 7255 7256 dlct1_tpda_in19: endpoint { 7257 remote-endpoint = <&prng_tpdm_out>; 7258 }; 7259 }; 7260 7261 port@14 { 7262 reg = <20>; 7263 7264 dlct1_tpda_in20: endpoint { 7265 remote-endpoint = <&qm_tpdm_out>; 7266 }; 7267 }; 7268 7269 port@15 { 7270 reg = <21>; 7271 7272 dlct1_tpda_in21: endpoint { 7273 remote-endpoint = <&gcc_tpdm_out>; 7274 }; 7275 }; 7276 7277 port@1a { 7278 reg = <26>; 7279 7280 dlct1_tpda_in26: endpoint { 7281 remote-endpoint = <&dlct1_tpdm_out>; 7282 }; 7283 }; 7284 7285 port@1b { 7286 reg = <27>; 7287 7288 dlct1_tpda_in27: endpoint { 7289 remote-endpoint = <&ipcc_tpdm_out>; 7290 }; 7291 }; 7292 }; 7293 7294 out-ports { 7295 port { 7296 dlct1_tpda_out: endpoint { 7297 remote-endpoint = <&dlct1_funnel_in0>; 7298 }; 7299 }; 7300 }; 7301 }; 7302 7303 funnel@10c2c000 { 7304 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7305 reg = <0x0 0x10c2c000 0x0 0x1000>; 7306 7307 clocks = <&aoss_qmp>; 7308 clock-names = "apb_pclk"; 7309 7310 in-ports { 7311 #address-cells = <1>; 7312 #size-cells = <0>; 7313 7314 port@0 { 7315 reg = <0>; 7316 7317 dlct1_funnel_in0: endpoint { 7318 remote-endpoint = <&dlct1_tpda_out>; 7319 }; 7320 }; 7321 7322 port@4 { 7323 reg = <4>; 7324 7325 dlct1_funnel_in4: endpoint { 7326 remote-endpoint = <&dlct2_funnel_out>; 7327 }; 7328 }; 7329 7330 port@5 { 7331 reg = <5>; 7332 7333 dlct1_funnel_in5: endpoint { 7334 remote-endpoint = <&ddr_funnel0_out>; 7335 }; 7336 }; 7337 }; 7338 7339 out-ports { 7340 port { 7341 dlct1_funnel_out: endpoint { 7342 remote-endpoint = <&funnel1_in6>; 7343 }; 7344 }; 7345 }; 7346 }; 7347 7348 tpdm@10c38000 { 7349 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7350 reg = <0x0 0x10c38000 0x0 0x1000>; 7351 7352 clocks = <&aoss_qmp>; 7353 clock-names = "apb_pclk"; 7354 7355 qcom,cmb-element-bits = <64>; 7356 qcom,cmb-msrs-num = <32>; 7357 7358 out-ports { 7359 port { 7360 dlct2_tpdm0_out: endpoint { 7361 remote-endpoint = <&dlct2_tpda_in16>; 7362 }; 7363 }; 7364 }; 7365 }; 7366 7367 tpdm@10c39000 { 7368 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7369 reg = <0x0 0x10c39000 0x0 0x1000>; 7370 7371 clocks = <&aoss_qmp>; 7372 clock-names = "apb_pclk"; 7373 7374 qcom,cmb-element-bits = <64>; 7375 qcom,cmb-msrs-num = <32>; 7376 7377 out-ports { 7378 port { 7379 dlct2_tpdm1_out: endpoint { 7380 remote-endpoint = <&dlct2_tpda_in17>; 7381 }; 7382 }; 7383 }; 7384 }; 7385 7386 tpda@10c3c000 { 7387 compatible = "qcom,coresight-tpda", "arm,primecell"; 7388 reg = <0x0 0x10c3c000 0x0 0x1000>; 7389 7390 clocks = <&aoss_qmp>; 7391 clock-names = "apb_pclk"; 7392 7393 in-ports { 7394 #address-cells = <1>; 7395 #size-cells = <0>; 7396 7397 port@4 { 7398 reg = <4>; 7399 7400 dlct2_tpda_in4: endpoint { 7401 remote-endpoint = <&mm_funnel_out>; 7402 }; 7403 }; 7404 7405 port@f { 7406 reg = <15>; 7407 7408 dlct2_tpda_in15: endpoint { 7409 remote-endpoint = <&mxa_tpdm_out>; 7410 }; 7411 }; 7412 7413 port@10 { 7414 reg = <16>; 7415 7416 dlct2_tpda_in16: endpoint { 7417 remote-endpoint = <&dlct2_tpdm0_out>; 7418 }; 7419 }; 7420 7421 port@11 { 7422 reg = <17>; 7423 7424 dlct2_tpda_in17: endpoint { 7425 remote-endpoint = <&dlct2_tpdm1_out>; 7426 }; 7427 }; 7428 }; 7429 7430 out-ports { 7431 port { 7432 dlct2_tpda_out: endpoint { 7433 remote-endpoint = <&dlct2_funnel_in0>; 7434 }; 7435 }; 7436 }; 7437 }; 7438 7439 funnel@10c3d000 { 7440 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7441 reg = <0x0 0x10c3d000 0x0 0x1000>; 7442 7443 clocks = <&aoss_qmp>; 7444 clock-names = "apb_pclk"; 7445 7446 in-ports { 7447 port { 7448 dlct2_funnel_in0: endpoint { 7449 remote-endpoint = <&dlct2_tpda_out>; 7450 }; 7451 }; 7452 }; 7453 7454 out-ports { 7455 port { 7456 dlct2_funnel_out: endpoint { 7457 remote-endpoint = <&dlct1_funnel_in4>; 7458 }; 7459 }; 7460 }; 7461 }; 7462 7463 tpdm@10cc1000 { 7464 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7465 reg = <0x0 0x10cc1000 0x0 0x1000>; 7466 7467 clocks = <&aoss_qmp>; 7468 clock-names = "apb_pclk"; 7469 7470 qcom,cmb-element-bits = <64>; 7471 qcom,cmb-msrs-num = <32>; 7472 qcom,dsb-element-bits = <32>; 7473 qcom,dsb-msrs-num = <32>; 7474 status = "disabled"; 7475 7476 out-ports { 7477 port { 7478 tmess_tpdm1_out: endpoint { 7479 remote-endpoint = <&tmess_tpda_in2>; 7480 }; 7481 }; 7482 }; 7483 }; 7484 7485 tpda@10cc4000 { 7486 compatible = "qcom,coresight-tpda", "arm,primecell"; 7487 reg = <0x0 0x10cc4000 0x0 0x1000>; 7488 7489 clocks = <&aoss_qmp>; 7490 clock-names = "apb_pclk"; 7491 7492 in-ports { 7493 #address-cells = <1>; 7494 #size-cells = <0>; 7495 7496 port@2 { 7497 reg = <2>; 7498 7499 tmess_tpda_in2: endpoint { 7500 remote-endpoint = <&tmess_tpdm1_out>; 7501 }; 7502 }; 7503 }; 7504 7505 out-ports { 7506 port { 7507 tmess_tpda_out: endpoint { 7508 remote-endpoint = <&tmess_funnel_in0>; 7509 }; 7510 }; 7511 }; 7512 }; 7513 7514 funnel@10cc5000 { 7515 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7516 reg = <0x0 0x10cc5000 0x0 0x1000>; 7517 7518 clocks = <&aoss_qmp>; 7519 clock-names = "apb_pclk"; 7520 7521 in-ports { 7522 port { 7523 tmess_funnel_in0: endpoint { 7524 remote-endpoint = <&tmess_tpda_out>; 7525 }; 7526 }; 7527 }; 7528 7529 out-ports { 7530 port { 7531 tmess_funnel_out: endpoint { 7532 remote-endpoint = <&funnel1_in2>; 7533 }; 7534 }; 7535 }; 7536 }; 7537 7538 funnel@10d04000 { 7539 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7540 reg = <0x0 0x10d04000 0x0 0x1000>; 7541 7542 clocks = <&aoss_qmp>; 7543 clock-names = "apb_pclk"; 7544 7545 in-ports { 7546 #address-cells = <1>; 7547 #size-cells = <0>; 7548 7549 port@6 { 7550 reg = <6>; 7551 7552 ddr_funnel0_in6: endpoint { 7553 remote-endpoint = <&ddr_funnel1_out>; 7554 }; 7555 }; 7556 }; 7557 7558 out-ports { 7559 port { 7560 ddr_funnel0_out: endpoint { 7561 remote-endpoint = <&dlct1_funnel_in5>; 7562 }; 7563 }; 7564 }; 7565 }; 7566 7567 tpdm@10d08000 { 7568 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7569 reg = <0x0 0x10d08000 0x0 0x1000>; 7570 7571 clocks = <&aoss_qmp>; 7572 clock-names = "apb_pclk"; 7573 7574 qcom,cmb-element-bits = <32>; 7575 qcom,cmb-msrs-num = <32>; 7576 7577 out-ports { 7578 port { 7579 llcc0_tpdm_out: endpoint { 7580 remote-endpoint = <&llcc_tpda_in0>; 7581 }; 7582 }; 7583 }; 7584 }; 7585 7586 tpdm@10d09000 { 7587 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7588 reg = <0x0 0x10d09000 0x0 0x1000>; 7589 7590 clocks = <&aoss_qmp>; 7591 clock-names = "apb_pclk"; 7592 7593 qcom,cmb-element-bits = <32>; 7594 qcom,cmb-msrs-num = <32>; 7595 7596 out-ports { 7597 port { 7598 llcc1_tpdm_out: endpoint { 7599 remote-endpoint = <&llcc_tpda_in1>; 7600 }; 7601 }; 7602 }; 7603 }; 7604 7605 tpdm@10d0a000 { 7606 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7607 reg = <0x0 0x10d0a000 0x0 0x1000>; 7608 7609 clocks = <&aoss_qmp>; 7610 clock-names = "apb_pclk"; 7611 7612 qcom,cmb-element-bits = <32>; 7613 qcom,cmb-msrs-num = <32>; 7614 7615 out-ports { 7616 port { 7617 llcc2_tpdm_out: endpoint { 7618 remote-endpoint = <&llcc_tpda_in2>; 7619 }; 7620 }; 7621 }; 7622 }; 7623 7624 tpdm@10d0b000 { 7625 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7626 reg = <0x0 0x10d0b000 0x0 0x1000>; 7627 7628 clocks = <&aoss_qmp>; 7629 clock-names = "apb_pclk"; 7630 7631 qcom,cmb-element-bits = <32>; 7632 qcom,cmb-msrs-num = <32>; 7633 7634 out-ports { 7635 port { 7636 llcc3_tpdm_out: endpoint { 7637 remote-endpoint = <&llcc_tpda_in3>; 7638 }; 7639 }; 7640 }; 7641 }; 7642 7643 tpdm@10d0c000 { 7644 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7645 reg = <0x0 0x10d0c000 0x0 0x1000>; 7646 7647 clocks = <&aoss_qmp>; 7648 clock-names = "apb_pclk"; 7649 7650 qcom,cmb-element-bits = <32>; 7651 qcom,cmb-msrs-num = <32>; 7652 7653 out-ports { 7654 port { 7655 llcc4_tpdm_out: endpoint { 7656 remote-endpoint = <&llcc_tpda_in4>; 7657 }; 7658 }; 7659 }; 7660 }; 7661 7662 tpdm@10d0d000 { 7663 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7664 reg = <0x0 0x10d0d000 0x0 0x1000>; 7665 7666 clocks = <&aoss_qmp>; 7667 clock-names = "apb_pclk"; 7668 7669 qcom,cmb-element-bits = <32>; 7670 qcom,cmb-msrs-num = <32>; 7671 7672 out-ports { 7673 port { 7674 llcc5_tpdm_out: endpoint { 7675 remote-endpoint = <&llcc_tpda_in5>; 7676 }; 7677 }; 7678 }; 7679 }; 7680 7681 tpdm@10d0e000 { 7682 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7683 reg = <0x0 0x10d0e000 0x0 0x1000>; 7684 7685 clocks = <&aoss_qmp>; 7686 clock-names = "apb_pclk"; 7687 7688 qcom,cmb-element-bits = <32>; 7689 qcom,cmb-msrs-num = <32>; 7690 7691 out-ports { 7692 port { 7693 llcc6_tpdm_out: endpoint { 7694 remote-endpoint = <&llcc_tpda_in6>; 7695 }; 7696 }; 7697 }; 7698 }; 7699 7700 tpdm@10d0f000 { 7701 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7702 reg = <0x0 0x10d0f000 0x0 0x1000>; 7703 7704 clocks = <&aoss_qmp>; 7705 clock-names = "apb_pclk"; 7706 7707 qcom,cmb-element-bits = <32>; 7708 qcom,cmb-msrs-num = <32>; 7709 7710 out-ports { 7711 port { 7712 llcc7_tpdm_out: endpoint { 7713 remote-endpoint = <&llcc_tpda_in7>; 7714 }; 7715 }; 7716 }; 7717 }; 7718 7719 tpda@10d12000 { 7720 compatible = "qcom,coresight-tpda", "arm,primecell"; 7721 reg = <0x0 0x10d12000 0x0 0x1000>; 7722 7723 clocks = <&aoss_qmp>; 7724 clock-names = "apb_pclk"; 7725 7726 in-ports { 7727 #address-cells = <1>; 7728 #size-cells = <0>; 7729 7730 port@0 { 7731 reg = <0>; 7732 7733 llcc_tpda_in0: endpoint { 7734 remote-endpoint = <&llcc0_tpdm_out>; 7735 }; 7736 }; 7737 7738 port@1 { 7739 reg = <1>; 7740 7741 llcc_tpda_in1: endpoint { 7742 remote-endpoint = <&llcc1_tpdm_out>; 7743 }; 7744 }; 7745 7746 port@2 { 7747 reg = <2>; 7748 7749 llcc_tpda_in2: endpoint { 7750 remote-endpoint = <&llcc2_tpdm_out>; 7751 }; 7752 }; 7753 7754 port@3 { 7755 reg = <3>; 7756 7757 llcc_tpda_in3: endpoint { 7758 remote-endpoint = <&llcc3_tpdm_out>; 7759 }; 7760 }; 7761 7762 port@4 { 7763 reg = <4>; 7764 7765 llcc_tpda_in4: endpoint { 7766 remote-endpoint = <&llcc4_tpdm_out>; 7767 }; 7768 }; 7769 7770 port@5 { 7771 reg = <5>; 7772 7773 llcc_tpda_in5: endpoint { 7774 remote-endpoint = <&llcc5_tpdm_out>; 7775 }; 7776 }; 7777 7778 port@6 { 7779 reg = <6>; 7780 7781 llcc_tpda_in6: endpoint { 7782 remote-endpoint = <&llcc6_tpdm_out>; 7783 }; 7784 }; 7785 7786 port@7 { 7787 reg = <7>; 7788 7789 llcc_tpda_in7: endpoint { 7790 remote-endpoint = <&llcc7_tpdm_out>; 7791 }; 7792 }; 7793 }; 7794 7795 out-ports { 7796 port { 7797 llcc_tpda_out: endpoint { 7798 remote-endpoint = <&ddr_funnel1_in0>; 7799 }; 7800 }; 7801 }; 7802 }; 7803 7804 funnel@10d13000 { 7805 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7806 reg = <0x0 0x10d13000 0x0 0x1000>; 7807 7808 clocks = <&aoss_qmp>; 7809 clock-names = "apb_pclk"; 7810 7811 in-ports { 7812 port { 7813 ddr_funnel1_in0: endpoint { 7814 remote-endpoint = <&llcc_tpda_out>; 7815 }; 7816 }; 7817 }; 7818 7819 out-ports { 7820 port { 7821 ddr_funnel1_out: endpoint { 7822 remote-endpoint = <&ddr_funnel0_in6>; 7823 }; 7824 }; 7825 }; 7826 }; 7827 7828 apps_smmu: iommu@15000000 { 7829 compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 7830 reg = <0 0x15000000 0 0x100000>; 7831 7832 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 7833 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 7834 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 7835 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 7836 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 7837 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 7838 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 7839 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 7840 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 7841 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 7842 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 7843 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 7844 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 7845 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 7846 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 7847 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 7848 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 7849 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 7850 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 7851 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 7852 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 7853 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 7854 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 7855 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 7856 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 7857 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 7858 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 7859 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 7860 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 7861 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 7862 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 7863 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 7864 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 7865 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 7866 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 7867 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 7868 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 7869 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 7870 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 7871 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 7872 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 7873 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 7874 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 7875 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 7876 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 7877 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 7878 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 7879 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 7880 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 7881 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 7882 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 7883 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 7884 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 7885 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 7886 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 7887 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 7888 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 7889 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 7890 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 7891 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 7892 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 7893 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 7894 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 7895 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 7896 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 7897 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 7898 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 7899 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 7900 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 7901 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 7902 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 7903 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 7904 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 7905 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 7906 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 7907 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 7908 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 7909 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 7910 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 7911 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 7912 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 7913 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 7914 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 7915 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 7916 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 7917 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 7918 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 7919 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 7920 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 7921 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 7922 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 7923 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 7924 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 7925 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 7926 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 7927 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 7928 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 7929 7930 #iommu-cells = <2>; 7931 #global-interrupts = <1>; 7932 7933 dma-coherent; 7934 }; 7935 7936 intc: interrupt-controller@17000000 { 7937 compatible = "arm,gic-v3"; 7938 reg = <0 0x17000000 0 0x10000>, /* GICD */ 7939 <0 0x17080000 0 0x300000>; /* GICR * 12 */ 7940 7941 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 7942 7943 #interrupt-cells = <3>; 7944 interrupt-controller; 7945 7946 #redistributor-regions = <1>; 7947 redistributor-stride = <0x0 0x40000>; 7948 7949 #address-cells = <2>; 7950 #size-cells = <2>; 7951 ranges; 7952 7953 gic_its: msi-controller@17040000 { 7954 compatible = "arm,gic-v3-its"; 7955 reg = <0 0x17040000 0 0x40000>; 7956 7957 msi-controller; 7958 #msi-cells = <1>; 7959 }; 7960 }; 7961 7962 apps_rsc: rsc@17500000 { 7963 compatible = "qcom,rpmh-rsc"; 7964 reg = <0 0x17500000 0 0x10000>, 7965 <0 0x17510000 0 0x10000>, 7966 <0 0x17520000 0 0x10000>; 7967 reg-names = "drv-0", "drv-1", "drv-2"; 7968 7969 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7970 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7971 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 7972 qcom,tcs-offset = <0xd00>; 7973 qcom,drv-id = <2>; 7974 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 7975 <WAKE_TCS 2>, <CONTROL_TCS 0>; 7976 7977 label = "apps_rsc"; 7978 power-domains = <&system_pd>; 7979 7980 apps_bcm_voter: bcm-voter { 7981 compatible = "qcom,bcm-voter"; 7982 }; 7983 7984 rpmhcc: clock-controller { 7985 compatible = "qcom,x1e80100-rpmh-clk"; 7986 7987 clocks = <&xo_board>; 7988 clock-names = "xo"; 7989 7990 #clock-cells = <1>; 7991 }; 7992 7993 rpmhpd: power-controller { 7994 compatible = "qcom,x1e80100-rpmhpd"; 7995 7996 operating-points-v2 = <&rpmhpd_opp_table>; 7997 7998 #power-domain-cells = <1>; 7999 8000 rpmhpd_opp_table: opp-table { 8001 compatible = "operating-points-v2"; 8002 8003 rpmhpd_opp_ret: opp-16 { 8004 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 8005 }; 8006 8007 rpmhpd_opp_min_svs: opp-48 { 8008 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 8009 }; 8010 8011 rpmhpd_opp_low_svs_d2: opp-52 { 8012 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 8013 }; 8014 8015 rpmhpd_opp_low_svs_d1: opp-56 { 8016 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 8017 }; 8018 8019 rpmhpd_opp_low_svs_d0: opp-60 { 8020 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 8021 }; 8022 8023 rpmhpd_opp_low_svs: opp-64 { 8024 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 8025 }; 8026 8027 rpmhpd_opp_low_svs_l1: opp-80 { 8028 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 8029 }; 8030 8031 rpmhpd_opp_svs: opp-128 { 8032 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 8033 }; 8034 8035 rpmhpd_opp_svs_l0: opp-144 { 8036 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 8037 }; 8038 8039 rpmhpd_opp_svs_l1: opp-192 { 8040 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 8041 }; 8042 8043 rpmhpd_opp_nom: opp-256 { 8044 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 8045 }; 8046 8047 rpmhpd_opp_nom_l1: opp-320 { 8048 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 8049 }; 8050 8051 rpmhpd_opp_nom_l2: opp-336 { 8052 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 8053 }; 8054 8055 rpmhpd_opp_turbo: opp-384 { 8056 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 8057 }; 8058 8059 rpmhpd_opp_turbo_l1: opp-416 { 8060 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 8061 }; 8062 }; 8063 }; 8064 }; 8065 8066 timer@17800000 { 8067 compatible = "arm,armv7-timer-mem"; 8068 reg = <0 0x17800000 0 0x1000>; 8069 8070 #address-cells = <2>; 8071 #size-cells = <1>; 8072 ranges = <0 0 0 0 0x20000000>; 8073 8074 frame@17801000 { 8075 reg = <0 0x17801000 0x1000>, 8076 <0 0x17802000 0x1000>; 8077 8078 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 8079 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 8080 8081 frame-number = <0>; 8082 }; 8083 8084 frame@17803000 { 8085 reg = <0 0x17803000 0x1000>; 8086 8087 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 8088 8089 frame-number = <1>; 8090 8091 status = "disabled"; 8092 }; 8093 8094 frame@17805000 { 8095 reg = <0 0x17805000 0x1000>; 8096 8097 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 8098 8099 frame-number = <2>; 8100 8101 status = "disabled"; 8102 }; 8103 8104 frame@17807000 { 8105 reg = <0 0x17807000 0x1000>; 8106 8107 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 8108 8109 frame-number = <3>; 8110 8111 status = "disabled"; 8112 }; 8113 8114 frame@17809000 { 8115 reg = <0 0x17809000 0x1000>; 8116 8117 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 8118 8119 frame-number = <4>; 8120 8121 status = "disabled"; 8122 }; 8123 8124 frame@1780b000 { 8125 reg = <0 0x1780b000 0x1000>; 8126 8127 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8128 8129 frame-number = <5>; 8130 8131 status = "disabled"; 8132 }; 8133 8134 frame@1780d000 { 8135 reg = <0 0x1780d000 0x1000>; 8136 8137 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8138 8139 frame-number = <6>; 8140 8141 status = "disabled"; 8142 }; 8143 }; 8144 8145 pmu@24091000 { 8146 compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 8147 reg = <0 0x24091000 0 0x1000>; 8148 8149 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 8150 8151 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 8152 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 8153 8154 operating-points-v2 = <&llcc_bwmon_opp_table>; 8155 8156 llcc_bwmon_opp_table: opp-table { 8157 compatible = "operating-points-v2"; 8158 8159 opp-0 { 8160 opp-peak-kBps = <800000>; 8161 }; 8162 8163 opp-1 { 8164 opp-peak-kBps = <2188000>; 8165 }; 8166 8167 opp-2 { 8168 opp-peak-kBps = <3072000>; 8169 }; 8170 8171 opp-3 { 8172 opp-peak-kBps = <6220800>; 8173 }; 8174 8175 opp-4 { 8176 opp-peak-kBps = <6835200>; 8177 }; 8178 8179 opp-5 { 8180 opp-peak-kBps = <8371200>; 8181 }; 8182 8183 opp-6 { 8184 opp-peak-kBps = <10944000>; 8185 }; 8186 8187 opp-7 { 8188 opp-peak-kBps = <12748800>; 8189 }; 8190 8191 opp-8 { 8192 opp-peak-kBps = <14745600>; 8193 }; 8194 8195 opp-9 { 8196 opp-peak-kBps = <16896000>; 8197 }; 8198 }; 8199 }; 8200 8201 /* cluster0 */ 8202 pmu@240b3400 { 8203 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8204 reg = <0 0x240b3400 0 0x600>; 8205 8206 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8207 8208 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8209 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8210 8211 operating-points-v2 = <&cpu_bwmon_opp_table>; 8212 8213 cpu_bwmon_opp_table: opp-table { 8214 compatible = "operating-points-v2"; 8215 8216 opp-0 { 8217 opp-peak-kBps = <4800000>; 8218 }; 8219 8220 opp-1 { 8221 opp-peak-kBps = <7464000>; 8222 }; 8223 8224 opp-2 { 8225 opp-peak-kBps = <9600000>; 8226 }; 8227 8228 opp-3 { 8229 opp-peak-kBps = <12896000>; 8230 }; 8231 8232 opp-4 { 8233 opp-peak-kBps = <14928000>; 8234 }; 8235 8236 opp-5 { 8237 opp-peak-kBps = <17064000>; 8238 }; 8239 }; 8240 }; 8241 8242 /* cluster2 */ 8243 pmu@240b5400 { 8244 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8245 reg = <0 0x240b5400 0 0x600>; 8246 8247 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8248 8249 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8250 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8251 8252 operating-points-v2 = <&cpu_bwmon_opp_table>; 8253 }; 8254 8255 /* cluster1 */ 8256 pmu@240b6400 { 8257 compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon"; 8258 reg = <0 0x240b6400 0 0x600>; 8259 8260 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 8261 8262 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 8263 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 8264 8265 operating-points-v2 = <&cpu_bwmon_opp_table>; 8266 }; 8267 8268 system-cache-controller@25000000 { 8269 compatible = "qcom,x1e80100-llcc"; 8270 reg = <0 0x25000000 0 0x200000>, 8271 <0 0x25200000 0 0x200000>, 8272 <0 0x25400000 0 0x200000>, 8273 <0 0x25600000 0 0x200000>, 8274 <0 0x25800000 0 0x200000>, 8275 <0 0x25a00000 0 0x200000>, 8276 <0 0x25c00000 0 0x200000>, 8277 <0 0x25e00000 0 0x200000>, 8278 <0 0x26000000 0 0x200000>, 8279 <0 0x26200000 0 0x200000>; 8280 reg-names = "llcc0_base", 8281 "llcc1_base", 8282 "llcc2_base", 8283 "llcc3_base", 8284 "llcc4_base", 8285 "llcc5_base", 8286 "llcc6_base", 8287 "llcc7_base", 8288 "llcc_broadcast_base", 8289 "llcc_broadcast_and_base"; 8290 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 8291 }; 8292 8293 remoteproc_cdsp: remoteproc@32300000 { 8294 compatible = "qcom,x1e80100-cdsp-pas"; 8295 reg = <0x0 0x32300000 0x0 0x10000>; 8296 8297 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 8298 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 8299 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 8300 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 8301 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 8302 interrupt-names = "wdog", 8303 "fatal", 8304 "ready", 8305 "handover", 8306 "stop-ack"; 8307 8308 clocks = <&rpmhcc RPMH_CXO_CLK>; 8309 clock-names = "xo"; 8310 8311 power-domains = <&rpmhpd RPMHPD_CX>, 8312 <&rpmhpd RPMHPD_MXC>, 8313 <&rpmhpd RPMHPD_NSP>; 8314 power-domain-names = "cx", 8315 "mxc", 8316 "nsp"; 8317 8318 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 8319 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 8320 8321 memory-region = <&cdsp_mem>, 8322 <&q6_cdsp_dtb_mem>; 8323 8324 qcom,qmp = <&aoss_qmp>; 8325 8326 qcom,smem-states = <&smp2p_cdsp_out 0>; 8327 qcom,smem-state-names = "stop"; 8328 8329 status = "disabled"; 8330 8331 glink-edge { 8332 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 8333 IPCC_MPROC_SIGNAL_GLINK_QMP 8334 IRQ_TYPE_EDGE_RISING>; 8335 mboxes = <&ipcc IPCC_CLIENT_CDSP 8336 IPCC_MPROC_SIGNAL_GLINK_QMP>; 8337 8338 label = "cdsp"; 8339 qcom,remote-pid = <5>; 8340 8341 fastrpc { 8342 compatible = "qcom,fastrpc"; 8343 qcom,glink-channels = "fastrpcglink-apps-dsp"; 8344 label = "cdsp"; 8345 qcom,non-secure-domain; 8346 #address-cells = <1>; 8347 #size-cells = <0>; 8348 8349 compute-cb@1 { 8350 compatible = "qcom,fastrpc-compute-cb"; 8351 reg = <1>; 8352 iommus = <&apps_smmu 0x0c01 0x20>; 8353 dma-coherent; 8354 }; 8355 8356 compute-cb@2 { 8357 compatible = "qcom,fastrpc-compute-cb"; 8358 reg = <2>; 8359 iommus = <&apps_smmu 0x0c02 0x20>; 8360 dma-coherent; 8361 }; 8362 8363 compute-cb@3 { 8364 compatible = "qcom,fastrpc-compute-cb"; 8365 reg = <3>; 8366 iommus = <&apps_smmu 0x0c03 0x20>; 8367 dma-coherent; 8368 }; 8369 8370 compute-cb@4 { 8371 compatible = "qcom,fastrpc-compute-cb"; 8372 reg = <4>; 8373 iommus = <&apps_smmu 0x0c04 0x20>; 8374 dma-coherent; 8375 }; 8376 8377 compute-cb@5 { 8378 compatible = "qcom,fastrpc-compute-cb"; 8379 reg = <5>; 8380 iommus = <&apps_smmu 0x0c05 0x20>; 8381 dma-coherent; 8382 }; 8383 8384 compute-cb@6 { 8385 compatible = "qcom,fastrpc-compute-cb"; 8386 reg = <6>; 8387 iommus = <&apps_smmu 0x0c06 0x20>; 8388 dma-coherent; 8389 }; 8390 8391 compute-cb@7 { 8392 compatible = "qcom,fastrpc-compute-cb"; 8393 reg = <7>; 8394 iommus = <&apps_smmu 0x0c07 0x20>; 8395 dma-coherent; 8396 }; 8397 8398 compute-cb@8 { 8399 compatible = "qcom,fastrpc-compute-cb"; 8400 reg = <8>; 8401 iommus = <&apps_smmu 0x0c08 0x20>; 8402 dma-coherent; 8403 }; 8404 8405 /* note: compute-cb@9 is secure */ 8406 8407 compute-cb@10 { 8408 compatible = "qcom,fastrpc-compute-cb"; 8409 reg = <10>; 8410 iommus = <&apps_smmu 0x0c0c 0x20>; 8411 dma-coherent; 8412 }; 8413 8414 compute-cb@11 { 8415 compatible = "qcom,fastrpc-compute-cb"; 8416 reg = <11>; 8417 iommus = <&apps_smmu 0x0c0d 0x20>; 8418 dma-coherent; 8419 }; 8420 8421 compute-cb@12 { 8422 compatible = "qcom,fastrpc-compute-cb"; 8423 reg = <12>; 8424 iommus = <&apps_smmu 0x0c0e 0x20>; 8425 dma-coherent; 8426 }; 8427 8428 compute-cb@13 { 8429 compatible = "qcom,fastrpc-compute-cb"; 8430 reg = <13>; 8431 iommus = <&apps_smmu 0x0c0f 0x20>; 8432 dma-coherent; 8433 }; 8434 }; 8435 }; 8436 }; 8437 }; 8438 8439 timer { 8440 compatible = "arm,armv8-timer"; 8441 8442 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 8443 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 8444 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 8445 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 8446 }; 8447 8448 thermal-zones { 8449 aoss0-thermal { 8450 thermal-sensors = <&tsens0 0>; 8451 8452 trips { 8453 trip-point0 { 8454 temperature = <90000>; 8455 hysteresis = <2000>; 8456 type = "hot"; 8457 }; 8458 8459 aoss0-critical { 8460 temperature = <125000>; 8461 hysteresis = <0>; 8462 type = "critical"; 8463 }; 8464 }; 8465 }; 8466 8467 cpu0-0-top-thermal { 8468 polling-delay-passive = <250>; 8469 8470 thermal-sensors = <&tsens0 1>; 8471 8472 trips { 8473 trip-point0 { 8474 temperature = <90000>; 8475 hysteresis = <2000>; 8476 type = "passive"; 8477 }; 8478 8479 trip-point1 { 8480 temperature = <95000>; 8481 hysteresis = <2000>; 8482 type = "passive"; 8483 }; 8484 8485 cpu-critical { 8486 temperature = <110000>; 8487 hysteresis = <1000>; 8488 type = "critical"; 8489 }; 8490 }; 8491 }; 8492 8493 cpu0-0-btm-thermal { 8494 polling-delay-passive = <250>; 8495 8496 thermal-sensors = <&tsens0 2>; 8497 8498 trips { 8499 trip-point0 { 8500 temperature = <90000>; 8501 hysteresis = <2000>; 8502 type = "passive"; 8503 }; 8504 8505 trip-point1 { 8506 temperature = <95000>; 8507 hysteresis = <2000>; 8508 type = "passive"; 8509 }; 8510 8511 cpu-critical { 8512 temperature = <110000>; 8513 hysteresis = <1000>; 8514 type = "critical"; 8515 }; 8516 }; 8517 }; 8518 8519 cpu0-1-top-thermal { 8520 polling-delay-passive = <250>; 8521 8522 thermal-sensors = <&tsens0 3>; 8523 8524 trips { 8525 trip-point0 { 8526 temperature = <90000>; 8527 hysteresis = <2000>; 8528 type = "passive"; 8529 }; 8530 8531 trip-point1 { 8532 temperature = <95000>; 8533 hysteresis = <2000>; 8534 type = "passive"; 8535 }; 8536 8537 cpu-critical { 8538 temperature = <110000>; 8539 hysteresis = <1000>; 8540 type = "critical"; 8541 }; 8542 }; 8543 }; 8544 8545 cpu0-1-btm-thermal { 8546 polling-delay-passive = <250>; 8547 8548 thermal-sensors = <&tsens0 4>; 8549 8550 trips { 8551 trip-point0 { 8552 temperature = <90000>; 8553 hysteresis = <2000>; 8554 type = "passive"; 8555 }; 8556 8557 trip-point1 { 8558 temperature = <95000>; 8559 hysteresis = <2000>; 8560 type = "passive"; 8561 }; 8562 8563 cpu-critical { 8564 temperature = <110000>; 8565 hysteresis = <1000>; 8566 type = "critical"; 8567 }; 8568 }; 8569 }; 8570 8571 cpu0-2-top-thermal { 8572 polling-delay-passive = <250>; 8573 8574 thermal-sensors = <&tsens0 5>; 8575 8576 trips { 8577 trip-point0 { 8578 temperature = <90000>; 8579 hysteresis = <2000>; 8580 type = "passive"; 8581 }; 8582 8583 trip-point1 { 8584 temperature = <95000>; 8585 hysteresis = <2000>; 8586 type = "passive"; 8587 }; 8588 8589 cpu-critical { 8590 temperature = <110000>; 8591 hysteresis = <1000>; 8592 type = "critical"; 8593 }; 8594 }; 8595 }; 8596 8597 cpu0-2-btm-thermal { 8598 polling-delay-passive = <250>; 8599 8600 thermal-sensors = <&tsens0 6>; 8601 8602 trips { 8603 trip-point0 { 8604 temperature = <90000>; 8605 hysteresis = <2000>; 8606 type = "passive"; 8607 }; 8608 8609 trip-point1 { 8610 temperature = <95000>; 8611 hysteresis = <2000>; 8612 type = "passive"; 8613 }; 8614 8615 cpu-critical { 8616 temperature = <110000>; 8617 hysteresis = <1000>; 8618 type = "critical"; 8619 }; 8620 }; 8621 }; 8622 8623 cpu0-3-top-thermal { 8624 polling-delay-passive = <250>; 8625 8626 thermal-sensors = <&tsens0 7>; 8627 8628 trips { 8629 trip-point0 { 8630 temperature = <90000>; 8631 hysteresis = <2000>; 8632 type = "passive"; 8633 }; 8634 8635 trip-point1 { 8636 temperature = <95000>; 8637 hysteresis = <2000>; 8638 type = "passive"; 8639 }; 8640 8641 cpu-critical { 8642 temperature = <110000>; 8643 hysteresis = <1000>; 8644 type = "critical"; 8645 }; 8646 }; 8647 }; 8648 8649 cpu0-3-btm-thermal { 8650 polling-delay-passive = <250>; 8651 8652 thermal-sensors = <&tsens0 8>; 8653 8654 trips { 8655 trip-point0 { 8656 temperature = <90000>; 8657 hysteresis = <2000>; 8658 type = "passive"; 8659 }; 8660 8661 trip-point1 { 8662 temperature = <95000>; 8663 hysteresis = <2000>; 8664 type = "passive"; 8665 }; 8666 8667 cpu-critical { 8668 temperature = <110000>; 8669 hysteresis = <1000>; 8670 type = "critical"; 8671 }; 8672 }; 8673 }; 8674 8675 cpuss0-top-thermal { 8676 thermal-sensors = <&tsens0 9>; 8677 8678 trips { 8679 trip-point0 { 8680 temperature = <90000>; 8681 hysteresis = <2000>; 8682 type = "hot"; 8683 }; 8684 8685 cpuss2-critical { 8686 temperature = <125000>; 8687 hysteresis = <0>; 8688 type = "critical"; 8689 }; 8690 }; 8691 }; 8692 8693 cpuss0-btm-thermal { 8694 thermal-sensors = <&tsens0 10>; 8695 8696 trips { 8697 trip-point0 { 8698 temperature = <90000>; 8699 hysteresis = <2000>; 8700 type = "hot"; 8701 }; 8702 8703 cpuss2-critical { 8704 temperature = <125000>; 8705 hysteresis = <0>; 8706 type = "critical"; 8707 }; 8708 }; 8709 }; 8710 8711 mem-thermal { 8712 thermal-sensors = <&tsens0 11>; 8713 8714 trips { 8715 trip-point0 { 8716 temperature = <90000>; 8717 hysteresis = <2000>; 8718 type = "hot"; 8719 }; 8720 8721 mem-critical { 8722 temperature = <125000>; 8723 hysteresis = <0>; 8724 type = "critical"; 8725 }; 8726 }; 8727 }; 8728 8729 video-thermal { 8730 polling-delay-passive = <250>; 8731 8732 thermal-sensors = <&tsens0 12>; 8733 8734 trips { 8735 trip-point0 { 8736 temperature = <125000>; 8737 hysteresis = <1000>; 8738 type = "passive"; 8739 }; 8740 }; 8741 }; 8742 8743 aoss1-thermal { 8744 thermal-sensors = <&tsens1 0>; 8745 8746 trips { 8747 trip-point0 { 8748 temperature = <90000>; 8749 hysteresis = <2000>; 8750 type = "hot"; 8751 }; 8752 8753 aoss0-critical { 8754 temperature = <125000>; 8755 hysteresis = <0>; 8756 type = "critical"; 8757 }; 8758 }; 8759 }; 8760 8761 cpu1-0-top-thermal { 8762 polling-delay-passive = <250>; 8763 8764 thermal-sensors = <&tsens1 1>; 8765 8766 trips { 8767 trip-point0 { 8768 temperature = <90000>; 8769 hysteresis = <2000>; 8770 type = "passive"; 8771 }; 8772 8773 trip-point1 { 8774 temperature = <95000>; 8775 hysteresis = <2000>; 8776 type = "passive"; 8777 }; 8778 8779 cpu-critical { 8780 temperature = <110000>; 8781 hysteresis = <1000>; 8782 type = "critical"; 8783 }; 8784 }; 8785 }; 8786 8787 cpu1-0-btm-thermal { 8788 polling-delay-passive = <250>; 8789 8790 thermal-sensors = <&tsens1 2>; 8791 8792 trips { 8793 trip-point0 { 8794 temperature = <90000>; 8795 hysteresis = <2000>; 8796 type = "passive"; 8797 }; 8798 8799 trip-point1 { 8800 temperature = <95000>; 8801 hysteresis = <2000>; 8802 type = "passive"; 8803 }; 8804 8805 cpu-critical { 8806 temperature = <110000>; 8807 hysteresis = <1000>; 8808 type = "critical"; 8809 }; 8810 }; 8811 }; 8812 8813 cpu1-1-top-thermal { 8814 polling-delay-passive = <250>; 8815 8816 thermal-sensors = <&tsens1 3>; 8817 8818 trips { 8819 trip-point0 { 8820 temperature = <90000>; 8821 hysteresis = <2000>; 8822 type = "passive"; 8823 }; 8824 8825 trip-point1 { 8826 temperature = <95000>; 8827 hysteresis = <2000>; 8828 type = "passive"; 8829 }; 8830 8831 cpu-critical { 8832 temperature = <110000>; 8833 hysteresis = <1000>; 8834 type = "critical"; 8835 }; 8836 }; 8837 }; 8838 8839 cpu1-1-btm-thermal { 8840 polling-delay-passive = <250>; 8841 8842 thermal-sensors = <&tsens1 4>; 8843 8844 trips { 8845 trip-point0 { 8846 temperature = <90000>; 8847 hysteresis = <2000>; 8848 type = "passive"; 8849 }; 8850 8851 trip-point1 { 8852 temperature = <95000>; 8853 hysteresis = <2000>; 8854 type = "passive"; 8855 }; 8856 8857 cpu-critical { 8858 temperature = <110000>; 8859 hysteresis = <1000>; 8860 type = "critical"; 8861 }; 8862 }; 8863 }; 8864 8865 cpu1-2-top-thermal { 8866 polling-delay-passive = <250>; 8867 8868 thermal-sensors = <&tsens1 5>; 8869 8870 trips { 8871 trip-point0 { 8872 temperature = <90000>; 8873 hysteresis = <2000>; 8874 type = "passive"; 8875 }; 8876 8877 trip-point1 { 8878 temperature = <95000>; 8879 hysteresis = <2000>; 8880 type = "passive"; 8881 }; 8882 8883 cpu-critical { 8884 temperature = <110000>; 8885 hysteresis = <1000>; 8886 type = "critical"; 8887 }; 8888 }; 8889 }; 8890 8891 cpu1-2-btm-thermal { 8892 polling-delay-passive = <250>; 8893 8894 thermal-sensors = <&tsens1 6>; 8895 8896 trips { 8897 trip-point0 { 8898 temperature = <90000>; 8899 hysteresis = <2000>; 8900 type = "passive"; 8901 }; 8902 8903 trip-point1 { 8904 temperature = <95000>; 8905 hysteresis = <2000>; 8906 type = "passive"; 8907 }; 8908 8909 cpu-critical { 8910 temperature = <110000>; 8911 hysteresis = <1000>; 8912 type = "critical"; 8913 }; 8914 }; 8915 }; 8916 8917 cpu1-3-top-thermal { 8918 polling-delay-passive = <250>; 8919 8920 thermal-sensors = <&tsens1 7>; 8921 8922 trips { 8923 trip-point0 { 8924 temperature = <90000>; 8925 hysteresis = <2000>; 8926 type = "passive"; 8927 }; 8928 8929 trip-point1 { 8930 temperature = <95000>; 8931 hysteresis = <2000>; 8932 type = "passive"; 8933 }; 8934 8935 cpu-critical { 8936 temperature = <110000>; 8937 hysteresis = <1000>; 8938 type = "critical"; 8939 }; 8940 }; 8941 }; 8942 8943 cpu1-3-btm-thermal { 8944 polling-delay-passive = <250>; 8945 8946 thermal-sensors = <&tsens1 8>; 8947 8948 trips { 8949 trip-point0 { 8950 temperature = <90000>; 8951 hysteresis = <2000>; 8952 type = "passive"; 8953 }; 8954 8955 trip-point1 { 8956 temperature = <95000>; 8957 hysteresis = <2000>; 8958 type = "passive"; 8959 }; 8960 8961 cpu-critical { 8962 temperature = <110000>; 8963 hysteresis = <1000>; 8964 type = "critical"; 8965 }; 8966 }; 8967 }; 8968 8969 cpuss1-top-thermal { 8970 thermal-sensors = <&tsens1 9>; 8971 8972 trips { 8973 trip-point0 { 8974 temperature = <90000>; 8975 hysteresis = <2000>; 8976 type = "hot"; 8977 }; 8978 8979 cpuss2-critical { 8980 temperature = <125000>; 8981 hysteresis = <0>; 8982 type = "critical"; 8983 }; 8984 }; 8985 }; 8986 8987 cpuss1-btm-thermal { 8988 thermal-sensors = <&tsens1 10>; 8989 8990 trips { 8991 trip-point0 { 8992 temperature = <90000>; 8993 hysteresis = <2000>; 8994 type = "hot"; 8995 }; 8996 8997 cpuss2-critical { 8998 temperature = <125000>; 8999 hysteresis = <0>; 9000 type = "critical"; 9001 }; 9002 }; 9003 }; 9004 9005 aoss2-thermal { 9006 thermal-sensors = <&tsens2 0>; 9007 9008 trips { 9009 trip-point0 { 9010 temperature = <90000>; 9011 hysteresis = <2000>; 9012 type = "hot"; 9013 }; 9014 9015 aoss0-critical { 9016 temperature = <125000>; 9017 hysteresis = <0>; 9018 type = "critical"; 9019 }; 9020 }; 9021 }; 9022 9023 cpu2-0-top-thermal { 9024 polling-delay-passive = <250>; 9025 9026 thermal-sensors = <&tsens2 1>; 9027 9028 trips { 9029 trip-point0 { 9030 temperature = <90000>; 9031 hysteresis = <2000>; 9032 type = "passive"; 9033 }; 9034 9035 trip-point1 { 9036 temperature = <95000>; 9037 hysteresis = <2000>; 9038 type = "passive"; 9039 }; 9040 9041 cpu-critical { 9042 temperature = <110000>; 9043 hysteresis = <1000>; 9044 type = "critical"; 9045 }; 9046 }; 9047 }; 9048 9049 cpu2-0-btm-thermal { 9050 polling-delay-passive = <250>; 9051 9052 thermal-sensors = <&tsens2 2>; 9053 9054 trips { 9055 trip-point0 { 9056 temperature = <90000>; 9057 hysteresis = <2000>; 9058 type = "passive"; 9059 }; 9060 9061 trip-point1 { 9062 temperature = <95000>; 9063 hysteresis = <2000>; 9064 type = "passive"; 9065 }; 9066 9067 cpu-critical { 9068 temperature = <110000>; 9069 hysteresis = <1000>; 9070 type = "critical"; 9071 }; 9072 }; 9073 }; 9074 9075 cpu2-1-top-thermal { 9076 polling-delay-passive = <250>; 9077 9078 thermal-sensors = <&tsens2 3>; 9079 9080 trips { 9081 trip-point0 { 9082 temperature = <90000>; 9083 hysteresis = <2000>; 9084 type = "passive"; 9085 }; 9086 9087 trip-point1 { 9088 temperature = <95000>; 9089 hysteresis = <2000>; 9090 type = "passive"; 9091 }; 9092 9093 cpu-critical { 9094 temperature = <110000>; 9095 hysteresis = <1000>; 9096 type = "critical"; 9097 }; 9098 }; 9099 }; 9100 9101 cpu2-1-btm-thermal { 9102 polling-delay-passive = <250>; 9103 9104 thermal-sensors = <&tsens2 4>; 9105 9106 trips { 9107 trip-point0 { 9108 temperature = <90000>; 9109 hysteresis = <2000>; 9110 type = "passive"; 9111 }; 9112 9113 trip-point1 { 9114 temperature = <95000>; 9115 hysteresis = <2000>; 9116 type = "passive"; 9117 }; 9118 9119 cpu-critical { 9120 temperature = <110000>; 9121 hysteresis = <1000>; 9122 type = "critical"; 9123 }; 9124 }; 9125 }; 9126 9127 cpu2-2-top-thermal { 9128 polling-delay-passive = <250>; 9129 9130 thermal-sensors = <&tsens2 5>; 9131 9132 trips { 9133 trip-point0 { 9134 temperature = <90000>; 9135 hysteresis = <2000>; 9136 type = "passive"; 9137 }; 9138 9139 trip-point1 { 9140 temperature = <95000>; 9141 hysteresis = <2000>; 9142 type = "passive"; 9143 }; 9144 9145 cpu-critical { 9146 temperature = <110000>; 9147 hysteresis = <1000>; 9148 type = "critical"; 9149 }; 9150 }; 9151 }; 9152 9153 cpu2-2-btm-thermal { 9154 polling-delay-passive = <250>; 9155 9156 thermal-sensors = <&tsens2 6>; 9157 9158 trips { 9159 trip-point0 { 9160 temperature = <90000>; 9161 hysteresis = <2000>; 9162 type = "passive"; 9163 }; 9164 9165 trip-point1 { 9166 temperature = <95000>; 9167 hysteresis = <2000>; 9168 type = "passive"; 9169 }; 9170 9171 cpu-critical { 9172 temperature = <110000>; 9173 hysteresis = <1000>; 9174 type = "critical"; 9175 }; 9176 }; 9177 }; 9178 9179 cpu2-3-top-thermal { 9180 polling-delay-passive = <250>; 9181 9182 thermal-sensors = <&tsens2 7>; 9183 9184 trips { 9185 trip-point0 { 9186 temperature = <90000>; 9187 hysteresis = <2000>; 9188 type = "passive"; 9189 }; 9190 9191 trip-point1 { 9192 temperature = <95000>; 9193 hysteresis = <2000>; 9194 type = "passive"; 9195 }; 9196 9197 cpu-critical { 9198 temperature = <110000>; 9199 hysteresis = <1000>; 9200 type = "critical"; 9201 }; 9202 }; 9203 }; 9204 9205 cpu2-3-btm-thermal { 9206 polling-delay-passive = <250>; 9207 9208 thermal-sensors = <&tsens2 8>; 9209 9210 trips { 9211 trip-point0 { 9212 temperature = <90000>; 9213 hysteresis = <2000>; 9214 type = "passive"; 9215 }; 9216 9217 trip-point1 { 9218 temperature = <95000>; 9219 hysteresis = <2000>; 9220 type = "passive"; 9221 }; 9222 9223 cpu-critical { 9224 temperature = <110000>; 9225 hysteresis = <1000>; 9226 type = "critical"; 9227 }; 9228 }; 9229 }; 9230 9231 cpuss2-top-thermal { 9232 thermal-sensors = <&tsens2 9>; 9233 9234 trips { 9235 trip-point0 { 9236 temperature = <90000>; 9237 hysteresis = <2000>; 9238 type = "hot"; 9239 }; 9240 9241 cpuss2-critical { 9242 temperature = <125000>; 9243 hysteresis = <0>; 9244 type = "critical"; 9245 }; 9246 }; 9247 }; 9248 9249 cpuss2-btm-thermal { 9250 thermal-sensors = <&tsens2 10>; 9251 9252 trips { 9253 trip-point0 { 9254 temperature = <90000>; 9255 hysteresis = <2000>; 9256 type = "hot"; 9257 }; 9258 9259 cpuss2-critical { 9260 temperature = <125000>; 9261 hysteresis = <0>; 9262 type = "critical"; 9263 }; 9264 }; 9265 }; 9266 9267 aoss3-thermal { 9268 thermal-sensors = <&tsens3 0>; 9269 9270 trips { 9271 trip-point0 { 9272 temperature = <90000>; 9273 hysteresis = <2000>; 9274 type = "hot"; 9275 }; 9276 9277 aoss0-critical { 9278 temperature = <125000>; 9279 hysteresis = <0>; 9280 type = "critical"; 9281 }; 9282 }; 9283 }; 9284 9285 nsp0-thermal { 9286 thermal-sensors = <&tsens3 1>; 9287 9288 trips { 9289 trip-point0 { 9290 temperature = <90000>; 9291 hysteresis = <2000>; 9292 type = "hot"; 9293 }; 9294 9295 nsp0-critical { 9296 temperature = <125000>; 9297 hysteresis = <0>; 9298 type = "critical"; 9299 }; 9300 }; 9301 }; 9302 9303 nsp1-thermal { 9304 thermal-sensors = <&tsens3 2>; 9305 9306 trips { 9307 trip-point0 { 9308 temperature = <90000>; 9309 hysteresis = <2000>; 9310 type = "hot"; 9311 }; 9312 9313 nsp1-critical { 9314 temperature = <125000>; 9315 hysteresis = <0>; 9316 type = "critical"; 9317 }; 9318 }; 9319 }; 9320 9321 nsp2-thermal { 9322 thermal-sensors = <&tsens3 3>; 9323 9324 trips { 9325 trip-point0 { 9326 temperature = <90000>; 9327 hysteresis = <2000>; 9328 type = "hot"; 9329 }; 9330 9331 nsp2-critical { 9332 temperature = <125000>; 9333 hysteresis = <0>; 9334 type = "critical"; 9335 }; 9336 }; 9337 }; 9338 9339 nsp3-thermal { 9340 thermal-sensors = <&tsens3 4>; 9341 9342 trips { 9343 trip-point0 { 9344 temperature = <90000>; 9345 hysteresis = <2000>; 9346 type = "hot"; 9347 }; 9348 9349 nsp3-critical { 9350 temperature = <125000>; 9351 hysteresis = <0>; 9352 type = "critical"; 9353 }; 9354 }; 9355 }; 9356 9357 gpuss-0-thermal { 9358 polling-delay-passive = <10>; 9359 9360 thermal-sensors = <&tsens3 5>; 9361 9362 trips { 9363 trip-point0 { 9364 temperature = <85000>; 9365 hysteresis = <1000>; 9366 type = "passive"; 9367 }; 9368 9369 trip-point1 { 9370 temperature = <90000>; 9371 hysteresis = <1000>; 9372 type = "hot"; 9373 }; 9374 9375 trip-point2 { 9376 temperature = <125000>; 9377 hysteresis = <1000>; 9378 type = "critical"; 9379 }; 9380 }; 9381 }; 9382 9383 gpuss-1-thermal { 9384 polling-delay-passive = <10>; 9385 9386 thermal-sensors = <&tsens3 6>; 9387 9388 trips { 9389 trip-point0 { 9390 temperature = <85000>; 9391 hysteresis = <1000>; 9392 type = "passive"; 9393 }; 9394 9395 trip-point1 { 9396 temperature = <90000>; 9397 hysteresis = <1000>; 9398 type = "hot"; 9399 }; 9400 9401 trip-point2 { 9402 temperature = <125000>; 9403 hysteresis = <1000>; 9404 type = "critical"; 9405 }; 9406 }; 9407 }; 9408 9409 gpuss-2-thermal { 9410 polling-delay-passive = <10>; 9411 9412 thermal-sensors = <&tsens3 7>; 9413 9414 trips { 9415 trip-point0 { 9416 temperature = <85000>; 9417 hysteresis = <1000>; 9418 type = "passive"; 9419 }; 9420 9421 trip-point1 { 9422 temperature = <90000>; 9423 hysteresis = <1000>; 9424 type = "hot"; 9425 }; 9426 9427 trip-point2 { 9428 temperature = <125000>; 9429 hysteresis = <1000>; 9430 type = "critical"; 9431 }; 9432 }; 9433 }; 9434 9435 gpuss-3-thermal { 9436 polling-delay-passive = <10>; 9437 9438 thermal-sensors = <&tsens3 8>; 9439 9440 trips { 9441 trip-point0 { 9442 temperature = <85000>; 9443 hysteresis = <1000>; 9444 type = "passive"; 9445 }; 9446 9447 trip-point1 { 9448 temperature = <90000>; 9449 hysteresis = <1000>; 9450 type = "hot"; 9451 }; 9452 9453 trip-point2 { 9454 temperature = <125000>; 9455 hysteresis = <1000>; 9456 type = "critical"; 9457 }; 9458 }; 9459 }; 9460 9461 gpuss-4-thermal { 9462 polling-delay-passive = <10>; 9463 9464 thermal-sensors = <&tsens3 9>; 9465 9466 trips { 9467 trip-point0 { 9468 temperature = <85000>; 9469 hysteresis = <1000>; 9470 type = "passive"; 9471 }; 9472 9473 trip-point1 { 9474 temperature = <90000>; 9475 hysteresis = <1000>; 9476 type = "hot"; 9477 }; 9478 9479 trip-point2 { 9480 temperature = <125000>; 9481 hysteresis = <1000>; 9482 type = "critical"; 9483 }; 9484 }; 9485 }; 9486 9487 gpuss-5-thermal { 9488 polling-delay-passive = <10>; 9489 9490 thermal-sensors = <&tsens3 10>; 9491 9492 trips { 9493 trip-point0 { 9494 temperature = <85000>; 9495 hysteresis = <1000>; 9496 type = "passive"; 9497 }; 9498 9499 trip-point1 { 9500 temperature = <90000>; 9501 hysteresis = <1000>; 9502 type = "hot"; 9503 }; 9504 9505 trip-point2 { 9506 temperature = <125000>; 9507 hysteresis = <1000>; 9508 type = "critical"; 9509 }; 9510 }; 9511 }; 9512 9513 gpuss-6-thermal { 9514 polling-delay-passive = <10>; 9515 9516 thermal-sensors = <&tsens3 11>; 9517 9518 trips { 9519 trip-point0 { 9520 temperature = <85000>; 9521 hysteresis = <1000>; 9522 type = "passive"; 9523 }; 9524 9525 trip-point1 { 9526 temperature = <90000>; 9527 hysteresis = <1000>; 9528 type = "hot"; 9529 }; 9530 9531 trip-point2 { 9532 temperature = <125000>; 9533 hysteresis = <1000>; 9534 type = "critical"; 9535 }; 9536 }; 9537 }; 9538 9539 gpuss-7-thermal { 9540 polling-delay-passive = <10>; 9541 9542 thermal-sensors = <&tsens3 12>; 9543 9544 trips { 9545 trip-point0 { 9546 temperature = <85000>; 9547 hysteresis = <1000>; 9548 type = "passive"; 9549 }; 9550 9551 trip-point1 { 9552 temperature = <90000>; 9553 hysteresis = <1000>; 9554 type = "hot"; 9555 }; 9556 9557 trip-point2 { 9558 temperature = <125000>; 9559 hysteresis = <1000>; 9560 type = "critical"; 9561 }; 9562 }; 9563 }; 9564 9565 camera0-thermal { 9566 thermal-sensors = <&tsens3 13>; 9567 9568 trips { 9569 trip-point0 { 9570 temperature = <90000>; 9571 hysteresis = <2000>; 9572 type = "hot"; 9573 }; 9574 9575 camera0-critical { 9576 temperature = <115000>; 9577 hysteresis = <0>; 9578 type = "critical"; 9579 }; 9580 }; 9581 }; 9582 9583 camera1-thermal { 9584 thermal-sensors = <&tsens3 14>; 9585 9586 trips { 9587 trip-point0 { 9588 temperature = <90000>; 9589 hysteresis = <2000>; 9590 type = "hot"; 9591 }; 9592 9593 camera0-critical { 9594 temperature = <115000>; 9595 hysteresis = <0>; 9596 type = "critical"; 9597 }; 9598 }; 9599 }; 9600 }; 9601}; 9602