xref: /linux/arch/arm/boot/dts/vt8500/wm8650.dtsi (revision ec71f661a572a770d7c861cd52a50cbbb0e1a8d1) 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
4 *
5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 */
7
8/ {
9	#address-cells = <1>;
10	#size-cells = <1>;
11	compatible = "wm,wm8650";
12
13	cpus {
14		#address-cells = <0>;
15		#size-cells = <0>;
16
17		cpu {
18			device_type = "cpu";
19			compatible = "arm,arm926ej-s";
20		};
21	};
22
23	memory {
24		device_type = "memory";
25		reg = <0x0 0x0>;
26	};
27
28 	aliases {
29		serial0 = &uart0;
30		serial1 = &uart1;
31	};
32
33	soc {
34		#address-cells = <1>;
35		#size-cells = <1>;
36		compatible = "simple-bus";
37		ranges;
38		interrupt-parent = <&intc0>;
39
40		intc0: interrupt-controller@d8140000 {
41			compatible = "via,vt8500-intc";
42			interrupt-controller;
43			reg = <0xd8140000 0x10000>;
44			#interrupt-cells = <1>;
45		};
46
47		/* Secondary IC cascaded to intc0 */
48		intc1: interrupt-controller@d8150000 {
49			compatible = "via,vt8500-intc";
50			interrupt-controller;
51			#interrupt-cells = <1>;
52			reg = <0xD8150000 0x10000>;
53			interrupts = <56 57 58 59 60 61 62 63>;
54		};
55
56		pinctrl: pinctrl@d8110000 {
57			compatible = "wm,wm8650-pinctrl";
58			reg = <0xd8110000 0x10000>;
59			interrupt-controller;
60			#interrupt-cells = <2>;
61			gpio-controller;
62			#gpio-cells = <2>;
63		};
64
65		chipid@d8120000 {
66			compatible = "via,vt8500-scc-id";
67			reg = <0xd8120000 0x4>;
68		};
69
70		pmc@d8130000 {
71			compatible = "via,vt8500-pmc";
72			reg = <0xd8130000 0x1000>;
73
74			clocks {
75				#address-cells = <1>;
76				#size-cells = <0>;
77
78				ref25: ref25M {
79					#clock-cells = <0>;
80					compatible = "fixed-clock";
81					clock-frequency = <25000000>;
82				};
83
84				ref24: ref24M {
85					#clock-cells = <0>;
86					compatible = "fixed-clock";
87					clock-frequency = <24000000>;
88				};
89
90				plla: plla {
91					#clock-cells = <0>;
92					compatible = "wm,wm8650-pll-clock";
93					clocks = <&ref25>;
94					reg = <0x200>;
95				};
96
97				pllb: pllb {
98					#clock-cells = <0>;
99					compatible = "wm,wm8650-pll-clock";
100					clocks = <&ref25>;
101					reg = <0x204>;
102				};
103
104				pllc: pllc {
105					#clock-cells = <0>;
106					compatible = "wm,wm8650-pll-clock";
107					clocks = <&ref25>;
108					reg = <0x208>;
109				};
110
111				plld: plld {
112					#clock-cells = <0>;
113					compatible = "wm,wm8650-pll-clock";
114					clocks = <&ref25>;
115					reg = <0x20c>;
116				};
117
118				plle: plle {
119					#clock-cells = <0>;
120					compatible = "wm,wm8650-pll-clock";
121					clocks = <&ref25>;
122					reg = <0x210>;
123				};
124
125				clkarm: arm {
126					#clock-cells = <0>;
127					compatible = "via,vt8500-device-clock";
128					clocks = <&plla>;
129					divisor-reg = <0x300>;
130				};
131
132				clkahb: ahb {
133					#clock-cells = <0>;
134					compatible = "via,vt8500-device-clock";
135					clocks = <&pllb>;
136					divisor-reg = <0x304>;
137				};
138
139				clkapb: apb {
140					#clock-cells = <0>;
141					compatible = "via,vt8500-device-clock";
142					clocks = <&pllb>;
143					divisor-reg = <0x320>;
144				};
145
146				clkddr: ddr {
147					#clock-cells = <0>;
148					compatible = "via,vt8500-device-clock";
149					clocks = <&plld>;
150					divisor-reg = <0x310>;
151				};
152
153				clkuart0: uart0 {
154 					#clock-cells = <0>;
155 					compatible = "via,vt8500-device-clock";
156					clocks = <&ref24>;
157					enable-reg = <0x250>;
158					enable-bit = <1>;
159 				};
160
161				clkuart1: uart1 {
162					#clock-cells = <0>;
163					compatible = "via,vt8500-device-clock";
164					clocks = <&ref24>;
165					enable-reg = <0x250>;
166					enable-bit = <2>;
167				};
168
169				clksdhc: sdhc {
170					#clock-cells = <0>;
171					compatible = "via,vt8500-device-clock";
172					clocks = <&pllb>;
173					divisor-reg = <0x328>;
174					divisor-mask = <0x3f>;
175					enable-reg = <0x254>;
176					enable-bit = <18>;
177				};
178			};
179		};
180
181		timer@d8130100 {
182			compatible = "via,vt8500-timer";
183			reg = <0xd8130100 0x28>;
184			interrupts = <36>, <37>, <38>, <39>;
185		};
186
187		usb@d8007900 {
188			compatible = "via,vt8500-ehci";
189			reg = <0xd8007900 0x200>;
190			interrupts = <43>;
191		};
192
193		usb@d8007b00 {
194			compatible = "platform-uhci";
195			reg = <0xd8007b00 0x200>;
196			interrupts = <43>;
197		};
198
199		sdhc@d800a000 {
200			compatible = "wm,wm8505-sdhc";
201			reg = <0xd800a000 0x400>;
202			interrupts = <20>, <21>;
203			clocks = <&clksdhc>;
204			bus-width = <4>;
205			sdon-inverted;
206		};
207
208		fb: fb@d8050800 {
209			compatible = "wm,wm8505-fb";
210			reg = <0xd8050800 0x200>;
211		};
212
213		ge_rops@d8050400 {
214			compatible = "wm,prizm-ge-rops";
215			reg = <0xd8050400 0x100>;
216		};
217
218		uart0: serial@d8200000 {
219			compatible = "via,vt8500-uart";
220			reg = <0xd8200000 0x1040>;
221			interrupts = <32>;
222			clocks = <&clkuart0>;
223			status = "disabled";
224		};
225
226		uart1: serial@d82b0000 {
227			compatible = "via,vt8500-uart";
228			reg = <0xd82b0000 0x1040>;
229			interrupts = <33>;
230			clocks = <&clkuart1>;
231			status = "disabled";
232		};
233
234		rtc@d8100000 {
235			compatible = "via,vt8500-rtc";
236			reg = <0xd8100000 0x10000>;
237			interrupts = <48>;
238		};
239
240		ethernet@d8004000 {
241			compatible = "via,vt8500-rhine";
242			reg = <0xd8004000 0x100>;
243			interrupts = <10>;
244		};
245	};
246};
247