1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 HVS module. 8 * 9 * The Hardware Video Scaler (HVS) is the piece of hardware that does 10 * translation, scaling, colorspace conversion, and compositing of 11 * pixels stored in framebuffers into a FIFO of pixels going out to 12 * the Pixel Valve (CRTC). It operates at the system clock rate (the 13 * system audio clock gate, specifically), which is much higher than 14 * the pixel clock rate. 15 * 16 * There is a single global HVS, with multiple output FIFOs that can 17 * be consumed by the PVs. This file just manages the resources for 18 * the HVS, while the vc4_crtc.c code actually drives HVS setup for 19 * each CRTC. 20 */ 21 22 #include <linux/bitfield.h> 23 #include <linux/clk.h> 24 #include <linux/component.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/platform_device.h> 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_drv.h> 30 #include <drm/drm_print.h> 31 #include <drm/drm_vblank.h> 32 33 #include <soc/bcm2835/raspberrypi-firmware.h> 34 35 #include "vc4_drv.h" 36 #include "vc4_regs.h" 37 38 static const struct debugfs_reg32 vc4_hvs_regs[] = { 39 VC4_REG32(SCALER_DISPCTRL), 40 VC4_REG32(SCALER_DISPSTAT), 41 VC4_REG32(SCALER_DISPID), 42 VC4_REG32(SCALER_DISPECTRL), 43 VC4_REG32(SCALER_DISPPROF), 44 VC4_REG32(SCALER_DISPDITHER), 45 VC4_REG32(SCALER_DISPEOLN), 46 VC4_REG32(SCALER_DISPLIST0), 47 VC4_REG32(SCALER_DISPLIST1), 48 VC4_REG32(SCALER_DISPLIST2), 49 VC4_REG32(SCALER_DISPLSTAT), 50 VC4_REG32(SCALER_DISPLACT0), 51 VC4_REG32(SCALER_DISPLACT1), 52 VC4_REG32(SCALER_DISPLACT2), 53 VC4_REG32(SCALER_DISPCTRL0), 54 VC4_REG32(SCALER_DISPBKGND0), 55 VC4_REG32(SCALER_DISPSTAT0), 56 VC4_REG32(SCALER_DISPBASE0), 57 VC4_REG32(SCALER_DISPCTRL1), 58 VC4_REG32(SCALER_DISPBKGND1), 59 VC4_REG32(SCALER_DISPSTAT1), 60 VC4_REG32(SCALER_DISPBASE1), 61 VC4_REG32(SCALER_DISPCTRL2), 62 VC4_REG32(SCALER_DISPBKGND2), 63 VC4_REG32(SCALER_DISPSTAT2), 64 VC4_REG32(SCALER_DISPBASE2), 65 VC4_REG32(SCALER_DISPALPHA2), 66 VC4_REG32(SCALER_OLEDOFFS), 67 VC4_REG32(SCALER_OLEDCOEF0), 68 VC4_REG32(SCALER_OLEDCOEF1), 69 VC4_REG32(SCALER_OLEDCOEF2), 70 }; 71 72 static const struct debugfs_reg32 vc6_hvs_regs[] = { 73 VC4_REG32(SCALER6_VERSION), 74 VC4_REG32(SCALER6_CXM_SIZE), 75 VC4_REG32(SCALER6_LBM_SIZE), 76 VC4_REG32(SCALER6_UBM_SIZE), 77 VC4_REG32(SCALER6_COBA_SIZE), 78 VC4_REG32(SCALER6_COB_SIZE), 79 VC4_REG32(SCALER6_CONTROL), 80 VC4_REG32(SCALER6_FETCHER_STATUS), 81 VC4_REG32(SCALER6_FETCH_STATUS), 82 VC4_REG32(SCALER6_HANDLE_ERROR), 83 VC4_REG32(SCALER6_DISP0_CTRL0), 84 VC4_REG32(SCALER6_DISP0_CTRL1), 85 VC4_REG32(SCALER6_DISP0_BGND), 86 VC4_REG32(SCALER6_DISP0_LPTRS), 87 VC4_REG32(SCALER6_DISP0_COB), 88 VC4_REG32(SCALER6_DISP0_STATUS), 89 VC4_REG32(SCALER6_DISP0_DL), 90 VC4_REG32(SCALER6_DISP0_RUN), 91 VC4_REG32(SCALER6_DISP1_CTRL0), 92 VC4_REG32(SCALER6_DISP1_CTRL1), 93 VC4_REG32(SCALER6_DISP1_BGND), 94 VC4_REG32(SCALER6_DISP1_LPTRS), 95 VC4_REG32(SCALER6_DISP1_COB), 96 VC4_REG32(SCALER6_DISP1_STATUS), 97 VC4_REG32(SCALER6_DISP1_DL), 98 VC4_REG32(SCALER6_DISP1_RUN), 99 VC4_REG32(SCALER6_DISP2_CTRL0), 100 VC4_REG32(SCALER6_DISP2_CTRL1), 101 VC4_REG32(SCALER6_DISP2_BGND), 102 VC4_REG32(SCALER6_DISP2_LPTRS), 103 VC4_REG32(SCALER6_DISP2_COB), 104 VC4_REG32(SCALER6_DISP2_STATUS), 105 VC4_REG32(SCALER6_DISP2_DL), 106 VC4_REG32(SCALER6_DISP2_RUN), 107 VC4_REG32(SCALER6_EOLN), 108 VC4_REG32(SCALER6_DL_STATUS), 109 VC4_REG32(SCALER6_BFG_MISC), 110 VC4_REG32(SCALER6_QOS0), 111 VC4_REG32(SCALER6_PROF0), 112 VC4_REG32(SCALER6_QOS1), 113 VC4_REG32(SCALER6_PROF1), 114 VC4_REG32(SCALER6_QOS2), 115 VC4_REG32(SCALER6_PROF2), 116 VC4_REG32(SCALER6_PRI_MAP0), 117 VC4_REG32(SCALER6_PRI_MAP1), 118 VC4_REG32(SCALER6_HISTCTRL), 119 VC4_REG32(SCALER6_HISTBIN0), 120 VC4_REG32(SCALER6_HISTBIN1), 121 VC4_REG32(SCALER6_HISTBIN2), 122 VC4_REG32(SCALER6_HISTBIN3), 123 VC4_REG32(SCALER6_HISTBIN4), 124 VC4_REG32(SCALER6_HISTBIN5), 125 VC4_REG32(SCALER6_HISTBIN6), 126 VC4_REG32(SCALER6_HISTBIN7), 127 VC4_REG32(SCALER6_HDR_CFG_REMAP), 128 VC4_REG32(SCALER6_COL_SPACE), 129 VC4_REG32(SCALER6_HVS_ID), 130 VC4_REG32(SCALER6_CFC1), 131 VC4_REG32(SCALER6_DISP_UPM_ISO0), 132 VC4_REG32(SCALER6_DISP_UPM_ISO1), 133 VC4_REG32(SCALER6_DISP_UPM_ISO2), 134 VC4_REG32(SCALER6_DISP_LBM_ISO0), 135 VC4_REG32(SCALER6_DISP_LBM_ISO1), 136 VC4_REG32(SCALER6_DISP_LBM_ISO2), 137 VC4_REG32(SCALER6_DISP_COB_ISO0), 138 VC4_REG32(SCALER6_DISP_COB_ISO1), 139 VC4_REG32(SCALER6_DISP_COB_ISO2), 140 VC4_REG32(SCALER6_BAD_COB), 141 VC4_REG32(SCALER6_BAD_LBM), 142 VC4_REG32(SCALER6_BAD_UPM), 143 VC4_REG32(SCALER6_BAD_AXI), 144 }; 145 146 static const struct debugfs_reg32 vc6_d_hvs_regs[] = { 147 VC4_REG32(SCALER6D_VERSION), 148 VC4_REG32(SCALER6D_CXM_SIZE), 149 VC4_REG32(SCALER6D_LBM_SIZE), 150 VC4_REG32(SCALER6D_UBM_SIZE), 151 VC4_REG32(SCALER6D_COBA_SIZE), 152 VC4_REG32(SCALER6D_COB_SIZE), 153 VC4_REG32(SCALER6D_CONTROL), 154 VC4_REG32(SCALER6D_FETCHER_STATUS), 155 VC4_REG32(SCALER6D_FETCH_STATUS), 156 VC4_REG32(SCALER6D_HANDLE_ERROR), 157 VC4_REG32(SCALER6D_DISP0_CTRL0), 158 VC4_REG32(SCALER6D_DISP0_CTRL1), 159 VC4_REG32(SCALER6D_DISP0_BGND0), 160 VC4_REG32(SCALER6D_DISP0_BGND1), 161 VC4_REG32(SCALER6D_DISP0_LPTRS), 162 VC4_REG32(SCALER6D_DISP0_COB), 163 VC4_REG32(SCALER6D_DISP0_STATUS), 164 VC4_REG32(SCALER6D_DISP0_DL), 165 VC4_REG32(SCALER6D_DISP0_RUN), 166 VC4_REG32(SCALER6D_DISP1_CTRL0), 167 VC4_REG32(SCALER6D_DISP1_CTRL1), 168 VC4_REG32(SCALER6D_DISP1_BGND0), 169 VC4_REG32(SCALER6D_DISP1_BGND1), 170 VC4_REG32(SCALER6D_DISP1_LPTRS), 171 VC4_REG32(SCALER6D_DISP1_COB), 172 VC4_REG32(SCALER6D_DISP1_STATUS), 173 VC4_REG32(SCALER6D_DISP1_DL), 174 VC4_REG32(SCALER6D_DISP1_RUN), 175 VC4_REG32(SCALER6D_DISP2_CTRL0), 176 VC4_REG32(SCALER6D_DISP2_CTRL1), 177 VC4_REG32(SCALER6D_DISP2_BGND0), 178 VC4_REG32(SCALER6D_DISP2_BGND1), 179 VC4_REG32(SCALER6D_DISP2_LPTRS), 180 VC4_REG32(SCALER6D_DISP2_COB), 181 VC4_REG32(SCALER6D_DISP2_STATUS), 182 VC4_REG32(SCALER6D_DISP2_DL), 183 VC4_REG32(SCALER6D_DISP2_RUN), 184 VC4_REG32(SCALER6D_EOLN), 185 VC4_REG32(SCALER6D_DL_STATUS), 186 VC4_REG32(SCALER6D_QOS0), 187 VC4_REG32(SCALER6D_PROF0), 188 VC4_REG32(SCALER6D_QOS1), 189 VC4_REG32(SCALER6D_PROF1), 190 VC4_REG32(SCALER6D_QOS2), 191 VC4_REG32(SCALER6D_PROF2), 192 VC4_REG32(SCALER6D_PRI_MAP0), 193 VC4_REG32(SCALER6D_PRI_MAP1), 194 VC4_REG32(SCALER6D_HISTCTRL), 195 VC4_REG32(SCALER6D_HISTBIN0), 196 VC4_REG32(SCALER6D_HISTBIN1), 197 VC4_REG32(SCALER6D_HISTBIN2), 198 VC4_REG32(SCALER6D_HISTBIN3), 199 VC4_REG32(SCALER6D_HISTBIN4), 200 VC4_REG32(SCALER6D_HISTBIN5), 201 VC4_REG32(SCALER6D_HISTBIN6), 202 VC4_REG32(SCALER6D_HISTBIN7), 203 VC4_REG32(SCALER6D_HVS_ID), 204 }; 205 206 void vc4_hvs_dump_state(struct vc4_hvs *hvs) 207 { 208 struct drm_device *drm = &hvs->vc4->base; 209 struct drm_printer p = drm_info_printer(&hvs->pdev->dev); 210 int idx, i; 211 212 if (!drm_dev_enter(drm, &idx)) 213 return; 214 215 drm_print_regset32(&p, &hvs->regset); 216 217 DRM_INFO("HVS ctx:\n"); 218 for (i = 0; i < 64; i += 4) { 219 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n", 220 i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D", 221 readl((u32 __iomem *)hvs->dlist + i + 0), 222 readl((u32 __iomem *)hvs->dlist + i + 1), 223 readl((u32 __iomem *)hvs->dlist + i + 2), 224 readl((u32 __iomem *)hvs->dlist + i + 3)); 225 } 226 227 drm_dev_exit(idx); 228 } 229 230 static int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data) 231 { 232 struct drm_debugfs_entry *entry = m->private; 233 struct drm_device *dev = entry->dev; 234 struct vc4_dev *vc4 = to_vc4_dev(dev); 235 struct drm_printer p = drm_seq_file_printer(m); 236 237 drm_printf(&p, "%d\n", atomic_read(&vc4->underrun)); 238 239 return 0; 240 } 241 242 static int vc4_hvs_debugfs_dlist(struct seq_file *m, void *data) 243 { 244 struct drm_debugfs_entry *entry = m->private; 245 struct drm_device *dev = entry->dev; 246 struct vc4_dev *vc4 = to_vc4_dev(dev); 247 struct vc4_hvs *hvs = vc4->hvs; 248 struct drm_printer p = drm_seq_file_printer(m); 249 unsigned int dlist_mem_size = hvs->dlist_mem_size; 250 unsigned int next_entry_start; 251 unsigned int i, j; 252 u32 dlist_word, dispstat; 253 254 for (i = 0; i < SCALER_CHANNELS_COUNT; i++) { 255 dispstat = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(i)), 256 SCALER_DISPSTATX_MODE); 257 if (dispstat == SCALER_DISPSTATX_MODE_DISABLED || 258 dispstat == SCALER_DISPSTATX_MODE_EOF) { 259 drm_printf(&p, "HVS chan %u disabled\n", i); 260 continue; 261 } 262 263 drm_printf(&p, "HVS chan %u:\n", i); 264 next_entry_start = 0; 265 266 for (j = HVS_READ(SCALER_DISPLISTX(i)); j < dlist_mem_size; j++) { 267 dlist_word = readl((u32 __iomem *)vc4->hvs->dlist + j); 268 drm_printf(&p, "dlist: %02d: 0x%08x\n", j, 269 dlist_word); 270 if (!next_entry_start || 271 next_entry_start == j) { 272 if (dlist_word & SCALER_CTL0_END) 273 break; 274 next_entry_start = j + 275 VC4_GET_FIELD(dlist_word, 276 SCALER_CTL0_SIZE); 277 } 278 } 279 } 280 281 return 0; 282 } 283 284 static int vc6_hvs_debugfs_dlist(struct seq_file *m, void *data) 285 { 286 struct drm_info_node *node = m->private; 287 struct drm_device *dev = node->minor->dev; 288 struct vc4_dev *vc4 = to_vc4_dev(dev); 289 struct vc4_hvs *hvs = vc4->hvs; 290 struct drm_printer p = drm_seq_file_printer(m); 291 unsigned int dlist_mem_size = hvs->dlist_mem_size; 292 unsigned int next_entry_start; 293 unsigned int i; 294 295 for (i = 0; i < SCALER_CHANNELS_COUNT; i++) { 296 unsigned int active_dlist, dispstat; 297 unsigned int j; 298 299 dispstat = VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_STATUS(i)), 300 SCALER6_DISPX_STATUS_MODE); 301 if (dispstat == SCALER6_DISPX_STATUS_MODE_DISABLED || 302 dispstat == SCALER6_DISPX_STATUS_MODE_EOF) { 303 drm_printf(&p, "HVS chan %u disabled\n", i); 304 continue; 305 } 306 307 drm_printf(&p, "HVS chan %u:\n", i); 308 309 active_dlist = VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_DL(i)), 310 SCALER6_DISPX_DL_LACT); 311 next_entry_start = 0; 312 313 for (j = active_dlist; j < dlist_mem_size; j++) { 314 u32 dlist_word; 315 316 dlist_word = readl((u32 __iomem *)vc4->hvs->dlist + j); 317 drm_printf(&p, "dlist: %02d: 0x%08x\n", j, 318 dlist_word); 319 if (!next_entry_start || 320 next_entry_start == j) { 321 if (dlist_word & SCALER_CTL0_END) 322 break; 323 next_entry_start = j + 324 VC4_GET_FIELD(dlist_word, 325 SCALER_CTL0_SIZE); 326 } 327 } 328 } 329 330 return 0; 331 } 332 333 static int vc6_hvs_debugfs_upm_allocs(struct seq_file *m, void *data) 334 { 335 struct drm_debugfs_entry *entry = m->private; 336 struct drm_device *dev = entry->dev; 337 struct vc4_dev *vc4 = to_vc4_dev(dev); 338 struct vc4_hvs *hvs = vc4->hvs; 339 struct drm_printer p = drm_seq_file_printer(m); 340 struct vc4_upm_refcounts *refcount; 341 unsigned int i; 342 343 drm_printf(&p, "UPM Handles:\n"); 344 for (i = 1; i <= VC4_NUM_UPM_HANDLES; i++) { 345 refcount = &hvs->upm_refcounts[i]; 346 drm_printf(&p, "handle %u: refcount %u, size %zu [%08llx + %08llx]\n", 347 i, refcount_read(&refcount->refcount), refcount->size, 348 refcount->upm.start, refcount->upm.size); 349 } 350 351 return 0; 352 } 353 354 /* The filter kernel is composed of dwords each containing 3 9-bit 355 * signed integers packed next to each other. 356 */ 357 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff) 358 #define VC4_PPF_FILTER_WORD(c0, c1, c2) \ 359 ((((c0) & 0x1ff) << 0) | \ 360 (((c1) & 0x1ff) << 9) | \ 361 (((c2) & 0x1ff) << 18)) 362 363 /* The whole filter kernel is arranged as the coefficients 0-16 going 364 * up, then a pad, then 17-31 going down and reversed within the 365 * dwords. This means that a linear phase kernel (where it's 366 * symmetrical at the boundary between 15 and 16) has the last 5 367 * dwords matching the first 5, but reversed. 368 */ 369 #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \ 370 c9, c10, c11, c12, c13, c14, c15) \ 371 {VC4_PPF_FILTER_WORD(c0, c1, c2), \ 372 VC4_PPF_FILTER_WORD(c3, c4, c5), \ 373 VC4_PPF_FILTER_WORD(c6, c7, c8), \ 374 VC4_PPF_FILTER_WORD(c9, c10, c11), \ 375 VC4_PPF_FILTER_WORD(c12, c13, c14), \ 376 VC4_PPF_FILTER_WORD(c15, c15, 0)} 377 378 #define VC4_LINEAR_PHASE_KERNEL_DWORDS 6 379 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1) 380 381 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali. 382 * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf 383 */ 384 static const u32 mitchell_netravali_1_3_1_3_kernel[] = 385 VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18, 386 50, 82, 119, 155, 187, 213, 227); 387 388 static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs, 389 struct drm_mm_node *space, 390 const u32 *kernel) 391 { 392 int ret, i; 393 u32 __iomem *dst_kernel; 394 395 /* 396 * NOTE: We don't need a call to drm_dev_enter()/drm_dev_exit() 397 * here since that function is only called from vc4_hvs_bind(). 398 */ 399 400 ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS); 401 if (ret) { 402 drm_err(&hvs->vc4->base, "Failed to allocate space for filter kernel: %d\n", 403 ret); 404 return ret; 405 } 406 407 dst_kernel = hvs->dlist + space->start; 408 409 for (i = 0; i < VC4_KERNEL_DWORDS; i++) { 410 if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS) 411 writel(kernel[i], &dst_kernel[i]); 412 else { 413 writel(kernel[VC4_KERNEL_DWORDS - i - 1], 414 &dst_kernel[i]); 415 } 416 } 417 418 return 0; 419 } 420 421 static void vc4_hvs_lut_load(struct vc4_hvs *hvs, 422 struct vc4_crtc *vc4_crtc) 423 { 424 struct vc4_dev *vc4 = hvs->vc4; 425 struct drm_device *drm = &vc4->base; 426 struct drm_crtc *crtc = &vc4_crtc->base; 427 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 428 int idx; 429 u32 i; 430 431 WARN_ON_ONCE(vc4->gen > VC4_GEN_5); 432 433 if (!drm_dev_enter(drm, &idx)) 434 return; 435 436 if (hvs->vc4->gen != VC4_GEN_4) 437 goto exit; 438 439 /* The LUT memory is laid out with each HVS channel in order, 440 * each of which takes 256 writes for R, 256 for G, then 256 441 * for B. 442 */ 443 HVS_WRITE(SCALER_GAMADDR, 444 SCALER_GAMADDR_AUTOINC | 445 (vc4_state->assigned_channel * 3 * crtc->gamma_size)); 446 447 for (i = 0; i < crtc->gamma_size; i++) 448 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]); 449 for (i = 0; i < crtc->gamma_size; i++) 450 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]); 451 for (i = 0; i < crtc->gamma_size; i++) 452 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]); 453 454 exit: 455 drm_dev_exit(idx); 456 } 457 458 static void vc4_hvs_update_gamma_lut(struct vc4_hvs *hvs, 459 struct vc4_crtc *vc4_crtc) 460 { 461 struct drm_crtc_state *crtc_state = vc4_crtc->base.state; 462 struct drm_color_lut *lut = crtc_state->gamma_lut->data; 463 u32 length = drm_color_lut_size(crtc_state->gamma_lut); 464 u32 i; 465 466 for (i = 0; i < length; i++) { 467 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8); 468 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8); 469 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8); 470 } 471 472 vc4_hvs_lut_load(hvs, vc4_crtc); 473 } 474 475 u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo) 476 { 477 struct vc4_dev *vc4 = hvs->vc4; 478 struct drm_device *drm = &vc4->base; 479 u8 field = 0; 480 int idx; 481 482 WARN_ON_ONCE(vc4->gen > VC4_GEN_6_D); 483 484 if (!drm_dev_enter(drm, &idx)) 485 return 0; 486 487 switch (vc4->gen) { 488 case VC4_GEN_6_C: 489 case VC4_GEN_6_D: 490 field = VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_STATUS(fifo)), 491 SCALER6_DISPX_STATUS_FRCNT); 492 break; 493 case VC4_GEN_5: 494 switch (fifo) { 495 case 0: 496 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 497 SCALER5_DISPSTAT1_FRCNT0); 498 break; 499 case 1: 500 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 501 SCALER5_DISPSTAT1_FRCNT1); 502 break; 503 case 2: 504 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2), 505 SCALER5_DISPSTAT2_FRCNT2); 506 break; 507 } 508 break; 509 case VC4_GEN_4: 510 switch (fifo) { 511 case 0: 512 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 513 SCALER_DISPSTAT1_FRCNT0); 514 break; 515 case 1: 516 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 517 SCALER_DISPSTAT1_FRCNT1); 518 break; 519 case 2: 520 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2), 521 SCALER_DISPSTAT2_FRCNT2); 522 break; 523 } 524 break; 525 default: 526 drm_err(drm, "Unknown VC4 generation: %d", vc4->gen); 527 break; 528 } 529 530 drm_dev_exit(idx); 531 return field; 532 } 533 534 int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output) 535 { 536 struct vc4_dev *vc4 = hvs->vc4; 537 u32 reg; 538 int ret; 539 540 WARN_ON_ONCE(vc4->gen > VC4_GEN_6_D); 541 542 switch (vc4->gen) { 543 case VC4_GEN_4: 544 return output; 545 546 case VC4_GEN_5: 547 /* 548 * NOTE: We should probably use 549 * drm_dev_enter()/drm_dev_exit() here, but this 550 * function is only used during the DRM device 551 * initialization, so we should be fine. 552 */ 553 554 switch (output) { 555 case 0: 556 return 0; 557 558 case 1: 559 return 1; 560 561 case 2: 562 reg = HVS_READ(SCALER_DISPECTRL); 563 ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg); 564 if (ret == 0) 565 return 2; 566 567 return 0; 568 569 case 3: 570 reg = HVS_READ(SCALER_DISPCTRL); 571 ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg); 572 if (ret == 3) 573 return -EPIPE; 574 575 return ret; 576 577 case 4: 578 reg = HVS_READ(SCALER_DISPEOLN); 579 ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg); 580 if (ret == 3) 581 return -EPIPE; 582 583 return ret; 584 585 case 5: 586 reg = HVS_READ(SCALER_DISPDITHER); 587 ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg); 588 if (ret == 3) 589 return -EPIPE; 590 591 return ret; 592 593 default: 594 return -EPIPE; 595 } 596 597 case VC4_GEN_6_C: 598 case VC4_GEN_6_D: 599 switch (output) { 600 case 0: 601 return 0; 602 603 case 2: 604 return 2; 605 606 case 1: 607 case 3: 608 case 4: 609 return 1; 610 611 default: 612 return -EPIPE; 613 } 614 615 default: 616 return -EPIPE; 617 } 618 } 619 620 static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc, 621 struct drm_display_mode *mode, bool oneshot) 622 { 623 struct vc4_dev *vc4 = hvs->vc4; 624 struct drm_device *drm = &vc4->base; 625 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 626 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); 627 unsigned int chan = vc4_crtc_state->assigned_channel; 628 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; 629 u32 dispbkgndx; 630 u32 dispctrl; 631 int idx; 632 633 WARN_ON_ONCE(vc4->gen > VC4_GEN_5); 634 635 if (!drm_dev_enter(drm, &idx)) 636 return -ENODEV; 637 638 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 639 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); 640 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 641 642 /* Turn on the scaler, which will wait for vstart to start 643 * compositing. 644 * When feeding the transposer, we should operate in oneshot 645 * mode. 646 */ 647 dispctrl = SCALER_DISPCTRLX_ENABLE; 648 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan)); 649 650 if (vc4->gen == VC4_GEN_4) { 651 dispctrl |= VC4_SET_FIELD(mode->hdisplay, 652 SCALER_DISPCTRLX_WIDTH) | 653 VC4_SET_FIELD(mode->vdisplay, 654 SCALER_DISPCTRLX_HEIGHT) | 655 (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0); 656 dispbkgndx |= SCALER_DISPBKGND_AUTOHS; 657 } else { 658 dispctrl |= VC4_SET_FIELD(mode->hdisplay, 659 SCALER5_DISPCTRLX_WIDTH) | 660 VC4_SET_FIELD(mode->vdisplay, 661 SCALER5_DISPCTRLX_HEIGHT) | 662 (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0); 663 dispbkgndx &= ~SCALER5_DISPBKGND_BCK2BCK; 664 } 665 666 HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl); 667 668 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; 669 dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE; 670 671 HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx | 672 ((vc4->gen == VC4_GEN_4) ? SCALER_DISPBKGND_GAMMA : 0) | 673 (interlace ? SCALER_DISPBKGND_INTERLACE : 0)); 674 675 /* Reload the LUT, since the SRAMs would have been disabled if 676 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once. 677 */ 678 vc4_hvs_lut_load(hvs, vc4_crtc); 679 680 drm_dev_exit(idx); 681 682 return 0; 683 } 684 685 static int vc6_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc, 686 struct drm_display_mode *mode, bool oneshot) 687 { 688 struct vc4_dev *vc4 = hvs->vc4; 689 struct drm_device *drm = &vc4->base; 690 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); 691 unsigned int chan = vc4_crtc_state->assigned_channel; 692 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; 693 u32 disp_ctrl1; 694 int idx; 695 696 WARN_ON_ONCE(vc4->gen < VC4_GEN_6_C); 697 698 if (!drm_dev_enter(drm, &idx)) 699 return -ENODEV; 700 701 HVS_WRITE(SCALER6_DISPX_CTRL0(chan), SCALER6_DISPX_CTRL0_RESET); 702 703 disp_ctrl1 = HVS_READ(SCALER6_DISPX_CTRL1(chan)); 704 disp_ctrl1 &= ~SCALER6_DISPX_CTRL1_INTLACE; 705 HVS_WRITE(SCALER6_DISPX_CTRL1(chan), 706 disp_ctrl1 | (interlace ? SCALER6_DISPX_CTRL1_INTLACE : 0)); 707 708 HVS_WRITE(SCALER6_DISPX_CTRL0(chan), 709 SCALER6_DISPX_CTRL0_ENB | 710 VC4_SET_FIELD(mode->hdisplay - 1, 711 SCALER6_DISPX_CTRL0_FWIDTH) | 712 (oneshot ? SCALER6_DISPX_CTRL0_ONESHOT : 0) | 713 VC4_SET_FIELD(mode->vdisplay - 1, 714 SCALER6_DISPX_CTRL0_LINES)); 715 716 drm_dev_exit(idx); 717 718 return 0; 719 } 720 721 static void __vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan) 722 { 723 struct vc4_dev *vc4 = hvs->vc4; 724 struct drm_device *drm = &vc4->base; 725 int idx; 726 727 WARN_ON_ONCE(vc4->gen > VC4_GEN_5); 728 729 if (!drm_dev_enter(drm, &idx)) 730 return; 731 732 if (!(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE)) 733 goto out; 734 735 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); 736 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 737 738 /* Once we leave, the scaler should be disabled and its fifo empty. */ 739 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET); 740 741 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)), 742 SCALER_DISPSTATX_MODE) != 743 SCALER_DISPSTATX_MODE_DISABLED); 744 745 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) & 746 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) != 747 SCALER_DISPSTATX_EMPTY); 748 749 out: 750 drm_dev_exit(idx); 751 } 752 753 static void __vc6_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan) 754 { 755 struct vc4_dev *vc4 = hvs->vc4; 756 struct drm_device *drm = &vc4->base; 757 int idx; 758 759 WARN_ON_ONCE(vc4->gen < VC4_GEN_6_C); 760 761 if (!drm_dev_enter(drm, &idx)) 762 return; 763 764 if (!(HVS_READ(SCALER6_DISPX_CTRL0(chan)) & SCALER6_DISPX_CTRL0_ENB)) 765 goto out; 766 767 HVS_WRITE(SCALER6_DISPX_CTRL0(chan), 768 HVS_READ(SCALER6_DISPX_CTRL0(chan)) | SCALER6_DISPX_CTRL0_RESET); 769 770 HVS_WRITE(SCALER6_DISPX_CTRL0(chan), 771 HVS_READ(SCALER6_DISPX_CTRL0(chan)) & ~SCALER6_DISPX_CTRL0_ENB); 772 773 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_STATUS(chan)), 774 SCALER6_DISPX_STATUS_MODE) != 775 SCALER6_DISPX_STATUS_MODE_DISABLED); 776 777 out: 778 drm_dev_exit(idx); 779 } 780 781 void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan) 782 { 783 struct vc4_dev *vc4 = hvs->vc4; 784 785 if (vc4->gen >= VC4_GEN_6_C) 786 __vc6_hvs_stop_channel(hvs, chan); 787 else 788 __vc4_hvs_stop_channel(hvs, chan); 789 } 790 791 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *state) 792 { 793 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 794 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); 795 struct drm_device *dev = crtc->dev; 796 struct vc4_dev *vc4 = to_vc4_dev(dev); 797 struct drm_plane *plane; 798 unsigned long flags; 799 const struct drm_plane_state *plane_state; 800 u32 dlist_count = 0; 801 int ret; 802 803 /* The pixelvalve can only feed one encoder (and encoders are 804 * 1:1 with connectors.) 805 */ 806 if (hweight32(crtc_state->connector_mask) > 1) 807 return -EINVAL; 808 809 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) { 810 u32 plane_dlist_count = vc4_plane_dlist_size(plane_state); 811 812 drm_dbg_driver(dev, "[CRTC:%d:%s] Found [PLANE:%d:%s] with DLIST size: %u\n", 813 crtc->base.id, crtc->name, 814 plane->base.id, plane->name, 815 plane_dlist_count); 816 817 dlist_count += plane_dlist_count; 818 } 819 820 dlist_count++; /* Account for SCALER_CTL0_END. */ 821 822 drm_dbg_driver(dev, "[CRTC:%d:%s] Allocating DLIST block with size: %u\n", 823 crtc->base.id, crtc->name, dlist_count); 824 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); 825 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm, 826 dlist_count); 827 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); 828 if (ret) { 829 drm_err(dev, "Failed to allocate DLIST entry: %d\n", ret); 830 return ret; 831 } 832 833 return 0; 834 } 835 836 static void vc4_hvs_install_dlist(struct drm_crtc *crtc) 837 { 838 struct drm_device *dev = crtc->dev; 839 struct vc4_dev *vc4 = to_vc4_dev(dev); 840 struct vc4_hvs *hvs = vc4->hvs; 841 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 842 int idx; 843 844 if (!drm_dev_enter(dev, &idx)) 845 return; 846 847 if (vc4->gen >= VC4_GEN_6_C) 848 HVS_WRITE(SCALER6_DISPX_LPTRS(vc4_state->assigned_channel), 849 VC4_SET_FIELD(vc4_state->mm.start, 850 SCALER6_DISPX_LPTRS_HEADE)); 851 else 852 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel), 853 vc4_state->mm.start); 854 855 drm_dev_exit(idx); 856 } 857 858 static void vc4_hvs_update_dlist(struct drm_crtc *crtc) 859 { 860 struct drm_device *dev = crtc->dev; 861 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 862 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 863 unsigned long flags; 864 865 if (crtc->state->event) { 866 crtc->state->event->pipe = drm_crtc_index(crtc); 867 868 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 869 870 spin_lock_irqsave(&dev->event_lock, flags); 871 872 if (!vc4_crtc->feeds_txp || vc4_state->txp_armed) { 873 vc4_crtc->event = crtc->state->event; 874 crtc->state->event = NULL; 875 } 876 877 spin_unlock_irqrestore(&dev->event_lock, flags); 878 } 879 880 spin_lock_irqsave(&vc4_crtc->irq_lock, flags); 881 vc4_crtc->current_dlist = vc4_state->mm.start; 882 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags); 883 } 884 885 void vc4_hvs_atomic_begin(struct drm_crtc *crtc, 886 struct drm_atomic_commit *state) 887 { 888 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 889 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 890 unsigned long flags; 891 892 spin_lock_irqsave(&vc4_crtc->irq_lock, flags); 893 vc4_crtc->current_hvs_channel = vc4_state->assigned_channel; 894 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags); 895 } 896 897 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, 898 struct drm_atomic_commit *state) 899 { 900 struct drm_device *dev = crtc->dev; 901 struct vc4_dev *vc4 = to_vc4_dev(dev); 902 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 903 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 904 bool oneshot = vc4_crtc->feeds_txp; 905 906 vc4_hvs_install_dlist(crtc); 907 vc4_hvs_update_dlist(crtc); 908 909 if (vc4->gen >= VC4_GEN_6_C) 910 vc6_hvs_init_channel(vc4->hvs, crtc, mode, oneshot); 911 else 912 vc4_hvs_init_channel(vc4->hvs, crtc, mode, oneshot); 913 } 914 915 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, 916 struct drm_atomic_commit *state) 917 { 918 struct drm_device *dev = crtc->dev; 919 struct vc4_dev *vc4 = to_vc4_dev(dev); 920 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); 921 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state); 922 unsigned int chan = vc4_state->assigned_channel; 923 924 vc4_hvs_stop_channel(vc4->hvs, chan); 925 } 926 927 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, 928 struct drm_atomic_commit *state) 929 { 930 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 931 crtc); 932 struct drm_device *dev = crtc->dev; 933 struct vc4_dev *vc4 = to_vc4_dev(dev); 934 struct vc4_hvs *hvs = vc4->hvs; 935 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 936 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 937 unsigned int channel = vc4_state->assigned_channel; 938 struct drm_plane *plane; 939 struct vc4_plane_state *vc4_plane_state; 940 bool debug_dump_regs = false; 941 bool enable_bg_fill = true; 942 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start; 943 u32 __iomem *dlist_next = dlist_start; 944 unsigned int zpos = 0; 945 bool found = false; 946 int idx; 947 948 WARN_ON_ONCE(vc4->gen > VC4_GEN_6_D); 949 950 if (!drm_dev_enter(dev, &idx)) { 951 vc4_crtc_send_vblank(crtc); 952 return; 953 } 954 955 if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) 956 goto exit; 957 958 if (debug_dump_regs) { 959 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc)); 960 vc4_hvs_dump_state(hvs); 961 } 962 963 /* Copy all the active planes' dlist contents to the hardware dlist. */ 964 do { 965 found = false; 966 967 drm_atomic_crtc_for_each_plane(plane, crtc) { 968 if (plane->state->normalized_zpos != zpos) 969 continue; 970 971 /* Is this the first active plane? */ 972 if (dlist_next == dlist_start) { 973 /* We need to enable background fill when a plane 974 * could be alpha blending from the background, i.e. 975 * where no other plane is underneath. It suffices to 976 * consider the first active plane here since we set 977 * needs_bg_fill such that either the first plane 978 * already needs it or all planes on top blend from 979 * the first or a lower plane. 980 */ 981 vc4_plane_state = to_vc4_plane_state(plane->state); 982 enable_bg_fill = vc4_plane_state->needs_bg_fill; 983 } 984 985 dlist_next += vc4_plane_write_dlist(plane, dlist_next); 986 987 found = true; 988 } 989 990 zpos++; 991 } while (found); 992 993 writel(SCALER_CTL0_END, dlist_next); 994 dlist_next++; 995 996 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); 997 998 if (vc4->gen >= VC4_GEN_6_C) { 999 /* This sets a black background color fill, as is the case 1000 * with other DRM drivers. 1001 */ 1002 if (enable_bg_fill) 1003 HVS_WRITE(SCALER6_DISPX_CTRL1(channel), 1004 HVS_READ(SCALER6_DISPX_CTRL1(channel)) | 1005 SCALER6_DISPX_CTRL1_BGENB); 1006 else 1007 HVS_WRITE(SCALER6_DISPX_CTRL1(channel), 1008 HVS_READ(SCALER6_DISPX_CTRL1(channel)) & 1009 ~SCALER6_DISPX_CTRL1_BGENB); 1010 } else { 1011 /* we can actually run with a lower core clock when background 1012 * fill is enabled on VC4_GEN_5 so leave it enabled always. 1013 */ 1014 HVS_WRITE(SCALER_DISPBKGNDX(channel), 1015 HVS_READ(SCALER_DISPBKGNDX(channel)) | 1016 SCALER_DISPBKGND_FILL); 1017 } 1018 1019 /* Only update DISPLIST if the CRTC was already running and is not 1020 * being disabled. 1021 * vc4_crtc_enable() takes care of updating the dlist just after 1022 * re-enabling VBLANK interrupts and before enabling the engine. 1023 * If the CRTC is being disabled, there's no point in updating this 1024 * information. 1025 */ 1026 if (crtc->state->active && old_state->active) { 1027 vc4_hvs_install_dlist(crtc); 1028 vc4_hvs_update_dlist(crtc); 1029 } 1030 1031 if (crtc->state->color_mgmt_changed) { 1032 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel)); 1033 1034 WARN_ON_ONCE(vc4->gen > VC4_GEN_5); 1035 1036 if (crtc->state->gamma_lut) { 1037 vc4_hvs_update_gamma_lut(hvs, vc4_crtc); 1038 dispbkgndx |= SCALER_DISPBKGND_GAMMA; 1039 } else { 1040 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step 1041 * in hardware, which is the same as a linear lut that 1042 * DRM expects us to use in absence of a user lut. 1043 */ 1044 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; 1045 } 1046 HVS_WRITE(SCALER_DISPBKGNDX(channel), dispbkgndx); 1047 } 1048 1049 if (debug_dump_regs) { 1050 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); 1051 vc4_hvs_dump_state(hvs); 1052 } 1053 1054 exit: 1055 drm_dev_exit(idx); 1056 } 1057 1058 void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel) 1059 { 1060 struct vc4_dev *vc4 = hvs->vc4; 1061 struct drm_device *drm = &vc4->base; 1062 u32 dispctrl; 1063 int idx; 1064 1065 WARN_ON(vc4->gen > VC4_GEN_5); 1066 1067 if (!drm_dev_enter(drm, &idx)) 1068 return; 1069 1070 dispctrl = HVS_READ(SCALER_DISPCTRL); 1071 dispctrl &= ~((vc4->gen == VC4_GEN_5) ? 1072 SCALER5_DISPCTRL_DSPEISLUR(channel) : 1073 SCALER_DISPCTRL_DSPEISLUR(channel)); 1074 1075 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 1076 1077 drm_dev_exit(idx); 1078 } 1079 1080 void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel) 1081 { 1082 struct vc4_dev *vc4 = hvs->vc4; 1083 struct drm_device *drm = &vc4->base; 1084 u32 dispctrl; 1085 int idx; 1086 1087 WARN_ON(vc4->gen > VC4_GEN_5); 1088 1089 if (!drm_dev_enter(drm, &idx)) 1090 return; 1091 1092 dispctrl = HVS_READ(SCALER_DISPCTRL); 1093 dispctrl |= ((vc4->gen == VC4_GEN_5) ? 1094 SCALER5_DISPCTRL_DSPEISLUR(channel) : 1095 SCALER_DISPCTRL_DSPEISLUR(channel)); 1096 1097 HVS_WRITE(SCALER_DISPSTAT, 1098 SCALER_DISPSTAT_EUFLOW(channel)); 1099 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 1100 1101 drm_dev_exit(idx); 1102 } 1103 1104 static void vc4_hvs_report_underrun(struct drm_device *dev) 1105 { 1106 struct vc4_dev *vc4 = to_vc4_dev(dev); 1107 1108 atomic_inc(&vc4->underrun); 1109 DRM_DEV_ERROR(dev->dev, "HVS underrun\n"); 1110 } 1111 1112 static irqreturn_t vc4_hvs_irq_handler(int irq, void *data) 1113 { 1114 struct drm_device *dev = data; 1115 struct vc4_dev *vc4 = to_vc4_dev(dev); 1116 struct vc4_hvs *hvs = vc4->hvs; 1117 irqreturn_t irqret = IRQ_NONE; 1118 int channel; 1119 u32 control; 1120 u32 status; 1121 u32 dspeislur; 1122 1123 WARN_ON(vc4->gen > VC4_GEN_5); 1124 1125 /* 1126 * NOTE: We don't need to protect the register access using 1127 * drm_dev_enter() there because the interrupt handler lifetime 1128 * is tied to the device itself, and not to the DRM device. 1129 * 1130 * So when the device will be gone, one of the first thing we 1131 * will be doing will be to unregister the interrupt handler, 1132 * and then unregister the DRM device. drm_dev_enter() would 1133 * thus always succeed if we are here. 1134 */ 1135 1136 status = HVS_READ(SCALER_DISPSTAT); 1137 control = HVS_READ(SCALER_DISPCTRL); 1138 1139 for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) { 1140 dspeislur = (vc4->gen == VC4_GEN_5) ? 1141 SCALER5_DISPCTRL_DSPEISLUR(channel) : 1142 SCALER_DISPCTRL_DSPEISLUR(channel); 1143 1144 /* Interrupt masking is not always honored, so check it here. */ 1145 if (status & SCALER_DISPSTAT_EUFLOW(channel) && 1146 control & dspeislur) { 1147 vc4_hvs_mask_underrun(hvs, channel); 1148 vc4_hvs_report_underrun(dev); 1149 1150 irqret = IRQ_HANDLED; 1151 } 1152 } 1153 1154 /* Clear every per-channel interrupt flag. */ 1155 HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) | 1156 SCALER_DISPSTAT_IRQMASK(1) | 1157 SCALER_DISPSTAT_IRQMASK(2)); 1158 1159 return irqret; 1160 } 1161 1162 int vc4_hvs_debugfs_init(struct drm_minor *minor) 1163 { 1164 struct drm_device *drm = minor->dev; 1165 struct vc4_dev *vc4 = to_vc4_dev(drm); 1166 struct vc4_hvs *hvs = vc4->hvs; 1167 1168 if (!vc4->hvs) 1169 return -ENODEV; 1170 1171 if (vc4->gen == VC4_GEN_4) 1172 debugfs_create_bool("hvs_load_tracker", S_IRUGO | S_IWUSR, 1173 minor->debugfs_root, 1174 &vc4->load_tracker_enabled); 1175 1176 if (vc4->gen >= VC4_GEN_6_C) { 1177 drm_debugfs_add_file(drm, "hvs_dlists", vc6_hvs_debugfs_dlist, NULL); 1178 drm_debugfs_add_file(drm, "hvs_upm", vc6_hvs_debugfs_upm_allocs, NULL); 1179 } else { 1180 drm_debugfs_add_file(drm, "hvs_dlists", vc4_hvs_debugfs_dlist, NULL); 1181 } 1182 1183 drm_debugfs_add_file(drm, "hvs_underrun", vc4_hvs_debugfs_underrun, NULL); 1184 1185 vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset); 1186 1187 return 0; 1188 } 1189 1190 struct vc4_hvs *__vc4_hvs_alloc(struct vc4_dev *vc4, 1191 void __iomem *regs, 1192 struct platform_device *pdev) 1193 { 1194 struct drm_device *drm = &vc4->base; 1195 struct vc4_hvs *hvs; 1196 unsigned int dlist_start; 1197 size_t dlist_size; 1198 size_t lbm_size; 1199 unsigned int i; 1200 1201 hvs = drmm_kzalloc(drm, sizeof(*hvs), GFP_KERNEL); 1202 if (!hvs) 1203 return ERR_PTR(-ENOMEM); 1204 1205 hvs->vc4 = vc4; 1206 hvs->regs = regs; 1207 hvs->pdev = pdev; 1208 1209 spin_lock_init(&hvs->mm_lock); 1210 1211 switch (vc4->gen) { 1212 case VC4_GEN_4: 1213 case VC4_GEN_5: 1214 /* Set up the HVS display list memory manager. We never 1215 * overwrite the setup from the bootloader (just 128b 1216 * out of our 16K), since we don't want to scramble the 1217 * screen when transitioning from the firmware's boot 1218 * setup to runtime. 1219 */ 1220 dlist_start = HVS_BOOTLOADER_DLIST_END; 1221 dlist_size = (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END; 1222 break; 1223 1224 case VC4_GEN_6_C: 1225 case VC4_GEN_6_D: 1226 dlist_start = HVS_BOOTLOADER_DLIST_END; 1227 1228 /* 1229 * If we are running a test, it means that we can't 1230 * access a register. Use a plausible size then. 1231 */ 1232 if (!kunit_get_current_test()) 1233 dlist_size = HVS_READ(SCALER6_CXM_SIZE); 1234 else 1235 dlist_size = 4096; 1236 1237 for (i = 0; i < VC4_NUM_UPM_HANDLES; i++) { 1238 refcount_set(&hvs->upm_refcounts[i].refcount, 0); 1239 hvs->upm_refcounts[i].hvs = hvs; 1240 } 1241 1242 break; 1243 1244 default: 1245 drm_err(drm, "Unknown VC4 generation: %d", vc4->gen); 1246 return ERR_PTR(-ENODEV); 1247 } 1248 1249 drm_mm_init(&hvs->dlist_mm, dlist_start, dlist_size); 1250 1251 hvs->dlist_mem_size = dlist_size; 1252 1253 /* Set up the HVS LBM memory manager. We could have some more 1254 * complicated data structure that allowed reuse of LBM areas 1255 * between planes when they don't overlap on the screen, but 1256 * for now we just allocate globally. 1257 */ 1258 1259 switch (vc4->gen) { 1260 case VC4_GEN_4: 1261 /* 48k words of 2x12-bit pixels */ 1262 lbm_size = 48 * SZ_1K; 1263 break; 1264 1265 case VC4_GEN_5: 1266 /* 60k words of 4x12-bit pixels */ 1267 lbm_size = 60 * SZ_1K; 1268 break; 1269 1270 case VC4_GEN_6_C: 1271 case VC4_GEN_6_D: 1272 /* 1273 * If we are running a test, it means that we can't 1274 * access a register. Use a plausible size then. 1275 */ 1276 lbm_size = 1024; 1277 break; 1278 1279 default: 1280 drm_err(drm, "Unknown VC4 generation: %d", vc4->gen); 1281 return ERR_PTR(-ENODEV); 1282 } 1283 1284 drm_mm_init(&hvs->lbm_mm, 0, lbm_size); 1285 1286 if (vc4->gen >= VC4_GEN_6_C) { 1287 ida_init(&hvs->upm_handles); 1288 1289 /* 1290 * NOTE: On BCM2712, the size can also be read through 1291 * the SCALER_UBM_SIZE register. We would need to do a 1292 * register access though, which we can't do with kunit 1293 * that also uses this function to create its mock 1294 * device. 1295 */ 1296 drm_mm_init(&hvs->upm_mm, 0, 1024 * HVS_UBM_WORD_SIZE); 1297 } 1298 1299 1300 vc4->hvs = hvs; 1301 1302 return hvs; 1303 } 1304 1305 static int vc4_hvs_hw_init(struct vc4_hvs *hvs) 1306 { 1307 struct vc4_dev *vc4 = hvs->vc4; 1308 u32 dispctrl, reg; 1309 1310 dispctrl = HVS_READ(SCALER_DISPCTRL); 1311 dispctrl |= SCALER_DISPCTRL_ENABLE; 1312 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 1313 1314 reg = HVS_READ(SCALER_DISPECTRL); 1315 reg &= ~SCALER_DISPECTRL_DSP2_MUX_MASK; 1316 HVS_WRITE(SCALER_DISPECTRL, 1317 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX)); 1318 1319 reg = HVS_READ(SCALER_DISPCTRL); 1320 reg &= ~SCALER_DISPCTRL_DSP3_MUX_MASK; 1321 HVS_WRITE(SCALER_DISPCTRL, 1322 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX)); 1323 1324 reg = HVS_READ(SCALER_DISPEOLN); 1325 reg &= ~SCALER_DISPEOLN_DSP4_MUX_MASK; 1326 HVS_WRITE(SCALER_DISPEOLN, 1327 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX)); 1328 1329 reg = HVS_READ(SCALER_DISPDITHER); 1330 reg &= ~SCALER_DISPDITHER_DSP5_MUX_MASK; 1331 HVS_WRITE(SCALER_DISPDITHER, 1332 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX)); 1333 1334 dispctrl = HVS_READ(SCALER_DISPCTRL); 1335 dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) | 1336 SCALER_DISPCTRL_DISPEIRQ(1) | 1337 SCALER_DISPCTRL_DISPEIRQ(2); 1338 1339 if (vc4->gen == VC4_GEN_4) 1340 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ | 1341 SCALER_DISPCTRL_SLVWREIRQ | 1342 SCALER_DISPCTRL_SLVRDEIRQ | 1343 SCALER_DISPCTRL_DSPEIEOF(0) | 1344 SCALER_DISPCTRL_DSPEIEOF(1) | 1345 SCALER_DISPCTRL_DSPEIEOF(2) | 1346 SCALER_DISPCTRL_DSPEIEOLN(0) | 1347 SCALER_DISPCTRL_DSPEIEOLN(1) | 1348 SCALER_DISPCTRL_DSPEIEOLN(2) | 1349 SCALER_DISPCTRL_DSPEISLUR(0) | 1350 SCALER_DISPCTRL_DSPEISLUR(1) | 1351 SCALER_DISPCTRL_DSPEISLUR(2) | 1352 SCALER_DISPCTRL_SCLEIRQ); 1353 else 1354 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ | 1355 SCALER5_DISPCTRL_SLVEIRQ | 1356 SCALER5_DISPCTRL_DSPEIEOF(0) | 1357 SCALER5_DISPCTRL_DSPEIEOF(1) | 1358 SCALER5_DISPCTRL_DSPEIEOF(2) | 1359 SCALER5_DISPCTRL_DSPEIEOLN(0) | 1360 SCALER5_DISPCTRL_DSPEIEOLN(1) | 1361 SCALER5_DISPCTRL_DSPEIEOLN(2) | 1362 SCALER5_DISPCTRL_DSPEISLUR(0) | 1363 SCALER5_DISPCTRL_DSPEISLUR(1) | 1364 SCALER5_DISPCTRL_DSPEISLUR(2) | 1365 SCALER_DISPCTRL_SCLEIRQ); 1366 1367 1368 /* Set AXI panic mode. 1369 * VC4 panics when < 2 lines in FIFO. 1370 * VC5 panics when less than 1 line in the FIFO. 1371 */ 1372 dispctrl &= ~(SCALER_DISPCTRL_PANIC0_MASK | 1373 SCALER_DISPCTRL_PANIC1_MASK | 1374 SCALER_DISPCTRL_PANIC2_MASK); 1375 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0); 1376 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1); 1377 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2); 1378 1379 /* Set AXI panic mode. 1380 * VC4 panics when < 2 lines in FIFO. 1381 * VC5 panics when less than 1 line in the FIFO. 1382 */ 1383 dispctrl &= ~(SCALER_DISPCTRL_PANIC0_MASK | 1384 SCALER_DISPCTRL_PANIC1_MASK | 1385 SCALER_DISPCTRL_PANIC2_MASK); 1386 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC0); 1387 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC1); 1388 dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2); 1389 1390 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 1391 1392 return 0; 1393 } 1394 1395 #define CFC1_N_NL_CSC_CTRL(x) (0xa000 + ((x) * 0x3000)) 1396 #define CFC1_N_MA_CSC_COEFF_C00(x) (0xa008 + ((x) * 0x3000)) 1397 #define CFC1_N_MA_CSC_COEFF_C01(x) (0xa00c + ((x) * 0x3000)) 1398 #define CFC1_N_MA_CSC_COEFF_C02(x) (0xa010 + ((x) * 0x3000)) 1399 #define CFC1_N_MA_CSC_COEFF_C03(x) (0xa014 + ((x) * 0x3000)) 1400 #define CFC1_N_MA_CSC_COEFF_C04(x) (0xa018 + ((x) * 0x3000)) 1401 #define CFC1_N_MA_CSC_COEFF_C10(x) (0xa01c + ((x) * 0x3000)) 1402 #define CFC1_N_MA_CSC_COEFF_C11(x) (0xa020 + ((x) * 0x3000)) 1403 #define CFC1_N_MA_CSC_COEFF_C12(x) (0xa024 + ((x) * 0x3000)) 1404 #define CFC1_N_MA_CSC_COEFF_C13(x) (0xa028 + ((x) * 0x3000)) 1405 #define CFC1_N_MA_CSC_COEFF_C14(x) (0xa02c + ((x) * 0x3000)) 1406 #define CFC1_N_MA_CSC_COEFF_C20(x) (0xa030 + ((x) * 0x3000)) 1407 #define CFC1_N_MA_CSC_COEFF_C21(x) (0xa034 + ((x) * 0x3000)) 1408 #define CFC1_N_MA_CSC_COEFF_C22(x) (0xa038 + ((x) * 0x3000)) 1409 #define CFC1_N_MA_CSC_COEFF_C23(x) (0xa03c + ((x) * 0x3000)) 1410 #define CFC1_N_MA_CSC_COEFF_C24(x) (0xa040 + ((x) * 0x3000)) 1411 1412 #define SCALER_PI_CMP_CSC_RED0(x) (0x200 + ((x) * 0x40)) 1413 #define SCALER_PI_CMP_CSC_RED1(x) (0x204 + ((x) * 0x40)) 1414 #define SCALER_PI_CMP_CSC_RED_CLAMP(x) (0x208 + ((x) * 0x40)) 1415 #define SCALER_PI_CMP_CSC_CFG(x) (0x20c + ((x) * 0x40)) 1416 #define SCALER_PI_CMP_CSC_GREEN0(x) (0x210 + ((x) * 0x40)) 1417 #define SCALER_PI_CMP_CSC_GREEN1(x) (0x214 + ((x) * 0x40)) 1418 #define SCALER_PI_CMP_CSC_GREEN_CLAMP(x) (0x218 + ((x) * 0x40)) 1419 #define SCALER_PI_CMP_CSC_BLUE0(x) (0x220 + ((x) * 0x40)) 1420 #define SCALER_PI_CMP_CSC_BLUE1(x) (0x224 + ((x) * 0x40)) 1421 #define SCALER_PI_CMP_CSC_BLUE_CLAMP(x) (0x228 + ((x) * 0x40)) 1422 1423 /* 4 S2.22 multiplication factors, and 1 S9.15 addititive element for each of 3 1424 * output components 1425 */ 1426 struct vc6_csc_coeff_entry { 1427 u32 csc[3][5]; 1428 }; 1429 1430 static const struct vc6_csc_coeff_entry csc_coeffs[2][3] = { 1431 [DRM_COLOR_YCBCR_LIMITED_RANGE] = { 1432 [DRM_COLOR_YCBCR_BT601] = { 1433 .csc = { 1434 { 0x004A8542, 0x0, 0x0066254A, 0x0, 0xFF908A0D }, 1435 { 0x004A8542, 0xFFE6ED5D, 0xFFCBF856, 0x0, 0x0043C9A3 }, 1436 { 0x004A8542, 0x00811A54, 0x0, 0x0, 0xFF759502 } 1437 } 1438 }, 1439 [DRM_COLOR_YCBCR_BT709] = { 1440 .csc = { 1441 { 0x004A8542, 0x0, 0x0072BC44, 0x0, 0xFF83F312 }, 1442 { 0x004A8542, 0xFFF25A22, 0xFFDDE4D0, 0x0, 0x00267064 }, 1443 { 0x004A8542, 0x00873197, 0x0, 0x0, 0xFF6F7DC0 } 1444 } 1445 }, 1446 [DRM_COLOR_YCBCR_BT2020] = { 1447 .csc = { 1448 { 0x004A8542, 0x0, 0x006B4A17, 0x0, 0xFF8B653F }, 1449 { 0x004A8542, 0xFFF402D9, 0xFFDDE4D0, 0x0, 0x0024C7AE }, 1450 { 0x004A8542, 0x008912CC, 0x0, 0x0, 0xFF6D9C8B } 1451 } 1452 } 1453 }, 1454 [DRM_COLOR_YCBCR_FULL_RANGE] = { 1455 [DRM_COLOR_YCBCR_BT601] = { 1456 .csc = { 1457 { 0x00400000, 0x0, 0x0059BA5E, 0x0, 0xFFA645A1 }, 1458 { 0x00400000, 0xFFE9F9AC, 0xFFD24B97, 0x0, 0x0043BABB }, 1459 { 0x00400000, 0x00716872, 0x0, 0x0, 0xFF8E978D } 1460 } 1461 }, 1462 [DRM_COLOR_YCBCR_BT709] = { 1463 .csc = { 1464 { 0x00400000, 0x0, 0x0064C985, 0x0, 0xFF9B367A }, 1465 { 0x00400000, 0xFFF402E1, 0xFFE20A40, 0x0, 0x0029F2DE }, 1466 { 0x00400000, 0x0076C226, 0x0, 0x0, 0xFF893DD9 } 1467 } 1468 }, 1469 [DRM_COLOR_YCBCR_BT2020] = { 1470 .csc = { 1471 { 0x00400000, 0x0, 0x005E3F14, 0x0, 0xFFA1C0EB }, 1472 { 0x00400000, 0xFFF577F6, 0xFFDB580F, 0x0, 0x002F2FFA }, 1473 { 0x00400000, 0x007868DB, 0x0, 0x0, 0xFF879724 } 1474 } 1475 } 1476 } 1477 }; 1478 1479 static int vc6_hvs_hw_init(struct vc4_hvs *hvs) 1480 { 1481 const struct vc6_csc_coeff_entry *coeffs; 1482 unsigned int i; 1483 1484 HVS_WRITE(SCALER6_CONTROL, 1485 SCALER6_CONTROL_HVS_EN | 1486 VC4_SET_FIELD(8, SCALER6_CONTROL_PF_LINES) | 1487 VC4_SET_FIELD(15, SCALER6_CONTROL_MAX_REQS)); 1488 1489 /* Set HVS arbiter priority to max */ 1490 HVS_WRITE(SCALER6(PRI_MAP0), 0xffffffff); 1491 HVS_WRITE(SCALER6(PRI_MAP1), 0xffffffff); 1492 1493 if (hvs->vc4->gen == VC4_GEN_6_C) { 1494 for (i = 0; i < 6; i++) { 1495 coeffs = &csc_coeffs[i / 3][i % 3]; 1496 1497 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C00(i), coeffs->csc[0][0]); 1498 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C01(i), coeffs->csc[0][1]); 1499 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C02(i), coeffs->csc[0][2]); 1500 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C03(i), coeffs->csc[0][3]); 1501 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C04(i), coeffs->csc[0][4]); 1502 1503 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C10(i), coeffs->csc[1][0]); 1504 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C11(i), coeffs->csc[1][1]); 1505 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C12(i), coeffs->csc[1][2]); 1506 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C13(i), coeffs->csc[1][3]); 1507 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C14(i), coeffs->csc[1][4]); 1508 1509 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C20(i), coeffs->csc[2][0]); 1510 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C21(i), coeffs->csc[2][1]); 1511 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C22(i), coeffs->csc[2][2]); 1512 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C23(i), coeffs->csc[2][3]); 1513 HVS_WRITE(CFC1_N_MA_CSC_COEFF_C24(i), coeffs->csc[2][4]); 1514 1515 HVS_WRITE(CFC1_N_NL_CSC_CTRL(i), BIT(15)); 1516 } 1517 } else { 1518 for (i = 0; i < 8; i++) { 1519 HVS_WRITE(SCALER_PI_CMP_CSC_RED0(i), 0x1f002566); 1520 HVS_WRITE(SCALER_PI_CMP_CSC_RED1(i), 0x3994); 1521 HVS_WRITE(SCALER_PI_CMP_CSC_RED_CLAMP(i), 0xfff00000); 1522 HVS_WRITE(SCALER_PI_CMP_CSC_CFG(i), 0x1); 1523 HVS_WRITE(SCALER_PI_CMP_CSC_GREEN0(i), 0x18002566); 1524 HVS_WRITE(SCALER_PI_CMP_CSC_GREEN1(i), 0xf927eee2); 1525 HVS_WRITE(SCALER_PI_CMP_CSC_GREEN_CLAMP(i), 0xfff00000); 1526 HVS_WRITE(SCALER_PI_CMP_CSC_BLUE0(i), 0x18002566); 1527 HVS_WRITE(SCALER_PI_CMP_CSC_BLUE1(i), 0x43d80000); 1528 HVS_WRITE(SCALER_PI_CMP_CSC_BLUE_CLAMP(i), 0xfff00000); 1529 } 1530 } 1531 1532 return 0; 1533 } 1534 1535 static int vc4_hvs_cob_init(struct vc4_hvs *hvs) 1536 { 1537 struct vc4_dev *vc4 = hvs->vc4; 1538 u32 reg, top, base; 1539 1540 /* 1541 * Recompute Composite Output Buffer (COB) allocations for the 1542 * displays 1543 */ 1544 switch (vc4->gen) { 1545 case VC4_GEN_4: 1546 /* The COB is 20736 pixels, or just over 10 lines at 2048 wide. 1547 * The bottom 2048 pixels are full 32bpp RGBA (intended for the 1548 * TXP composing RGBA to memory), whilst the remainder are only 1549 * 24bpp RGB. 1550 * 1551 * Assign 3 lines to channels 1 & 2, and just over 4 lines to 1552 * channel 0. 1553 */ 1554 #define VC4_COB_SIZE 20736 1555 #define VC4_COB_LINE_WIDTH 2048 1556 #define VC4_COB_NUM_LINES 3 1557 reg = 0; 1558 top = VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES; 1559 reg |= (top - 1) << 16; 1560 HVS_WRITE(SCALER_DISPBASE2, reg); 1561 reg = top; 1562 top += VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES; 1563 reg |= (top - 1) << 16; 1564 HVS_WRITE(SCALER_DISPBASE1, reg); 1565 reg = top; 1566 top = VC4_COB_SIZE; 1567 reg |= (top - 1) << 16; 1568 HVS_WRITE(SCALER_DISPBASE0, reg); 1569 break; 1570 1571 case VC4_GEN_5: 1572 /* The COB is 44416 pixels, or 10.8 lines at 4096 wide. 1573 * The bottom 4096 pixels are full RGBA (intended for the TXP 1574 * composing RGBA to memory), whilst the remainder are only 1575 * RGB. Addressing is always pixel wide. 1576 * 1577 * Assign 3 lines of 4096 to channels 1 & 2, and just over 4 1578 * lines. to channel 0. 1579 */ 1580 #define VC5_COB_SIZE 44416 1581 #define VC5_COB_LINE_WIDTH 4096 1582 #define VC5_COB_NUM_LINES 3 1583 reg = 0; 1584 top = VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES; 1585 reg |= top << 16; 1586 HVS_WRITE(SCALER_DISPBASE2, reg); 1587 top += 16; 1588 reg = top; 1589 top += VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES; 1590 reg |= top << 16; 1591 HVS_WRITE(SCALER_DISPBASE1, reg); 1592 top += 16; 1593 reg = top; 1594 top = VC5_COB_SIZE; 1595 reg |= top << 16; 1596 HVS_WRITE(SCALER_DISPBASE0, reg); 1597 break; 1598 1599 case VC4_GEN_6_C: 1600 case VC4_GEN_6_D: 1601 #define VC6_COB_LINE_WIDTH 3840 1602 #define VC6_COB_NUM_LINES 4 1603 base = 0; 1604 top = 3840; 1605 1606 HVS_WRITE(SCALER6_DISPX_COB(2), 1607 VC4_SET_FIELD(top, SCALER6_DISPX_COB_TOP) | 1608 VC4_SET_FIELD(base, SCALER6_DISPX_COB_BASE)); 1609 1610 base = top + 16; 1611 top += VC6_COB_LINE_WIDTH * VC6_COB_NUM_LINES; 1612 1613 HVS_WRITE(SCALER6_DISPX_COB(1), 1614 VC4_SET_FIELD(top, SCALER6_DISPX_COB_TOP) | 1615 VC4_SET_FIELD(base, SCALER6_DISPX_COB_BASE)); 1616 1617 base = top + 16; 1618 top += VC6_COB_LINE_WIDTH * VC6_COB_NUM_LINES; 1619 1620 HVS_WRITE(SCALER6_DISPX_COB(0), 1621 VC4_SET_FIELD(top, SCALER6_DISPX_COB_TOP) | 1622 VC4_SET_FIELD(base, SCALER6_DISPX_COB_BASE)); 1623 break; 1624 1625 default: 1626 return -EINVAL; 1627 } 1628 1629 return 0; 1630 } 1631 1632 static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) 1633 { 1634 struct platform_device *pdev = to_platform_device(dev); 1635 struct drm_device *drm = dev_get_drvdata(master); 1636 struct vc4_dev *vc4 = to_vc4_dev(drm); 1637 struct vc4_hvs *hvs = NULL; 1638 void __iomem *regs; 1639 int ret; 1640 1641 regs = vc4_ioremap_regs(pdev, 0); 1642 if (IS_ERR(regs)) 1643 return PTR_ERR(regs); 1644 1645 hvs = __vc4_hvs_alloc(vc4, regs, pdev); 1646 if (IS_ERR(hvs)) 1647 return PTR_ERR(hvs); 1648 1649 hvs->regset.base = hvs->regs; 1650 1651 if (vc4->gen == VC4_GEN_6_C) { 1652 hvs->regset.regs = vc6_hvs_regs; 1653 hvs->regset.nregs = ARRAY_SIZE(vc6_hvs_regs); 1654 1655 if (VC4_GET_FIELD(HVS_READ(SCALER6_VERSION), SCALER6_VERSION) == 1656 SCALER6_VERSION_D0) { 1657 vc4->gen = VC4_GEN_6_D; 1658 hvs->regset.regs = vc6_d_hvs_regs; 1659 hvs->regset.nregs = ARRAY_SIZE(vc6_d_hvs_regs); 1660 } 1661 } else { 1662 hvs->regset.regs = vc4_hvs_regs; 1663 hvs->regset.nregs = ARRAY_SIZE(vc4_hvs_regs); 1664 } 1665 1666 if (vc4->gen >= VC4_GEN_6_C) { 1667 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); 1668 if (ret) 1669 return ret; 1670 } 1671 1672 if (drm_dev_dma_dev(drm) == drm->dev) 1673 drm_dev_set_dma_dev(drm, dev); 1674 1675 if (vc4->gen >= VC4_GEN_5) { 1676 struct rpi_firmware *firmware; 1677 struct device_node *node; 1678 unsigned int max_rate; 1679 1680 node = rpi_firmware_find_node(); 1681 if (!node) 1682 return -EINVAL; 1683 1684 firmware = rpi_firmware_get(node); 1685 of_node_put(node); 1686 if (!firmware) 1687 return -EPROBE_DEFER; 1688 1689 hvs->core_clk = devm_clk_get(&pdev->dev, 1690 (vc4->gen >= VC4_GEN_6_C) ? "core" : NULL); 1691 if (IS_ERR(hvs->core_clk)) { 1692 dev_err(&pdev->dev, "Couldn't get core clock\n"); 1693 return PTR_ERR(hvs->core_clk); 1694 } 1695 1696 hvs->disp_clk = devm_clk_get(&pdev->dev, 1697 (vc4->gen >= VC4_GEN_6_C) ? "disp" : NULL); 1698 if (IS_ERR(hvs->disp_clk)) { 1699 dev_err(&pdev->dev, "Couldn't get disp clock\n"); 1700 return PTR_ERR(hvs->disp_clk); 1701 } 1702 1703 max_rate = rpi_firmware_clk_get_max_rate(firmware, 1704 RPI_FIRMWARE_CORE_CLK_ID); 1705 rpi_firmware_put(firmware); 1706 if (max_rate >= 550000000) 1707 hvs->vc5_hdmi_enable_hdmi_20 = true; 1708 1709 if (max_rate >= 600000000) 1710 hvs->vc5_hdmi_enable_4096by2160 = true; 1711 1712 hvs->max_core_rate = max_rate; 1713 1714 ret = clk_prepare_enable(hvs->core_clk); 1715 if (ret) { 1716 dev_err(&pdev->dev, "Couldn't enable the core clock\n"); 1717 return ret; 1718 } 1719 1720 ret = clk_prepare_enable(hvs->disp_clk); 1721 if (ret) { 1722 dev_err(&pdev->dev, "Couldn't enable the disp clock\n"); 1723 return ret; 1724 } 1725 } 1726 1727 if (vc4->gen >= VC4_GEN_5) 1728 hvs->dlist = hvs->regs + SCALER5_DLIST_START; 1729 else 1730 hvs->dlist = hvs->regs + SCALER_DLIST_START; 1731 1732 if (vc4->gen >= VC4_GEN_6_C) 1733 ret = vc6_hvs_hw_init(hvs); 1734 else 1735 ret = vc4_hvs_hw_init(hvs); 1736 if (ret) 1737 return ret; 1738 1739 /* Upload filter kernels. We only have the one for now, so we 1740 * keep it around for the lifetime of the driver. 1741 */ 1742 ret = vc4_hvs_upload_linear_kernel(hvs, 1743 &hvs->mitchell_netravali_filter, 1744 mitchell_netravali_1_3_1_3_kernel); 1745 if (ret) 1746 return ret; 1747 1748 ret = vc4_hvs_cob_init(hvs); 1749 if (ret) 1750 return ret; 1751 1752 if (vc4->gen < VC4_GEN_6_C) { 1753 ret = devm_request_irq(dev, platform_get_irq(pdev, 0), 1754 vc4_hvs_irq_handler, 0, "vc4 hvs", drm); 1755 if (ret) 1756 return ret; 1757 } 1758 1759 return 0; 1760 } 1761 1762 static void vc4_hvs_unbind(struct device *dev, struct device *master, 1763 void *data) 1764 { 1765 struct drm_device *drm = data; 1766 struct vc4_dev *vc4 = to_vc4_dev(drm); 1767 struct vc4_hvs *hvs = vc4->hvs; 1768 struct drm_mm_node *node, *next; 1769 1770 if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter)) 1771 drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter); 1772 1773 drm_mm_for_each_node_safe(node, next, &vc4->hvs->dlist_mm) 1774 drm_mm_remove_node(node); 1775 1776 drm_mm_takedown(&vc4->hvs->dlist_mm); 1777 1778 drm_mm_for_each_node_safe(node, next, &vc4->hvs->lbm_mm) 1779 drm_mm_remove_node(node); 1780 drm_mm_takedown(&vc4->hvs->lbm_mm); 1781 1782 clk_disable_unprepare(hvs->disp_clk); 1783 clk_disable_unprepare(hvs->core_clk); 1784 1785 vc4->hvs = NULL; 1786 } 1787 1788 static const struct component_ops vc4_hvs_ops = { 1789 .bind = vc4_hvs_bind, 1790 .unbind = vc4_hvs_unbind, 1791 }; 1792 1793 static int vc4_hvs_dev_probe(struct platform_device *pdev) 1794 { 1795 return component_add(&pdev->dev, &vc4_hvs_ops); 1796 } 1797 1798 static void vc4_hvs_dev_remove(struct platform_device *pdev) 1799 { 1800 component_del(&pdev->dev, &vc4_hvs_ops); 1801 } 1802 1803 static const struct of_device_id vc4_hvs_dt_match[] = { 1804 { .compatible = "brcm,bcm2711-hvs" }, 1805 { .compatible = "brcm,bcm2712-hvs" }, 1806 { .compatible = "brcm,bcm2835-hvs" }, 1807 {} 1808 }; 1809 1810 struct platform_driver vc4_hvs_driver = { 1811 .probe = vc4_hvs_dev_probe, 1812 .remove = vc4_hvs_dev_remove, 1813 .driver = { 1814 .name = "vc4_hvs", 1815 .of_match_table = vc4_hvs_dt_match, 1816 }, 1817 }; 1818