1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_audio_helper.h> 35 #include <drm/display/drm_hdmi_cec_helper.h> 36 #include <drm/display/drm_hdmi_helper.h> 37 #include <drm/display/drm_hdmi_state_helper.h> 38 #include <drm/display/drm_scdc_helper.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_drv.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_probe_helper.h> 44 #include <drm/drm_simple_kms_helper.h> 45 #include <linux/clk.h> 46 #include <linux/component.h> 47 #include <linux/gpio/consumer.h> 48 #include <linux/i2c.h> 49 #include <linux/of.h> 50 #include <linux/of_address.h> 51 #include <linux/pm_runtime.h> 52 #include <linux/rational.h> 53 #include <linux/reset.h> 54 #include <sound/dmaengine_pcm.h> 55 #include <sound/hdmi-codec.h> 56 #include <sound/jack.h> 57 #include <sound/pcm_drm_eld.h> 58 #include <sound/pcm_params.h> 59 #include <sound/soc.h> 60 #include "media/cec.h" 61 #include "vc4_drv.h" 62 #include "vc4_hdmi.h" 63 #include "vc4_hdmi_regs.h" 64 #include "vc4_regs.h" 65 66 #define VC5_HDMI_HORZA_HFP_SHIFT 16 67 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 68 #define VC5_HDMI_HORZA_VPOS BIT(15) 69 #define VC5_HDMI_HORZA_HPOS BIT(14) 70 #define VC5_HDMI_HORZA_HAP_SHIFT 0 71 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 72 73 #define VC5_HDMI_HORZB_HBP_SHIFT 16 74 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 75 #define VC5_HDMI_HORZB_HSP_SHIFT 0 76 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 77 78 #define VC5_HDMI_VERTA_VSP_SHIFT 24 79 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 80 #define VC5_HDMI_VERTA_VFP_SHIFT 16 81 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 82 #define VC5_HDMI_VERTA_VAL_SHIFT 0 83 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 84 85 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 86 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 87 88 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 89 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 90 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 91 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 92 93 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 94 95 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 96 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 97 98 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 99 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 100 101 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 102 103 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 104 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 105 106 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0) 107 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0) 108 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4) 109 110 # define VC4_HD_M_SW_RST BIT(2) 111 # define VC4_HD_M_ENABLE BIT(0) 112 113 #define HSM_MIN_CLOCK_FREQ 120000000 114 #define CEC_CLOCK_FREQ 40000 115 116 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 117 118 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi) 119 { 120 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 121 122 lockdep_assert_held(&vc4_hdmi->mutex); 123 124 if (!display->is_hdmi) 125 return false; 126 127 if (!display->hdmi.scdc.supported || 128 !display->hdmi.scdc.scrambling.supported) 129 return false; 130 131 return true; 132 } 133 134 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 135 unsigned int bpc, 136 enum drm_output_color_format fmt) 137 { 138 unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt); 139 140 return clock > HDMI_14_MAX_TMDS_CLK; 141 } 142 143 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 144 { 145 struct drm_debugfs_entry *entry = m->private; 146 struct vc4_hdmi *vc4_hdmi = entry->file.data; 147 struct drm_device *drm = vc4_hdmi->connector.dev; 148 struct drm_printer p = drm_seq_file_printer(m); 149 int idx; 150 151 if (!drm_dev_enter(drm, &idx)) 152 return -ENODEV; 153 154 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 155 156 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 157 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 158 drm_print_regset32(&p, &vc4_hdmi->cec_regset); 159 drm_print_regset32(&p, &vc4_hdmi->csc_regset); 160 drm_print_regset32(&p, &vc4_hdmi->dvp_regset); 161 drm_print_regset32(&p, &vc4_hdmi->phy_regset); 162 drm_print_regset32(&p, &vc4_hdmi->ram_regset); 163 drm_print_regset32(&p, &vc4_hdmi->rm_regset); 164 165 pm_runtime_put(&vc4_hdmi->pdev->dev); 166 167 drm_dev_exit(idx); 168 169 return 0; 170 } 171 172 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 173 { 174 struct drm_device *drm = vc4_hdmi->connector.dev; 175 unsigned long flags; 176 int idx; 177 178 /* 179 * We can be called by our bind callback, when the 180 * connector->dev pointer might not be initialised yet. 181 */ 182 if (drm && !drm_dev_enter(drm, &idx)) 183 return; 184 185 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 186 187 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 188 udelay(1); 189 HDMI_WRITE(HDMI_M_CTL, 0); 190 191 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 192 193 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 194 VC4_HDMI_SW_RESET_HDMI | 195 VC4_HDMI_SW_RESET_FORMAT_DETECT); 196 197 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 198 199 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 200 201 if (drm) 202 drm_dev_exit(idx); 203 } 204 205 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 206 { 207 struct drm_device *drm = vc4_hdmi->connector.dev; 208 unsigned long flags; 209 int idx; 210 211 /* 212 * We can be called by our bind callback, when the 213 * connector->dev pointer might not be initialised yet. 214 */ 215 if (drm && !drm_dev_enter(drm, &idx)) 216 return; 217 218 reset_control_reset(vc4_hdmi->reset); 219 220 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 221 222 HDMI_WRITE(HDMI_DVP_CTL, 0); 223 224 HDMI_WRITE(HDMI_CLOCK_STOP, 225 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 226 227 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 228 229 if (drm) 230 drm_dev_exit(idx); 231 } 232 233 #ifdef CONFIG_DRM_VC4_HDMI_CEC 234 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 235 { 236 struct drm_device *drm = vc4_hdmi->connector.dev; 237 unsigned long cec_rate; 238 unsigned long flags; 239 u16 clk_cnt; 240 u32 value; 241 int idx; 242 243 /* 244 * This function is called by our runtime_resume implementation 245 * and thus at bind time, when we haven't registered our 246 * connector yet and thus don't have a pointer to the DRM 247 * device. 248 */ 249 if (drm && !drm_dev_enter(drm, &idx)) 250 return; 251 252 cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 253 254 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 255 256 value = HDMI_READ(HDMI_CEC_CNTRL_1); 257 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 258 259 /* 260 * Set the clock divider: the hsm_clock rate and this divider 261 * setting will give a 40 kHz CEC clock. 262 */ 263 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 264 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 265 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 266 267 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 268 269 if (drm) 270 drm_dev_exit(idx); 271 } 272 #else 273 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 274 #endif 275 276 static int vc4_hdmi_reset_link(struct drm_connector *connector, 277 struct drm_modeset_acquire_ctx *ctx) 278 { 279 struct drm_device *drm; 280 struct vc4_hdmi *vc4_hdmi; 281 struct drm_connector_state *conn_state; 282 struct drm_crtc_state *crtc_state; 283 struct drm_crtc *crtc; 284 bool scrambling_needed; 285 u8 config; 286 int ret; 287 288 if (!connector) 289 return 0; 290 291 drm = connector->dev; 292 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx); 293 if (ret) 294 return ret; 295 296 conn_state = connector->state; 297 crtc = conn_state->crtc; 298 if (!crtc) 299 return 0; 300 301 ret = drm_modeset_lock(&crtc->mutex, ctx); 302 if (ret) 303 return ret; 304 305 crtc_state = crtc->state; 306 if (!crtc_state->active) 307 return 0; 308 309 vc4_hdmi = connector_to_vc4_hdmi(connector); 310 mutex_lock(&vc4_hdmi->mutex); 311 312 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) { 313 mutex_unlock(&vc4_hdmi->mutex); 314 return 0; 315 } 316 317 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode, 318 vc4_hdmi->output_bpc, 319 vc4_hdmi->output_format); 320 if (!scrambling_needed) { 321 mutex_unlock(&vc4_hdmi->mutex); 322 return 0; 323 } 324 325 if (conn_state->commit && 326 !try_wait_for_completion(&conn_state->commit->hw_done)) { 327 mutex_unlock(&vc4_hdmi->mutex); 328 return 0; 329 } 330 331 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config); 332 if (ret < 0) { 333 drm_err(drm, "Failed to read TMDS config: %d\n", ret); 334 mutex_unlock(&vc4_hdmi->mutex); 335 return 0; 336 } 337 338 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) { 339 mutex_unlock(&vc4_hdmi->mutex); 340 return 0; 341 } 342 343 mutex_unlock(&vc4_hdmi->mutex); 344 345 /* 346 * HDMI 2.0 says that one should not send scrambled data 347 * prior to configuring the sink scrambling, and that 348 * TMDS clock/data transmission should be suspended when 349 * changing the TMDS clock rate in the sink. So let's 350 * just do a full modeset here, even though some sinks 351 * would be perfectly happy if were to just reconfigure 352 * the SCDC settings on the fly. 353 */ 354 return drm_atomic_helper_reset_crtc(crtc, ctx); 355 } 356 357 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, 358 struct drm_modeset_acquire_ctx *ctx, 359 enum drm_connector_status status) 360 { 361 struct drm_connector *connector = &vc4_hdmi->connector; 362 int ret; 363 364 /* 365 * NOTE: This function should really be called with vc4_hdmi->mutex 366 * held, but doing so results in reentrancy issues since 367 * cec_s_phys_addr() might call .adap_enable, which leads to that 368 * funtion being called with our mutex held. 369 * 370 * A similar situation occurs with vc4_hdmi_reset_link() that 371 * will call into our KMS hooks if the scrambling was enabled. 372 * 373 * Concurrency isn't an issue at the moment since we don't share 374 * any state with any of the other frameworks so we can ignore 375 * the lock for now. 376 */ 377 378 drm_atomic_helper_connector_hdmi_hotplug(connector, ctx, status); 379 380 if (status != connector_status_connected) 381 return; 382 383 for (;;) { 384 ret = vc4_hdmi_reset_link(connector, ctx); 385 if (ret == -EDEADLK) { 386 drm_modeset_backoff(ctx); 387 continue; 388 } 389 390 break; 391 } 392 } 393 394 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector, 395 struct drm_modeset_acquire_ctx *ctx, 396 bool force) 397 { 398 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 399 enum drm_connector_status status = connector_status_disconnected; 400 int ret; 401 402 /* 403 * NOTE: This function should really take vc4_hdmi->mutex, but 404 * doing so results in reentrancy issues since 405 * vc4_hdmi_handle_hotplug() can call into other functions that 406 * would take the mutex while it's held here. 407 * 408 * Concurrency isn't an issue at the moment since we don't share 409 * any state with any of the other frameworks so we can ignore 410 * the lock for now. 411 */ 412 413 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 414 if (ret) { 415 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n", 416 ret); 417 return connector_status_unknown; 418 } 419 420 if (vc4_hdmi->hpd_gpio) { 421 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 422 status = connector_status_connected; 423 } else { 424 if (vc4_hdmi->variant->hp_detect && 425 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 426 status = connector_status_connected; 427 } 428 429 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status); 430 pm_runtime_put(&vc4_hdmi->pdev->dev); 431 432 return status; 433 } 434 435 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 436 { 437 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 438 int ret = 0; 439 440 ret = drm_edid_connector_add_modes(connector); 441 442 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { 443 struct drm_device *drm = connector->dev; 444 const struct drm_display_mode *mode; 445 446 list_for_each_entry(mode, &connector->probed_modes, head) { 447 if (vc4_hdmi_mode_needs_scrambling(mode, 8, DRM_OUTPUT_COLOR_FORMAT_RGB444)) { 448 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 449 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 450 } 451 } 452 } 453 454 return ret; 455 } 456 457 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 458 struct drm_atomic_commit *state) 459 { 460 struct drm_connector_state *old_state = 461 drm_atomic_get_old_connector_state(state, connector); 462 struct drm_connector_state *new_state = 463 drm_atomic_get_new_connector_state(state, connector); 464 struct drm_crtc *crtc = new_state->crtc; 465 466 if (!crtc) 467 return 0; 468 469 if (old_state->tv.margins.left != new_state->tv.margins.left || 470 old_state->tv.margins.right != new_state->tv.margins.right || 471 old_state->tv.margins.top != new_state->tv.margins.top || 472 old_state->tv.margins.bottom != new_state->tv.margins.bottom) { 473 struct drm_crtc_state *crtc_state; 474 int ret; 475 476 crtc_state = drm_atomic_get_crtc_state(state, crtc); 477 if (IS_ERR(crtc_state)) 478 return PTR_ERR(crtc_state); 479 480 /* 481 * Strictly speaking, we should be calling 482 * drm_atomic_helper_check_planes() after our call to 483 * drm_atomic_add_affected_planes(). However, the 484 * connector atomic_check is called as part of 485 * drm_atomic_helper_check_modeset() that already 486 * happens before a call to 487 * drm_atomic_helper_check_planes() in 488 * drm_atomic_helper_check(). 489 */ 490 ret = drm_atomic_add_affected_planes(state, crtc); 491 if (ret) 492 return ret; 493 } 494 495 if (old_state->colorspace != new_state->colorspace) { 496 struct drm_crtc_state *crtc_state; 497 498 crtc_state = drm_atomic_get_crtc_state(state, crtc); 499 if (IS_ERR(crtc_state)) 500 return PTR_ERR(crtc_state); 501 502 crtc_state->mode_changed = true; 503 } 504 505 return drm_atomic_helper_connector_hdmi_check(connector, state); 506 } 507 508 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 509 { 510 drm_atomic_helper_connector_reset(connector); 511 __drm_atomic_helper_connector_hdmi_state_init(connector, connector->state); 512 drm_atomic_helper_connector_tv_margins_reset(connector); 513 } 514 515 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 516 .debugfs_init = drm_hdmi_connector_debugfs_init, 517 .force = drm_atomic_helper_connector_hdmi_force, 518 .fill_modes = drm_helper_probe_single_connector_modes, 519 .reset = vc4_hdmi_connector_reset, 520 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 521 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 522 }; 523 524 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 525 .detect_ctx = vc4_hdmi_connector_detect_ctx, 526 .get_modes = vc4_hdmi_connector_get_modes, 527 .atomic_check = vc4_hdmi_connector_atomic_check, 528 .mode_valid = drm_hdmi_connector_mode_valid, 529 }; 530 531 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs; 532 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs; 533 534 static int vc4_hdmi_connector_init(struct drm_device *dev, 535 struct vc4_hdmi *vc4_hdmi) 536 { 537 struct drm_connector *connector = &vc4_hdmi->connector; 538 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 539 unsigned int max_bpc = 8; 540 int ret; 541 542 if (vc4_hdmi->variant->supports_hdr) 543 max_bpc = 12; 544 545 ret = drmm_connector_hdmi_ini2(dev, connector, 546 "Broadcom", "Videocore", 547 &vc4_hdmi_connector_funcs, 548 &vc4_hdmi_hdmi_connector_funcs, 549 DRM_MODE_CONNECTOR_HDMIA, 550 vc4_hdmi->ddc, 551 BIT(DRM_OUTPUT_COLOR_FORMAT_RGB444) | 552 BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422) | 553 BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444), 554 max_bpc); 555 if (ret) 556 return ret; 557 558 ret = drm_connector_hdmi_audio_init(connector, dev->dev, 559 &vc4_hdmi_audio_funcs, 560 8, 0, false, -1); 561 if (ret) 562 return ret; 563 564 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 565 566 /* 567 * Some of the properties below require access to state, like bpc. 568 * Allocate some default initial connector state with our reset helper. 569 */ 570 if (connector->funcs->reset) 571 connector->funcs->reset(connector); 572 573 /* Create and attach TV margin props to this connector. */ 574 ret = drm_mode_create_tv_margin_properties(dev); 575 if (ret) 576 return ret; 577 578 ret = drm_mode_create_hdmi_colorspace_property(connector, 0); 579 if (ret) 580 return ret; 581 582 drm_connector_attach_colorspace_property(connector); 583 drm_connector_attach_tv_margin_properties(connector); 584 585 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 586 DRM_CONNECTOR_POLL_DISCONNECT); 587 588 connector->interlace_allowed = 1; 589 connector->doublescan_allowed = 0; 590 connector->stereo_allowed = 1; 591 592 ret = drm_connector_attach_broadcast_rgb_property(connector); 593 if (ret) 594 return ret; 595 596 drm_connector_attach_encoder(connector, encoder); 597 598 return 0; 599 } 600 601 static int vc4_hdmi_stop_packet(struct vc4_hdmi *vc4_hdmi, 602 enum hdmi_infoframe_type type, 603 bool poll) 604 { 605 struct drm_device *drm = vc4_hdmi->connector.dev; 606 u32 packet_id = type - 0x80; 607 unsigned long flags; 608 int ret = 0; 609 int idx; 610 611 if (!drm_dev_enter(drm, &idx)) 612 return -ENODEV; 613 614 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 615 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 616 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 617 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 618 619 if (poll) { 620 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 621 BIT(packet_id)), 100); 622 } 623 624 drm_dev_exit(idx); 625 return ret; 626 } 627 628 static int vc4_hdmi_clear_infoframe(struct drm_connector *connector, 629 enum hdmi_infoframe_type type) 630 { 631 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 632 struct drm_device *drm = connector->dev; 633 int ret; 634 int idx; 635 636 if (!drm_dev_enter(drm, &idx)) 637 return 0; 638 639 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 640 VC4_HDMI_RAM_PACKET_ENABLE), 641 "Packet RAM has to be on to store the packet."); 642 643 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true); 644 if (ret) 645 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret); 646 647 drm_dev_exit(idx); 648 649 return ret; 650 } 651 652 static int vc4_hdmi_write_infoframe(struct drm_connector *connector, 653 enum hdmi_infoframe_type type, 654 const u8 *infoframe, size_t len) 655 { 656 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 657 struct drm_device *drm = connector->dev; 658 u32 packet_id = type - 0x80; 659 const struct vc4_hdmi_register *ram_packet_start = 660 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 661 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 662 u32 packet_reg_next = ram_packet_start->offset + 663 VC4_HDMI_PACKET_STRIDE * (packet_id + 1); 664 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 665 ram_packet_start->reg); 666 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {}; 667 unsigned long flags; 668 ssize_t i; 669 int ret; 670 int idx; 671 672 if (!drm_dev_enter(drm, &idx)) 673 return 0; 674 675 if (len > sizeof(buffer)) { 676 ret = -ENOMEM; 677 goto out; 678 } 679 680 memcpy(buffer, infoframe, len); 681 682 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 683 VC4_HDMI_RAM_PACKET_ENABLE), 684 "Packet RAM has to be on to store the packet."); 685 686 ret = vc4_hdmi_stop_packet(vc4_hdmi, type, true); 687 if (ret) { 688 drm_err(drm, "Failed to wait for infoframe to go idle: %d\n", ret); 689 goto out; 690 } 691 692 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 693 694 for (i = 0; i < len; i += 7) { 695 writel(buffer[i + 0] << 0 | 696 buffer[i + 1] << 8 | 697 buffer[i + 2] << 16, 698 base + packet_reg); 699 packet_reg += 4; 700 701 writel(buffer[i + 3] << 0 | 702 buffer[i + 4] << 8 | 703 buffer[i + 5] << 16 | 704 buffer[i + 6] << 24, 705 base + packet_reg); 706 packet_reg += 4; 707 } 708 709 /* 710 * clear remainder of packet ram as it's included in the 711 * infoframe and triggers a checksum error on hdmi analyser 712 */ 713 for (; packet_reg < packet_reg_next; packet_reg += 4) 714 writel(0, base + packet_reg); 715 716 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 717 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 718 719 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 720 721 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 722 BIT(packet_id)), 100); 723 if (ret) 724 drm_err(drm, "Failed to wait for infoframe to start: %d\n", ret); 725 726 out: 727 drm_dev_exit(idx); 728 return ret; 729 } 730 731 static int vc4_hdmi_clear_avi_infoframe(struct drm_connector *connector) 732 { 733 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_AVI); 734 } 735 736 static int vc4_hdmi_clear_hdmi_infoframe(struct drm_connector *connector) 737 { 738 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_VENDOR); 739 } 740 741 static int vc4_hdmi_clear_audio_infoframe(struct drm_connector *connector) 742 { 743 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_AUDIO); 744 } 745 746 static int vc4_hdmi_clear_hdr_drm_infoframe(struct drm_connector *connector) 747 { 748 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_DRM); 749 } 750 751 static int vc4_hdmi_clear_spd_infoframe(struct drm_connector *connector) 752 { 753 return vc4_hdmi_clear_infoframe(connector, HDMI_INFOFRAME_TYPE_SPD); 754 } 755 756 static int vc4_hdmi_write_avi_infoframe(struct drm_connector *connector, 757 const u8 *buffer, size_t len) 758 { 759 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_AVI, 760 buffer, len); 761 } 762 763 static int vc4_hdmi_write_hdmi_infoframe(struct drm_connector *connector, 764 const u8 *buffer, size_t len) 765 { 766 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_VENDOR, 767 buffer, len); 768 } 769 770 static int vc4_hdmi_write_audio_infoframe(struct drm_connector *connector, 771 const u8 *buffer, size_t len) 772 { 773 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_AUDIO, 774 buffer, len); 775 } 776 777 static int vc4_hdmi_write_hdr_drm_infoframe(struct drm_connector *connector, 778 const u8 *buffer, size_t len) 779 { 780 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_DRM, 781 buffer, len); 782 } 783 784 static int vc4_hdmi_write_spd_infoframe(struct drm_connector *connector, 785 const u8 *buffer, size_t len) 786 { 787 return vc4_hdmi_write_infoframe(connector, HDMI_INFOFRAME_TYPE_SPD, 788 buffer, len); 789 } 790 791 #define SCRAMBLING_POLLING_DELAY_MS 1000 792 793 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 794 { 795 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 796 struct drm_connector *connector = &vc4_hdmi->connector; 797 struct drm_device *drm = connector->dev; 798 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 799 unsigned long flags; 800 int idx; 801 802 lockdep_assert_held(&vc4_hdmi->mutex); 803 804 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) 805 return; 806 807 if (!vc4_hdmi_mode_needs_scrambling(mode, 808 vc4_hdmi->output_bpc, 809 vc4_hdmi->output_format)) 810 return; 811 812 if (!drm_dev_enter(drm, &idx)) 813 return; 814 815 drm_scdc_set_high_tmds_clock_ratio(connector, true); 816 drm_scdc_set_scrambling(connector, true); 817 818 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 819 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 820 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 821 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 822 823 drm_dev_exit(idx); 824 825 vc4_hdmi->scdc_enabled = true; 826 827 queue_delayed_work(system_percpu_wq, &vc4_hdmi->scrambling_work, 828 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 829 } 830 831 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 832 { 833 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 834 struct drm_connector *connector = &vc4_hdmi->connector; 835 struct drm_device *drm = connector->dev; 836 unsigned long flags; 837 int idx; 838 839 lockdep_assert_held(&vc4_hdmi->mutex); 840 841 if (!vc4_hdmi->scdc_enabled) 842 return; 843 844 vc4_hdmi->scdc_enabled = false; 845 846 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 847 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 848 849 if (!drm_dev_enter(drm, &idx)) 850 return; 851 852 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 853 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 854 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 855 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 856 857 drm_scdc_set_scrambling(connector, false); 858 drm_scdc_set_high_tmds_clock_ratio(connector, false); 859 860 drm_dev_exit(idx); 861 } 862 863 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 864 { 865 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 866 struct vc4_hdmi, 867 scrambling_work); 868 struct drm_connector *connector = &vc4_hdmi->connector; 869 870 if (drm_scdc_get_scrambling_status(connector)) 871 return; 872 873 drm_scdc_set_high_tmds_clock_ratio(connector, true); 874 drm_scdc_set_scrambling(connector, true); 875 876 queue_delayed_work(system_percpu_wq, &vc4_hdmi->scrambling_work, 877 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 878 } 879 880 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 881 struct drm_atomic_commit *state) 882 { 883 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 884 struct drm_device *drm = vc4_hdmi->connector.dev; 885 struct vc4_dev *vc4 = to_vc4_dev(drm); 886 unsigned long flags; 887 int idx; 888 889 mutex_lock(&vc4_hdmi->mutex); 890 891 vc4_hdmi->packet_ram_enabled = false; 892 893 if (!drm_dev_enter(drm, &idx)) 894 goto out; 895 896 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 897 898 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, VC4_HDMI_RAM_PACKET_ENABLE); 899 900 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 901 902 if (vc4->gen >= VC4_GEN_6_C) 903 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | 904 VC4_HD_VID_CTL_BLANKPIX); 905 906 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 907 908 mdelay(1); 909 910 /* 911 * TODO: This should work on BCM2712, but doesn't for some 912 * reason and result in a system lockup. 913 */ 914 if (vc4->gen < VC4_GEN_6_C) { 915 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 916 HDMI_WRITE(HDMI_VID_CTL, 917 HDMI_READ(HDMI_VID_CTL) & 918 ~VC4_HD_VID_CTL_ENABLE); 919 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 920 } 921 922 vc4_hdmi_disable_scrambling(encoder); 923 924 drm_dev_exit(idx); 925 926 out: 927 mutex_unlock(&vc4_hdmi->mutex); 928 } 929 930 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 931 struct drm_atomic_commit *state) 932 { 933 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 934 struct drm_device *drm = vc4_hdmi->connector.dev; 935 unsigned long flags; 936 int idx; 937 938 mutex_lock(&vc4_hdmi->mutex); 939 940 if (!drm_dev_enter(drm, &idx)) 941 goto out; 942 943 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 944 HDMI_WRITE(HDMI_VID_CTL, 945 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 946 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 947 948 if (vc4_hdmi->variant->phy_disable) 949 vc4_hdmi->variant->phy_disable(vc4_hdmi); 950 951 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 952 clk_disable_unprepare(vc4_hdmi->pixel_clock); 953 954 pm_runtime_put(&vc4_hdmi->pdev->dev); 955 956 drm_dev_exit(idx); 957 958 out: 959 mutex_unlock(&vc4_hdmi->mutex); 960 } 961 962 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 963 struct drm_connector_state *state, 964 const struct drm_display_mode *mode) 965 { 966 struct drm_device *drm = vc4_hdmi->connector.dev; 967 unsigned long flags; 968 u32 csc_ctl; 969 int idx; 970 971 if (!drm_dev_enter(drm, &idx)) 972 return; 973 974 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 975 976 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 977 VC4_HD_CSC_CTL_ORDER); 978 979 if (state->hdmi.is_limited_range) { 980 /* CEA VICs other than #1 requre limited range RGB 981 * output unless overridden by an AVI infoframe. 982 * Apply a colorspace conversion to squash 0-255 down 983 * to 16-235. The matrix here is: 984 * 985 * [ 0 0 0.8594 16] 986 * [ 0 0.8594 0 16] 987 * [ 0.8594 0 0 16] 988 * [ 0 0 0 1] 989 */ 990 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 991 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 992 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 993 VC4_HD_CSC_CTL_MODE); 994 995 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 996 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 997 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 998 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 999 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 1000 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 1001 } 1002 1003 /* The RGB order applies even when CSC is disabled. */ 1004 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1005 1006 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1007 1008 drm_dev_exit(idx); 1009 } 1010 1011 /* 1012 * Matrices for (internal) RGB to RGB output. 1013 * 1014 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1015 */ 1016 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = { 1017 { 1018 /* 1019 * Full range - unity 1020 * 1021 * [ 1 0 0 0] 1022 * [ 0 1 0 0] 1023 * [ 0 0 1 0] 1024 */ 1025 { 0x2000, 0x0000, 0x0000, 0x0000 }, 1026 { 0x0000, 0x2000, 0x0000, 0x0000 }, 1027 { 0x0000, 0x0000, 0x2000, 0x0000 }, 1028 }, 1029 { 1030 /* 1031 * Limited range 1032 * 1033 * CEA VICs other than #1 require limited range RGB 1034 * output unless overridden by an AVI infoframe. Apply a 1035 * colorspace conversion to squash 0-255 down to 16-235. 1036 * The matrix here is: 1037 * 1038 * [ 0.8594 0 0 16] 1039 * [ 0 0.8594 0 16] 1040 * [ 0 0 0.8594 16] 1041 */ 1042 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 1043 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 1044 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 1045 }, 1046 }; 1047 1048 /* 1049 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace 1050 * 1051 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1052 */ 1053 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = { 1054 { 1055 /* 1056 * Full Range 1057 * 1058 * [ 0.299000 0.587000 0.114000 0 ] 1059 * [ -0.168736 -0.331264 0.500000 128 ] 1060 * [ 0.500000 -0.418688 -0.081312 128 ] 1061 */ 1062 { 0x0991, 0x12c9, 0x03a6, 0x0000 }, 1063 { 0xfa9b, 0xf567, 0x1000, 0x2000 }, 1064 { 0x1000, 0xf29b, 0xfd67, 0x2000 }, 1065 }, 1066 { 1067 /* Limited Range 1068 * 1069 * [ 0.255785 0.502160 0.097523 16 ] 1070 * [ -0.147644 -0.289856 0.437500 128 ] 1071 * [ 0.437500 -0.366352 -0.071148 128 ] 1072 */ 1073 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1074 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1075 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1076 }, 1077 }; 1078 1079 /* 1080 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace 1081 * 1082 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1083 */ 1084 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = { 1085 { 1086 /* 1087 * Full Range 1088 * 1089 * [ 0.212600 0.715200 0.072200 0 ] 1090 * [ -0.114572 -0.385428 0.500000 128 ] 1091 * [ 0.500000 -0.454153 -0.045847 128 ] 1092 */ 1093 { 0x06ce, 0x16e3, 0x024f, 0x0000 }, 1094 { 0xfc56, 0xf3ac, 0x1000, 0x2000 }, 1095 { 0x1000, 0xf179, 0xfe89, 0x2000 }, 1096 }, 1097 { 1098 /* 1099 * Limited Range 1100 * 1101 * [ 0.181906 0.611804 0.061758 16 ] 1102 * [ -0.100268 -0.337232 0.437500 128 ] 1103 * [ 0.437500 -0.397386 -0.040114 128 ] 1104 */ 1105 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1106 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1107 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1108 }, 1109 }; 1110 1111 /* 1112 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace 1113 * 1114 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1115 */ 1116 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = { 1117 { 1118 /* 1119 * Full Range 1120 * 1121 * [ 0.262700 0.678000 0.059300 0 ] 1122 * [ -0.139630 -0.360370 0.500000 128 ] 1123 * [ 0.500000 -0.459786 -0.040214 128 ] 1124 */ 1125 { 0x0868, 0x15b2, 0x01e6, 0x0000 }, 1126 { 0xfb89, 0xf479, 0x1000, 0x2000 }, 1127 { 0x1000, 0xf14a, 0xfeb8, 0x2000 }, 1128 }, 1129 { 1130 /* Limited Range 1131 * 1132 * [ 0.224732 0.580008 0.050729 16 ] 1133 * [ -0.122176 -0.315324 0.437500 128 ] 1134 * [ 0.437500 -0.402312 -0.035188 128 ] 1135 */ 1136 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1137 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1138 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1139 }, 1140 }; 1141 1142 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 1143 const u16 coeffs[3][4]) 1144 { 1145 lockdep_assert_held(&vc4_hdmi->hw_lock); 1146 1147 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 1148 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 1149 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 1150 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 1151 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 1152 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 1153 } 1154 1155 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi, 1156 const u16 coeffs[3][4]) 1157 { 1158 lockdep_assert_held(&vc4_hdmi->hw_lock); 1159 1160 /* YUV444 needs the CSC matrices using the channels in a different order */ 1161 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]); 1162 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]); 1163 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]); 1164 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]); 1165 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]); 1166 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]); 1167 } 1168 1169 static const u16 1170 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4] 1171 { 1172 switch (colorspace) { 1173 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC: 1174 case DRM_MODE_COLORIMETRY_XVYCC_601: 1175 case DRM_MODE_COLORIMETRY_SYCC_601: 1176 case DRM_MODE_COLORIMETRY_OPYCC_601: 1177 case DRM_MODE_COLORIMETRY_BT601_YCC: 1178 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited]; 1179 1180 default: 1181 case DRM_MODE_COLORIMETRY_NO_DATA: 1182 case DRM_MODE_COLORIMETRY_BT709_YCC: 1183 case DRM_MODE_COLORIMETRY_XVYCC_709: 1184 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED: 1185 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT: 1186 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited]; 1187 1188 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 1189 case DRM_MODE_COLORIMETRY_BT2020_YCC: 1190 case DRM_MODE_COLORIMETRY_BT2020_RGB: 1191 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 1192 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 1193 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited]; 1194 } 1195 } 1196 1197 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1198 struct drm_connector_state *state, 1199 const struct drm_display_mode *mode) 1200 { 1201 struct drm_device *drm = vc4_hdmi->connector.dev; 1202 unsigned int lim_range = state->hdmi.is_limited_range ? 1 : 0; 1203 unsigned long flags; 1204 const u16 (*csc)[4]; 1205 u32 if_cfg = 0; 1206 u32 if_xbar = 0x543210; 1207 u32 csc_chan_ctl = 0; 1208 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1209 VC5_MT_CP_CSC_CTL_MODE); 1210 int idx; 1211 1212 if (!drm_dev_enter(drm, &idx)) 1213 return; 1214 1215 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1216 1217 switch (state->hdmi.output_format) { 1218 case DRM_OUTPUT_COLOR_FORMAT_YCBCR444: 1219 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1220 1221 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc); 1222 break; 1223 1224 case DRM_OUTPUT_COLOR_FORMAT_YCBCR422: 1225 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1226 1227 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 1228 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 1229 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 1230 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 1231 1232 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 1233 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 1234 1235 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 1236 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 1237 1238 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc); 1239 break; 1240 1241 case DRM_OUTPUT_COLOR_FORMAT_RGB444: 1242 if_xbar = 0x354021; 1243 1244 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]); 1245 break; 1246 1247 default: 1248 break; 1249 } 1250 1251 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 1252 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 1253 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 1254 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1255 1256 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1257 1258 drm_dev_exit(idx); 1259 } 1260 1261 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1262 struct drm_connector_state *state, 1263 const struct drm_display_mode *mode) 1264 { 1265 struct drm_device *drm = vc4_hdmi->connector.dev; 1266 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1267 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1268 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1269 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1270 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1271 VC4_HDMI_VERTA_VSP) | 1272 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1273 VC4_HDMI_VERTA_VFP) | 1274 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 1275 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1276 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1277 interlaced, 1278 VC4_HDMI_VERTB_VBP)); 1279 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1280 VC4_SET_FIELD(mode->crtc_vtotal - 1281 mode->crtc_vsync_end, 1282 VC4_HDMI_VERTB_VBP)); 1283 unsigned long flags; 1284 u32 reg; 1285 int idx; 1286 1287 if (!drm_dev_enter(drm, &idx)) 1288 return; 1289 1290 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1291 1292 HDMI_WRITE(HDMI_HORZA, 1293 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 1294 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 1295 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1296 VC4_HDMI_HORZA_HAP)); 1297 1298 HDMI_WRITE(HDMI_HORZB, 1299 VC4_SET_FIELD((mode->htotal - 1300 mode->hsync_end) * pixel_rep, 1301 VC4_HDMI_HORZB_HBP) | 1302 VC4_SET_FIELD((mode->hsync_end - 1303 mode->hsync_start) * pixel_rep, 1304 VC4_HDMI_HORZB_HSP) | 1305 VC4_SET_FIELD((mode->hsync_start - 1306 mode->hdisplay) * pixel_rep, 1307 VC4_HDMI_HORZB_HFP)); 1308 1309 HDMI_WRITE(HDMI_VERTA0, verta); 1310 HDMI_WRITE(HDMI_VERTA1, verta); 1311 1312 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1313 HDMI_WRITE(HDMI_VERTB1, vertb); 1314 1315 reg = HDMI_READ(HDMI_MISC_CONTROL); 1316 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1317 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); 1318 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1319 1320 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1321 1322 drm_dev_exit(idx); 1323 } 1324 1325 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1326 struct drm_connector_state *state, 1327 const struct drm_display_mode *mode) 1328 { 1329 struct drm_device *drm = vc4_hdmi->connector.dev; 1330 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1331 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1332 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1333 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1334 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1335 VC5_HDMI_VERTA_VSP) | 1336 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1337 VC5_HDMI_VERTA_VFP) | 1338 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1339 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 1340 VC5_HDMI_VERTB_VSPO) | 1341 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1342 interlaced, 1343 VC4_HDMI_VERTB_VBP)); 1344 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1345 VC4_SET_FIELD(mode->crtc_vtotal - 1346 mode->crtc_vsync_end, 1347 VC4_HDMI_VERTB_VBP)); 1348 unsigned long flags; 1349 unsigned char gcp; 1350 u32 reg; 1351 int idx; 1352 1353 if (!drm_dev_enter(drm, &idx)) 1354 return; 1355 1356 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1357 1358 HDMI_WRITE(HDMI_HORZA, 1359 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1360 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1361 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1362 VC5_HDMI_HORZA_HAP) | 1363 VC4_SET_FIELD((mode->hsync_start - 1364 mode->hdisplay) * pixel_rep, 1365 VC5_HDMI_HORZA_HFP)); 1366 1367 HDMI_WRITE(HDMI_HORZB, 1368 VC4_SET_FIELD((mode->htotal - 1369 mode->hsync_end) * pixel_rep, 1370 VC5_HDMI_HORZB_HBP) | 1371 VC4_SET_FIELD((mode->hsync_end - 1372 mode->hsync_start) * pixel_rep, 1373 VC5_HDMI_HORZB_HSP)); 1374 1375 HDMI_WRITE(HDMI_VERTA0, verta); 1376 HDMI_WRITE(HDMI_VERTA1, verta); 1377 1378 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1379 HDMI_WRITE(HDMI_VERTB1, vertb); 1380 1381 switch (state->hdmi.output_bpc) { 1382 case 12: 1383 gcp = 6; 1384 break; 1385 case 10: 1386 gcp = 5; 1387 break; 1388 case 8: 1389 default: 1390 gcp = 0; 1391 break; 1392 } 1393 1394 /* 1395 * YCC422 is always 36-bit and not considered deep colour so 1396 * doesn't signal in GCP. 1397 */ 1398 if (state->hdmi.output_format == DRM_OUTPUT_COLOR_FORMAT_YCBCR422) { 1399 gcp = 0; 1400 } 1401 1402 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1403 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1404 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1405 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1406 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1407 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1408 1409 reg = HDMI_READ(HDMI_GCP_WORD_1); 1410 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1411 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1412 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK; 1413 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE; 1414 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1415 1416 reg = HDMI_READ(HDMI_GCP_CONFIG); 1417 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1418 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1419 1420 reg = HDMI_READ(HDMI_MISC_CONTROL); 1421 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1422 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); 1423 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1424 1425 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1426 1427 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1428 1429 drm_dev_exit(idx); 1430 } 1431 1432 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1433 { 1434 struct drm_device *drm = vc4_hdmi->connector.dev; 1435 unsigned long flags; 1436 u32 drift; 1437 int ret; 1438 int idx; 1439 1440 if (!drm_dev_enter(drm, &idx)) 1441 return; 1442 1443 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1444 1445 drift = HDMI_READ(HDMI_FIFO_CTL); 1446 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1447 1448 HDMI_WRITE(HDMI_FIFO_CTL, 1449 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1450 HDMI_WRITE(HDMI_FIFO_CTL, 1451 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1452 1453 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1454 1455 usleep_range(1000, 1100); 1456 1457 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1458 1459 HDMI_WRITE(HDMI_FIFO_CTL, 1460 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1461 HDMI_WRITE(HDMI_FIFO_CTL, 1462 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1463 1464 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1465 1466 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1467 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1468 WARN_ONCE(ret, "Timeout waiting for " 1469 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1470 1471 drm_dev_exit(idx); 1472 } 1473 1474 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1475 struct drm_atomic_commit *state) 1476 { 1477 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1478 struct drm_device *drm = vc4_hdmi->connector.dev; 1479 struct drm_connector *connector = &vc4_hdmi->connector; 1480 struct drm_connector_state *conn_state = 1481 drm_atomic_get_new_connector_state(state, connector); 1482 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1483 unsigned long long tmds_char_rate = conn_state->hdmi.tmds_char_rate; 1484 unsigned long bvb_rate, hsm_rate; 1485 unsigned long flags; 1486 int ret; 1487 int idx; 1488 1489 mutex_lock(&vc4_hdmi->mutex); 1490 1491 if (!drm_dev_enter(drm, &idx)) 1492 goto out; 1493 1494 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1495 if (ret < 0) { 1496 drm_err(drm, "Failed to retain power domain: %d\n", ret); 1497 goto err_dev_exit; 1498 } 1499 1500 /* 1501 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1502 * be faster than pixel clock, infinitesimally faster, tested in 1503 * simulation. Otherwise, exact value is unimportant for HDMI 1504 * operation." This conflicts with bcm2835's vc4 documentation, which 1505 * states HSM's clock has to be at least 108% of the pixel clock. 1506 * 1507 * Real life tests reveal that vc4's firmware statement holds up, and 1508 * users are able to use pixel clocks closer to HSM's, namely for 1509 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1510 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1511 * 162MHz. 1512 * 1513 * Additionally, the AXI clock needs to be at least 25% of 1514 * pixel clock, but HSM ends up being the limiting factor. 1515 */ 1516 hsm_rate = max_t(unsigned long, 1517 HSM_MIN_CLOCK_FREQ, 1518 div_u64(tmds_char_rate, 100) * 101); 1519 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1520 if (ret) { 1521 drm_err(drm, "Failed to set HSM clock rate: %d\n", ret); 1522 goto err_put_runtime_pm; 1523 } 1524 1525 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1526 if (ret) { 1527 drm_err(drm, "Failed to set pixel clock rate: %d\n", ret); 1528 goto err_put_runtime_pm; 1529 } 1530 1531 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1532 if (ret) { 1533 drm_err(drm, "Failed to turn on pixel clock: %d\n", ret); 1534 goto err_put_runtime_pm; 1535 } 1536 1537 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1538 1539 if (tmds_char_rate > 297000000) 1540 bvb_rate = 300000000; 1541 else if (tmds_char_rate > 148500000) 1542 bvb_rate = 150000000; 1543 else 1544 bvb_rate = 75000000; 1545 1546 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1547 if (ret) { 1548 drm_err(drm, "Failed to set pixel bvb clock rate: %d\n", ret); 1549 goto err_disable_pixel_clock; 1550 } 1551 1552 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1553 if (ret) { 1554 drm_err(drm, "Failed to turn on pixel bvb clock: %d\n", ret); 1555 goto err_disable_pixel_clock; 1556 } 1557 1558 if (vc4_hdmi->variant->phy_init) 1559 vc4_hdmi->variant->phy_init(vc4_hdmi, conn_state); 1560 1561 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1562 1563 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1564 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1565 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1566 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1567 1568 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1569 1570 if (vc4_hdmi->variant->set_timings) 1571 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1572 1573 drm_dev_exit(idx); 1574 1575 mutex_unlock(&vc4_hdmi->mutex); 1576 1577 return; 1578 1579 err_disable_pixel_clock: 1580 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1581 err_put_runtime_pm: 1582 pm_runtime_put(&vc4_hdmi->pdev->dev); 1583 err_dev_exit: 1584 drm_dev_exit(idx); 1585 out: 1586 mutex_unlock(&vc4_hdmi->mutex); 1587 return; 1588 } 1589 1590 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1591 struct drm_atomic_commit *state) 1592 { 1593 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1594 struct drm_device *drm = vc4_hdmi->connector.dev; 1595 struct drm_connector *connector = &vc4_hdmi->connector; 1596 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1597 struct drm_connector_state *conn_state = 1598 drm_atomic_get_new_connector_state(state, connector); 1599 unsigned long flags; 1600 int idx; 1601 1602 mutex_lock(&vc4_hdmi->mutex); 1603 1604 if (!drm_dev_enter(drm, &idx)) 1605 goto out; 1606 1607 if (vc4_hdmi->variant->csc_setup) 1608 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1609 1610 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1611 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1612 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1613 1614 drm_dev_exit(idx); 1615 1616 out: 1617 mutex_unlock(&vc4_hdmi->mutex); 1618 } 1619 1620 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1621 struct drm_atomic_commit *state) 1622 { 1623 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1624 struct drm_connector *connector = &vc4_hdmi->connector; 1625 struct drm_device *drm = connector->dev; 1626 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1627 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1628 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1629 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1630 unsigned long flags; 1631 int ret; 1632 int idx; 1633 1634 mutex_lock(&vc4_hdmi->mutex); 1635 1636 if (!drm_dev_enter(drm, &idx)) 1637 goto out; 1638 1639 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1640 1641 HDMI_WRITE(HDMI_VID_CTL, 1642 (HDMI_READ(HDMI_VID_CTL) & 1643 ~(VC4_HD_VID_CTL_VSYNC_LOW | VC4_HD_VID_CTL_HSYNC_LOW)) | 1644 VC4_HD_VID_CTL_ENABLE | 1645 VC4_HD_VID_CTL_CLRRGB | 1646 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1647 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1648 VC4_HD_VID_CTL_BLANK_INSERT_EN | 1649 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1650 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1651 1652 HDMI_WRITE(HDMI_VID_CTL, 1653 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1654 1655 if (display->is_hdmi) { 1656 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1657 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1658 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1659 1660 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1661 1662 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1663 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1664 WARN_ONCE(ret, "Timeout waiting for " 1665 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1666 } else { 1667 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1668 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1669 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1670 1671 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1672 1673 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1674 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1675 WARN_ONCE(ret, "Timeout waiting for " 1676 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1677 } 1678 1679 if (display->is_hdmi) { 1680 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1681 1682 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1683 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1684 1685 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1686 vc4_hdmi->packet_ram_enabled = true; 1687 1688 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 1689 } 1690 1691 vc4_hdmi_recenter_fifo(vc4_hdmi); 1692 vc4_hdmi_enable_scrambling(encoder); 1693 1694 drm_dev_exit(idx); 1695 1696 out: 1697 mutex_unlock(&vc4_hdmi->mutex); 1698 } 1699 1700 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1701 struct drm_crtc_state *crtc_state, 1702 struct drm_connector_state *conn_state) 1703 { 1704 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1705 1706 mutex_lock(&vc4_hdmi->mutex); 1707 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1708 &crtc_state->adjusted_mode); 1709 vc4_hdmi->output_bpc = conn_state->hdmi.output_bpc; 1710 vc4_hdmi->output_format = conn_state->hdmi.output_format; 1711 mutex_unlock(&vc4_hdmi->mutex); 1712 } 1713 1714 static enum drm_mode_status 1715 vc4_hdmi_connector_clock_valid(const struct drm_connector *connector, 1716 const struct drm_display_mode *mode, 1717 unsigned long long clock) 1718 { 1719 const struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1720 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 1721 1722 if (clock > vc4_hdmi->variant->max_pixel_clock) 1723 return MODE_CLOCK_HIGH; 1724 1725 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) 1726 return MODE_CLOCK_HIGH; 1727 1728 /* 4096x2160@60 is not reliable without overclocking core */ 1729 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && 1730 mode->hdisplay > 3840 && mode->vdisplay >= 2160 && 1731 drm_mode_vrefresh(mode) >= 50) 1732 return MODE_CLOCK_HIGH; 1733 1734 return MODE_OK; 1735 } 1736 1737 static const struct drm_connector_hdmi_funcs vc4_hdmi_hdmi_connector_funcs = { 1738 .tmds_char_rate_valid = vc4_hdmi_connector_clock_valid, 1739 .avi = { 1740 .clear_infoframe = vc4_hdmi_clear_avi_infoframe, 1741 .write_infoframe = vc4_hdmi_write_avi_infoframe, 1742 }, 1743 .hdmi = { 1744 .clear_infoframe = vc4_hdmi_clear_hdmi_infoframe, 1745 .write_infoframe = vc4_hdmi_write_hdmi_infoframe, 1746 }, 1747 .audio = { 1748 .clear_infoframe = vc4_hdmi_clear_audio_infoframe, 1749 .write_infoframe = vc4_hdmi_write_audio_infoframe, 1750 }, 1751 .hdr_drm = { 1752 .clear_infoframe = vc4_hdmi_clear_hdr_drm_infoframe, 1753 .write_infoframe = vc4_hdmi_write_hdr_drm_infoframe, 1754 }, 1755 .spd = { 1756 .clear_infoframe = vc4_hdmi_clear_spd_infoframe, 1757 .write_infoframe = vc4_hdmi_write_spd_infoframe, 1758 }, 1759 }; 1760 1761 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1762 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1763 1764 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1765 struct drm_crtc_state *crtc_state, 1766 struct drm_connector_state *conn_state) 1767 { 1768 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1769 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1770 unsigned long long tmds_char_rate = mode->clock * 1000; 1771 unsigned long long tmds_bit_rate; 1772 1773 if (vc4_hdmi->variant->unsupported_odd_h_timings) { 1774 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1775 /* Only try to fixup DBLCLK modes to get 480i and 576i 1776 * working. 1777 * A generic solution for all modes with odd horizontal 1778 * timing values seems impossible based on trying to 1779 * solve it for 1366x768 monitors. 1780 */ 1781 if ((mode->hsync_start - mode->hdisplay) & 1) 1782 mode->hsync_start--; 1783 if ((mode->hsync_end - mode->hsync_start) & 1) 1784 mode->hsync_end--; 1785 } 1786 1787 /* Now check whether we still have odd values remaining */ 1788 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1789 (mode->hsync_end % 2) || (mode->htotal % 2)) 1790 return -EINVAL; 1791 } 1792 1793 /* 1794 * The 1440p@60 pixel rate is in the same range than the first 1795 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1796 * bandwidth). Slightly lower the frequency to bring it out of 1797 * the WiFi range. 1798 */ 1799 tmds_bit_rate = tmds_char_rate * 10; 1800 if (vc4_hdmi->disable_wifi_frequencies && 1801 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1802 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1803 mode->clock = 238560; 1804 tmds_char_rate = mode->clock * 1000; 1805 } 1806 1807 return 0; 1808 } 1809 1810 static enum drm_mode_status 1811 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1812 const struct drm_display_mode *mode) 1813 { 1814 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1815 1816 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1817 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1818 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1819 (mode->hsync_end % 2) || (mode->htotal % 2))) 1820 return MODE_H_ILLEGAL; 1821 1822 return MODE_OK; 1823 } 1824 1825 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1826 .atomic_check = vc4_hdmi_encoder_atomic_check, 1827 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1828 .mode_valid = vc4_hdmi_encoder_mode_valid, 1829 }; 1830 1831 static int vc4_hdmi_late_register(struct drm_encoder *encoder) 1832 { 1833 struct drm_device *drm = encoder->dev; 1834 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1835 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1836 1837 drm_debugfs_add_file(drm, variant->debugfs_name, 1838 vc4_hdmi_debugfs_regs, vc4_hdmi); 1839 1840 return 0; 1841 } 1842 1843 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 1844 .late_register = vc4_hdmi_late_register, 1845 }; 1846 1847 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1848 { 1849 int i; 1850 u32 channel_map = 0; 1851 1852 for (i = 0; i < 8; i++) { 1853 if (channel_mask & BIT(i)) 1854 channel_map |= i << (3 * i); 1855 } 1856 return channel_map; 1857 } 1858 1859 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1860 { 1861 int i; 1862 u32 channel_map = 0; 1863 1864 for (i = 0; i < 8; i++) { 1865 if (channel_mask & BIT(i)) 1866 channel_map |= i << (4 * i); 1867 } 1868 return channel_map; 1869 } 1870 1871 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 1872 { 1873 struct drm_device *drm = vc4_hdmi->connector.dev; 1874 unsigned long flags; 1875 u32 hotplug; 1876 int idx; 1877 1878 if (!drm_dev_enter(drm, &idx)) 1879 return false; 1880 1881 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1882 hotplug = HDMI_READ(HDMI_HOTPLUG); 1883 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1884 1885 drm_dev_exit(idx); 1886 1887 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 1888 } 1889 1890 /* HDMI audio codec callbacks */ 1891 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1892 unsigned int samplerate) 1893 { 1894 struct drm_device *drm = vc4_hdmi->connector.dev; 1895 u32 hsm_clock; 1896 unsigned long flags; 1897 unsigned long n, m; 1898 int idx; 1899 1900 if (!drm_dev_enter(drm, &idx)) 1901 return; 1902 1903 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1904 rational_best_approximation(hsm_clock, samplerate, 1905 VC4_HD_MAI_SMP_N_MASK >> 1906 VC4_HD_MAI_SMP_N_SHIFT, 1907 (VC4_HD_MAI_SMP_M_MASK >> 1908 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1909 &n, &m); 1910 1911 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1912 HDMI_WRITE(HDMI_MAI_SMP, 1913 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1914 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1915 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1916 1917 drm_dev_exit(idx); 1918 } 1919 1920 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1921 { 1922 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1923 u32 n, cts; 1924 u64 tmp; 1925 1926 lockdep_assert_held(&vc4_hdmi->mutex); 1927 lockdep_assert_held(&vc4_hdmi->hw_lock); 1928 1929 n = 128 * samplerate / 1000; 1930 tmp = (u64)(mode->clock * 1000) * n; 1931 do_div(tmp, 128 * samplerate); 1932 cts = tmp; 1933 1934 HDMI_WRITE(HDMI_CRP_CFG, 1935 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1936 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1937 1938 /* 1939 * We could get slightly more accurate clocks in some cases by 1940 * providing a CTS_1 value. The two CTS values are alternated 1941 * between based on the period fields 1942 */ 1943 HDMI_WRITE(HDMI_CTS_0, cts); 1944 HDMI_WRITE(HDMI_CTS_1, cts); 1945 } 1946 1947 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1948 { 1949 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1950 1951 return snd_soc_card_get_drvdata(card); 1952 } 1953 1954 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1955 { 1956 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1957 1958 lockdep_assert_held(&vc4_hdmi->mutex); 1959 1960 /* 1961 * If the encoder is currently in DVI mode, treat the codec DAI 1962 * as missing. 1963 */ 1964 if (!display->is_hdmi) 1965 return false; 1966 1967 return true; 1968 } 1969 1970 static int vc4_hdmi_audio_startup(struct drm_connector *connector) 1971 { 1972 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 1973 struct drm_device *drm = vc4_hdmi->connector.dev; 1974 unsigned long flags; 1975 int ret = 0; 1976 int idx; 1977 1978 mutex_lock(&vc4_hdmi->mutex); 1979 1980 if (!drm_dev_enter(drm, &idx)) { 1981 ret = -ENODEV; 1982 goto out; 1983 } 1984 1985 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1986 ret = -ENOTSUPP; 1987 goto out_dev_exit; 1988 } 1989 1990 vc4_hdmi->audio.streaming = true; 1991 1992 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1993 HDMI_WRITE(HDMI_MAI_CTL, 1994 VC4_HD_MAI_CTL_RESET | 1995 VC4_HD_MAI_CTL_FLUSH | 1996 VC4_HD_MAI_CTL_DLATE | 1997 VC4_HD_MAI_CTL_ERRORE | 1998 VC4_HD_MAI_CTL_ERRORF); 1999 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2000 2001 if (vc4_hdmi->variant->phy_rng_enable) 2002 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 2003 2004 out_dev_exit: 2005 drm_dev_exit(idx); 2006 out: 2007 mutex_unlock(&vc4_hdmi->mutex); 2008 2009 return ret; 2010 } 2011 2012 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 2013 { 2014 struct device *dev = &vc4_hdmi->pdev->dev; 2015 unsigned long flags; 2016 int ret; 2017 2018 lockdep_assert_held(&vc4_hdmi->mutex); 2019 2020 vc4_hdmi->audio.streaming = false; 2021 ret = vc4_hdmi_stop_packet(vc4_hdmi, HDMI_INFOFRAME_TYPE_AUDIO, false); 2022 if (ret) 2023 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 2024 2025 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2026 2027 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 2028 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 2029 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 2030 2031 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2032 } 2033 2034 static void vc4_hdmi_audio_shutdown(struct drm_connector *connector) 2035 { 2036 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2037 struct drm_device *drm = vc4_hdmi->connector.dev; 2038 unsigned long flags; 2039 int idx; 2040 2041 mutex_lock(&vc4_hdmi->mutex); 2042 2043 if (!drm_dev_enter(drm, &idx)) 2044 goto out; 2045 2046 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2047 2048 HDMI_WRITE(HDMI_MAI_CTL, 2049 VC4_HD_MAI_CTL_DLATE | 2050 VC4_HD_MAI_CTL_ERRORE | 2051 VC4_HD_MAI_CTL_ERRORF); 2052 2053 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2054 2055 if (vc4_hdmi->variant->phy_rng_disable) 2056 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 2057 2058 vc4_hdmi->audio.streaming = false; 2059 vc4_hdmi_audio_reset(vc4_hdmi); 2060 2061 drm_dev_exit(idx); 2062 2063 out: 2064 mutex_unlock(&vc4_hdmi->mutex); 2065 } 2066 2067 static int sample_rate_to_mai_fmt(int samplerate) 2068 { 2069 switch (samplerate) { 2070 case 8000: 2071 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 2072 case 11025: 2073 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 2074 case 12000: 2075 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 2076 case 16000: 2077 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 2078 case 22050: 2079 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 2080 case 24000: 2081 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 2082 case 32000: 2083 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 2084 case 44100: 2085 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 2086 case 48000: 2087 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 2088 case 64000: 2089 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 2090 case 88200: 2091 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 2092 case 96000: 2093 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 2094 case 128000: 2095 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 2096 case 176400: 2097 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 2098 case 192000: 2099 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 2100 default: 2101 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 2102 } 2103 } 2104 2105 /* HDMI audio codec callbacks */ 2106 static int vc4_hdmi_audio_prepare(struct drm_connector *connector, 2107 struct hdmi_codec_daifmt *daifmt, 2108 struct hdmi_codec_params *params) 2109 { 2110 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2111 struct drm_device *drm = vc4_hdmi->connector.dev; 2112 struct vc4_dev *vc4 = to_vc4_dev(drm); 2113 unsigned int sample_rate = params->sample_rate; 2114 unsigned int channels = params->channels; 2115 unsigned long flags; 2116 u32 audio_packet_config, channel_mask; 2117 u32 channel_map; 2118 u32 mai_audio_format; 2119 u32 mai_sample_rate; 2120 int ret = 0; 2121 int idx; 2122 2123 dev_dbg(&vc4_hdmi->pdev->dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 2124 sample_rate, params->sample_width, channels); 2125 2126 mutex_lock(&vc4_hdmi->mutex); 2127 2128 if (!drm_dev_enter(drm, &idx)) { 2129 ret = -ENODEV; 2130 goto out; 2131 } 2132 2133 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2134 ret = -EINVAL; 2135 goto out_dev_exit; 2136 } 2137 2138 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 2139 2140 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2141 HDMI_WRITE(HDMI_MAI_CTL, 2142 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 2143 VC4_HD_MAI_CTL_WHOLSMP | 2144 VC4_HD_MAI_CTL_CHALIGN | 2145 VC4_HD_MAI_CTL_ENABLE); 2146 2147 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 2148 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 2149 params->channels == 8) 2150 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 2151 else 2152 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 2153 HDMI_WRITE(HDMI_MAI_FMT, 2154 VC4_SET_FIELD(mai_sample_rate, 2155 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 2156 VC4_SET_FIELD(mai_audio_format, 2157 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 2158 2159 /* The B frame identifier should match the value used by alsa-lib (8) */ 2160 audio_packet_config = 2161 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 2162 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 2163 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 2164 2165 channel_mask = GENMASK(channels - 1, 0); 2166 audio_packet_config |= VC4_SET_FIELD(channel_mask, 2167 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 2168 2169 /* Set the MAI threshold */ 2170 switch (vc4->gen) { 2171 case VC4_GEN_6_D: 2172 HDMI_WRITE(HDMI_MAI_THR, 2173 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICHIGH) | 2174 VC4_SET_FIELD(0x10, VC6_D_HD_MAI_THR_PANICLOW) | 2175 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQHIGH) | 2176 VC4_SET_FIELD(0x1c, VC6_D_HD_MAI_THR_DREQLOW)); 2177 break; 2178 case VC4_GEN_6_C: 2179 case VC4_GEN_5: 2180 HDMI_WRITE(HDMI_MAI_THR, 2181 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 2182 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 2183 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQHIGH) | 2184 VC4_SET_FIELD(0x1c, VC4_HD_MAI_THR_DREQLOW)); 2185 break; 2186 case VC4_GEN_4: 2187 HDMI_WRITE(HDMI_MAI_THR, 2188 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICHIGH) | 2189 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_PANICLOW) | 2190 VC4_SET_FIELD(0x6, VC4_HD_MAI_THR_DREQHIGH) | 2191 VC4_SET_FIELD(0x8, VC4_HD_MAI_THR_DREQLOW)); 2192 break; 2193 default: 2194 drm_err(drm, "Unknown VC4 generation: %d", vc4->gen); 2195 break; 2196 } 2197 2198 HDMI_WRITE(HDMI_MAI_CONFIG, 2199 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 2200 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 2201 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 2202 2203 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 2204 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 2205 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 2206 2207 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 2208 2209 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2210 2211 ret = drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, 2212 ¶ms->cea); 2213 if (ret) 2214 goto out_dev_exit; 2215 2216 out_dev_exit: 2217 drm_dev_exit(idx); 2218 out: 2219 mutex_unlock(&vc4_hdmi->mutex); 2220 2221 return ret; 2222 } 2223 2224 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 2225 .name = "vc4-hdmi-cpu-dai-component", 2226 .legacy_dai_naming = 1, 2227 }; 2228 2229 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 2230 { 2231 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 2232 2233 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 2234 2235 return 0; 2236 } 2237 2238 static const struct snd_soc_dai_ops vc4_snd_dai_ops = { 2239 .probe = vc4_hdmi_audio_cpu_dai_probe, 2240 }; 2241 2242 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 2243 .name = "vc4-hdmi-cpu-dai", 2244 .ops = &vc4_snd_dai_ops, 2245 .playback = { 2246 .stream_name = "Playback", 2247 .channels_min = 1, 2248 .channels_max = 8, 2249 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 2250 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 2251 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 2252 SNDRV_PCM_RATE_192000, 2253 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 2254 }, 2255 }; 2256 2257 static const struct snd_dmaengine_pcm_config pcm_conf = { 2258 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2259 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2260 }; 2261 2262 static const struct drm_connector_hdmi_audio_funcs vc4_hdmi_audio_funcs = { 2263 .startup = vc4_hdmi_audio_startup, 2264 .prepare = vc4_hdmi_audio_prepare, 2265 .shutdown = vc4_hdmi_audio_shutdown, 2266 }; 2267 2268 static int vc4_hdmi_codec_init(struct snd_soc_pcm_runtime *rtd) 2269 { 2270 struct vc4_hdmi *vc4_hdmi = snd_soc_card_get_drvdata(rtd->card); 2271 struct snd_soc_component *component = snd_soc_rtd_to_codec(rtd, 0)->component; 2272 int ret; 2273 2274 ret = snd_soc_card_jack_new(rtd->card, "HDMI Jack", SND_JACK_LINEOUT, 2275 &vc4_hdmi->hdmi_jack); 2276 if (ret) { 2277 dev_err(rtd->dev, "HDMI Jack creation failed: %d\n", ret); 2278 return ret; 2279 } 2280 2281 return snd_soc_component_set_jack(component, &vc4_hdmi->hdmi_jack, NULL); 2282 } 2283 2284 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2285 { 2286 const struct vc4_hdmi_register *mai_data = 2287 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2288 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2289 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2290 struct device *dev = &vc4_hdmi->pdev->dev; 2291 const __be32 *addr; 2292 int index, len; 2293 int ret; 2294 2295 /* 2296 * ASoC makes it a bit hard to retrieve a pointer to the 2297 * vc4_hdmi structure. Registering the card will overwrite our 2298 * device drvdata with a pointer to the snd_soc_card structure, 2299 * which can then be used to retrieve whatever drvdata we want 2300 * to associate. 2301 * 2302 * However, that doesn't fly in the case where we wouldn't 2303 * register an ASoC card (because of an old DT that is missing 2304 * the dmas properties for example), then the card isn't 2305 * registered and the device drvdata wouldn't be set. 2306 * 2307 * We can deal with both cases by making sure a snd_soc_card 2308 * pointer and a vc4_hdmi structure are pointing to the same 2309 * memory address, so we can treat them indistinctly without any 2310 * issue. 2311 */ 2312 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2313 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2314 2315 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 2316 dev_warn(dev, 2317 "'dmas' DT property is missing or empty, no HDMI audio\n"); 2318 return 0; 2319 } 2320 2321 if (mai_data->reg != VC4_HD) { 2322 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2323 return -EINVAL; 2324 } 2325 2326 /* 2327 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2328 * the bus address specified in the DT, because the physical address 2329 * (the one returned by platform_get_resource()) is not appropriate 2330 * for DMA transfers. 2331 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2332 */ 2333 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2334 /* Before BCM2711, we don't have a named register range */ 2335 if (index < 0) 2336 index = 1; 2337 2338 addr = of_get_address(dev->of_node, index, NULL, NULL); 2339 if (!addr) 2340 return -EINVAL; 2341 2342 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2343 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2344 vc4_hdmi->audio.dma_data.maxburst = 2; 2345 2346 /* 2347 * NOTE: Strictly speaking, we should probably use a DRM-managed 2348 * registration there to avoid removing all the audio components 2349 * by the time the driver doesn't have any user anymore. 2350 * 2351 * However, the ASoC core uses a number of devm_kzalloc calls 2352 * when registering, even when using non-device-managed 2353 * functions (such as in snd_soc_register_component()). 2354 * 2355 * If we call snd_soc_unregister_component() in a DRM-managed 2356 * action, the device-managed actions have already been executed 2357 * and thus we would access memory that has been freed. 2358 * 2359 * Using device-managed hooks here probably leaves us open to a 2360 * bunch of issues if userspace still has a handle on the ALSA 2361 * device when the device is removed. However, this is mitigated 2362 * by the use of drm_dev_enter()/drm_dev_exit() in the audio 2363 * path to prevent the access to the device resources if it 2364 * isn't there anymore. 2365 * 2366 * Then, the vc4_hdmi structure is DRM-managed and thus only 2367 * freed whenever the last user has closed the DRM device file. 2368 * It should thus outlive ALSA in most situations. 2369 */ 2370 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2371 if (ret) { 2372 dev_err(dev, "Could not register PCM component: %d\n", ret); 2373 return ret; 2374 } 2375 2376 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2377 &vc4_hdmi_audio_cpu_dai_drv, 1); 2378 if (ret) { 2379 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2380 return ret; 2381 } 2382 2383 ret = drm_connector_hdmi_audio_init(&vc4_hdmi->connector, dev, 2384 &vc4_hdmi_audio_funcs, 8, 0, false, 2385 -1); 2386 if (ret) 2387 return ret; 2388 2389 dai_link->cpus = &vc4_hdmi->audio.cpu; 2390 dai_link->codecs = &vc4_hdmi->audio.codec; 2391 dai_link->platforms = &vc4_hdmi->audio.platform; 2392 2393 dai_link->num_cpus = 1; 2394 dai_link->num_codecs = 1; 2395 dai_link->num_platforms = 1; 2396 2397 dai_link->name = "MAI"; 2398 dai_link->stream_name = "MAI PCM"; 2399 dai_link->codecs->dai_name = "i2s-hifi"; 2400 dai_link->cpus->dai_name = dev_name(dev); 2401 dai_link->codecs->name = dev_name(&vc4_hdmi->connector.hdmi_audio.codec_pdev->dev); 2402 dai_link->platforms->name = dev_name(dev); 2403 dai_link->init = vc4_hdmi_codec_init; 2404 2405 card->dai_link = dai_link; 2406 card->num_links = 1; 2407 card->name = vc4_hdmi->variant->card_name; 2408 card->driver_name = "vc4-hdmi"; 2409 card->dev = dev; 2410 card->owner = THIS_MODULE; 2411 2412 /* 2413 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2414 * stores a pointer to the snd card object in dev->driver_data. This 2415 * means we cannot use it for something else. The hdmi back-pointer is 2416 * now stored in card->drvdata and should be retrieved with 2417 * snd_soc_card_get_drvdata() if needed. 2418 */ 2419 snd_soc_card_set_drvdata(card, vc4_hdmi); 2420 ret = devm_snd_soc_register_card(dev, card); 2421 if (ret) 2422 dev_err_probe(dev, ret, "Could not register sound card\n"); 2423 2424 return ret; 2425 2426 } 2427 2428 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2429 { 2430 struct vc4_hdmi *vc4_hdmi = priv; 2431 struct drm_connector *connector = &vc4_hdmi->connector; 2432 struct drm_device *dev = connector->dev; 2433 2434 if (dev && dev->registered) 2435 drm_connector_helper_hpd_irq_event(connector); 2436 2437 return IRQ_HANDLED; 2438 } 2439 2440 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2441 { 2442 struct drm_connector *connector = &vc4_hdmi->connector; 2443 struct platform_device *pdev = vc4_hdmi->pdev; 2444 int ret; 2445 2446 if (vc4_hdmi->variant->external_irq_controller) { 2447 int hpd = platform_get_irq_byname(pdev, "hpd-connected"); 2448 2449 if (hpd < 0) 2450 return hpd; 2451 2452 ret = devm_request_threaded_irq(&pdev->dev, hpd, 2453 NULL, 2454 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2455 "vc4 hdmi hpd connected", vc4_hdmi); 2456 if (ret) 2457 return ret; 2458 2459 hpd = platform_get_irq_byname(pdev, "hpd-removed"); 2460 if (hpd < 0) 2461 return hpd; 2462 2463 ret = devm_request_threaded_irq(&pdev->dev, hpd, 2464 NULL, 2465 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2466 "vc4 hdmi hpd disconnected", vc4_hdmi); 2467 if (ret) 2468 return ret; 2469 2470 connector->polled = DRM_CONNECTOR_POLL_HPD; 2471 } 2472 2473 return 0; 2474 } 2475 2476 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2477 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2478 { 2479 struct vc4_hdmi *vc4_hdmi = priv; 2480 2481 if (vc4_hdmi->cec_rx_msg.len) 2482 drm_connector_hdmi_cec_received_msg(&vc4_hdmi->connector, 2483 &vc4_hdmi->cec_rx_msg); 2484 2485 return IRQ_HANDLED; 2486 } 2487 2488 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2489 { 2490 struct vc4_hdmi *vc4_hdmi = priv; 2491 2492 if (vc4_hdmi->cec_tx_ok) { 2493 drm_connector_hdmi_cec_transmit_done(&vc4_hdmi->connector, 2494 CEC_TX_STATUS_OK, 2495 0, 0, 0, 0); 2496 } else { 2497 /* 2498 * This CEC implementation makes 1 retry, so if we 2499 * get a NACK, then that means it made 2 attempts. 2500 */ 2501 drm_connector_hdmi_cec_transmit_done(&vc4_hdmi->connector, 2502 CEC_TX_STATUS_NACK, 2503 0, 2, 0, 0); 2504 } 2505 return IRQ_HANDLED; 2506 } 2507 2508 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2509 { 2510 struct vc4_hdmi *vc4_hdmi = priv; 2511 irqreturn_t ret; 2512 2513 if (vc4_hdmi->cec_irq_was_rx) 2514 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2515 else 2516 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2517 2518 return ret; 2519 } 2520 2521 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2522 { 2523 struct drm_device *dev = vc4_hdmi->connector.dev; 2524 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2525 unsigned int i; 2526 2527 lockdep_assert_held(&vc4_hdmi->hw_lock); 2528 2529 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2530 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2531 2532 if (msg->len > 16) { 2533 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2534 return; 2535 } 2536 2537 for (i = 0; i < msg->len; i += 4) { 2538 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2539 2540 msg->msg[i] = val & 0xff; 2541 msg->msg[i + 1] = (val >> 8) & 0xff; 2542 msg->msg[i + 2] = (val >> 16) & 0xff; 2543 msg->msg[i + 3] = (val >> 24) & 0xff; 2544 } 2545 } 2546 2547 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2548 { 2549 u32 cntrl1; 2550 2551 /* 2552 * We don't need to protect the register access using 2553 * drm_dev_enter() there because the interrupt handler lifetime 2554 * is tied to the device itself, and not to the DRM device. 2555 * 2556 * So when the device will be gone, one of the first thing we 2557 * will be doing will be to unregister the interrupt handler, 2558 * and then unregister the DRM device. drm_dev_enter() would 2559 * thus always succeed if we are here. 2560 */ 2561 2562 lockdep_assert_held(&vc4_hdmi->hw_lock); 2563 2564 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2565 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2566 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2567 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2568 2569 return IRQ_WAKE_THREAD; 2570 } 2571 2572 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2573 { 2574 struct vc4_hdmi *vc4_hdmi = priv; 2575 irqreturn_t ret; 2576 2577 spin_lock(&vc4_hdmi->hw_lock); 2578 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2579 spin_unlock(&vc4_hdmi->hw_lock); 2580 2581 return ret; 2582 } 2583 2584 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2585 { 2586 u32 cntrl1; 2587 2588 lockdep_assert_held(&vc4_hdmi->hw_lock); 2589 2590 /* 2591 * We don't need to protect the register access using 2592 * drm_dev_enter() there because the interrupt handler lifetime 2593 * is tied to the device itself, and not to the DRM device. 2594 * 2595 * So when the device will be gone, one of the first thing we 2596 * will be doing will be to unregister the interrupt handler, 2597 * and then unregister the DRM device. drm_dev_enter() would 2598 * thus always succeed if we are here. 2599 */ 2600 2601 vc4_hdmi->cec_rx_msg.len = 0; 2602 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2603 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2604 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2605 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2606 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2607 2608 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2609 2610 return IRQ_WAKE_THREAD; 2611 } 2612 2613 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2614 { 2615 struct vc4_hdmi *vc4_hdmi = priv; 2616 irqreturn_t ret; 2617 2618 spin_lock(&vc4_hdmi->hw_lock); 2619 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2620 spin_unlock(&vc4_hdmi->hw_lock); 2621 2622 return ret; 2623 } 2624 2625 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2626 { 2627 struct vc4_hdmi *vc4_hdmi = priv; 2628 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2629 irqreturn_t ret; 2630 u32 cntrl5; 2631 2632 /* 2633 * We don't need to protect the register access using 2634 * drm_dev_enter() there because the interrupt handler lifetime 2635 * is tied to the device itself, and not to the DRM device. 2636 * 2637 * So when the device will be gone, one of the first thing we 2638 * will be doing will be to unregister the interrupt handler, 2639 * and then unregister the DRM device. drm_dev_enter() would 2640 * thus always succeed if we are here. 2641 */ 2642 2643 if (!(stat & VC4_HDMI_CPU_CEC)) 2644 return IRQ_NONE; 2645 2646 spin_lock(&vc4_hdmi->hw_lock); 2647 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2648 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2649 if (vc4_hdmi->cec_irq_was_rx) 2650 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2651 else 2652 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2653 2654 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2655 spin_unlock(&vc4_hdmi->hw_lock); 2656 2657 return ret; 2658 } 2659 2660 static int vc4_hdmi_cec_enable(struct drm_connector *connector) 2661 { 2662 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2663 struct drm_device *drm = vc4_hdmi->connector.dev; 2664 /* clock period in microseconds */ 2665 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2666 unsigned long flags; 2667 u32 val; 2668 int ret; 2669 int idx; 2670 2671 if (!drm_dev_enter(drm, &idx)) 2672 /* 2673 * We can't return an error code, because the CEC 2674 * framework will emit WARN_ON messages at unbind 2675 * otherwise. 2676 */ 2677 return 0; 2678 2679 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2680 if (ret) { 2681 drm_dev_exit(idx); 2682 return ret; 2683 } 2684 2685 mutex_lock(&vc4_hdmi->mutex); 2686 2687 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2688 2689 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2690 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2691 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2692 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2693 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2694 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2695 2696 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2697 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2698 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2699 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2700 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2701 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2702 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2703 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2704 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2705 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2706 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2707 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2708 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2709 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2710 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2711 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2712 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2713 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2714 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2715 2716 if (!vc4_hdmi->variant->external_irq_controller) 2717 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2718 2719 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2720 2721 mutex_unlock(&vc4_hdmi->mutex); 2722 drm_dev_exit(idx); 2723 2724 return 0; 2725 } 2726 2727 static int vc4_hdmi_cec_disable(struct drm_connector *connector) 2728 { 2729 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2730 struct drm_device *drm = vc4_hdmi->connector.dev; 2731 unsigned long flags; 2732 int idx; 2733 2734 if (!drm_dev_enter(drm, &idx)) 2735 /* 2736 * We can't return an error code, because the CEC 2737 * framework will emit WARN_ON messages at unbind 2738 * otherwise. 2739 */ 2740 return 0; 2741 2742 mutex_lock(&vc4_hdmi->mutex); 2743 2744 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2745 2746 if (!vc4_hdmi->variant->external_irq_controller) 2747 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2748 2749 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2750 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2751 2752 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2753 2754 mutex_unlock(&vc4_hdmi->mutex); 2755 2756 pm_runtime_put(&vc4_hdmi->pdev->dev); 2757 2758 drm_dev_exit(idx); 2759 2760 return 0; 2761 } 2762 2763 static int vc4_hdmi_cec_adap_enable(struct drm_connector *connector, bool enable) 2764 { 2765 if (enable) 2766 return vc4_hdmi_cec_enable(connector); 2767 else 2768 return vc4_hdmi_cec_disable(connector); 2769 } 2770 2771 static int vc4_hdmi_cec_adap_log_addr(struct drm_connector *connector, u8 log_addr) 2772 { 2773 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2774 struct drm_device *drm = vc4_hdmi->connector.dev; 2775 unsigned long flags; 2776 int idx; 2777 2778 if (!drm_dev_enter(drm, &idx)) 2779 /* 2780 * We can't return an error code, because the CEC 2781 * framework will emit WARN_ON messages at unbind 2782 * otherwise. 2783 */ 2784 return 0; 2785 2786 mutex_lock(&vc4_hdmi->mutex); 2787 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2788 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2789 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2790 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2791 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2792 mutex_unlock(&vc4_hdmi->mutex); 2793 2794 drm_dev_exit(idx); 2795 2796 return 0; 2797 } 2798 2799 static int vc4_hdmi_cec_adap_transmit(struct drm_connector *connector, u8 attempts, 2800 u32 signal_free_time, struct cec_msg *msg) 2801 { 2802 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2803 struct drm_device *dev = vc4_hdmi->connector.dev; 2804 unsigned long flags; 2805 u32 val; 2806 unsigned int i; 2807 int idx; 2808 2809 if (!drm_dev_enter(dev, &idx)) 2810 return -ENODEV; 2811 2812 if (msg->len > 16) { 2813 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2814 drm_dev_exit(idx); 2815 return -ENOMEM; 2816 } 2817 2818 mutex_lock(&vc4_hdmi->mutex); 2819 2820 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2821 2822 for (i = 0; i < msg->len; i += 4) 2823 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2824 (msg->msg[i]) | 2825 (msg->msg[i + 1] << 8) | 2826 (msg->msg[i + 2] << 16) | 2827 (msg->msg[i + 3] << 24)); 2828 2829 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2830 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2831 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2832 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2833 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2834 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2835 2836 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2837 2838 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2839 mutex_unlock(&vc4_hdmi->mutex); 2840 drm_dev_exit(idx); 2841 2842 return 0; 2843 } 2844 2845 static int vc4_hdmi_cec_init(struct drm_connector *connector) 2846 { 2847 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 2848 struct platform_device *pdev = vc4_hdmi->pdev; 2849 struct device *dev = &pdev->dev; 2850 int ret; 2851 2852 if (vc4_hdmi->variant->external_irq_controller) { 2853 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"), 2854 vc4_cec_irq_handler_rx_bare, 2855 vc4_cec_irq_handler_rx_thread, 0, 2856 "vc4 hdmi cec rx", vc4_hdmi); 2857 if (ret) 2858 return ret; 2859 2860 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"), 2861 vc4_cec_irq_handler_tx_bare, 2862 vc4_cec_irq_handler_tx_thread, 0, 2863 "vc4 hdmi cec tx", vc4_hdmi); 2864 if (ret) 2865 return ret; 2866 } else { 2867 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 2868 vc4_cec_irq_handler, 2869 vc4_cec_irq_handler_thread, 0, 2870 "vc4 hdmi cec", vc4_hdmi); 2871 if (ret) 2872 return ret; 2873 } 2874 2875 return 0; 2876 } 2877 2878 static const struct drm_connector_hdmi_cec_funcs vc4_hdmi_cec_funcs = { 2879 .init = vc4_hdmi_cec_init, 2880 .enable = vc4_hdmi_cec_adap_enable, 2881 .log_addr = vc4_hdmi_cec_adap_log_addr, 2882 .transmit = vc4_hdmi_cec_adap_transmit, 2883 }; 2884 2885 static int vc4_hdmi_cec_register(struct vc4_hdmi *vc4_hdmi) 2886 { 2887 struct platform_device *pdev = vc4_hdmi->pdev; 2888 struct device *dev = &pdev->dev; 2889 2890 if (!of_property_present(dev->of_node, "interrupts")) { 2891 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2892 return 0; 2893 } 2894 2895 /* 2896 * NOTE: the CEC adapter will be unregistered by drmm cleanup from 2897 * drm_managed_release(), which is called from drm_dev_release() 2898 * during device unbind. 2899 * 2900 * However, the CEC framework already cleans up the CEC adapter 2901 * only when the last user has closed its file descriptor, so we 2902 * don't need to handle it in DRM. 2903 * 2904 * There's still a problematic sequence: if we unregister our 2905 * CEC adapter, but the userspace keeps a handle on the CEC 2906 * adapter but not the DRM device for some reason. In such a 2907 * case, our vc4_hdmi structure will be freed, but the 2908 * cec_adapter structure will have a dangling pointer to what 2909 * used to be our HDMI controller. If we get a CEC call at that 2910 * moment, we could end up with a use-after-free. Fortunately, 2911 * the CEC framework already handles this too, by calling 2912 * cec_is_registered() in cec_ioctl() and cec_poll(). 2913 */ 2914 return drmm_connector_hdmi_cec_register(&vc4_hdmi->connector, 2915 &vc4_hdmi_cec_funcs, 2916 vc4_hdmi->variant->card_name, 2917 1, 2918 &pdev->dev); 2919 } 2920 #else 2921 static int vc4_hdmi_cec_register(struct vc4_hdmi *vc4_hdmi) 2922 { 2923 return 0; 2924 } 2925 #endif 2926 2927 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr) 2928 { 2929 struct debugfs_reg32 *regs = ptr; 2930 2931 kfree(regs); 2932 } 2933 2934 static int vc4_hdmi_build_regset(struct drm_device *drm, 2935 struct vc4_hdmi *vc4_hdmi, 2936 struct debugfs_regset32 *regset, 2937 enum vc4_hdmi_regs reg) 2938 { 2939 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2940 struct debugfs_reg32 *regs, *new_regs; 2941 unsigned int count = 0; 2942 unsigned int i; 2943 int ret; 2944 2945 regs = kzalloc_objs(*regs, variant->num_registers); 2946 if (!regs) 2947 return -ENOMEM; 2948 2949 for (i = 0; i < variant->num_registers; i++) { 2950 const struct vc4_hdmi_register *field = &variant->registers[i]; 2951 2952 if (field->reg != reg) 2953 continue; 2954 2955 regs[count].name = field->name; 2956 regs[count].offset = field->offset; 2957 count++; 2958 } 2959 2960 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2961 if (!new_regs) 2962 return -ENOMEM; 2963 2964 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2965 regset->regs = new_regs; 2966 regset->nregs = count; 2967 2968 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs); 2969 if (ret) 2970 return ret; 2971 2972 return 0; 2973 } 2974 2975 static int vc4_hdmi_init_resources(struct drm_device *drm, 2976 struct vc4_hdmi *vc4_hdmi) 2977 { 2978 struct platform_device *pdev = vc4_hdmi->pdev; 2979 struct device *dev = &pdev->dev; 2980 int ret; 2981 2982 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2983 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2984 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2985 2986 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2987 if (IS_ERR(vc4_hdmi->hd_regs)) 2988 return PTR_ERR(vc4_hdmi->hd_regs); 2989 2990 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2991 if (ret) 2992 return ret; 2993 2994 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2995 if (ret) 2996 return ret; 2997 2998 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2999 if (IS_ERR(vc4_hdmi->pixel_clock)) { 3000 ret = PTR_ERR(vc4_hdmi->pixel_clock); 3001 if (ret != -EPROBE_DEFER) 3002 drm_err(drm, "Failed to get pixel clock\n"); 3003 return ret; 3004 } 3005 3006 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3007 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3008 drm_err(drm, "Failed to get HDMI state machine clock\n"); 3009 return PTR_ERR(vc4_hdmi->hsm_clock); 3010 } 3011 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 3012 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 3013 3014 return 0; 3015 } 3016 3017 static int vc5_hdmi_init_resources(struct drm_device *drm, 3018 struct vc4_hdmi *vc4_hdmi) 3019 { 3020 struct platform_device *pdev = vc4_hdmi->pdev; 3021 struct device *dev = &pdev->dev; 3022 struct resource *res; 3023 int ret; 3024 3025 vc4_hdmi->hdmicore_regs = devm_platform_ioremap_resource_byname(pdev, 3026 "hdmi"); 3027 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 3028 return PTR_ERR(vc4_hdmi->hdmicore_regs); 3029 3030 /* This is shared between both HDMI controllers. Cannot 3031 * claim for both instances. Lets not convert to using 3032 * devm_platform_ioremap_resource_byname() like 3033 * the rest 3034 */ 3035 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 3036 if (!res) 3037 return -ENODEV; 3038 3039 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 3040 if (!vc4_hdmi->hd_regs) 3041 return -ENOMEM; 3042 3043 vc4_hdmi->cec_regs = devm_platform_ioremap_resource_byname(pdev, 3044 "cec"); 3045 if (IS_ERR(vc4_hdmi->cec_regs)) 3046 return PTR_ERR(vc4_hdmi->cec_regs); 3047 3048 vc4_hdmi->csc_regs = devm_platform_ioremap_resource_byname(pdev, 3049 "csc"); 3050 if (IS_ERR(vc4_hdmi->csc_regs)) 3051 return PTR_ERR(vc4_hdmi->csc_regs); 3052 3053 vc4_hdmi->dvp_regs = devm_platform_ioremap_resource_byname(pdev, 3054 "dvp"); 3055 if (IS_ERR(vc4_hdmi->dvp_regs)) 3056 return PTR_ERR(vc4_hdmi->dvp_regs); 3057 3058 vc4_hdmi->phy_regs = devm_platform_ioremap_resource_byname(pdev, 3059 "phy"); 3060 3061 if (IS_ERR(vc4_hdmi->phy_regs)) 3062 return PTR_ERR(vc4_hdmi->phy_regs); 3063 3064 vc4_hdmi->ram_regs = devm_platform_ioremap_resource_byname(pdev, 3065 "packet"); 3066 if (IS_ERR(vc4_hdmi->ram_regs)) 3067 return PTR_ERR(vc4_hdmi->ram_regs); 3068 3069 vc4_hdmi->rm_regs = devm_platform_ioremap_resource_byname(pdev, "rm"); 3070 if (IS_ERR(vc4_hdmi->rm_regs)) 3071 return PTR_ERR(vc4_hdmi->rm_regs); 3072 3073 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3074 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3075 drm_err(drm, "Failed to get HDMI state machine clock\n"); 3076 return PTR_ERR(vc4_hdmi->hsm_clock); 3077 } 3078 3079 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 3080 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 3081 drm_err(drm, "Failed to get pixel bvb clock\n"); 3082 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 3083 } 3084 3085 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 3086 if (IS_ERR(vc4_hdmi->audio_clock)) { 3087 drm_err(drm, "Failed to get audio clock\n"); 3088 return PTR_ERR(vc4_hdmi->audio_clock); 3089 } 3090 3091 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 3092 if (IS_ERR(vc4_hdmi->cec_clock)) { 3093 drm_err(drm, "Failed to get CEC clock\n"); 3094 return PTR_ERR(vc4_hdmi->cec_clock); 3095 } 3096 3097 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 3098 if (IS_ERR(vc4_hdmi->reset)) { 3099 drm_err(drm, "Failed to get HDMI reset line\n"); 3100 return PTR_ERR(vc4_hdmi->reset); 3101 } 3102 3103 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3104 if (ret) 3105 return ret; 3106 3107 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3108 if (ret) 3109 return ret; 3110 3111 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC); 3112 if (ret) 3113 return ret; 3114 3115 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC); 3116 if (ret) 3117 return ret; 3118 3119 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP); 3120 if (ret) 3121 return ret; 3122 3123 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY); 3124 if (ret) 3125 return ret; 3126 3127 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM); 3128 if (ret) 3129 return ret; 3130 3131 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM); 3132 if (ret) 3133 return ret; 3134 3135 return 0; 3136 } 3137 3138 static int vc4_hdmi_runtime_suspend(struct device *dev) 3139 { 3140 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3141 unsigned long flags; 3142 3143 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3144 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 3145 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3146 3147 clk_disable_unprepare(vc4_hdmi->audio_clock); 3148 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3149 3150 return 0; 3151 } 3152 3153 static int vc4_hdmi_runtime_resume(struct device *dev) 3154 { 3155 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3156 unsigned long rate, flags; 3157 u32 __maybe_unused value; 3158 int ret; 3159 3160 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 3161 if (ret) 3162 return ret; 3163 3164 /* 3165 * Whenever the RaspberryPi boots without an HDMI monitor 3166 * plugged in, the firmware won't have initialized the HSM clock 3167 * rate and it will be reported as 0. 3168 * 3169 * If we try to access a register of the controller in such a 3170 * case, it will lead to a silent CPU stall. Let's make sure we 3171 * prevent such a case. 3172 */ 3173 rate = clk_get_rate(vc4_hdmi->hsm_clock); 3174 if (!rate) { 3175 ret = -EINVAL; 3176 goto err_disable_clk; 3177 } 3178 3179 ret = clk_prepare_enable(vc4_hdmi->audio_clock); 3180 if (ret) 3181 goto err_disable_clk; 3182 3183 if (vc4_hdmi->variant->reset) 3184 vc4_hdmi->variant->reset(vc4_hdmi); 3185 3186 #ifdef CONFIG_DRM_VC4_HDMI_CEC 3187 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3188 value = HDMI_READ(HDMI_CEC_CNTRL_1); 3189 /* Set the logical address to Unregistered */ 3190 value |= VC4_HDMI_CEC_ADDR_MASK; 3191 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 3192 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3193 3194 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 3195 3196 if (!vc4_hdmi->variant->external_irq_controller) { 3197 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3198 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 3199 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3200 } 3201 #endif 3202 3203 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3204 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, VC4_HDMI_RAM_PACKET_ENABLE); 3205 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3206 3207 return 0; 3208 3209 err_disable_clk: 3210 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3211 return ret; 3212 } 3213 3214 static void vc4_hdmi_put_ddc(void *ptr) 3215 { 3216 struct vc4_hdmi *vc4_hdmi = ptr; 3217 3218 i2c_put_adapter(vc4_hdmi->ddc); 3219 } 3220 3221 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 3222 { 3223 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 3224 struct platform_device *pdev = to_platform_device(dev); 3225 struct drm_device *drm = dev_get_drvdata(master); 3226 struct vc4_hdmi *vc4_hdmi; 3227 struct drm_encoder *encoder; 3228 struct device_node *ddc_node; 3229 int ret; 3230 3231 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL); 3232 if (!vc4_hdmi) 3233 return -ENOMEM; 3234 3235 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex); 3236 if (ret) 3237 return ret; 3238 3239 spin_lock_init(&vc4_hdmi->hw_lock); 3240 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 3241 3242 dev_set_drvdata(dev, vc4_hdmi); 3243 encoder = &vc4_hdmi->encoder.base; 3244 vc4_hdmi->encoder.type = variant->encoder_type; 3245 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 3246 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 3247 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 3248 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 3249 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 3250 vc4_hdmi->pdev = pdev; 3251 vc4_hdmi->variant = variant; 3252 3253 /* 3254 * Since we don't know the state of the controller and its 3255 * display (if any), let's assume it's always enabled. 3256 * vc4_hdmi_disable_scrambling() will thus run at boot, make 3257 * sure it's disabled, and avoid any inconsistency. 3258 */ 3259 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 3260 vc4_hdmi->scdc_enabled = true; 3261 3262 ret = variant->init_resources(drm, vc4_hdmi); 3263 if (ret) 3264 return ret; 3265 3266 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 3267 if (!ddc_node) { 3268 drm_err(drm, "Failed to find ddc node in device tree\n"); 3269 return -ENODEV; 3270 } 3271 3272 vc4_hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 3273 of_node_put(ddc_node); 3274 if (!vc4_hdmi->ddc) { 3275 drm_err(drm, "Failed to get ddc i2c adapter by node\n"); 3276 return -EPROBE_DEFER; 3277 } 3278 3279 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc, vc4_hdmi); 3280 if (ret) 3281 return ret; 3282 3283 /* Only use the GPIO HPD pin if present in the DT, otherwise 3284 * we'll use the HDMI core's register. 3285 */ 3286 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 3287 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 3288 return PTR_ERR(vc4_hdmi->hpd_gpio); 3289 } 3290 3291 vc4_hdmi->disable_wifi_frequencies = 3292 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 3293 3294 ret = devm_pm_runtime_enable(dev); 3295 if (ret) 3296 return ret; 3297 3298 /* 3299 * We need to have the device powered up at this point to call 3300 * our reset hook and for the CEC init. 3301 */ 3302 ret = pm_runtime_resume_and_get(dev); 3303 if (ret) 3304 return ret; 3305 3306 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 3307 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1") || 3308 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi0") || 3309 of_device_is_compatible(dev->of_node, "brcm,bcm2712-hdmi1")) && 3310 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 3311 clk_prepare_enable(vc4_hdmi->pixel_clock); 3312 clk_prepare_enable(vc4_hdmi->hsm_clock); 3313 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 3314 } 3315 3316 ret = drmm_encoder_init(drm, encoder, 3317 &vc4_hdmi_encoder_funcs, 3318 DRM_MODE_ENCODER_TMDS, 3319 NULL); 3320 if (ret) 3321 goto err_put_runtime_pm; 3322 3323 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 3324 3325 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 3326 if (ret) 3327 goto err_put_runtime_pm; 3328 3329 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 3330 if (ret) 3331 goto err_put_runtime_pm; 3332 3333 ret = vc4_hdmi_cec_register(vc4_hdmi); 3334 if (ret) 3335 goto err_put_runtime_pm; 3336 3337 ret = vc4_hdmi_audio_init(vc4_hdmi); 3338 if (ret) 3339 goto err_put_runtime_pm; 3340 3341 pm_runtime_put_sync(dev); 3342 3343 return 0; 3344 3345 err_put_runtime_pm: 3346 pm_runtime_put_sync(dev); 3347 3348 return ret; 3349 } 3350 3351 static const struct component_ops vc4_hdmi_ops = { 3352 .bind = vc4_hdmi_bind, 3353 }; 3354 3355 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3356 { 3357 return component_add(&pdev->dev, &vc4_hdmi_ops); 3358 } 3359 3360 static void vc4_hdmi_dev_remove(struct platform_device *pdev) 3361 { 3362 component_del(&pdev->dev, &vc4_hdmi_ops); 3363 } 3364 3365 static const struct vc4_hdmi_variant bcm2835_variant = { 3366 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3367 .debugfs_name = "hdmi_regs", 3368 .card_name = "vc4-hdmi", 3369 .max_pixel_clock = 162000000, 3370 .registers = vc4_hdmi_fields, 3371 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3372 3373 .init_resources = vc4_hdmi_init_resources, 3374 .csc_setup = vc4_hdmi_csc_setup, 3375 .reset = vc4_hdmi_reset, 3376 .set_timings = vc4_hdmi_set_timings, 3377 .phy_init = vc4_hdmi_phy_init, 3378 .phy_disable = vc4_hdmi_phy_disable, 3379 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3380 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3381 .channel_map = vc4_hdmi_channel_map, 3382 .supports_hdr = false, 3383 }; 3384 3385 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3386 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3387 .debugfs_name = "hdmi0_regs", 3388 .card_name = "vc4-hdmi-0", 3389 .max_pixel_clock = 600000000, 3390 .registers = vc5_hdmi_hdmi0_fields, 3391 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3392 .phy_lane_mapping = { 3393 PHY_LANE_0, 3394 PHY_LANE_1, 3395 PHY_LANE_2, 3396 PHY_LANE_CK, 3397 }, 3398 .unsupported_odd_h_timings = true, 3399 .external_irq_controller = true, 3400 3401 .init_resources = vc5_hdmi_init_resources, 3402 .csc_setup = vc5_hdmi_csc_setup, 3403 .reset = vc5_hdmi_reset, 3404 .set_timings = vc5_hdmi_set_timings, 3405 .phy_init = vc5_hdmi_phy_init, 3406 .phy_disable = vc5_hdmi_phy_disable, 3407 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3408 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3409 .channel_map = vc5_hdmi_channel_map, 3410 .supports_hdr = true, 3411 .hp_detect = vc5_hdmi_hp_detect, 3412 }; 3413 3414 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3415 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3416 .debugfs_name = "hdmi1_regs", 3417 .card_name = "vc4-hdmi-1", 3418 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3419 .registers = vc5_hdmi_hdmi1_fields, 3420 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3421 .phy_lane_mapping = { 3422 PHY_LANE_1, 3423 PHY_LANE_0, 3424 PHY_LANE_CK, 3425 PHY_LANE_2, 3426 }, 3427 .unsupported_odd_h_timings = true, 3428 .external_irq_controller = true, 3429 3430 .init_resources = vc5_hdmi_init_resources, 3431 .csc_setup = vc5_hdmi_csc_setup, 3432 .reset = vc5_hdmi_reset, 3433 .set_timings = vc5_hdmi_set_timings, 3434 .phy_init = vc5_hdmi_phy_init, 3435 .phy_disable = vc5_hdmi_phy_disable, 3436 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3437 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3438 .channel_map = vc5_hdmi_channel_map, 3439 .supports_hdr = true, 3440 .hp_detect = vc5_hdmi_hp_detect, 3441 }; 3442 3443 static const struct vc4_hdmi_variant bcm2712_hdmi0_variant = { 3444 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3445 .debugfs_name = "hdmi0_regs", 3446 .card_name = "vc4-hdmi-0", 3447 .max_pixel_clock = 600000000, 3448 .registers = vc6_hdmi_hdmi0_fields, 3449 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi0_fields), 3450 .phy_lane_mapping = { 3451 PHY_LANE_0, 3452 PHY_LANE_1, 3453 PHY_LANE_2, 3454 PHY_LANE_CK, 3455 }, 3456 .unsupported_odd_h_timings = false, 3457 .external_irq_controller = true, 3458 3459 .init_resources = vc5_hdmi_init_resources, 3460 .csc_setup = vc5_hdmi_csc_setup, 3461 .reset = vc5_hdmi_reset, 3462 .set_timings = vc5_hdmi_set_timings, 3463 .phy_init = vc6_hdmi_phy_init, 3464 .phy_disable = vc6_hdmi_phy_disable, 3465 .channel_map = vc5_hdmi_channel_map, 3466 .supports_hdr = true, 3467 .hp_detect = vc5_hdmi_hp_detect, 3468 }; 3469 3470 static const struct vc4_hdmi_variant bcm2712_hdmi1_variant = { 3471 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3472 .debugfs_name = "hdmi1_regs", 3473 .card_name = "vc4-hdmi-1", 3474 .max_pixel_clock = 600000000, 3475 .registers = vc6_hdmi_hdmi1_fields, 3476 .num_registers = ARRAY_SIZE(vc6_hdmi_hdmi1_fields), 3477 .phy_lane_mapping = { 3478 PHY_LANE_0, 3479 PHY_LANE_1, 3480 PHY_LANE_2, 3481 PHY_LANE_CK, 3482 }, 3483 .unsupported_odd_h_timings = false, 3484 .external_irq_controller = true, 3485 3486 .init_resources = vc5_hdmi_init_resources, 3487 .csc_setup = vc5_hdmi_csc_setup, 3488 .reset = vc5_hdmi_reset, 3489 .set_timings = vc5_hdmi_set_timings, 3490 .phy_init = vc6_hdmi_phy_init, 3491 .phy_disable = vc6_hdmi_phy_disable, 3492 .channel_map = vc5_hdmi_channel_map, 3493 .supports_hdr = true, 3494 .hp_detect = vc5_hdmi_hp_detect, 3495 }; 3496 3497 static const struct of_device_id vc4_hdmi_dt_match[] = { 3498 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3499 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3500 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3501 { .compatible = "brcm,bcm2712-hdmi0", .data = &bcm2712_hdmi0_variant }, 3502 { .compatible = "brcm,bcm2712-hdmi1", .data = &bcm2712_hdmi1_variant }, 3503 {} 3504 }; 3505 3506 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3507 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3508 vc4_hdmi_runtime_resume, 3509 NULL) 3510 }; 3511 3512 struct platform_driver vc4_hdmi_driver = { 3513 .probe = vc4_hdmi_dev_probe, 3514 .remove = vc4_hdmi_dev_remove, 3515 .driver = { 3516 .name = "vc4_hdmi", 3517 .of_match_table = vc4_hdmi_dt_match, 3518 .pm = &vc4_hdmi_pm_ops, 3519 }, 3520 }; 3521