xref: /linux/arch/arm64/boot/dts/freescale/tqma8xx.dtsi (revision 2f24482304ebd32c5aa374f31465b9941a860b92) 
1// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
2/*
3 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
5 * Author: Alexander Stein
6 */
7
8/ {
9	memory@80000000 {
10		device_type = "memory";
11		reg = <0x00000000 0x80000000 0 0x40000000>;
12	};
13
14	reg_1v8: regulator-1v8 {
15		compatible = "regulator-fixed";
16		regulator-name = "V_1V8";
17		regulator-min-microvolt = <1800000>;
18		regulator-max-microvolt = <1800000>;
19	};
20
21	reg_3v3: regulator-3v3 {
22		compatible = "regulator-fixed";
23		regulator-name = "V_3V3";
24		regulator-min-microvolt = <3300000>;
25		regulator-max-microvolt = <3300000>;
26	};
27
28	reserved-memory {
29		#address-cells = <2>;
30		#size-cells = <2>;
31		ranges;
32
33		/*
34		 * global autoconfigured region for contiguous allocations
35		 * must not exceed memory size and region
36		 */
37		linux,cma {
38			compatible = "shared-dma-pool";
39			reusable;
40			size = <0 0x20000000>;
41			alloc-ranges = <0 0x96000000 0 0x30000000>;
42			linux,cma-default;
43		};
44	};
45};
46
47/* TQMa8Xx only uses industrial grade, reduce trip points accordingly */
48&cpu_alert0 {
49	temperature = <95000>;
50};
51
52&cpu_crit0 {
53	temperature = <100000>;
54};
55/* end of temperature grade adjustments */
56
57&flexspi0 {
58	pinctrl-names = "default";
59	pinctrl-0 = <&pinctrl_flexspi0>;
60	status = "okay";
61
62	flash0: flash@0 {
63		reg = <0>;
64		compatible = "jedec,spi-nor";
65		spi-max-frequency = <66000000>;
66		spi-tx-bus-width = <1>;
67		spi-rx-bus-width = <4>;
68		vcc-supply = <&reg_1v8>;
69
70		partitions {
71			compatible = "fixed-partitions";
72			#address-cells = <1>;
73			#size-cells = <1>;
74		};
75	};
76};
77
78&i2c1 {
79	#address-cells = <1>;
80	#size-cells = <0>;
81	clock-frequency = <100000>;
82	pinctrl-names = "default", "gpio";
83	pinctrl-0 = <&pinctrl_lpi2c1>;
84	pinctrl-1 = <&pinctrl_lpi2c1gpio>;
85	scl-gpios = <&lsio_gpio1 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
86	sda-gpios = <&lsio_gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
87	status = "okay";
88
89	se97: temperature-sensor@1b {
90		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
91		reg = <0x1b>;
92	};
93
94	pcf85063: rtc@51 {
95		compatible = "nxp,pcf85063a";
96		reg = <0x51>;
97		quartz-load-femtofarads = <7000>;
98	};
99
100	at24c02: eeprom@53 {
101		compatible = "nxp,se97b", "atmel,24c02";
102		reg = <0x53>;
103		pagesize = <16>;
104		read-only;
105		vcc-supply = <&reg_3v3>;
106	};
107
108	m24c64: eeprom@57 {
109		compatible = "atmel,24c64";
110		reg = <0x57>;
111		pagesize = <32>;
112		vcc-supply = <&reg_3v3>;
113	};
114};
115
116&jpegdec {
117	status = "okay";
118};
119
120&jpegenc {
121	status = "okay";
122};
123
124
125&mu_m0 {
126	status = "okay";
127};
128
129&mu1_m0 {
130	status = "okay";
131};
132
133&thermal_zones {
134	pmic_thermal: pmic-thermal {
135		polling-delay-passive = <250>;
136		polling-delay = <2000>;
137		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
138
139		trips {
140			pmic_alert0: trip0 {
141				temperature = <110000>;
142				hysteresis = <2000>;
143				type = "passive";
144			};
145
146			pmic_crit0: trip1 {
147				temperature = <125000>;
148				hysteresis = <2000>;
149				type = "critical";
150			};
151		};
152
153		cooling-maps {
154			map0 {
155				trip = <&pmic_alert0>;
156				cooling-device =
157					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
158					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
159					<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
160					<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
161			};
162		};
163	};
164};
165
166&usdhc1 {
167	pinctrl-names = "default", "state_100mhz", "state_200mhz";
168	pinctrl-0 = <&pinctrl_usdhc1>;
169	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
170	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
171	vqmmc-supply = <&reg_1v8>;
172	vmmc-supply = <&reg_3v3>;
173	bus-width = <8>;
174	non-removable;
175	no-sdio;
176	no-sd;
177	status = "okay";
178};
179
180&vpu {
181	compatible = "nxp,imx8qxp-vpu";
182	status = "okay";
183};
184
185&vpu_core0 {
186	memory-region = <&decoder_boot>, <&decoder_rpc>;
187	status = "okay";
188};
189
190&vpu_core1 {
191	memory-region = <&encoder_boot>, <&encoder_rpc>;
192	status = "okay";
193};
194
195&iomuxc {
196	pinctrl_flexspi0: flexspi0grp {
197		fsl,pins = <
198			IMX8QXP_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x0600004d
199			IMX8QXP_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x0600004d
200			IMX8QXP_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x0600004d
201			IMX8QXP_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x0600004d
202			IMX8QXP_QSPI0A_DQS_LSIO_QSPI0A_DQS	0x0600004d
203			IMX8QXP_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x0600004d
204			IMX8QXP_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x0600004d
205			IMX8QXP_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x0600004d
206			IMX8QXP_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x0600004d
207			IMX8QXP_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x0600004d
208			IMX8QXP_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x0600004d
209			IMX8QXP_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x0600004d
210			IMX8QXP_QSPI0B_DQS_LSIO_QSPI0B_DQS	0x0600004d
211			IMX8QXP_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x0600004d
212			IMX8QXP_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x0600004d
213		>;
214	};
215
216	pinctrl_lpi2c1: lpi2c1grp {
217		fsl,pins = <
218			IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x06000021
219			IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x06000021
220		>;
221	};
222
223	pinctrl_lpi2c1gpio: lpi2c1gpiogrp {
224		fsl,pins = <
225			IMX8QXP_MIPI_DSI0_GPIO0_00_LSIO_GPIO1_IO27	0x06000021
226			IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28	0x06000021
227		>;
228	};
229
230	pinctrl_usdhc1: usdhc1grp {
231		fsl,pins = <
232			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
233			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
234			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
235			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
236			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
237			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
238			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
239			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
240			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
241			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
242			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
243		>;
244	};
245
246	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
247		fsl,pins = <
248			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK	0x06000040
249			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD	0x00000020
250			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
251			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
252			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
253			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
254			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
255			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
256			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
257			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
258			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
259		>;
260	};
261
262	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
263		fsl,pins = <
264			IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK	0x06000040
265			IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD	0x00000020
266			IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
267			IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
268			IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
269			IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
270			IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
271			IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
272			IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
273			IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
274			IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000040
275		>;
276	};
277};
278