1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Performance events: 4 * 5 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> 6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8 * 9 * Data type definitions, declarations, prototypes. 10 * 11 * Started by: Thomas Gleixner and Ingo Molnar 12 * 13 * For licencing details see kernel-base/COPYING 14 */ 15 #ifndef _UAPI_LINUX_PERF_EVENT_H 16 #define _UAPI_LINUX_PERF_EVENT_H 17 18 #include <linux/types.h> 19 #include <linux/ioctl.h> 20 #include <asm/byteorder.h> 21 22 /* 23 * User-space ABI bits: 24 */ 25 26 /* 27 * attr.type 28 */ 29 enum perf_type_id { 30 PERF_TYPE_HARDWARE = 0, 31 PERF_TYPE_SOFTWARE = 1, 32 PERF_TYPE_TRACEPOINT = 2, 33 PERF_TYPE_HW_CACHE = 3, 34 PERF_TYPE_RAW = 4, 35 PERF_TYPE_BREAKPOINT = 5, 36 37 PERF_TYPE_MAX, /* non-ABI */ 38 }; 39 40 /* 41 * attr.config layout for type PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE 42 * PERF_TYPE_HARDWARE: 0xEEEEEEEE000000AA 43 * AA: hardware event ID 44 * EEEEEEEE: PMU type ID 45 * PERF_TYPE_HW_CACHE: 0xEEEEEEEE00DDCCBB 46 * BB: hardware cache ID 47 * CC: hardware cache op ID 48 * DD: hardware cache op result ID 49 * EEEEEEEE: PMU type ID 50 * If the PMU type ID is 0, the PERF_TYPE_RAW will be applied. 51 */ 52 #define PERF_PMU_TYPE_SHIFT 32 53 #define PERF_HW_EVENT_MASK 0xffffffff 54 55 /* 56 * Generalized performance event event_id types, used by the 57 * attr.event_id parameter of the sys_perf_event_open() 58 * syscall: 59 */ 60 enum perf_hw_id { 61 /* 62 * Common hardware events, generalized by the kernel: 63 */ 64 PERF_COUNT_HW_CPU_CYCLES = 0, 65 PERF_COUNT_HW_INSTRUCTIONS = 1, 66 PERF_COUNT_HW_CACHE_REFERENCES = 2, 67 PERF_COUNT_HW_CACHE_MISSES = 3, 68 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 69 PERF_COUNT_HW_BRANCH_MISSES = 5, 70 PERF_COUNT_HW_BUS_CYCLES = 6, 71 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 72 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 73 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 74 75 PERF_COUNT_HW_MAX, /* non-ABI */ 76 }; 77 78 /* 79 * Generalized hardware cache events: 80 * 81 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 82 * { read, write, prefetch } x 83 * { accesses, misses } 84 */ 85 enum perf_hw_cache_id { 86 PERF_COUNT_HW_CACHE_L1D = 0, 87 PERF_COUNT_HW_CACHE_L1I = 1, 88 PERF_COUNT_HW_CACHE_LL = 2, 89 PERF_COUNT_HW_CACHE_DTLB = 3, 90 PERF_COUNT_HW_CACHE_ITLB = 4, 91 PERF_COUNT_HW_CACHE_BPU = 5, 92 PERF_COUNT_HW_CACHE_NODE = 6, 93 94 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 95 }; 96 97 enum perf_hw_cache_op_id { 98 PERF_COUNT_HW_CACHE_OP_READ = 0, 99 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 100 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 101 102 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 103 }; 104 105 enum perf_hw_cache_op_result_id { 106 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 107 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 108 109 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 110 }; 111 112 /* 113 * Special "software" events provided by the kernel, even if the hardware 114 * does not support performance events. These events measure various 115 * physical and sw events of the kernel (and allow the profiling of them as 116 * well): 117 */ 118 enum perf_sw_ids { 119 PERF_COUNT_SW_CPU_CLOCK = 0, 120 PERF_COUNT_SW_TASK_CLOCK = 1, 121 PERF_COUNT_SW_PAGE_FAULTS = 2, 122 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 123 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 124 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 125 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 126 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 127 PERF_COUNT_SW_EMULATION_FAULTS = 8, 128 PERF_COUNT_SW_DUMMY = 9, 129 PERF_COUNT_SW_BPF_OUTPUT = 10, 130 PERF_COUNT_SW_CGROUP_SWITCHES = 11, 131 132 PERF_COUNT_SW_MAX, /* non-ABI */ 133 }; 134 135 /* 136 * Bits that can be set in attr.sample_type to request information 137 * in the overflow packets. 138 */ 139 enum perf_event_sample_format { 140 PERF_SAMPLE_IP = 1U << 0, 141 PERF_SAMPLE_TID = 1U << 1, 142 PERF_SAMPLE_TIME = 1U << 2, 143 PERF_SAMPLE_ADDR = 1U << 3, 144 PERF_SAMPLE_READ = 1U << 4, 145 PERF_SAMPLE_CALLCHAIN = 1U << 5, 146 PERF_SAMPLE_ID = 1U << 6, 147 PERF_SAMPLE_CPU = 1U << 7, 148 PERF_SAMPLE_PERIOD = 1U << 8, 149 PERF_SAMPLE_STREAM_ID = 1U << 9, 150 PERF_SAMPLE_RAW = 1U << 10, 151 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 152 PERF_SAMPLE_REGS_USER = 1U << 12, 153 PERF_SAMPLE_STACK_USER = 1U << 13, 154 PERF_SAMPLE_WEIGHT = 1U << 14, 155 PERF_SAMPLE_DATA_SRC = 1U << 15, 156 PERF_SAMPLE_IDENTIFIER = 1U << 16, 157 PERF_SAMPLE_TRANSACTION = 1U << 17, 158 PERF_SAMPLE_REGS_INTR = 1U << 18, 159 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 160 PERF_SAMPLE_AUX = 1U << 20, 161 PERF_SAMPLE_CGROUP = 1U << 21, 162 PERF_SAMPLE_DATA_PAGE_SIZE = 1U << 22, 163 PERF_SAMPLE_CODE_PAGE_SIZE = 1U << 23, 164 PERF_SAMPLE_WEIGHT_STRUCT = 1U << 24, 165 166 PERF_SAMPLE_MAX = 1U << 25, /* non-ABI */ 167 }; 168 169 #define PERF_SAMPLE_WEIGHT_TYPE (PERF_SAMPLE_WEIGHT | PERF_SAMPLE_WEIGHT_STRUCT) 170 /* 171 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 172 * 173 * If the user does not pass priv level information via branch_sample_type, 174 * the kernel uses the event's priv level. Branch and event priv levels do 175 * not have to match. Branch priv level is checked for permissions. 176 * 177 * The branch types can be combined, however BRANCH_ANY covers all types 178 * of branches and therefore it supersedes all the other types. 179 */ 180 enum perf_branch_sample_type_shift { 181 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 182 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 183 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 184 185 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 186 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 187 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 188 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 189 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 190 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 191 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 192 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 193 194 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 195 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 196 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 197 198 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 199 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 200 201 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 202 203 PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT = 17, /* save low level index of raw branch records */ 204 205 PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18, /* save privilege mode */ 206 207 PERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19, /* save occurrences of events on a branch */ 208 209 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 210 }; 211 212 enum perf_branch_sample_type { 213 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 214 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 215 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 216 217 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 218 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 219 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 220 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 221 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 222 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 223 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 224 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 225 226 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 227 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 228 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 229 230 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 231 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 232 233 PERF_SAMPLE_BRANCH_TYPE_SAVE = 234 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 235 236 PERF_SAMPLE_BRANCH_HW_INDEX = 1U << PERF_SAMPLE_BRANCH_HW_INDEX_SHIFT, 237 238 PERF_SAMPLE_BRANCH_PRIV_SAVE = 1U << PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT, 239 240 PERF_SAMPLE_BRANCH_COUNTERS = 1U << PERF_SAMPLE_BRANCH_COUNTERS_SHIFT, 241 242 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 243 }; 244 245 /* 246 * Common flow change classification 247 */ 248 enum { 249 PERF_BR_UNKNOWN = 0, /* unknown */ 250 PERF_BR_COND = 1, /* conditional */ 251 PERF_BR_UNCOND = 2, /* unconditional */ 252 PERF_BR_IND = 3, /* indirect */ 253 PERF_BR_CALL = 4, /* function call */ 254 PERF_BR_IND_CALL = 5, /* indirect function call */ 255 PERF_BR_RET = 6, /* function return */ 256 PERF_BR_SYSCALL = 7, /* syscall */ 257 PERF_BR_SYSRET = 8, /* syscall return */ 258 PERF_BR_COND_CALL = 9, /* conditional function call */ 259 PERF_BR_COND_RET = 10, /* conditional function return */ 260 PERF_BR_ERET = 11, /* exception return */ 261 PERF_BR_IRQ = 12, /* irq */ 262 PERF_BR_SERROR = 13, /* system error */ 263 PERF_BR_NO_TX = 14, /* not in transaction */ 264 PERF_BR_EXTEND_ABI = 15, /* extend ABI */ 265 PERF_BR_MAX, 266 }; 267 268 /* 269 * Common branch speculation outcome classification 270 */ 271 enum { 272 PERF_BR_SPEC_NA = 0, /* Not available */ 273 PERF_BR_SPEC_WRONG_PATH = 1, /* Speculative but on wrong path */ 274 PERF_BR_NON_SPEC_CORRECT_PATH = 2, /* Non-speculative but on correct path */ 275 PERF_BR_SPEC_CORRECT_PATH = 3, /* Speculative and on correct path */ 276 PERF_BR_SPEC_MAX, 277 }; 278 279 enum { 280 PERF_BR_NEW_FAULT_ALGN = 0, /* Alignment fault */ 281 PERF_BR_NEW_FAULT_DATA = 1, /* Data fault */ 282 PERF_BR_NEW_FAULT_INST = 2, /* Inst fault */ 283 PERF_BR_NEW_ARCH_1 = 3, /* Architecture specific */ 284 PERF_BR_NEW_ARCH_2 = 4, /* Architecture specific */ 285 PERF_BR_NEW_ARCH_3 = 5, /* Architecture specific */ 286 PERF_BR_NEW_ARCH_4 = 6, /* Architecture specific */ 287 PERF_BR_NEW_ARCH_5 = 7, /* Architecture specific */ 288 PERF_BR_NEW_MAX, 289 }; 290 291 enum { 292 PERF_BR_PRIV_UNKNOWN = 0, 293 PERF_BR_PRIV_USER = 1, 294 PERF_BR_PRIV_KERNEL = 2, 295 PERF_BR_PRIV_HV = 3, 296 }; 297 298 #define PERF_BR_ARM64_FIQ PERF_BR_NEW_ARCH_1 299 #define PERF_BR_ARM64_DEBUG_HALT PERF_BR_NEW_ARCH_2 300 #define PERF_BR_ARM64_DEBUG_EXIT PERF_BR_NEW_ARCH_3 301 #define PERF_BR_ARM64_DEBUG_INST PERF_BR_NEW_ARCH_4 302 #define PERF_BR_ARM64_DEBUG_DATA PERF_BR_NEW_ARCH_5 303 304 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 305 (PERF_SAMPLE_BRANCH_USER|\ 306 PERF_SAMPLE_BRANCH_KERNEL|\ 307 PERF_SAMPLE_BRANCH_HV) 308 309 /* 310 * Values to determine ABI of the registers dump. 311 */ 312 enum perf_sample_regs_abi { 313 PERF_SAMPLE_REGS_ABI_NONE = 0, 314 PERF_SAMPLE_REGS_ABI_32 = 1, 315 PERF_SAMPLE_REGS_ABI_64 = 2, 316 }; 317 318 /* 319 * Values for the memory transaction event qualifier, mostly for 320 * abort events. Multiple bits can be set. 321 */ 322 enum { 323 PERF_TXN_ELISION = (1 << 0), /* From elision */ 324 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 325 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 326 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 327 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 328 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 329 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 330 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 331 332 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 333 334 /* bits 32..63 are reserved for the abort code */ 335 336 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 337 PERF_TXN_ABORT_SHIFT = 32, 338 }; 339 340 /* 341 * The format of the data returned by read() on a perf event fd, 342 * as specified by attr.read_format: 343 * 344 * struct read_format { 345 * { u64 value; 346 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 347 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 348 * { u64 id; } && PERF_FORMAT_ID 349 * { u64 lost; } && PERF_FORMAT_LOST 350 * } && !PERF_FORMAT_GROUP 351 * 352 * { u64 nr; 353 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 354 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 355 * { u64 value; 356 * { u64 id; } && PERF_FORMAT_ID 357 * { u64 lost; } && PERF_FORMAT_LOST 358 * } cntr[nr]; 359 * } && PERF_FORMAT_GROUP 360 * }; 361 */ 362 enum perf_event_read_format { 363 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 364 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 365 PERF_FORMAT_ID = 1U << 2, 366 PERF_FORMAT_GROUP = 1U << 3, 367 PERF_FORMAT_LOST = 1U << 4, 368 369 PERF_FORMAT_MAX = 1U << 5, /* non-ABI */ 370 }; 371 372 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 373 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 374 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 375 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 376 /* add: sample_stack_user */ 377 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 378 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 379 #define PERF_ATTR_SIZE_VER6 120 /* add: aux_sample_size */ 380 #define PERF_ATTR_SIZE_VER7 128 /* add: sig_data */ 381 #define PERF_ATTR_SIZE_VER8 136 /* add: config3 */ 382 383 /* 384 * Hardware event_id to monitor via a performance monitoring event: 385 * 386 * @sample_max_stack: Max number of frame pointers in a callchain, 387 * should be < /proc/sys/kernel/perf_event_max_stack 388 * Max number of entries of branch stack 389 * should be < hardware limit 390 */ 391 struct perf_event_attr { 392 393 /* 394 * Major type: hardware/software/tracepoint/etc. 395 */ 396 __u32 type; 397 398 /* 399 * Size of the attr structure, for fwd/bwd compat. 400 */ 401 __u32 size; 402 403 /* 404 * Type specific configuration information. 405 */ 406 __u64 config; 407 408 union { 409 __u64 sample_period; 410 __u64 sample_freq; 411 }; 412 413 __u64 sample_type; 414 __u64 read_format; 415 416 __u64 disabled : 1, /* off by default */ 417 inherit : 1, /* children inherit it */ 418 pinned : 1, /* must always be on PMU */ 419 exclusive : 1, /* only group on PMU */ 420 exclude_user : 1, /* don't count user */ 421 exclude_kernel : 1, /* ditto kernel */ 422 exclude_hv : 1, /* ditto hypervisor */ 423 exclude_idle : 1, /* don't count when idle */ 424 mmap : 1, /* include mmap data */ 425 comm : 1, /* include comm data */ 426 freq : 1, /* use freq, not period */ 427 inherit_stat : 1, /* per task counts */ 428 enable_on_exec : 1, /* next exec enables */ 429 task : 1, /* trace fork/exit */ 430 watermark : 1, /* wakeup_watermark */ 431 /* 432 * precise_ip: 433 * 434 * 0 - SAMPLE_IP can have arbitrary skid 435 * 1 - SAMPLE_IP must have constant skid 436 * 2 - SAMPLE_IP requested to have 0 skid 437 * 3 - SAMPLE_IP must have 0 skid 438 * 439 * See also PERF_RECORD_MISC_EXACT_IP 440 */ 441 precise_ip : 2, /* skid constraint */ 442 mmap_data : 1, /* non-exec mmap data */ 443 sample_id_all : 1, /* sample_type all events */ 444 445 exclude_host : 1, /* don't count in host */ 446 exclude_guest : 1, /* don't count in guest */ 447 448 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 449 exclude_callchain_user : 1, /* exclude user callchains */ 450 mmap2 : 1, /* include mmap with inode data */ 451 comm_exec : 1, /* flag comm events that are due to an exec */ 452 use_clockid : 1, /* use @clockid for time fields */ 453 context_switch : 1, /* context switch data */ 454 write_backward : 1, /* Write ring buffer from end to beginning */ 455 namespaces : 1, /* include namespaces data */ 456 ksymbol : 1, /* include ksymbol events */ 457 bpf_event : 1, /* include bpf events */ 458 aux_output : 1, /* generate AUX records instead of events */ 459 cgroup : 1, /* include cgroup events */ 460 text_poke : 1, /* include text poke events */ 461 build_id : 1, /* use build id in mmap2 events */ 462 inherit_thread : 1, /* children only inherit if cloned with CLONE_THREAD */ 463 remove_on_exec : 1, /* event is removed from task on exec */ 464 sigtrap : 1, /* send synchronous SIGTRAP on event */ 465 __reserved_1 : 26; 466 467 union { 468 __u32 wakeup_events; /* wakeup every n events */ 469 __u32 wakeup_watermark; /* bytes before wakeup */ 470 }; 471 472 __u32 bp_type; 473 union { 474 __u64 bp_addr; 475 __u64 kprobe_func; /* for perf_kprobe */ 476 __u64 uprobe_path; /* for perf_uprobe */ 477 __u64 config1; /* extension of config */ 478 }; 479 union { 480 __u64 bp_len; 481 __u64 kprobe_addr; /* when kprobe_func == NULL */ 482 __u64 probe_offset; /* for perf_[k,u]probe */ 483 __u64 config2; /* extension of config1 */ 484 }; 485 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 486 487 /* 488 * Defines set of user regs to dump on samples. 489 * See asm/perf_regs.h for details. 490 */ 491 __u64 sample_regs_user; 492 493 /* 494 * Defines size of the user stack to dump on samples. 495 */ 496 __u32 sample_stack_user; 497 498 __s32 clockid; 499 /* 500 * Defines set of regs to dump for each sample 501 * state captured on: 502 * - precise = 0: PMU interrupt 503 * - precise > 0: sampled instruction 504 * 505 * See asm/perf_regs.h for details. 506 */ 507 __u64 sample_regs_intr; 508 509 /* 510 * Wakeup watermark for AUX area 511 */ 512 __u32 aux_watermark; 513 __u16 sample_max_stack; 514 __u16 __reserved_2; 515 __u32 aux_sample_size; 516 517 union { 518 __u32 aux_action; 519 struct { 520 __u32 aux_start_paused : 1, /* start AUX area tracing paused */ 521 aux_pause : 1, /* on overflow, pause AUX area tracing */ 522 aux_resume : 1, /* on overflow, resume AUX area tracing */ 523 __reserved_3 : 29; 524 }; 525 }; 526 527 /* 528 * User provided data if sigtrap=1, passed back to user via 529 * siginfo_t::si_perf_data, e.g. to permit user to identify the event. 530 * Note, siginfo_t::si_perf_data is long-sized, and sig_data will be 531 * truncated accordingly on 32 bit architectures. 532 */ 533 __u64 sig_data; 534 535 __u64 config3; /* extension of config2 */ 536 }; 537 538 /* 539 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 540 * to query bpf programs attached to the same perf tracepoint 541 * as the given perf event. 542 */ 543 struct perf_event_query_bpf { 544 /* 545 * The below ids array length 546 */ 547 __u32 ids_len; 548 /* 549 * Set by the kernel to indicate the number of 550 * available programs 551 */ 552 __u32 prog_cnt; 553 /* 554 * User provided buffer to store program ids 555 */ 556 __u32 ids[]; 557 }; 558 559 /* 560 * Ioctls that can be done on a perf event fd: 561 */ 562 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 563 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 564 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 565 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 566 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 567 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 568 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 569 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 570 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 571 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 572 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 573 #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 574 575 enum perf_event_ioc_flags { 576 PERF_IOC_FLAG_GROUP = 1U << 0, 577 }; 578 579 /* 580 * Structure of the page that can be mapped via mmap 581 */ 582 struct perf_event_mmap_page { 583 __u32 version; /* version number of this structure */ 584 __u32 compat_version; /* lowest version this is compat with */ 585 586 /* 587 * Bits needed to read the hw events in user-space. 588 * 589 * u32 seq, time_mult, time_shift, index, width; 590 * u64 count, enabled, running; 591 * u64 cyc, time_offset; 592 * s64 pmc = 0; 593 * 594 * do { 595 * seq = pc->lock; 596 * barrier() 597 * 598 * enabled = pc->time_enabled; 599 * running = pc->time_running; 600 * 601 * if (pc->cap_usr_time && enabled != running) { 602 * cyc = rdtsc(); 603 * time_offset = pc->time_offset; 604 * time_mult = pc->time_mult; 605 * time_shift = pc->time_shift; 606 * } 607 * 608 * index = pc->index; 609 * count = pc->offset; 610 * if (pc->cap_user_rdpmc && index) { 611 * width = pc->pmc_width; 612 * pmc = rdpmc(index - 1); 613 * } 614 * 615 * barrier(); 616 * } while (pc->lock != seq); 617 * 618 * NOTE: for obvious reason this only works on self-monitoring 619 * processes. 620 */ 621 __u32 lock; /* seqlock for synchronization */ 622 __u32 index; /* hardware event identifier */ 623 __s64 offset; /* add to hardware event value */ 624 __u64 time_enabled; /* time event active */ 625 __u64 time_running; /* time event on cpu */ 626 union { 627 __u64 capabilities; 628 struct { 629 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 630 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 631 632 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 633 cap_user_time : 1, /* The time_{shift,mult,offset} fields are used */ 634 cap_user_time_zero : 1, /* The time_zero field is used */ 635 cap_user_time_short : 1, /* the time_{cycle,mask} fields are used */ 636 cap_____res : 58; 637 }; 638 }; 639 640 /* 641 * If cap_user_rdpmc this field provides the bit-width of the value 642 * read using the rdpmc() or equivalent instruction. This can be used 643 * to sign extend the result like: 644 * 645 * pmc <<= 64 - width; 646 * pmc >>= 64 - width; // signed shift right 647 * count += pmc; 648 */ 649 __u16 pmc_width; 650 651 /* 652 * If cap_usr_time the below fields can be used to compute the time 653 * delta since time_enabled (in ns) using rdtsc or similar. 654 * 655 * u64 quot, rem; 656 * u64 delta; 657 * 658 * quot = (cyc >> time_shift); 659 * rem = cyc & (((u64)1 << time_shift) - 1); 660 * delta = time_offset + quot * time_mult + 661 * ((rem * time_mult) >> time_shift); 662 * 663 * Where time_offset,time_mult,time_shift and cyc are read in the 664 * seqcount loop described above. This delta can then be added to 665 * enabled and possible running (if index), improving the scaling: 666 * 667 * enabled += delta; 668 * if (index) 669 * running += delta; 670 * 671 * quot = count / running; 672 * rem = count % running; 673 * count = quot * enabled + (rem * enabled) / running; 674 */ 675 __u16 time_shift; 676 __u32 time_mult; 677 __u64 time_offset; 678 /* 679 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 680 * from sample timestamps. 681 * 682 * time = timestamp - time_zero; 683 * quot = time / time_mult; 684 * rem = time % time_mult; 685 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 686 * 687 * And vice versa: 688 * 689 * quot = cyc >> time_shift; 690 * rem = cyc & (((u64)1 << time_shift) - 1); 691 * timestamp = time_zero + quot * time_mult + 692 * ((rem * time_mult) >> time_shift); 693 */ 694 __u64 time_zero; 695 696 __u32 size; /* Header size up to __reserved[] fields. */ 697 __u32 __reserved_1; 698 699 /* 700 * If cap_usr_time_short, the hardware clock is less than 64bit wide 701 * and we must compute the 'cyc' value, as used by cap_usr_time, as: 702 * 703 * cyc = time_cycles + ((cyc - time_cycles) & time_mask) 704 * 705 * NOTE: this form is explicitly chosen such that cap_usr_time_short 706 * is a correction on top of cap_usr_time, and code that doesn't 707 * know about cap_usr_time_short still works under the assumption 708 * the counter doesn't wrap. 709 */ 710 __u64 time_cycles; 711 __u64 time_mask; 712 713 /* 714 * Hole for extension of the self monitor capabilities 715 */ 716 717 __u8 __reserved[116*8]; /* align to 1k. */ 718 719 /* 720 * Control data for the mmap() data buffer. 721 * 722 * User-space reading the @data_head value should issue an smp_rmb(), 723 * after reading this value. 724 * 725 * When the mapping is PROT_WRITE the @data_tail value should be 726 * written by userspace to reflect the last read data, after issueing 727 * an smp_mb() to separate the data read from the ->data_tail store. 728 * In this case the kernel will not over-write unread data. 729 * 730 * See perf_output_put_handle() for the data ordering. 731 * 732 * data_{offset,size} indicate the location and size of the perf record 733 * buffer within the mmapped area. 734 */ 735 __u64 data_head; /* head in the data section */ 736 __u64 data_tail; /* user-space written tail */ 737 __u64 data_offset; /* where the buffer starts */ 738 __u64 data_size; /* data buffer size */ 739 740 /* 741 * AUX area is defined by aux_{offset,size} fields that should be set 742 * by the userspace, so that 743 * 744 * aux_offset >= data_offset + data_size 745 * 746 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 747 * 748 * Ring buffer pointers aux_{head,tail} have the same semantics as 749 * data_{head,tail} and same ordering rules apply. 750 */ 751 __u64 aux_head; 752 __u64 aux_tail; 753 __u64 aux_offset; 754 __u64 aux_size; 755 }; 756 757 /* 758 * The current state of perf_event_header::misc bits usage: 759 * ('|' used bit, '-' unused bit) 760 * 761 * 012 CDEF 762 * |||---------|||| 763 * 764 * Where: 765 * 0-2 CPUMODE_MASK 766 * 767 * C PROC_MAP_PARSE_TIMEOUT 768 * D MMAP_DATA / COMM_EXEC / FORK_EXEC / SWITCH_OUT 769 * E MMAP_BUILD_ID / EXACT_IP / SCHED_OUT_PREEMPT 770 * F (reserved) 771 */ 772 773 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 774 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 775 #define PERF_RECORD_MISC_KERNEL (1 << 0) 776 #define PERF_RECORD_MISC_USER (2 << 0) 777 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 778 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 779 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 780 781 /* 782 * Indicates that /proc/PID/maps parsing are truncated by time out. 783 */ 784 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 785 /* 786 * Following PERF_RECORD_MISC_* are used on different 787 * events, so can reuse the same bit position: 788 * 789 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 790 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 791 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 792 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 793 */ 794 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 795 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 796 #define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 797 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 798 /* 799 * These PERF_RECORD_MISC_* flags below are safely reused 800 * for the following events: 801 * 802 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 803 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 804 * PERF_RECORD_MISC_MMAP_BUILD_ID - PERF_RECORD_MMAP2 event 805 * 806 * 807 * PERF_RECORD_MISC_EXACT_IP: 808 * Indicates that the content of PERF_SAMPLE_IP points to 809 * the actual instruction that triggered the event. See also 810 * perf_event_attr::precise_ip. 811 * 812 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 813 * Indicates that thread was preempted in TASK_RUNNING state. 814 * 815 * PERF_RECORD_MISC_MMAP_BUILD_ID: 816 * Indicates that mmap2 event carries build id data. 817 */ 818 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 819 #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 820 #define PERF_RECORD_MISC_MMAP_BUILD_ID (1 << 14) 821 /* 822 * Reserve the last bit to indicate some extended misc field 823 */ 824 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 825 826 struct perf_event_header { 827 __u32 type; 828 __u16 misc; 829 __u16 size; 830 }; 831 832 struct perf_ns_link_info { 833 __u64 dev; 834 __u64 ino; 835 }; 836 837 enum { 838 NET_NS_INDEX = 0, 839 UTS_NS_INDEX = 1, 840 IPC_NS_INDEX = 2, 841 PID_NS_INDEX = 3, 842 USER_NS_INDEX = 4, 843 MNT_NS_INDEX = 5, 844 CGROUP_NS_INDEX = 6, 845 846 NR_NAMESPACES, /* number of available namespaces */ 847 }; 848 849 enum perf_event_type { 850 851 /* 852 * If perf_event_attr.sample_id_all is set then all event types will 853 * have the sample_type selected fields related to where/when 854 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 855 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 856 * just after the perf_event_header and the fields already present for 857 * the existing fields, i.e. at the end of the payload. That way a newer 858 * perf.data file will be supported by older perf tools, with these new 859 * optional fields being ignored. 860 * 861 * struct sample_id { 862 * { u32 pid, tid; } && PERF_SAMPLE_TID 863 * { u64 time; } && PERF_SAMPLE_TIME 864 * { u64 id; } && PERF_SAMPLE_ID 865 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 866 * { u32 cpu, res; } && PERF_SAMPLE_CPU 867 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 868 * } && perf_event_attr::sample_id_all 869 * 870 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 871 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 872 * relative to header.size. 873 */ 874 875 /* 876 * The MMAP events record the PROT_EXEC mappings so that we can 877 * correlate userspace IPs to code. They have the following structure: 878 * 879 * struct { 880 * struct perf_event_header header; 881 * 882 * u32 pid, tid; 883 * u64 addr; 884 * u64 len; 885 * u64 pgoff; 886 * char filename[]; 887 * struct sample_id sample_id; 888 * }; 889 */ 890 PERF_RECORD_MMAP = 1, 891 892 /* 893 * struct { 894 * struct perf_event_header header; 895 * u64 id; 896 * u64 lost; 897 * struct sample_id sample_id; 898 * }; 899 */ 900 PERF_RECORD_LOST = 2, 901 902 /* 903 * struct { 904 * struct perf_event_header header; 905 * 906 * u32 pid, tid; 907 * char comm[]; 908 * struct sample_id sample_id; 909 * }; 910 */ 911 PERF_RECORD_COMM = 3, 912 913 /* 914 * struct { 915 * struct perf_event_header header; 916 * u32 pid, ppid; 917 * u32 tid, ptid; 918 * u64 time; 919 * struct sample_id sample_id; 920 * }; 921 */ 922 PERF_RECORD_EXIT = 4, 923 924 /* 925 * struct { 926 * struct perf_event_header header; 927 * u64 time; 928 * u64 id; 929 * u64 stream_id; 930 * struct sample_id sample_id; 931 * }; 932 */ 933 PERF_RECORD_THROTTLE = 5, 934 PERF_RECORD_UNTHROTTLE = 6, 935 936 /* 937 * struct { 938 * struct perf_event_header header; 939 * u32 pid, ppid; 940 * u32 tid, ptid; 941 * u64 time; 942 * struct sample_id sample_id; 943 * }; 944 */ 945 PERF_RECORD_FORK = 7, 946 947 /* 948 * struct { 949 * struct perf_event_header header; 950 * u32 pid, tid; 951 * 952 * struct read_format values; 953 * struct sample_id sample_id; 954 * }; 955 */ 956 PERF_RECORD_READ = 8, 957 958 /* 959 * struct { 960 * struct perf_event_header header; 961 * 962 * # 963 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 964 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 965 * # is fixed relative to header. 966 * # 967 * 968 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 969 * { u64 ip; } && PERF_SAMPLE_IP 970 * { u32 pid, tid; } && PERF_SAMPLE_TID 971 * { u64 time; } && PERF_SAMPLE_TIME 972 * { u64 addr; } && PERF_SAMPLE_ADDR 973 * { u64 id; } && PERF_SAMPLE_ID 974 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 975 * { u32 cpu, res; } && PERF_SAMPLE_CPU 976 * { u64 period; } && PERF_SAMPLE_PERIOD 977 * 978 * { struct read_format values; } && PERF_SAMPLE_READ 979 * 980 * { u64 nr, 981 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 982 * 983 * # 984 * # The RAW record below is opaque data wrt the ABI 985 * # 986 * # That is, the ABI doesn't make any promises wrt to 987 * # the stability of its content, it may vary depending 988 * # on event, hardware, kernel version and phase of 989 * # the moon. 990 * # 991 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 992 * # 993 * 994 * { u32 size; 995 * char data[size];}&& PERF_SAMPLE_RAW 996 * 997 * { u64 nr; 998 * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX 999 * { u64 from, to, flags } lbr[nr]; 1000 * # 1001 * # The format of the counters is decided by the 1002 * # "branch_counter_nr" and "branch_counter_width", 1003 * # which are defined in the ABI. 1004 * # 1005 * { u64 counters; } cntr[nr] && PERF_SAMPLE_BRANCH_COUNTERS 1006 * } && PERF_SAMPLE_BRANCH_STACK 1007 * 1008 * { u64 abi; # enum perf_sample_regs_abi 1009 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 1010 * 1011 * { u64 size; 1012 * char data[size]; 1013 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 1014 * 1015 * { union perf_sample_weight 1016 * { 1017 * u64 full; && PERF_SAMPLE_WEIGHT 1018 * #if defined(__LITTLE_ENDIAN_BITFIELD) 1019 * struct { 1020 * u32 var1_dw; 1021 * u16 var2_w; 1022 * u16 var3_w; 1023 * } && PERF_SAMPLE_WEIGHT_STRUCT 1024 * #elif defined(__BIG_ENDIAN_BITFIELD) 1025 * struct { 1026 * u16 var3_w; 1027 * u16 var2_w; 1028 * u32 var1_dw; 1029 * } && PERF_SAMPLE_WEIGHT_STRUCT 1030 * #endif 1031 * } 1032 * } 1033 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 1034 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 1035 * { u64 abi; # enum perf_sample_regs_abi 1036 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 1037 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 1038 * { u64 size; 1039 * char data[size]; } && PERF_SAMPLE_AUX 1040 * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE 1041 * { u64 code_page_size;} && PERF_SAMPLE_CODE_PAGE_SIZE 1042 * }; 1043 */ 1044 PERF_RECORD_SAMPLE = 9, 1045 1046 /* 1047 * The MMAP2 records are an augmented version of MMAP, they add 1048 * maj, min, ino numbers to be used to uniquely identify each mapping 1049 * 1050 * struct { 1051 * struct perf_event_header header; 1052 * 1053 * u32 pid, tid; 1054 * u64 addr; 1055 * u64 len; 1056 * u64 pgoff; 1057 * union { 1058 * struct { 1059 * u32 maj; 1060 * u32 min; 1061 * u64 ino; 1062 * u64 ino_generation; 1063 * }; 1064 * struct { 1065 * u8 build_id_size; 1066 * u8 __reserved_1; 1067 * u16 __reserved_2; 1068 * u8 build_id[20]; 1069 * }; 1070 * }; 1071 * u32 prot, flags; 1072 * char filename[]; 1073 * struct sample_id sample_id; 1074 * }; 1075 */ 1076 PERF_RECORD_MMAP2 = 10, 1077 1078 /* 1079 * Records that new data landed in the AUX buffer part. 1080 * 1081 * struct { 1082 * struct perf_event_header header; 1083 * 1084 * u64 aux_offset; 1085 * u64 aux_size; 1086 * u64 flags; 1087 * struct sample_id sample_id; 1088 * }; 1089 */ 1090 PERF_RECORD_AUX = 11, 1091 1092 /* 1093 * Indicates that instruction trace has started 1094 * 1095 * struct { 1096 * struct perf_event_header header; 1097 * u32 pid; 1098 * u32 tid; 1099 * struct sample_id sample_id; 1100 * }; 1101 */ 1102 PERF_RECORD_ITRACE_START = 12, 1103 1104 /* 1105 * Records the dropped/lost sample number. 1106 * 1107 * struct { 1108 * struct perf_event_header header; 1109 * 1110 * u64 lost; 1111 * struct sample_id sample_id; 1112 * }; 1113 */ 1114 PERF_RECORD_LOST_SAMPLES = 13, 1115 1116 /* 1117 * Records a context switch in or out (flagged by 1118 * PERF_RECORD_MISC_SWITCH_OUT). See also 1119 * PERF_RECORD_SWITCH_CPU_WIDE. 1120 * 1121 * struct { 1122 * struct perf_event_header header; 1123 * struct sample_id sample_id; 1124 * }; 1125 */ 1126 PERF_RECORD_SWITCH = 14, 1127 1128 /* 1129 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 1130 * next_prev_tid that are the next (switching out) or previous 1131 * (switching in) pid/tid. 1132 * 1133 * struct { 1134 * struct perf_event_header header; 1135 * u32 next_prev_pid; 1136 * u32 next_prev_tid; 1137 * struct sample_id sample_id; 1138 * }; 1139 */ 1140 PERF_RECORD_SWITCH_CPU_WIDE = 15, 1141 1142 /* 1143 * struct { 1144 * struct perf_event_header header; 1145 * u32 pid; 1146 * u32 tid; 1147 * u64 nr_namespaces; 1148 * { u64 dev, inode; } [nr_namespaces]; 1149 * struct sample_id sample_id; 1150 * }; 1151 */ 1152 PERF_RECORD_NAMESPACES = 16, 1153 1154 /* 1155 * Record ksymbol register/unregister events: 1156 * 1157 * struct { 1158 * struct perf_event_header header; 1159 * u64 addr; 1160 * u32 len; 1161 * u16 ksym_type; 1162 * u16 flags; 1163 * char name[]; 1164 * struct sample_id sample_id; 1165 * }; 1166 */ 1167 PERF_RECORD_KSYMBOL = 17, 1168 1169 /* 1170 * Record bpf events: 1171 * enum perf_bpf_event_type { 1172 * PERF_BPF_EVENT_UNKNOWN = 0, 1173 * PERF_BPF_EVENT_PROG_LOAD = 1, 1174 * PERF_BPF_EVENT_PROG_UNLOAD = 2, 1175 * }; 1176 * 1177 * struct { 1178 * struct perf_event_header header; 1179 * u16 type; 1180 * u16 flags; 1181 * u32 id; 1182 * u8 tag[BPF_TAG_SIZE]; 1183 * struct sample_id sample_id; 1184 * }; 1185 */ 1186 PERF_RECORD_BPF_EVENT = 18, 1187 1188 /* 1189 * struct { 1190 * struct perf_event_header header; 1191 * u64 id; 1192 * char path[]; 1193 * struct sample_id sample_id; 1194 * }; 1195 */ 1196 PERF_RECORD_CGROUP = 19, 1197 1198 /* 1199 * Records changes to kernel text i.e. self-modified code. 'old_len' is 1200 * the number of old bytes, 'new_len' is the number of new bytes. Either 1201 * 'old_len' or 'new_len' may be zero to indicate, for example, the 1202 * addition or removal of a trampoline. 'bytes' contains the old bytes 1203 * followed immediately by the new bytes. 1204 * 1205 * struct { 1206 * struct perf_event_header header; 1207 * u64 addr; 1208 * u16 old_len; 1209 * u16 new_len; 1210 * u8 bytes[]; 1211 * struct sample_id sample_id; 1212 * }; 1213 */ 1214 PERF_RECORD_TEXT_POKE = 20, 1215 1216 /* 1217 * Data written to the AUX area by hardware due to aux_output, may need 1218 * to be matched to the event by an architecture-specific hardware ID. 1219 * This records the hardware ID, but requires sample_id to provide the 1220 * event ID. e.g. Intel PT uses this record to disambiguate PEBS-via-PT 1221 * records from multiple events. 1222 * 1223 * struct { 1224 * struct perf_event_header header; 1225 * u64 hw_id; 1226 * struct sample_id sample_id; 1227 * }; 1228 */ 1229 PERF_RECORD_AUX_OUTPUT_HW_ID = 21, 1230 1231 PERF_RECORD_MAX, /* non-ABI */ 1232 }; 1233 1234 enum perf_record_ksymbol_type { 1235 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 1236 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 1237 /* 1238 * Out of line code such as kprobe-replaced instructions or optimized 1239 * kprobes or ftrace trampolines. 1240 */ 1241 PERF_RECORD_KSYMBOL_TYPE_OOL = 2, 1242 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 1243 }; 1244 1245 #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 1246 1247 enum perf_bpf_event_type { 1248 PERF_BPF_EVENT_UNKNOWN = 0, 1249 PERF_BPF_EVENT_PROG_LOAD = 1, 1250 PERF_BPF_EVENT_PROG_UNLOAD = 2, 1251 PERF_BPF_EVENT_MAX, /* non-ABI */ 1252 }; 1253 1254 #define PERF_MAX_STACK_DEPTH 127 1255 #define PERF_MAX_CONTEXTS_PER_STACK 8 1256 1257 enum perf_callchain_context { 1258 PERF_CONTEXT_HV = (__u64)-32, 1259 PERF_CONTEXT_KERNEL = (__u64)-128, 1260 PERF_CONTEXT_USER = (__u64)-512, 1261 1262 PERF_CONTEXT_GUEST = (__u64)-2048, 1263 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1264 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1265 1266 PERF_CONTEXT_MAX = (__u64)-4095, 1267 }; 1268 1269 /** 1270 * PERF_RECORD_AUX::flags bits 1271 */ 1272 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 1273 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 1274 #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 1275 #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ 1276 #define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */ 1277 1278 /* CoreSight PMU AUX buffer formats */ 1279 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */ 1280 #define PERF_AUX_FLAG_CORESIGHT_FORMAT_RAW 0x0100 /* Raw format of the source */ 1281 1282 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1283 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 1284 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 1285 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1286 1287 #if defined(__LITTLE_ENDIAN_BITFIELD) 1288 union perf_mem_data_src { 1289 __u64 val; 1290 struct { 1291 __u64 mem_op:5, /* type of opcode */ 1292 mem_lvl:14, /* memory hierarchy level */ 1293 mem_snoop:5, /* snoop mode */ 1294 mem_lock:2, /* lock instr */ 1295 mem_dtlb:7, /* tlb access */ 1296 mem_lvl_num:4, /* memory hierarchy level number */ 1297 mem_remote:1, /* remote */ 1298 mem_snoopx:2, /* snoop mode, ext */ 1299 mem_blk:3, /* access blocked */ 1300 mem_hops:3, /* hop level */ 1301 mem_rsvd:18; 1302 }; 1303 }; 1304 #elif defined(__BIG_ENDIAN_BITFIELD) 1305 union perf_mem_data_src { 1306 __u64 val; 1307 struct { 1308 __u64 mem_rsvd:18, 1309 mem_hops:3, /* hop level */ 1310 mem_blk:3, /* access blocked */ 1311 mem_snoopx:2, /* snoop mode, ext */ 1312 mem_remote:1, /* remote */ 1313 mem_lvl_num:4, /* memory hierarchy level number */ 1314 mem_dtlb:7, /* tlb access */ 1315 mem_lock:2, /* lock instr */ 1316 mem_snoop:5, /* snoop mode */ 1317 mem_lvl:14, /* memory hierarchy level */ 1318 mem_op:5; /* type of opcode */ 1319 }; 1320 }; 1321 #else 1322 #error "Unknown endianness" 1323 #endif 1324 1325 /* type of opcode (load/store/prefetch,code) */ 1326 #define PERF_MEM_OP_NA 0x01 /* not available */ 1327 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 1328 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 1329 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 1330 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 1331 #define PERF_MEM_OP_SHIFT 0 1332 1333 /* 1334 * PERF_MEM_LVL_* namespace being depricated to some extent in the 1335 * favour of newer composite PERF_MEM_{LVLNUM_,REMOTE_,SNOOPX_} fields. 1336 * Supporting this namespace inorder to not break defined ABIs. 1337 * 1338 * memory hierarchy (memory level, hit or miss) 1339 */ 1340 #define PERF_MEM_LVL_NA 0x01 /* not available */ 1341 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 1342 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 1343 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 1344 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 1345 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 1346 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 1347 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1348 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1349 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1350 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1351 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1352 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1353 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1354 #define PERF_MEM_LVL_SHIFT 5 1355 1356 #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 1357 #define PERF_MEM_REMOTE_SHIFT 37 1358 1359 #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 1360 #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 1361 #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 1362 #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1363 #define PERF_MEM_LVLNUM_L2_MHB 0x05 /* L2 Miss Handling Buffer */ 1364 #define PERF_MEM_LVLNUM_MSC 0x06 /* Memory-side Cache */ 1365 /* 0x7 available */ 1366 #define PERF_MEM_LVLNUM_UNC 0x08 /* Uncached */ 1367 #define PERF_MEM_LVLNUM_CXL 0x09 /* CXL */ 1368 #define PERF_MEM_LVLNUM_IO 0x0a /* I/O */ 1369 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 1370 #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB / L1 Miss Handling Buffer */ 1371 #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 1372 #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 1373 #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 1374 1375 #define PERF_MEM_LVLNUM_SHIFT 33 1376 1377 /* snoop mode */ 1378 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1379 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1380 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1381 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1382 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1383 #define PERF_MEM_SNOOP_SHIFT 19 1384 1385 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1386 #define PERF_MEM_SNOOPX_PEER 0x02 /* xfer from peer */ 1387 #define PERF_MEM_SNOOPX_SHIFT 38 1388 1389 /* locked instruction */ 1390 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 1391 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1392 #define PERF_MEM_LOCK_SHIFT 24 1393 1394 /* TLB access */ 1395 #define PERF_MEM_TLB_NA 0x01 /* not available */ 1396 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1397 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1398 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 1399 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 1400 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1401 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1402 #define PERF_MEM_TLB_SHIFT 26 1403 1404 /* Access blocked */ 1405 #define PERF_MEM_BLK_NA 0x01 /* not available */ 1406 #define PERF_MEM_BLK_DATA 0x02 /* data could not be forwarded */ 1407 #define PERF_MEM_BLK_ADDR 0x04 /* address conflict */ 1408 #define PERF_MEM_BLK_SHIFT 40 1409 1410 /* hop level */ 1411 #define PERF_MEM_HOPS_0 0x01 /* remote core, same node */ 1412 #define PERF_MEM_HOPS_1 0x02 /* remote node, same socket */ 1413 #define PERF_MEM_HOPS_2 0x03 /* remote socket, same board */ 1414 #define PERF_MEM_HOPS_3 0x04 /* remote board */ 1415 /* 5-7 available */ 1416 #define PERF_MEM_HOPS_SHIFT 43 1417 1418 #define PERF_MEM_S(a, s) \ 1419 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1420 1421 /* 1422 * single taken branch record layout: 1423 * 1424 * from: source instruction (may not always be a branch insn) 1425 * to: branch target 1426 * mispred: branch target was mispredicted 1427 * predicted: branch target was predicted 1428 * 1429 * support for mispred, predicted is optional. In case it 1430 * is not supported mispred = predicted = 0. 1431 * 1432 * in_tx: running in a hardware transaction 1433 * abort: aborting a hardware transaction 1434 * cycles: cycles from last branch (or 0 if not supported) 1435 * type: branch type 1436 * spec: branch speculation info (or 0 if not supported) 1437 */ 1438 struct perf_branch_entry { 1439 __u64 from; 1440 __u64 to; 1441 __u64 mispred:1, /* target mispredicted */ 1442 predicted:1,/* target predicted */ 1443 in_tx:1, /* in transaction */ 1444 abort:1, /* transaction abort */ 1445 cycles:16, /* cycle count to last branch */ 1446 type:4, /* branch type */ 1447 spec:2, /* branch speculation info */ 1448 new_type:4, /* additional branch type */ 1449 priv:3, /* privilege level */ 1450 reserved:31; 1451 }; 1452 1453 /* Size of used info bits in struct perf_branch_entry */ 1454 #define PERF_BRANCH_ENTRY_INFO_BITS_MAX 33 1455 1456 union perf_sample_weight { 1457 __u64 full; 1458 #if defined(__LITTLE_ENDIAN_BITFIELD) 1459 struct { 1460 __u32 var1_dw; 1461 __u16 var2_w; 1462 __u16 var3_w; 1463 }; 1464 #elif defined(__BIG_ENDIAN_BITFIELD) 1465 struct { 1466 __u16 var3_w; 1467 __u16 var2_w; 1468 __u32 var1_dw; 1469 }; 1470 #else 1471 #error "Unknown endianness" 1472 #endif 1473 }; 1474 1475 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 1476