1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 Alibaba Group Holding Limited. 4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/clock/thead,th1520-clk-ap.h> 9#include <dt-bindings/power/thead,th1520-power.h> 10#include <dt-bindings/reset/thead,th1520-reset.h> 11 12/ { 13 compatible = "thead,th1520"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus: cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 timebase-frequency = <3000000>; 21 22 c910_0: cpu@0 { 23 compatible = "thead,c910", "riscv"; 24 device_type = "cpu"; 25 riscv,isa = "rv64imafdc"; 26 riscv,isa-base = "rv64i"; 27 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 28 "ziccrse", "zicntr", "zicsr", 29 "zifencei", "zihpm", "zfh", 30 "xtheadvector"; 31 thead,vlenb = <16>; 32 reg = <0>; 33 i-cache-block-size = <64>; 34 i-cache-size = <65536>; 35 i-cache-sets = <512>; 36 d-cache-block-size = <64>; 37 d-cache-size = <65536>; 38 d-cache-sets = <512>; 39 next-level-cache = <&l2_cache>; 40 mmu-type = "riscv,sv39"; 41 42 cpu0_intc: interrupt-controller { 43 compatible = "riscv,cpu-intc"; 44 interrupt-controller; 45 #interrupt-cells = <1>; 46 }; 47 }; 48 49 c910_1: cpu@1 { 50 compatible = "thead,c910", "riscv"; 51 device_type = "cpu"; 52 riscv,isa = "rv64imafdc"; 53 riscv,isa-base = "rv64i"; 54 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 55 "ziccrse", "zicntr", "zicsr", 56 "zifencei", "zihpm", "zfh", 57 "xtheadvector"; 58 thead,vlenb = <16>; 59 reg = <1>; 60 i-cache-block-size = <64>; 61 i-cache-size = <65536>; 62 i-cache-sets = <512>; 63 d-cache-block-size = <64>; 64 d-cache-size = <65536>; 65 d-cache-sets = <512>; 66 next-level-cache = <&l2_cache>; 67 mmu-type = "riscv,sv39"; 68 69 cpu1_intc: interrupt-controller { 70 compatible = "riscv,cpu-intc"; 71 interrupt-controller; 72 #interrupt-cells = <1>; 73 }; 74 }; 75 76 c910_2: cpu@2 { 77 compatible = "thead,c910", "riscv"; 78 device_type = "cpu"; 79 riscv,isa = "rv64imafdc"; 80 riscv,isa-base = "rv64i"; 81 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 82 "ziccrse", "zicntr", "zicsr", 83 "zifencei", "zihpm", "zfh", 84 "xtheadvector"; 85 thead,vlenb = <16>; 86 reg = <2>; 87 i-cache-block-size = <64>; 88 i-cache-size = <65536>; 89 i-cache-sets = <512>; 90 d-cache-block-size = <64>; 91 d-cache-size = <65536>; 92 d-cache-sets = <512>; 93 next-level-cache = <&l2_cache>; 94 mmu-type = "riscv,sv39"; 95 96 cpu2_intc: interrupt-controller { 97 compatible = "riscv,cpu-intc"; 98 interrupt-controller; 99 #interrupt-cells = <1>; 100 }; 101 }; 102 103 c910_3: cpu@3 { 104 compatible = "thead,c910", "riscv"; 105 device_type = "cpu"; 106 riscv,isa = "rv64imafdc"; 107 riscv,isa-base = "rv64i"; 108 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 109 "ziccrse", "zicntr", "zicsr", 110 "zifencei", "zihpm", "zfh", 111 "xtheadvector"; 112 thead,vlenb = <16>; 113 reg = <3>; 114 i-cache-block-size = <64>; 115 i-cache-size = <65536>; 116 i-cache-sets = <512>; 117 d-cache-block-size = <64>; 118 d-cache-size = <65536>; 119 d-cache-sets = <512>; 120 next-level-cache = <&l2_cache>; 121 mmu-type = "riscv,sv39"; 122 123 cpu3_intc: interrupt-controller { 124 compatible = "riscv,cpu-intc"; 125 interrupt-controller; 126 #interrupt-cells = <1>; 127 }; 128 }; 129 130 l2_cache: l2-cache { 131 compatible = "cache"; 132 cache-block-size = <64>; 133 cache-level = <2>; 134 cache-size = <1048576>; 135 cache-sets = <1024>; 136 cache-unified; 137 }; 138 }; 139 140 pmu { 141 compatible = "riscv,pmu"; 142 riscv,event-to-mhpmcounters = 143 <0x00003 0x00003 0x0007fff8>, 144 <0x00004 0x00004 0x0007fff8>, 145 <0x00005 0x00005 0x0007fff8>, 146 <0x00006 0x00006 0x0007fff8>, 147 <0x00007 0x00007 0x0007fff8>, 148 <0x00008 0x00008 0x0007fff8>, 149 <0x00009 0x00009 0x0007fff8>, 150 <0x0000a 0x0000a 0x0007fff8>, 151 <0x10000 0x10000 0x0007fff8>, 152 <0x10001 0x10001 0x0007fff8>, 153 <0x10002 0x10002 0x0007fff8>, 154 <0x10003 0x10003 0x0007fff8>, 155 <0x10010 0x10010 0x0007fff8>, 156 <0x10011 0x10011 0x0007fff8>, 157 <0x10012 0x10012 0x0007fff8>, 158 <0x10013 0x10013 0x0007fff8>; 159 riscv,event-to-mhpmevent = 160 <0x00003 0x00000000 0x00000001>, 161 <0x00004 0x00000000 0x00000002>, 162 <0x00006 0x00000000 0x00000006>, 163 <0x00005 0x00000000 0x00000007>, 164 <0x00007 0x00000000 0x00000008>, 165 <0x00008 0x00000000 0x00000009>, 166 <0x00009 0x00000000 0x0000000a>, 167 <0x0000a 0x00000000 0x0000000b>, 168 <0x10000 0x00000000 0x0000000c>, 169 <0x10001 0x00000000 0x0000000d>, 170 <0x10002 0x00000000 0x0000000e>, 171 <0x10003 0x00000000 0x0000000f>, 172 <0x10010 0x00000000 0x00000010>, 173 <0x10011 0x00000000 0x00000011>, 174 <0x10012 0x00000000 0x00000012>, 175 <0x10013 0x00000000 0x00000013>; 176 riscv,raw-event-to-mhpmcounters = 177 <0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>, 178 <0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>, 179 <0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>, 180 <0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>, 181 <0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>, 182 <0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>, 183 <0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>, 184 <0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>, 185 <0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>, 186 <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>, 187 <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>, 188 <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>, 189 <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>, 190 <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>, 191 <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>, 192 <0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>, 193 <0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>, 194 <0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>, 195 <0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>, 196 <0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>, 197 <0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>, 198 <0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>, 199 <0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>, 200 <0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>, 201 <0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>, 202 <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>, 203 <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>, 204 <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>, 205 <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>, 206 <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>, 207 <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>, 208 <0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>, 209 <0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>, 210 <0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>, 211 <0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>, 212 <0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>, 213 <0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>, 214 <0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>, 215 <0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>, 216 <0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>, 217 <0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>, 218 <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>; 219 }; 220 221 osc: oscillator { 222 compatible = "fixed-clock"; 223 clock-output-names = "osc_24m"; 224 #clock-cells = <0>; 225 }; 226 227 osc_32k: 32k-oscillator { 228 compatible = "fixed-clock"; 229 clock-output-names = "osc_32k"; 230 #clock-cells = <0>; 231 }; 232 233 aonsys_clk: clock-73728000 { 234 compatible = "fixed-clock"; 235 clock-frequency = <73728000>; 236 clock-output-names = "aonsys_clk"; 237 #clock-cells = <0>; 238 }; 239 240 gpu_mem_clk: mem-clk { 241 compatible = "fixed-clock"; 242 clock-frequency = <0>; 243 clock-output-names = "gpu_mem_clk"; 244 #clock-cells = <0>; 245 }; 246 247 stmmac_axi_config: stmmac-axi-config { 248 snps,wr_osr_lmt = <15>; 249 snps,rd_osr_lmt = <15>; 250 snps,blen = <0 0 64 32 0 0 0>; 251 }; 252 253 aon: aon { 254 compatible = "thead,th1520-aon"; 255 mboxes = <&mbox_910t 1>; 256 mbox-names = "aon"; 257 resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>; 258 reset-names = "gpu-clkgen"; 259 #power-domain-cells = <1>; 260 }; 261 262 soc { 263 compatible = "simple-bus"; 264 interrupt-parent = <&plic>; 265 #address-cells = <2>; 266 #size-cells = <2>; 267 dma-noncoherent; 268 ranges; 269 270 plic: interrupt-controller@ffd8000000 { 271 compatible = "thead,th1520-plic", "thead,c900-plic"; 272 reg = <0xff 0xd8000000 0x0 0x01000000>; 273 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 274 <&cpu1_intc 11>, <&cpu1_intc 9>, 275 <&cpu2_intc 11>, <&cpu2_intc 9>, 276 <&cpu3_intc 11>, <&cpu3_intc 9>; 277 interrupt-controller; 278 #address-cells = <0>; 279 #interrupt-cells = <2>; 280 riscv,ndev = <240>; 281 }; 282 283 clint: timer@ffdc000000 { 284 compatible = "thead,th1520-clint", "thead,c900-clint"; 285 reg = <0xff 0xdc000000 0x0 0x00010000>; 286 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 287 <&cpu1_intc 3>, <&cpu1_intc 7>, 288 <&cpu2_intc 3>, <&cpu2_intc 7>, 289 <&cpu3_intc 3>, <&cpu3_intc 7>; 290 }; 291 292 rst_vi: reset-controller@ffe4040100 { 293 compatible = "thead,th1520-reset-vi"; 294 reg = <0xff 0xe4040100 0x0 0x8>; 295 #reset-cells = <1>; 296 }; 297 298 spi0: spi@ffe700c000 { 299 compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; 300 reg = <0xff 0xe700c000 0x0 0x1000>; 301 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&clk CLK_SPI>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 status = "disabled"; 306 }; 307 308 uart0: serial@ffe7014000 { 309 compatible = "snps,dw-apb-uart"; 310 reg = <0xff 0xe7014000 0x0 0x100>; 311 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; 313 clock-names = "baudclk", "apb_pclk"; 314 reg-shift = <2>; 315 reg-io-width = <4>; 316 status = "disabled"; 317 }; 318 319 gmac1: ethernet@ffe7060000 { 320 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; 321 reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; 322 reg-names = "dwmac", "apb"; 323 interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; 324 interrupt-names = "macirq"; 325 clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>, 326 <&clk CLK_PERISYS_APB4_HCLK>; 327 clock-names = "stmmaceth", "pclk", "apb"; 328 snps,pbl = <32>; 329 snps,fixed-burst; 330 snps,multicast-filter-bins = <64>; 331 snps,perfect-filter-entries = <32>; 332 snps,axi-config = <&stmmac_axi_config>; 333 status = "disabled"; 334 335 mdio1: mdio { 336 compatible = "snps,dwmac-mdio"; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 }; 340 }; 341 342 gmac0: ethernet@ffe7070000 { 343 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; 344 reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; 345 reg-names = "dwmac", "apb"; 346 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; 347 interrupt-names = "macirq"; 348 clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>, 349 <&clk CLK_PERISYS_APB4_HCLK>; 350 clock-names = "stmmaceth", "pclk", "apb"; 351 snps,pbl = <32>; 352 snps,fixed-burst; 353 snps,multicast-filter-bins = <64>; 354 snps,perfect-filter-entries = <32>; 355 snps,axi-config = <&stmmac_axi_config>; 356 status = "disabled"; 357 358 mdio0: mdio { 359 compatible = "snps,dwmac-mdio"; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 }; 363 }; 364 365 emmc: mmc@ffe7080000 { 366 compatible = "thead,th1520-dwcmshc"; 367 reg = <0xff 0xe7080000 0x0 0x10000>; 368 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&clk CLK_EMMC_SDIO>; 370 clock-names = "core"; 371 status = "disabled"; 372 }; 373 374 sdio0: mmc@ffe7090000 { 375 compatible = "thead,th1520-dwcmshc"; 376 reg = <0xff 0xe7090000 0x0 0x10000>; 377 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&clk CLK_EMMC_SDIO>; 379 clock-names = "core"; 380 status = "disabled"; 381 }; 382 383 sdio1: mmc@ffe70a0000 { 384 compatible = "thead,th1520-dwcmshc"; 385 reg = <0xff 0xe70a0000 0x0 0x10000>; 386 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&clk CLK_EMMC_SDIO>; 388 clock-names = "core"; 389 status = "disabled"; 390 }; 391 392 uart1: serial@ffe7f00000 { 393 compatible = "snps,dw-apb-uart"; 394 reg = <0xff 0xe7f00000 0x0 0x100>; 395 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; 397 clock-names = "baudclk", "apb_pclk"; 398 reg-shift = <2>; 399 reg-io-width = <4>; 400 status = "disabled"; 401 }; 402 403 uart3: serial@ffe7f04000 { 404 compatible = "snps,dw-apb-uart"; 405 reg = <0xff 0xe7f04000 0x0 0x100>; 406 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; 408 clock-names = "baudclk", "apb_pclk"; 409 reg-shift = <2>; 410 reg-io-width = <4>; 411 status = "disabled"; 412 }; 413 414 gpio@ffe7f34000 { 415 compatible = "snps,dw-apb-gpio"; 416 reg = <0xff 0xe7f34000 0x0 0x1000>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 clocks = <&clk CLK_GPIO2>; 420 clock-names = "bus"; 421 422 gpio2: gpio-controller@0 { 423 compatible = "snps,dw-apb-gpio-port"; 424 gpio-controller; 425 #gpio-cells = <2>; 426 ngpios = <32>; 427 gpio-ranges = <&padctrl0_apsys 0 0 32>; 428 reg = <0>; 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 432 }; 433 }; 434 435 gpio@ffe7f38000 { 436 compatible = "snps,dw-apb-gpio"; 437 reg = <0xff 0xe7f38000 0x0 0x1000>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 clocks = <&clk CLK_GPIO3>; 441 clock-names = "bus"; 442 443 gpio3: gpio-controller@0 { 444 compatible = "snps,dw-apb-gpio-port"; 445 gpio-controller; 446 #gpio-cells = <2>; 447 ngpios = <23>; 448 gpio-ranges = <&padctrl0_apsys 0 32 23>; 449 reg = <0>; 450 interrupt-controller; 451 #interrupt-cells = <2>; 452 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; 453 }; 454 }; 455 456 padctrl1_apsys: pinctrl@ffe7f3c000 { 457 compatible = "thead,th1520-pinctrl"; 458 reg = <0xff 0xe7f3c000 0x0 0x1000>; 459 clocks = <&clk CLK_PADCTRL1>; 460 thead,pad-group = <2>; 461 }; 462 463 gpio@ffec005000 { 464 compatible = "snps,dw-apb-gpio"; 465 reg = <0xff 0xec005000 0x0 0x1000>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 clocks = <&clk CLK_GPIO0>; 469 clock-names = "bus"; 470 471 gpio0: gpio-controller@0 { 472 compatible = "snps,dw-apb-gpio-port"; 473 gpio-controller; 474 #gpio-cells = <2>; 475 ngpios = <32>; 476 gpio-ranges = <&padctrl1_apsys 0 0 32>; 477 reg = <0>; 478 interrupt-controller; 479 #interrupt-cells = <2>; 480 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; 481 }; 482 }; 483 484 gpio@ffec006000 { 485 compatible = "snps,dw-apb-gpio"; 486 reg = <0xff 0xec006000 0x0 0x1000>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 clocks = <&clk CLK_GPIO1>; 490 clock-names = "bus"; 491 492 gpio1: gpio-controller@0 { 493 compatible = "snps,dw-apb-gpio-port"; 494 gpio-controller; 495 #gpio-cells = <2>; 496 ngpios = <31>; 497 gpio-ranges = <&padctrl1_apsys 0 32 31>; 498 reg = <0>; 499 interrupt-controller; 500 #interrupt-cells = <2>; 501 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; 502 }; 503 }; 504 505 padctrl0_apsys: pinctrl@ffec007000 { 506 compatible = "thead,th1520-pinctrl"; 507 reg = <0xff 0xec007000 0x0 0x1000>; 508 clocks = <&clk CLK_PADCTRL0>; 509 thead,pad-group = <3>; 510 }; 511 512 uart2: serial@ffec010000 { 513 compatible = "snps,dw-apb-uart"; 514 reg = <0xff 0xec010000 0x0 0x4000>; 515 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; 517 clock-names = "baudclk", "apb_pclk"; 518 reg-shift = <2>; 519 reg-io-width = <4>; 520 status = "disabled"; 521 }; 522 523 pwm: pwm@ffec01c000 { 524 compatible = "thead,th1520-pwm"; 525 reg = <0xff 0xec01c000 0x0 0x4000>; 526 clocks = <&clk CLK_PWM>; 527 #pwm-cells = <3>; 528 }; 529 530 rst_misc: reset-controller@ffec02c000 { 531 compatible = "thead,th1520-reset-misc"; 532 reg = <0xff 0xec02c000 0x0 0x18>; 533 #reset-cells = <1>; 534 }; 535 536 rst_vp: reset-controller@ffecc30000 { 537 compatible = "thead,th1520-reset-vp"; 538 reg = <0xff 0xecc30000 0x0 0x14>; 539 #reset-cells = <1>; 540 }; 541 542 clk: clock-controller@ffef010000 { 543 compatible = "thead,th1520-clk-ap"; 544 reg = <0xff 0xef010000 0x0 0x1000>; 545 clocks = <&osc>; 546 #clock-cells = <1>; 547 }; 548 549 rst_ap: reset-controller@ffef014000 { 550 compatible = "thead,th1520-reset-ap"; 551 reg = <0xff 0xef014000 0x0 0x1000>; 552 #reset-cells = <1>; 553 }; 554 555 rst_dsp: reset-controller@ffef040028 { 556 compatible = "thead,th1520-reset-dsp"; 557 reg = <0xff 0xef040028 0x0 0x4>; 558 #reset-cells = <1>; 559 }; 560 561 gpu: gpu@ffef400000 { 562 compatible = "thead,th1520-gpu", "img,img-bxm-4-64", 563 "img,img-rogue"; 564 reg = <0xff 0xef400000 0x0 0x100000>; 565 interrupt-parent = <&plic>; 566 interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&clk_vo CLK_GPU_CORE>, 568 <&gpu_mem_clk>, 569 <&clk_vo CLK_GPU_CFG_ACLK>; 570 clock-names = "core", "mem", "sys"; 571 power-domains = <&aon TH1520_GPU_PD>; 572 resets = <&rst TH1520_RESET_ID_GPU>; 573 }; 574 575 rst: reset-controller@ffef528000 { 576 compatible = "thead,th1520-reset"; 577 reg = <0xff 0xef528000 0x0 0x4f>; 578 #reset-cells = <1>; 579 }; 580 581 clk_vo: clock-controller@ffef528050 { 582 compatible = "thead,th1520-clk-vo"; 583 reg = <0xff 0xef528050 0x0 0xfb0>; 584 clocks = <&clk CLK_VIDEO_PLL>; 585 #clock-cells = <1>; 586 }; 587 588 dmac0: dma-controller@ffefc00000 { 589 compatible = "snps,axi-dma-1.01a"; 590 reg = <0xff 0xefc00000 0x0 0x1000>; 591 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>; 593 clock-names = "core-clk", "cfgr-clk"; 594 #dma-cells = <1>; 595 dma-channels = <4>; 596 snps,block-size = <65536 65536 65536 65536>; 597 snps,priority = <0 1 2 3>; 598 snps,dma-masters = <1>; 599 snps,data-width = <4>; 600 snps,axi-max-burst-len = <16>; 601 status = "disabled"; 602 }; 603 604 timer0: timer@ffefc32000 { 605 compatible = "snps,dw-apb-timer"; 606 reg = <0xff 0xefc32000 0x0 0x14>; 607 clocks = <&clk CLK_PERI_APB_PCLK>; 608 clock-names = "timer"; 609 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 610 status = "disabled"; 611 }; 612 613 timer1: timer@ffefc32014 { 614 compatible = "snps,dw-apb-timer"; 615 reg = <0xff 0xefc32014 0x0 0x14>; 616 clocks = <&clk CLK_PERI_APB_PCLK>; 617 clock-names = "timer"; 618 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 619 status = "disabled"; 620 }; 621 622 timer2: timer@ffefc32028 { 623 compatible = "snps,dw-apb-timer"; 624 reg = <0xff 0xefc32028 0x0 0x14>; 625 clocks = <&clk CLK_PERI_APB_PCLK>; 626 clock-names = "timer"; 627 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 628 status = "disabled"; 629 }; 630 631 timer3: timer@ffefc3203c { 632 compatible = "snps,dw-apb-timer"; 633 reg = <0xff 0xefc3203c 0x0 0x14>; 634 clocks = <&clk CLK_PERI_APB_PCLK>; 635 clock-names = "timer"; 636 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 637 status = "disabled"; 638 }; 639 640 uart4: serial@fff7f08000 { 641 compatible = "snps,dw-apb-uart"; 642 reg = <0xff 0xf7f08000 0x0 0x4000>; 643 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; 645 clock-names = "baudclk", "apb_pclk"; 646 reg-shift = <2>; 647 reg-io-width = <4>; 648 status = "disabled"; 649 }; 650 651 uart5: serial@fff7f0c000 { 652 compatible = "snps,dw-apb-uart"; 653 reg = <0xff 0xf7f0c000 0x0 0x4000>; 654 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; 656 clock-names = "baudclk", "apb_pclk"; 657 reg-shift = <2>; 658 reg-io-width = <4>; 659 status = "disabled"; 660 }; 661 662 timer4: timer@ffffc33000 { 663 compatible = "snps,dw-apb-timer"; 664 reg = <0xff 0xffc33000 0x0 0x14>; 665 clocks = <&clk CLK_PERI_APB_PCLK>; 666 clock-names = "timer"; 667 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 668 status = "disabled"; 669 }; 670 671 timer5: timer@ffffc33014 { 672 compatible = "snps,dw-apb-timer"; 673 reg = <0xff 0xffc33014 0x0 0x14>; 674 clocks = <&clk CLK_PERI_APB_PCLK>; 675 clock-names = "timer"; 676 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 677 status = "disabled"; 678 }; 679 680 timer6: timer@ffffc33028 { 681 compatible = "snps,dw-apb-timer"; 682 reg = <0xff 0xffc33028 0x0 0x14>; 683 clocks = <&clk CLK_PERI_APB_PCLK>; 684 clock-names = "timer"; 685 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 686 status = "disabled"; 687 }; 688 689 timer7: timer@ffffc3303c { 690 compatible = "snps,dw-apb-timer"; 691 reg = <0xff 0xffc3303c 0x0 0x14>; 692 clocks = <&clk CLK_PERI_APB_PCLK>; 693 clock-names = "timer"; 694 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 695 status = "disabled"; 696 }; 697 698 mbox_910t: mailbox@ffffc38000 { 699 compatible = "thead,th1520-mbox"; 700 reg = <0xff 0xffc38000 0x0 0x6000>, 701 <0xff 0xffc40000 0x0 0x6000>, 702 <0xff 0xffc4c000 0x0 0x2000>, 703 <0xff 0xffc54000 0x0 0x2000>; 704 reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2"; 705 clocks = <&clk CLK_MBOX0>, <&clk CLK_MBOX1>, <&clk CLK_MBOX2>, 706 <&clk CLK_MBOX3>; 707 clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1", 708 "clk-remote-icu2"; 709 interrupt-parent = <&plic>; 710 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 711 #mbox-cells = <1>; 712 }; 713 714 gpio@fffff41000 { 715 compatible = "snps,dw-apb-gpio"; 716 reg = <0xff 0xfff41000 0x0 0x1000>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 720 aogpio: gpio-controller@0 { 721 compatible = "snps,dw-apb-gpio-port"; 722 gpio-controller; 723 #gpio-cells = <2>; 724 ngpios = <16>; 725 gpio-ranges = <&padctrl_aosys 0 9 16>; 726 reg = <0>; 727 interrupt-controller; 728 #interrupt-cells = <2>; 729 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; 730 }; 731 }; 732 733 rst_ao: reset-controller@fffff44000 { 734 compatible = "thead,th1520-reset-ao"; 735 reg = <0xff 0xfff44000 0x0 0x2000>; 736 #reset-cells = <1>; 737 status = "reserved"; 738 }; 739 740 padctrl_aosys: pinctrl@fffff4a000 { 741 compatible = "thead,th1520-pinctrl"; 742 reg = <0xff 0xfff4a000 0x0 0x2000>; 743 clocks = <&aonsys_clk>; 744 thead,pad-group = <1>; 745 }; 746 747 pvt: pvt@fffff4e000 { 748 compatible = "moortec,mr75203"; 749 reg = <0xff 0xfff4e000 0x0 0x80>, 750 <0xff 0xfff4e080 0x0 0x100>, 751 <0xff 0xfff4e180 0x0 0x680>, 752 <0xff 0xfff4e800 0x0 0x600>; 753 reg-names = "common", "ts", "pd", "vm"; 754 clocks = <&aonsys_clk>; 755 #thermal-sensor-cells = <1>; 756 }; 757 758 gpio@fffff52000 { 759 compatible = "snps,dw-apb-gpio"; 760 reg = <0xff 0xfff52000 0x0 0x1000>; 761 #address-cells = <1>; 762 #size-cells = <0>; 763 764 gpio4: gpio-controller@0 { 765 compatible = "snps,dw-apb-gpio-port"; 766 gpio-controller; 767 #gpio-cells = <2>; 768 ngpios = <23>; 769 gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>; 770 reg = <0>; 771 interrupt-controller; 772 #interrupt-cells = <2>; 773 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; 774 }; 775 }; 776 }; 777}; 778