1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2021 Alibaba Group Holding Limited. 4 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 5 */ 6 7#include <dt-bindings/interrupt-controller/irq.h> 8#include <dt-bindings/clock/thead,th1520-clk-ap.h> 9#include <dt-bindings/power/thead,th1520-power.h> 10 11/ { 12 compatible = "thead,th1520"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus: cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 timebase-frequency = <3000000>; 20 21 c910_0: cpu@0 { 22 compatible = "thead,c910", "riscv"; 23 device_type = "cpu"; 24 riscv,isa = "rv64imafdc"; 25 riscv,isa-base = "rv64i"; 26 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 27 "zifencei", "zihpm"; 28 reg = <0>; 29 i-cache-block-size = <64>; 30 i-cache-size = <65536>; 31 i-cache-sets = <512>; 32 d-cache-block-size = <64>; 33 d-cache-size = <65536>; 34 d-cache-sets = <512>; 35 next-level-cache = <&l2_cache>; 36 mmu-type = "riscv,sv39"; 37 38 cpu0_intc: interrupt-controller { 39 compatible = "riscv,cpu-intc"; 40 interrupt-controller; 41 #interrupt-cells = <1>; 42 }; 43 }; 44 45 c910_1: cpu@1 { 46 compatible = "thead,c910", "riscv"; 47 device_type = "cpu"; 48 riscv,isa = "rv64imafdc"; 49 riscv,isa-base = "rv64i"; 50 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 51 "zifencei", "zihpm"; 52 reg = <1>; 53 i-cache-block-size = <64>; 54 i-cache-size = <65536>; 55 i-cache-sets = <512>; 56 d-cache-block-size = <64>; 57 d-cache-size = <65536>; 58 d-cache-sets = <512>; 59 next-level-cache = <&l2_cache>; 60 mmu-type = "riscv,sv39"; 61 62 cpu1_intc: interrupt-controller { 63 compatible = "riscv,cpu-intc"; 64 interrupt-controller; 65 #interrupt-cells = <1>; 66 }; 67 }; 68 69 c910_2: cpu@2 { 70 compatible = "thead,c910", "riscv"; 71 device_type = "cpu"; 72 riscv,isa = "rv64imafdc"; 73 riscv,isa-base = "rv64i"; 74 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 75 "zifencei", "zihpm"; 76 reg = <2>; 77 i-cache-block-size = <64>; 78 i-cache-size = <65536>; 79 i-cache-sets = <512>; 80 d-cache-block-size = <64>; 81 d-cache-size = <65536>; 82 d-cache-sets = <512>; 83 next-level-cache = <&l2_cache>; 84 mmu-type = "riscv,sv39"; 85 86 cpu2_intc: interrupt-controller { 87 compatible = "riscv,cpu-intc"; 88 interrupt-controller; 89 #interrupt-cells = <1>; 90 }; 91 }; 92 93 c910_3: cpu@3 { 94 compatible = "thead,c910", "riscv"; 95 device_type = "cpu"; 96 riscv,isa = "rv64imafdc"; 97 riscv,isa-base = "rv64i"; 98 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 99 "zifencei", "zihpm"; 100 reg = <3>; 101 i-cache-block-size = <64>; 102 i-cache-size = <65536>; 103 i-cache-sets = <512>; 104 d-cache-block-size = <64>; 105 d-cache-size = <65536>; 106 d-cache-sets = <512>; 107 next-level-cache = <&l2_cache>; 108 mmu-type = "riscv,sv39"; 109 110 cpu3_intc: interrupt-controller { 111 compatible = "riscv,cpu-intc"; 112 interrupt-controller; 113 #interrupt-cells = <1>; 114 }; 115 }; 116 117 l2_cache: l2-cache { 118 compatible = "cache"; 119 cache-block-size = <64>; 120 cache-level = <2>; 121 cache-size = <1048576>; 122 cache-sets = <1024>; 123 cache-unified; 124 }; 125 }; 126 127 pmu { 128 compatible = "riscv,pmu"; 129 riscv,event-to-mhpmcounters = 130 <0x00003 0x00003 0x0007fff8>, 131 <0x00004 0x00004 0x0007fff8>, 132 <0x00005 0x00005 0x0007fff8>, 133 <0x00006 0x00006 0x0007fff8>, 134 <0x00007 0x00007 0x0007fff8>, 135 <0x00008 0x00008 0x0007fff8>, 136 <0x00009 0x00009 0x0007fff8>, 137 <0x0000a 0x0000a 0x0007fff8>, 138 <0x10000 0x10000 0x0007fff8>, 139 <0x10001 0x10001 0x0007fff8>, 140 <0x10002 0x10002 0x0007fff8>, 141 <0x10003 0x10003 0x0007fff8>, 142 <0x10010 0x10010 0x0007fff8>, 143 <0x10011 0x10011 0x0007fff8>, 144 <0x10012 0x10012 0x0007fff8>, 145 <0x10013 0x10013 0x0007fff8>; 146 riscv,event-to-mhpmevent = 147 <0x00003 0x00000000 0x00000001>, 148 <0x00004 0x00000000 0x00000002>, 149 <0x00006 0x00000000 0x00000006>, 150 <0x00005 0x00000000 0x00000007>, 151 <0x00007 0x00000000 0x00000008>, 152 <0x00008 0x00000000 0x00000009>, 153 <0x00009 0x00000000 0x0000000a>, 154 <0x0000a 0x00000000 0x0000000b>, 155 <0x10000 0x00000000 0x0000000c>, 156 <0x10001 0x00000000 0x0000000d>, 157 <0x10002 0x00000000 0x0000000e>, 158 <0x10003 0x00000000 0x0000000f>, 159 <0x10010 0x00000000 0x00000010>, 160 <0x10011 0x00000000 0x00000011>, 161 <0x10012 0x00000000 0x00000012>, 162 <0x10013 0x00000000 0x00000013>; 163 riscv,raw-event-to-mhpmcounters = 164 <0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>, 165 <0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>, 166 <0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>, 167 <0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>, 168 <0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>, 169 <0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>, 170 <0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>, 171 <0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>, 172 <0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>, 173 <0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>, 174 <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>, 175 <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>, 176 <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>, 177 <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>, 178 <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>, 179 <0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>, 180 <0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>, 181 <0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>, 182 <0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>, 183 <0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>, 184 <0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>, 185 <0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>, 186 <0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>, 187 <0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>, 188 <0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>, 189 <0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>, 190 <0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>, 191 <0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>, 192 <0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>, 193 <0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>, 194 <0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>, 195 <0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>, 196 <0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>, 197 <0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>, 198 <0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>, 199 <0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>, 200 <0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>, 201 <0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>, 202 <0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>, 203 <0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>, 204 <0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>, 205 <0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>; 206 }; 207 208 osc: oscillator { 209 compatible = "fixed-clock"; 210 clock-output-names = "osc_24m"; 211 #clock-cells = <0>; 212 }; 213 214 osc_32k: 32k-oscillator { 215 compatible = "fixed-clock"; 216 clock-output-names = "osc_32k"; 217 #clock-cells = <0>; 218 }; 219 220 aonsys_clk: clock-73728000 { 221 compatible = "fixed-clock"; 222 clock-frequency = <73728000>; 223 clock-output-names = "aonsys_clk"; 224 #clock-cells = <0>; 225 }; 226 227 stmmac_axi_config: stmmac-axi-config { 228 snps,wr_osr_lmt = <15>; 229 snps,rd_osr_lmt = <15>; 230 snps,blen = <0 0 64 32 0 0 0>; 231 }; 232 233 aon: aon { 234 compatible = "thead,th1520-aon"; 235 mboxes = <&mbox_910t 1>; 236 mbox-names = "aon"; 237 #power-domain-cells = <1>; 238 }; 239 240 soc { 241 compatible = "simple-bus"; 242 interrupt-parent = <&plic>; 243 #address-cells = <2>; 244 #size-cells = <2>; 245 dma-noncoherent; 246 ranges; 247 248 plic: interrupt-controller@ffd8000000 { 249 compatible = "thead,th1520-plic", "thead,c900-plic"; 250 reg = <0xff 0xd8000000 0x0 0x01000000>; 251 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 252 <&cpu1_intc 11>, <&cpu1_intc 9>, 253 <&cpu2_intc 11>, <&cpu2_intc 9>, 254 <&cpu3_intc 11>, <&cpu3_intc 9>; 255 interrupt-controller; 256 #address-cells = <0>; 257 #interrupt-cells = <2>; 258 riscv,ndev = <240>; 259 }; 260 261 clint: timer@ffdc000000 { 262 compatible = "thead,th1520-clint", "thead,c900-clint"; 263 reg = <0xff 0xdc000000 0x0 0x00010000>; 264 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 265 <&cpu1_intc 3>, <&cpu1_intc 7>, 266 <&cpu2_intc 3>, <&cpu2_intc 7>, 267 <&cpu3_intc 3>, <&cpu3_intc 7>; 268 }; 269 270 spi0: spi@ffe700c000 { 271 compatible = "thead,th1520-spi", "snps,dw-apb-ssi"; 272 reg = <0xff 0xe700c000 0x0 0x1000>; 273 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; 274 clocks = <&clk CLK_SPI>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 status = "disabled"; 278 }; 279 280 uart0: serial@ffe7014000 { 281 compatible = "snps,dw-apb-uart"; 282 reg = <0xff 0xe7014000 0x0 0x100>; 283 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>; 285 clock-names = "baudclk", "apb_pclk"; 286 reg-shift = <2>; 287 reg-io-width = <4>; 288 status = "disabled"; 289 }; 290 291 gmac1: ethernet@ffe7060000 { 292 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; 293 reg = <0xff 0xe7060000 0x0 0x2000>, <0xff 0xec004000 0x0 0x1000>; 294 reg-names = "dwmac", "apb"; 295 interrupts = <67 IRQ_TYPE_LEVEL_HIGH>; 296 interrupt-names = "macirq"; 297 clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC1>; 298 clock-names = "stmmaceth", "pclk"; 299 snps,pbl = <32>; 300 snps,fixed-burst; 301 snps,multicast-filter-bins = <64>; 302 snps,perfect-filter-entries = <32>; 303 snps,axi-config = <&stmmac_axi_config>; 304 status = "disabled"; 305 306 mdio1: mdio { 307 compatible = "snps,dwmac-mdio"; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 }; 311 }; 312 313 gmac0: ethernet@ffe7070000 { 314 compatible = "thead,th1520-gmac", "snps,dwmac-3.70a"; 315 reg = <0xff 0xe7070000 0x0 0x2000>, <0xff 0xec003000 0x0 0x1000>; 316 reg-names = "dwmac", "apb"; 317 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; 318 interrupt-names = "macirq"; 319 clocks = <&clk CLK_GMAC_AXI>, <&clk CLK_GMAC0>; 320 clock-names = "stmmaceth", "pclk"; 321 snps,pbl = <32>; 322 snps,fixed-burst; 323 snps,multicast-filter-bins = <64>; 324 snps,perfect-filter-entries = <32>; 325 snps,axi-config = <&stmmac_axi_config>; 326 status = "disabled"; 327 328 mdio0: mdio { 329 compatible = "snps,dwmac-mdio"; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 }; 333 }; 334 335 emmc: mmc@ffe7080000 { 336 compatible = "thead,th1520-dwcmshc"; 337 reg = <0xff 0xe7080000 0x0 0x10000>; 338 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&clk CLK_EMMC_SDIO>; 340 clock-names = "core"; 341 status = "disabled"; 342 }; 343 344 sdio0: mmc@ffe7090000 { 345 compatible = "thead,th1520-dwcmshc"; 346 reg = <0xff 0xe7090000 0x0 0x10000>; 347 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&clk CLK_EMMC_SDIO>; 349 clock-names = "core"; 350 status = "disabled"; 351 }; 352 353 sdio1: mmc@ffe70a0000 { 354 compatible = "thead,th1520-dwcmshc"; 355 reg = <0xff 0xe70a0000 0x0 0x10000>; 356 interrupts = <71 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&clk CLK_EMMC_SDIO>; 358 clock-names = "core"; 359 status = "disabled"; 360 }; 361 362 uart1: serial@ffe7f00000 { 363 compatible = "snps,dw-apb-uart"; 364 reg = <0xff 0xe7f00000 0x0 0x100>; 365 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>; 367 clock-names = "baudclk", "apb_pclk"; 368 reg-shift = <2>; 369 reg-io-width = <4>; 370 status = "disabled"; 371 }; 372 373 uart3: serial@ffe7f04000 { 374 compatible = "snps,dw-apb-uart"; 375 reg = <0xff 0xe7f04000 0x0 0x100>; 376 interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>; 378 clock-names = "baudclk", "apb_pclk"; 379 reg-shift = <2>; 380 reg-io-width = <4>; 381 status = "disabled"; 382 }; 383 384 gpio@ffe7f34000 { 385 compatible = "snps,dw-apb-gpio"; 386 reg = <0xff 0xe7f34000 0x0 0x1000>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 clocks = <&clk CLK_GPIO2>; 390 clock-names = "bus"; 391 392 gpio2: gpio-controller@0 { 393 compatible = "snps,dw-apb-gpio-port"; 394 gpio-controller; 395 #gpio-cells = <2>; 396 ngpios = <32>; 397 gpio-ranges = <&padctrl0_apsys 0 0 32>; 398 reg = <0>; 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 402 }; 403 }; 404 405 gpio@ffe7f38000 { 406 compatible = "snps,dw-apb-gpio"; 407 reg = <0xff 0xe7f38000 0x0 0x1000>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 clocks = <&clk CLK_GPIO3>; 411 clock-names = "bus"; 412 413 gpio3: gpio-controller@0 { 414 compatible = "snps,dw-apb-gpio-port"; 415 gpio-controller; 416 #gpio-cells = <2>; 417 ngpios = <23>; 418 gpio-ranges = <&padctrl0_apsys 0 32 23>; 419 reg = <0>; 420 interrupt-controller; 421 #interrupt-cells = <2>; 422 interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; 423 }; 424 }; 425 426 padctrl1_apsys: pinctrl@ffe7f3c000 { 427 compatible = "thead,th1520-pinctrl"; 428 reg = <0xff 0xe7f3c000 0x0 0x1000>; 429 clocks = <&clk CLK_PADCTRL1>; 430 thead,pad-group = <2>; 431 }; 432 433 gpio@ffec005000 { 434 compatible = "snps,dw-apb-gpio"; 435 reg = <0xff 0xec005000 0x0 0x1000>; 436 #address-cells = <1>; 437 #size-cells = <0>; 438 clocks = <&clk CLK_GPIO0>; 439 clock-names = "bus"; 440 441 gpio0: gpio-controller@0 { 442 compatible = "snps,dw-apb-gpio-port"; 443 gpio-controller; 444 #gpio-cells = <2>; 445 ngpios = <32>; 446 gpio-ranges = <&padctrl1_apsys 0 0 32>; 447 reg = <0>; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; 451 }; 452 }; 453 454 gpio@ffec006000 { 455 compatible = "snps,dw-apb-gpio"; 456 reg = <0xff 0xec006000 0x0 0x1000>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 clocks = <&clk CLK_GPIO1>; 460 clock-names = "bus"; 461 462 gpio1: gpio-controller@0 { 463 compatible = "snps,dw-apb-gpio-port"; 464 gpio-controller; 465 #gpio-cells = <2>; 466 ngpios = <31>; 467 gpio-ranges = <&padctrl1_apsys 0 32 31>; 468 reg = <0>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; 472 }; 473 }; 474 475 padctrl0_apsys: pinctrl@ffec007000 { 476 compatible = "thead,th1520-pinctrl"; 477 reg = <0xff 0xec007000 0x0 0x1000>; 478 clocks = <&clk CLK_PADCTRL0>; 479 thead,pad-group = <3>; 480 }; 481 482 uart2: serial@ffec010000 { 483 compatible = "snps,dw-apb-uart"; 484 reg = <0xff 0xec010000 0x0 0x4000>; 485 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>; 487 clock-names = "baudclk", "apb_pclk"; 488 reg-shift = <2>; 489 reg-io-width = <4>; 490 status = "disabled"; 491 }; 492 493 clk: clock-controller@ffef010000 { 494 compatible = "thead,th1520-clk-ap"; 495 reg = <0xff 0xef010000 0x0 0x1000>; 496 clocks = <&osc>; 497 #clock-cells = <1>; 498 }; 499 500 rst: reset-controller@ffef528000 { 501 compatible = "thead,th1520-reset"; 502 reg = <0xff 0xef528000 0x0 0x4f>; 503 #reset-cells = <1>; 504 }; 505 506 clk_vo: clock-controller@ffef528050 { 507 compatible = "thead,th1520-clk-vo"; 508 reg = <0xff 0xef528050 0x0 0xfb0>; 509 clocks = <&clk CLK_VIDEO_PLL>; 510 #clock-cells = <1>; 511 }; 512 513 dmac0: dma-controller@ffefc00000 { 514 compatible = "snps,axi-dma-1.01a"; 515 reg = <0xff 0xefc00000 0x0 0x1000>; 516 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&clk CLK_PERI_APB_PCLK>, <&clk CLK_PERI_APB_PCLK>; 518 clock-names = "core-clk", "cfgr-clk"; 519 #dma-cells = <1>; 520 dma-channels = <4>; 521 snps,block-size = <65536 65536 65536 65536>; 522 snps,priority = <0 1 2 3>; 523 snps,dma-masters = <1>; 524 snps,data-width = <4>; 525 snps,axi-max-burst-len = <16>; 526 status = "disabled"; 527 }; 528 529 timer0: timer@ffefc32000 { 530 compatible = "snps,dw-apb-timer"; 531 reg = <0xff 0xefc32000 0x0 0x14>; 532 clocks = <&clk CLK_PERI_APB_PCLK>; 533 clock-names = "timer"; 534 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 535 status = "disabled"; 536 }; 537 538 timer1: timer@ffefc32014 { 539 compatible = "snps,dw-apb-timer"; 540 reg = <0xff 0xefc32014 0x0 0x14>; 541 clocks = <&clk CLK_PERI_APB_PCLK>; 542 clock-names = "timer"; 543 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 544 status = "disabled"; 545 }; 546 547 timer2: timer@ffefc32028 { 548 compatible = "snps,dw-apb-timer"; 549 reg = <0xff 0xefc32028 0x0 0x14>; 550 clocks = <&clk CLK_PERI_APB_PCLK>; 551 clock-names = "timer"; 552 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 553 status = "disabled"; 554 }; 555 556 timer3: timer@ffefc3203c { 557 compatible = "snps,dw-apb-timer"; 558 reg = <0xff 0xefc3203c 0x0 0x14>; 559 clocks = <&clk CLK_PERI_APB_PCLK>; 560 clock-names = "timer"; 561 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 562 status = "disabled"; 563 }; 564 565 uart4: serial@fff7f08000 { 566 compatible = "snps,dw-apb-uart"; 567 reg = <0xff 0xf7f08000 0x0 0x4000>; 568 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 569 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>; 570 clock-names = "baudclk", "apb_pclk"; 571 reg-shift = <2>; 572 reg-io-width = <4>; 573 status = "disabled"; 574 }; 575 576 uart5: serial@fff7f0c000 { 577 compatible = "snps,dw-apb-uart"; 578 reg = <0xff 0xf7f0c000 0x0 0x4000>; 579 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>; 581 clock-names = "baudclk", "apb_pclk"; 582 reg-shift = <2>; 583 reg-io-width = <4>; 584 status = "disabled"; 585 }; 586 587 timer4: timer@ffffc33000 { 588 compatible = "snps,dw-apb-timer"; 589 reg = <0xff 0xffc33000 0x0 0x14>; 590 clocks = <&clk CLK_PERI_APB_PCLK>; 591 clock-names = "timer"; 592 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 593 status = "disabled"; 594 }; 595 596 timer5: timer@ffffc33014 { 597 compatible = "snps,dw-apb-timer"; 598 reg = <0xff 0xffc33014 0x0 0x14>; 599 clocks = <&clk CLK_PERI_APB_PCLK>; 600 clock-names = "timer"; 601 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 602 status = "disabled"; 603 }; 604 605 timer6: timer@ffffc33028 { 606 compatible = "snps,dw-apb-timer"; 607 reg = <0xff 0xffc33028 0x0 0x14>; 608 clocks = <&clk CLK_PERI_APB_PCLK>; 609 clock-names = "timer"; 610 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 611 status = "disabled"; 612 }; 613 614 timer7: timer@ffffc3303c { 615 compatible = "snps,dw-apb-timer"; 616 reg = <0xff 0xffc3303c 0x0 0x14>; 617 clocks = <&clk CLK_PERI_APB_PCLK>; 618 clock-names = "timer"; 619 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 620 status = "disabled"; 621 }; 622 623 mbox_910t: mailbox@ffffc38000 { 624 compatible = "thead,th1520-mbox"; 625 reg = <0xff 0xffc38000 0x0 0x6000>, 626 <0xff 0xffc40000 0x0 0x6000>, 627 <0xff 0xffc4c000 0x0 0x2000>, 628 <0xff 0xffc54000 0x0 0x2000>; 629 reg-names = "local", "remote-icu0", "remote-icu1", "remote-icu2"; 630 clocks = <&clk CLK_MBOX0>, <&clk CLK_MBOX1>, <&clk CLK_MBOX2>, 631 <&clk CLK_MBOX3>; 632 clock-names = "clk-local", "clk-remote-icu0", "clk-remote-icu1", 633 "clk-remote-icu2"; 634 interrupt-parent = <&plic>; 635 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 636 #mbox-cells = <1>; 637 }; 638 639 gpio@fffff41000 { 640 compatible = "snps,dw-apb-gpio"; 641 reg = <0xff 0xfff41000 0x0 0x1000>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 645 aogpio: gpio-controller@0 { 646 compatible = "snps,dw-apb-gpio-port"; 647 gpio-controller; 648 #gpio-cells = <2>; 649 ngpios = <16>; 650 gpio-ranges = <&padctrl_aosys 0 9 16>; 651 reg = <0>; 652 interrupt-controller; 653 #interrupt-cells = <2>; 654 interrupts = <76 IRQ_TYPE_LEVEL_HIGH>; 655 }; 656 }; 657 658 padctrl_aosys: pinctrl@fffff4a000 { 659 compatible = "thead,th1520-pinctrl"; 660 reg = <0xff 0xfff4a000 0x0 0x2000>; 661 clocks = <&aonsys_clk>; 662 thead,pad-group = <1>; 663 }; 664 665 gpio@fffff52000 { 666 compatible = "snps,dw-apb-gpio"; 667 reg = <0xff 0xfff52000 0x0 0x1000>; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 671 gpio4: gpio-controller@0 { 672 compatible = "snps,dw-apb-gpio-port"; 673 gpio-controller; 674 #gpio-cells = <2>; 675 ngpios = <23>; 676 gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>; 677 reg = <0>; 678 interrupt-controller; 679 #interrupt-cells = <2>; 680 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; 681 }; 682 }; 683 }; 684}; 685