1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra30-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra30-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/soc/tegra-pmc.h> 8#include <dt-bindings/thermal/thermal.h> 9 10#include "tegra30-peripherals-opp.dtsi" 11 12/ { 13 compatible = "nvidia,tegra30"; 14 interrupt-parent = <&lic>; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 memory@80000000 { 19 device_type = "memory"; 20 reg = <0x80000000 0x0>; 21 }; 22 23 pcie@3000 { 24 compatible = "nvidia,tegra30-pcie"; 25 device_type = "pci"; 26 reg = <0x00003000 0x00000800>, /* PADS registers */ 27 <0x00003800 0x00000200>, /* AFI registers */ 28 <0x10000000 0x10000000>; /* configuration space */ 29 reg-names = "pads", "afi", "cs"; 30 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 31 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 32 interrupt-names = "intr", "msi"; 33 34 #interrupt-cells = <1>; 35 interrupt-map-mask = <0 0 0 0>; 36 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 37 38 bus-range = <0x00 0xff>; 39 #address-cells = <3>; 40 #size-cells = <2>; 41 42 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */ 43 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */ 44 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */ 45 <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */ 46 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */ 47 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ 48 49 clocks = <&tegra_car TEGRA30_CLK_PCIE>, 50 <&tegra_car TEGRA30_CLK_AFI>, 51 <&tegra_car TEGRA30_CLK_PLL_E>, 52 <&tegra_car TEGRA30_CLK_CML0>; 53 clock-names = "pex", "afi", "pll_e", "cml"; 54 resets = <&tegra_car 70>, 55 <&tegra_car 72>, 56 <&tegra_car 74>; 57 reset-names = "pex", "afi", "pcie_x"; 58 power-domains = <&pd_core>; 59 operating-points-v2 = <&pcie_dvfs_opp_table>; 60 status = "disabled"; 61 62 pci@1,0 { 63 device_type = "pci"; 64 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; 65 reg = <0x000800 0 0 0 0>; 66 bus-range = <0x00 0xff>; 67 status = "disabled"; 68 69 #address-cells = <3>; 70 #size-cells = <2>; 71 ranges; 72 73 nvidia,num-lanes = <2>; 74 }; 75 76 pci@2,0 { 77 device_type = "pci"; 78 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; 79 reg = <0x001000 0 0 0 0>; 80 bus-range = <0x00 0xff>; 81 status = "disabled"; 82 83 #address-cells = <3>; 84 #size-cells = <2>; 85 ranges; 86 87 nvidia,num-lanes = <2>; 88 }; 89 90 pci@3,0 { 91 device_type = "pci"; 92 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; 93 reg = <0x001800 0 0 0 0>; 94 bus-range = <0x00 0xff>; 95 status = "disabled"; 96 97 #address-cells = <3>; 98 #size-cells = <2>; 99 ranges; 100 101 nvidia,num-lanes = <2>; 102 }; 103 }; 104 105 sram@40000000 { 106 compatible = "mmio-sram"; 107 reg = <0x40000000 0x40000>; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges = <0 0x40000000 0x40000>; 111 112 vde_pool: sram@400 { 113 reg = <0x400 0x3fc00>; 114 pool; 115 }; 116 }; 117 118 host1x@50000000 { 119 compatible = "nvidia,tegra30-host1x"; 120 reg = <0x50000000 0x00024000>; 121 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 122 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 123 interrupt-names = "syncpt", "host1x"; 124 clocks = <&tegra_car TEGRA30_CLK_HOST1X>; 125 clock-names = "host1x"; 126 resets = <&tegra_car 28>, <&mc TEGRA30_MC_RESET_HC>; 127 reset-names = "host1x", "mc"; 128 iommus = <&mc TEGRA_SWGROUP_HC>; 129 power-domains = <&pd_heg>; 130 operating-points-v2 = <&host1x_dvfs_opp_table>; 131 132 #address-cells = <1>; 133 #size-cells = <1>; 134 135 ranges = <0x54000000 0x54000000 0x04000000>; 136 137 mpe@54040000 { 138 compatible = "nvidia,tegra30-mpe"; 139 reg = <0x54040000 0x00040000>; 140 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&tegra_car TEGRA30_CLK_MPE>; 142 resets = <&tegra_car 60>; 143 reset-names = "mpe"; 144 power-domains = <&pd_mpe>; 145 operating-points-v2 = <&mpe_dvfs_opp_table>; 146 147 iommus = <&mc TEGRA_SWGROUP_MPE>; 148 149 status = "disabled"; 150 }; 151 152 vi@54080000 { 153 compatible = "nvidia,tegra30-vi", "nvidia,tegra20-vi"; 154 reg = <0x54080000 0x00000800>; 155 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&tegra_car TEGRA30_CLK_VI>; 157 resets = <&tegra_car 20>; 158 reset-names = "vi"; 159 power-domains = <&pd_venc>; 160 operating-points-v2 = <&vi_dvfs_opp_table>; 161 162 iommus = <&mc TEGRA_SWGROUP_VI>; 163 164 status = "disabled"; 165 166 #address-cells = <1>; 167 #size-cells = <1>; 168 169 ranges = <0x0 0x54080000 0x4000>; 170 171 csi: csi@800 { 172 compatible = "nvidia,tegra30-csi"; 173 reg = <0x800 0x200>; 174 clocks = <&tegra_car TEGRA30_CLK_CSI>, 175 <&tegra_car TEGRA30_CLK_CSIA_PAD>, 176 <&tegra_car TEGRA30_CLK_CSIB_PAD>; 177 clock-names = "csi", "csia-pad", "csib-pad"; 178 power-domains = <&pd_venc>; 179 #nvidia,mipi-calibrate-cells = <1>; 180 status = "disabled"; 181 182 #address-cells = <1>; 183 #size-cells = <0>; 184 }; 185 }; 186 187 epp@540c0000 { 188 compatible = "nvidia,tegra30-epp"; 189 reg = <0x540c0000 0x00040000>; 190 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&tegra_car TEGRA30_CLK_EPP>; 192 resets = <&tegra_car 19>; 193 reset-names = "epp"; 194 power-domains = <&pd_heg>; 195 operating-points-v2 = <&epp_dvfs_opp_table>; 196 197 iommus = <&mc TEGRA_SWGROUP_EPP>; 198 199 status = "disabled"; 200 }; 201 202 isp@54100000 { 203 compatible = "nvidia,tegra30-isp"; 204 reg = <0x54100000 0x00040000>; 205 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&tegra_car TEGRA30_CLK_ISP>; 207 resets = <&tegra_car 23>; 208 reset-names = "isp"; 209 power-domains = <&pd_venc>; 210 211 iommus = <&mc TEGRA_SWGROUP_ISP>; 212 213 status = "disabled"; 214 }; 215 216 gr2d@54140000 { 217 compatible = "nvidia,tegra30-gr2d"; 218 reg = <0x54140000 0x00040000>; 219 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 220 clocks = <&tegra_car TEGRA30_CLK_GR2D>; 221 resets = <&tegra_car 21>, <&mc TEGRA30_MC_RESET_2D>; 222 reset-names = "2d", "mc"; 223 power-domains = <&pd_heg>; 224 operating-points-v2 = <&gr2d_dvfs_opp_table>; 225 226 iommus = <&mc TEGRA_SWGROUP_G2>; 227 }; 228 229 gr3d@54180000 { 230 compatible = "nvidia,tegra30-gr3d"; 231 reg = <0x54180000 0x00040000>; 232 clocks = <&tegra_car TEGRA30_CLK_GR3D>, 233 <&tegra_car TEGRA30_CLK_GR3D2>; 234 clock-names = "3d", "3d2"; 235 resets = <&tegra_car 24>, 236 <&tegra_car 98>, 237 <&mc TEGRA30_MC_RESET_3D>, 238 <&mc TEGRA30_MC_RESET_3D2>; 239 reset-names = "3d", "3d2", "mc", "mc2"; 240 power-domains = <&pd_3d0>, <&pd_3d1>; 241 power-domain-names = "3d0", "3d1"; 242 operating-points-v2 = <&gr3d_dvfs_opp_table>; 243 244 iommus = <&mc TEGRA_SWGROUP_NV>, 245 <&mc TEGRA_SWGROUP_NV2>; 246 }; 247 248 dc@54200000 { 249 compatible = "nvidia,tegra30-dc"; 250 reg = <0x54200000 0x00040000>; 251 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&tegra_car TEGRA30_CLK_DISP1>, 253 <&tegra_car TEGRA30_CLK_PLL_P>; 254 clock-names = "dc", "parent"; 255 resets = <&tegra_car 27>; 256 reset-names = "dc"; 257 power-domains = <&pd_core>; 258 operating-points-v2 = <&disp1_dvfs_opp_table>; 259 260 iommus = <&mc TEGRA_SWGROUP_DC>; 261 262 nvidia,head = <0>; 263 264 interconnects = <&mc TEGRA30_MC_DISPLAY0A &emc>, 265 <&mc TEGRA30_MC_DISPLAY0B &emc>, 266 <&mc TEGRA30_MC_DISPLAY1B &emc>, 267 <&mc TEGRA30_MC_DISPLAY0C &emc>, 268 <&mc TEGRA30_MC_DISPLAYHC &emc>; 269 interconnect-names = "wina", 270 "winb", 271 "winb-vfilter", 272 "winc", 273 "cursor"; 274 275 rgb { 276 status = "disabled"; 277 }; 278 }; 279 280 dc@54240000 { 281 compatible = "nvidia,tegra30-dc"; 282 reg = <0x54240000 0x00040000>; 283 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 284 clocks = <&tegra_car TEGRA30_CLK_DISP2>, 285 <&tegra_car TEGRA30_CLK_PLL_P>; 286 clock-names = "dc", "parent"; 287 resets = <&tegra_car 26>; 288 reset-names = "dc"; 289 power-domains = <&pd_core>; 290 operating-points-v2 = <&disp2_dvfs_opp_table>; 291 292 iommus = <&mc TEGRA_SWGROUP_DCB>; 293 294 nvidia,head = <1>; 295 296 interconnects = <&mc TEGRA30_MC_DISPLAY0AB &emc>, 297 <&mc TEGRA30_MC_DISPLAY0BB &emc>, 298 <&mc TEGRA30_MC_DISPLAY1BB &emc>, 299 <&mc TEGRA30_MC_DISPLAY0CB &emc>, 300 <&mc TEGRA30_MC_DISPLAYHCB &emc>; 301 interconnect-names = "wina", 302 "winb", 303 "winb-vfilter", 304 "winc", 305 "cursor"; 306 307 rgb { 308 status = "disabled"; 309 }; 310 }; 311 312 hdmi@54280000 { 313 compatible = "nvidia,tegra30-hdmi"; 314 reg = <0x54280000 0x00040000>; 315 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&tegra_car TEGRA30_CLK_HDMI>, 317 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; 318 clock-names = "hdmi", "parent"; 319 resets = <&tegra_car 51>; 320 reset-names = "hdmi"; 321 power-domains = <&pd_core>; 322 operating-points-v2 = <&hdmi_dvfs_opp_table>; 323 status = "disabled"; 324 }; 325 326 tvo@542c0000 { 327 compatible = "nvidia,tegra30-tvo"; 328 reg = <0x542c0000 0x00040000>; 329 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&tegra_car TEGRA30_CLK_TVO>; 331 power-domains = <&pd_core>; 332 operating-points-v2 = <&tvo_dvfs_opp_table>; 333 status = "disabled"; 334 }; 335 336 dsi@54300000 { 337 compatible = "nvidia,tegra30-dsi"; 338 reg = <0x54300000 0x00040000>; 339 clocks = <&tegra_car TEGRA30_CLK_DSIA>, 340 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; 341 clock-names = "dsi", "parent"; 342 resets = <&tegra_car 48>; 343 reset-names = "dsi"; 344 power-domains = <&pd_core>; 345 operating-points-v2 = <&dsia_dvfs_opp_table>; 346 status = "disabled"; 347 }; 348 349 dsi@54400000 { 350 compatible = "nvidia,tegra30-dsi"; 351 reg = <0x54400000 0x00040000>; 352 clocks = <&tegra_car TEGRA30_CLK_DSIB>, 353 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>; 354 clock-names = "dsi", "parent"; 355 resets = <&tegra_car 84>; 356 reset-names = "dsi"; 357 power-domains = <&pd_core>; 358 operating-points-v2 = <&dsib_dvfs_opp_table>; 359 status = "disabled"; 360 }; 361 }; 362 363 timer@50040600 { 364 compatible = "arm,cortex-a9-twd-timer"; 365 reg = <0x50040600 0x20>; 366 interrupt-parent = <&intc>; 367 interrupts = <GIC_PPI 13 368 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 369 clocks = <&tegra_car TEGRA30_CLK_TWD>; 370 }; 371 372 intc: interrupt-controller@50041000 { 373 compatible = "arm,cortex-a9-gic"; 374 reg = <0x50041000 0x1000>, 375 <0x50040100 0x0100>; 376 interrupt-controller; 377 #interrupt-cells = <3>; 378 interrupt-parent = <&intc>; 379 }; 380 381 cache-controller@50043000 { 382 compatible = "arm,pl310-cache"; 383 reg = <0x50043000 0x1000>; 384 arm,data-latency = <6 6 2>; 385 arm,tag-latency = <5 5 2>; 386 cache-unified; 387 cache-level = <2>; 388 }; 389 390 lic: interrupt-controller@60004000 { 391 compatible = "nvidia,tegra30-ictlr"; 392 reg = <0x60004000 0x100>, 393 <0x60004100 0x50>, 394 <0x60004200 0x50>, 395 <0x60004300 0x50>, 396 <0x60004400 0x50>; 397 interrupt-controller; 398 #interrupt-cells = <3>; 399 interrupt-parent = <&intc>; 400 }; 401 402 timer@60005000 { 403 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 404 reg = <0x60005000 0x400>; 405 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&tegra_car TEGRA30_CLK_TIMER>; 412 }; 413 414 tegra_car: clock@60006000 { 415 compatible = "nvidia,tegra30-car"; 416 reg = <0x60006000 0x1000>; 417 #clock-cells = <1>; 418 #reset-cells = <1>; 419 420 pll-c { 421 compatible = "nvidia,tegra30-pllc"; 422 clocks = <&tegra_car TEGRA30_CLK_PLL_C>; 423 power-domains = <&pd_core>; 424 operating-points-v2 = <&pll_c_dvfs_opp_table>; 425 }; 426 427 pll-e { 428 compatible = "nvidia,tegra30-plle"; 429 clocks = <&tegra_car TEGRA30_CLK_PLL_E>; 430 power-domains = <&pd_core>; 431 operating-points-v2 = <&pll_e_dvfs_opp_table>; 432 }; 433 434 pll-m { 435 compatible = "nvidia,tegra30-pllm"; 436 clocks = <&tegra_car TEGRA30_CLK_PLL_M>; 437 power-domains = <&pd_core>; 438 operating-points-v2 = <&pll_m_dvfs_opp_table>; 439 }; 440 441 sclk { 442 compatible = "nvidia,tegra30-sclk"; 443 clocks = <&tegra_car TEGRA30_CLK_SCLK>; 444 power-domains = <&pd_core>; 445 operating-points-v2 = <&sclk_dvfs_opp_table>; 446 }; 447 }; 448 449 flow-controller@60007000 { 450 compatible = "nvidia,tegra30-flowctrl"; 451 reg = <0x60007000 0x1000>; 452 }; 453 454 apbdma: dma-controller@6000a000 { 455 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 456 reg = <0x6000a000 0x1400>; 457 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&tegra_car TEGRA30_CLK_APBDMA>; 490 resets = <&tegra_car 34>; 491 reset-names = "dma"; 492 #dma-cells = <1>; 493 }; 494 495 ahb: ahb@6000c000 { 496 compatible = "nvidia,tegra30-ahb"; 497 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */ 498 }; 499 500 actmon: actmon@6000c800 { 501 compatible = "nvidia,tegra30-actmon"; 502 reg = <0x6000c800 0x400>; 503 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&tegra_car TEGRA30_CLK_ACTMON>, 505 <&tegra_car TEGRA30_CLK_EMC>; 506 clock-names = "actmon", "emc"; 507 resets = <&tegra_car TEGRA30_CLK_ACTMON>; 508 reset-names = "actmon"; 509 operating-points-v2 = <&emc_bw_dfs_opp_table>; 510 interconnects = <&mc TEGRA30_MC_MPCORER &emc>; 511 interconnect-names = "cpu-read"; 512 #cooling-cells = <2>; 513 }; 514 515 gpio: gpio@6000d000 { 516 compatible = "nvidia,tegra30-gpio"; 517 reg = <0x6000d000 0x1000>; 518 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 526 #gpio-cells = <2>; 527 gpio-controller; 528 #interrupt-cells = <2>; 529 interrupt-controller; 530 gpio-ranges = <&pinmux 0 0 248>; 531 }; 532 533 vde@6001a000 { 534 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde"; 535 reg = <0x6001a000 0x1000>, /* Syntax Engine */ 536 <0x6001b000 0x1000>, /* Video Bitstream Engine */ 537 <0x6001c000 0x100>, /* Macroblock Engine */ 538 <0x6001c200 0x100>, /* Post-processing Engine */ 539 <0x6001c400 0x100>, /* Motion Compensation Engine */ 540 <0x6001c600 0x100>, /* Transform Engine */ 541 <0x6001c800 0x100>, /* Pixel prediction block */ 542 <0x6001ca00 0x100>, /* Video DMA */ 543 <0x6001d800 0x400>; /* Video frame controls */ 544 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 545 "tfe", "ppb", "vdma", "frameid"; 546 iram = <&vde_pool>; /* IRAM region */ 547 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 548 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 549 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 550 interrupt-names = "sync-token", "bsev", "sxe"; 551 clocks = <&tegra_car TEGRA30_CLK_VDE>; 552 reset-names = "vde", "mc"; 553 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; 554 iommus = <&mc TEGRA_SWGROUP_VDE>; 555 power-domains = <&pd_vde>; 556 operating-points-v2 = <&vde_dvfs_opp_table>; 557 }; 558 559 apbmisc@70000800 { 560 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; 561 reg = <0x70000800 0x64>, /* Chip revision */ 562 <0x70000008 0x04>; /* Strapping options */ 563 }; 564 565 pinmux: pinmux@70000868 { 566 compatible = "nvidia,tegra30-pinmux"; 567 reg = <0x70000868 0x0d4>, /* Pad control registers */ 568 <0x70003000 0x3e4>; /* Mux registers */ 569 }; 570 571 /* 572 * There are two serial driver i.e. 8250 based simple serial 573 * driver and APB DMA based serial driver for higher baudrate 574 * and performace. To enable the 8250 based driver, the compatible 575 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable 576 * the APB DMA based serial driver, the compatible is 577 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". 578 */ 579 uarta: serial@70006000 { 580 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 581 reg = <0x70006000 0x40>; 582 reg-shift = <2>; 583 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&tegra_car TEGRA30_CLK_UARTA>; 585 resets = <&tegra_car 6>; 586 dmas = <&apbdma 8>, <&apbdma 8>; 587 dma-names = "rx", "tx"; 588 status = "disabled"; 589 }; 590 591 uartb: serial@70006040 { 592 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 593 reg = <0x70006040 0x40>; 594 reg-shift = <2>; 595 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&tegra_car TEGRA30_CLK_UARTB>; 597 resets = <&tegra_car 7>; 598 dmas = <&apbdma 9>, <&apbdma 9>; 599 dma-names = "rx", "tx"; 600 status = "disabled"; 601 }; 602 603 uartc: serial@70006200 { 604 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 605 reg = <0x70006200 0x100>; 606 reg-shift = <2>; 607 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&tegra_car TEGRA30_CLK_UARTC>; 609 resets = <&tegra_car 55>; 610 dmas = <&apbdma 10>, <&apbdma 10>; 611 dma-names = "rx", "tx"; 612 status = "disabled"; 613 }; 614 615 uartd: serial@70006300 { 616 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 617 reg = <0x70006300 0x100>; 618 reg-shift = <2>; 619 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&tegra_car TEGRA30_CLK_UARTD>; 621 resets = <&tegra_car 65>; 622 dmas = <&apbdma 19>, <&apbdma 19>; 623 dma-names = "rx", "tx"; 624 status = "disabled"; 625 }; 626 627 uarte: serial@70006400 { 628 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; 629 reg = <0x70006400 0x100>; 630 reg-shift = <2>; 631 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&tegra_car TEGRA30_CLK_UARTE>; 633 resets = <&tegra_car 66>; 634 dmas = <&apbdma 20>, <&apbdma 20>; 635 dma-names = "rx", "tx"; 636 status = "disabled"; 637 }; 638 639 gmi@70009000 { 640 compatible = "nvidia,tegra30-gmi"; 641 reg = <0x70009000 0x1000>; 642 #address-cells = <2>; 643 #size-cells = <1>; 644 ranges = <0 0 0x48000000 0x7ffffff>; 645 clocks = <&tegra_car TEGRA30_CLK_NOR>; 646 clock-names = "gmi"; 647 resets = <&tegra_car 42>; 648 reset-names = "gmi"; 649 power-domains = <&pd_core>; 650 operating-points-v2 = <&nor_dvfs_opp_table>; 651 status = "disabled"; 652 }; 653 654 pwm: pwm@7000a000 { 655 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 656 reg = <0x7000a000 0x100>; 657 #pwm-cells = <2>; 658 clocks = <&tegra_car TEGRA30_CLK_PWM>; 659 resets = <&tegra_car 17>; 660 reset-names = "pwm"; 661 power-domains = <&pd_core>; 662 operating-points-v2 = <&pwm_dvfs_opp_table>; 663 status = "disabled"; 664 }; 665 666 i2c@7000c000 { 667 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 668 reg = <0x7000c000 0x100>; 669 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 clocks = <&tegra_car TEGRA30_CLK_I2C1>, 673 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 674 clock-names = "div-clk", "fast-clk"; 675 resets = <&tegra_car 12>; 676 reset-names = "i2c"; 677 dmas = <&apbdma 21>, <&apbdma 21>; 678 dma-names = "rx", "tx"; 679 status = "disabled"; 680 }; 681 682 i2c@7000c400 { 683 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 684 reg = <0x7000c400 0x100>; 685 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 clocks = <&tegra_car TEGRA30_CLK_I2C2>, 689 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 690 clock-names = "div-clk", "fast-clk"; 691 resets = <&tegra_car 54>; 692 reset-names = "i2c"; 693 dmas = <&apbdma 22>, <&apbdma 22>; 694 dma-names = "rx", "tx"; 695 status = "disabled"; 696 }; 697 698 i2c@7000c500 { 699 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 700 reg = <0x7000c500 0x100>; 701 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 702 #address-cells = <1>; 703 #size-cells = <0>; 704 clocks = <&tegra_car TEGRA30_CLK_I2C3>, 705 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 706 clock-names = "div-clk", "fast-clk"; 707 resets = <&tegra_car 67>; 708 reset-names = "i2c"; 709 dmas = <&apbdma 23>, <&apbdma 23>; 710 dma-names = "rx", "tx"; 711 status = "disabled"; 712 }; 713 714 i2c@7000c700 { 715 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 716 reg = <0x7000c700 0x100>; 717 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 clocks = <&tegra_car TEGRA30_CLK_I2C4>, 721 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 722 resets = <&tegra_car 103>; 723 reset-names = "i2c"; 724 clock-names = "div-clk", "fast-clk"; 725 dmas = <&apbdma 26>, <&apbdma 26>; 726 dma-names = "rx", "tx"; 727 status = "disabled"; 728 }; 729 730 i2c@7000d000 { 731 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; 732 reg = <0x7000d000 0x100>; 733 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 clocks = <&tegra_car TEGRA30_CLK_I2C5>, 737 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; 738 clock-names = "div-clk", "fast-clk"; 739 resets = <&tegra_car 47>; 740 reset-names = "i2c"; 741 dmas = <&apbdma 24>, <&apbdma 24>; 742 dma-names = "rx", "tx"; 743 status = "disabled"; 744 }; 745 746 spi@7000d400 { 747 compatible = "nvidia,tegra30-slink"; 748 reg = <0x7000d400 0x200>; 749 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 750 #address-cells = <1>; 751 #size-cells = <0>; 752 clocks = <&tegra_car TEGRA30_CLK_SBC1>; 753 resets = <&tegra_car 41>; 754 reset-names = "spi"; 755 dmas = <&apbdma 15>, <&apbdma 15>; 756 dma-names = "rx", "tx"; 757 power-domains = <&pd_core>; 758 operating-points-v2 = <&sbc1_dvfs_opp_table>; 759 status = "disabled"; 760 }; 761 762 spi@7000d600 { 763 compatible = "nvidia,tegra30-slink"; 764 reg = <0x7000d600 0x200>; 765 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 766 #address-cells = <1>; 767 #size-cells = <0>; 768 clocks = <&tegra_car TEGRA30_CLK_SBC2>; 769 resets = <&tegra_car 44>; 770 reset-names = "spi"; 771 dmas = <&apbdma 16>, <&apbdma 16>; 772 dma-names = "rx", "tx"; 773 power-domains = <&pd_core>; 774 operating-points-v2 = <&sbc2_dvfs_opp_table>; 775 status = "disabled"; 776 }; 777 778 spi@7000d800 { 779 compatible = "nvidia,tegra30-slink"; 780 reg = <0x7000d800 0x200>; 781 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 clocks = <&tegra_car TEGRA30_CLK_SBC3>; 785 resets = <&tegra_car 46>; 786 reset-names = "spi"; 787 dmas = <&apbdma 17>, <&apbdma 17>; 788 dma-names = "rx", "tx"; 789 power-domains = <&pd_core>; 790 operating-points-v2 = <&sbc3_dvfs_opp_table>; 791 status = "disabled"; 792 }; 793 794 spi@7000da00 { 795 compatible = "nvidia,tegra30-slink"; 796 reg = <0x7000da00 0x200>; 797 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 clocks = <&tegra_car TEGRA30_CLK_SBC4>; 801 resets = <&tegra_car 68>; 802 reset-names = "spi"; 803 dmas = <&apbdma 18>, <&apbdma 18>; 804 dma-names = "rx", "tx"; 805 power-domains = <&pd_core>; 806 operating-points-v2 = <&sbc4_dvfs_opp_table>; 807 status = "disabled"; 808 }; 809 810 spi@7000dc00 { 811 compatible = "nvidia,tegra30-slink"; 812 reg = <0x7000dc00 0x200>; 813 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 clocks = <&tegra_car TEGRA30_CLK_SBC5>; 817 resets = <&tegra_car 104>; 818 reset-names = "spi"; 819 dmas = <&apbdma 27>, <&apbdma 27>; 820 dma-names = "rx", "tx"; 821 power-domains = <&pd_core>; 822 operating-points-v2 = <&sbc5_dvfs_opp_table>; 823 status = "disabled"; 824 }; 825 826 spi@7000de00 { 827 compatible = "nvidia,tegra30-slink"; 828 reg = <0x7000de00 0x200>; 829 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 clocks = <&tegra_car TEGRA30_CLK_SBC6>; 833 resets = <&tegra_car 106>; 834 reset-names = "spi"; 835 dmas = <&apbdma 28>, <&apbdma 28>; 836 dma-names = "rx", "tx"; 837 power-domains = <&pd_core>; 838 operating-points-v2 = <&sbc6_dvfs_opp_table>; 839 status = "disabled"; 840 }; 841 842 rtc@7000e000 { 843 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; 844 reg = <0x7000e000 0x100>; 845 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&tegra_car TEGRA30_CLK_RTC>; 847 }; 848 849 kbc@7000e200 { 850 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; 851 reg = <0x7000e200 0x100>; 852 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&tegra_car TEGRA30_CLK_KBC>; 854 resets = <&tegra_car 36>; 855 reset-names = "kbc"; 856 status = "disabled"; 857 }; 858 859 tegra_pmc: pmc@7000e400 { 860 compatible = "nvidia,tegra30-pmc"; 861 reg = <0x7000e400 0x400>; 862 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; 863 clock-names = "pclk", "clk32k_in"; 864 #clock-cells = <1>; 865 866 pd_core: core-domain { 867 #power-domain-cells = <0>; 868 operating-points-v2 = <&core_opp_table>; 869 }; 870 871 powergates { 872 pd_heg: heg { 873 clocks = <&tegra_car TEGRA30_CLK_GR2D>, 874 <&tegra_car TEGRA30_CLK_EPP>, 875 <&tegra_car TEGRA30_CLK_HOST1X>; 876 resets = <&mc TEGRA30_MC_RESET_2D>, 877 <&mc TEGRA30_MC_RESET_EPP>, 878 <&mc TEGRA30_MC_RESET_HC>, 879 <&tegra_car TEGRA30_CLK_GR2D>, 880 <&tegra_car TEGRA30_CLK_EPP>, 881 <&tegra_car TEGRA30_CLK_HOST1X>; 882 power-domains = <&pd_core>; 883 #power-domain-cells = <0>; 884 }; 885 886 pd_mpe: mpe { 887 clocks = <&tegra_car TEGRA30_CLK_MPE>; 888 resets = <&mc TEGRA30_MC_RESET_MPE>, 889 <&tegra_car TEGRA30_CLK_MPE>; 890 power-domains = <&pd_core>; 891 #power-domain-cells = <0>; 892 }; 893 894 pd_3d0: td { 895 clocks = <&tegra_car TEGRA30_CLK_GR3D>; 896 resets = <&mc TEGRA30_MC_RESET_3D>, 897 <&tegra_car TEGRA30_CLK_GR3D>; 898 power-domains = <&pd_core>; 899 #power-domain-cells = <0>; 900 }; 901 902 pd_3d1: td2 { 903 clocks = <&tegra_car TEGRA30_CLK_GR3D2>; 904 resets = <&mc TEGRA30_MC_RESET_3D2>, 905 <&tegra_car TEGRA30_CLK_GR3D2>; 906 power-domains = <&pd_core>; 907 #power-domain-cells = <0>; 908 }; 909 910 pd_vde: vdec { 911 clocks = <&tegra_car TEGRA30_CLK_VDE>; 912 resets = <&mc TEGRA30_MC_RESET_VDE>, 913 <&tegra_car TEGRA30_CLK_VDE>; 914 power-domains = <&pd_core>; 915 #power-domain-cells = <0>; 916 }; 917 918 pd_venc: venc { 919 clocks = <&tegra_car TEGRA30_CLK_ISP>, 920 <&tegra_car TEGRA30_CLK_VI>, 921 <&tegra_car TEGRA30_CLK_CSI>; 922 resets = <&mc TEGRA30_MC_RESET_ISP>, 923 <&mc TEGRA30_MC_RESET_VI>, 924 <&tegra_car TEGRA30_CLK_ISP>, 925 <&tegra_car 20 /* VI */>, 926 <&tegra_car TEGRA30_CLK_CSI>; 927 power-domains = <&pd_core>; 928 #power-domain-cells = <0>; 929 }; 930 }; 931 }; 932 933 mc: memory-controller@7000f000 { 934 compatible = "nvidia,tegra30-mc"; 935 reg = <0x7000f000 0x400>; 936 clocks = <&tegra_car TEGRA30_CLK_MC>; 937 clock-names = "mc"; 938 939 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 940 941 #iommu-cells = <1>; 942 #reset-cells = <1>; 943 #interconnect-cells = <1>; 944 }; 945 946 emc: memory-controller@7000f400 { 947 compatible = "nvidia,tegra30-emc"; 948 reg = <0x7000f400 0x400>; 949 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&tegra_car TEGRA30_CLK_EMC>; 951 power-domains = <&pd_core>; 952 953 nvidia,memory-controller = <&mc>; 954 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 955 956 #interconnect-cells = <0>; 957 }; 958 959 fuse@7000f800 { 960 compatible = "nvidia,tegra30-efuse"; 961 reg = <0x7000f800 0x400>; 962 clocks = <&tegra_car TEGRA30_CLK_FUSE>; 963 clock-names = "fuse"; 964 resets = <&tegra_car 39>; 965 reset-names = "fuse"; 966 power-domains = <&pd_core>; 967 operating-points-v2 = <&fuse_burn_dvfs_opp_table>; 968 }; 969 970 tsensor: tsensor@70014000 { 971 compatible = "nvidia,tegra30-tsensor"; 972 reg = <0x70014000 0x500>; 973 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; 975 resets = <&tegra_car TEGRA30_CLK_TSENSOR>; 976 977 assigned-clocks = <&tegra_car TEGRA30_CLK_TSENSOR>; 978 assigned-clock-parents = <&tegra_car TEGRA30_CLK_CLK_M>; 979 assigned-clock-rates = <500000>; 980 981 #thermal-sensor-cells = <1>; 982 }; 983 984 hda@70030000 { 985 compatible = "nvidia,tegra30-hda"; 986 reg = <0x70030000 0x10000>; 987 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&tegra_car TEGRA30_CLK_HDA>, 989 <&tegra_car TEGRA30_CLK_HDA2HDMI>, 990 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>; 991 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 992 resets = <&tegra_car 125>, /* hda */ 993 <&tegra_car 128>, /* hda2hdmi */ 994 <&tegra_car 111>; /* hda2codec_2x */ 995 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 996 status = "disabled"; 997 }; 998 999 ahub@70080000 { 1000 compatible = "nvidia,tegra30-ahub"; 1001 reg = <0x70080000 0x200>, 1002 <0x70080200 0x100>; 1003 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, 1005 <&tegra_car TEGRA30_CLK_APBIF>; 1006 clock-names = "d_audio", "apbif"; 1007 resets = <&tegra_car 106>, /* d_audio */ 1008 <&tegra_car 107>, /* apbif */ 1009 <&tegra_car 30>, /* i2s0 */ 1010 <&tegra_car 11>, /* i2s1 */ 1011 <&tegra_car 18>, /* i2s2 */ 1012 <&tegra_car 101>, /* i2s3 */ 1013 <&tegra_car 102>, /* i2s4 */ 1014 <&tegra_car 108>, /* dam0 */ 1015 <&tegra_car 109>, /* dam1 */ 1016 <&tegra_car 110>, /* dam2 */ 1017 <&tegra_car 10>; /* spdif */ 1018 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 1019 "i2s3", "i2s4", "dam0", "dam1", "dam2", 1020 "spdif"; 1021 dmas = <&apbdma 1>, <&apbdma 1>, 1022 <&apbdma 2>, <&apbdma 2>, 1023 <&apbdma 3>, <&apbdma 3>, 1024 <&apbdma 4>, <&apbdma 4>; 1025 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 1026 "rx3", "tx3"; 1027 ranges; 1028 #address-cells = <1>; 1029 #size-cells = <1>; 1030 1031 tegra_i2s0: i2s@70080300 { 1032 compatible = "nvidia,tegra30-i2s"; 1033 reg = <0x70080300 0x100>; 1034 nvidia,ahub-cif-ids = <4 4>; 1035 clocks = <&tegra_car TEGRA30_CLK_I2S0>; 1036 resets = <&tegra_car 30>; 1037 reset-names = "i2s"; 1038 status = "disabled"; 1039 }; 1040 1041 tegra_i2s1: i2s@70080400 { 1042 compatible = "nvidia,tegra30-i2s"; 1043 reg = <0x70080400 0x100>; 1044 nvidia,ahub-cif-ids = <5 5>; 1045 clocks = <&tegra_car TEGRA30_CLK_I2S1>; 1046 resets = <&tegra_car 11>; 1047 reset-names = "i2s"; 1048 status = "disabled"; 1049 }; 1050 1051 tegra_i2s2: i2s@70080500 { 1052 compatible = "nvidia,tegra30-i2s"; 1053 reg = <0x70080500 0x100>; 1054 nvidia,ahub-cif-ids = <6 6>; 1055 clocks = <&tegra_car TEGRA30_CLK_I2S2>; 1056 resets = <&tegra_car 18>; 1057 reset-names = "i2s"; 1058 status = "disabled"; 1059 }; 1060 1061 tegra_i2s3: i2s@70080600 { 1062 compatible = "nvidia,tegra30-i2s"; 1063 reg = <0x70080600 0x100>; 1064 nvidia,ahub-cif-ids = <7 7>; 1065 clocks = <&tegra_car TEGRA30_CLK_I2S3>; 1066 resets = <&tegra_car 101>; 1067 reset-names = "i2s"; 1068 status = "disabled"; 1069 }; 1070 1071 tegra_i2s4: i2s@70080700 { 1072 compatible = "nvidia,tegra30-i2s"; 1073 reg = <0x70080700 0x100>; 1074 nvidia,ahub-cif-ids = <8 8>; 1075 clocks = <&tegra_car TEGRA30_CLK_I2S4>; 1076 resets = <&tegra_car 102>; 1077 reset-names = "i2s"; 1078 status = "disabled"; 1079 }; 1080 }; 1081 1082 mmc@78000000 { 1083 compatible = "nvidia,tegra30-sdhci"; 1084 reg = <0x78000000 0x200>; 1085 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; 1087 clock-names = "sdhci"; 1088 resets = <&tegra_car 14>; 1089 reset-names = "sdhci"; 1090 power-domains = <&pd_core>; 1091 operating-points-v2 = <&sdmmc1_dvfs_opp_table>; 1092 status = "disabled"; 1093 }; 1094 1095 mmc@78000200 { 1096 compatible = "nvidia,tegra30-sdhci"; 1097 reg = <0x78000200 0x200>; 1098 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; 1100 clock-names = "sdhci"; 1101 resets = <&tegra_car 9>; 1102 reset-names = "sdhci"; 1103 status = "disabled"; 1104 }; 1105 1106 mmc@78000400 { 1107 compatible = "nvidia,tegra30-sdhci"; 1108 reg = <0x78000400 0x200>; 1109 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; 1111 clock-names = "sdhci"; 1112 resets = <&tegra_car 69>; 1113 reset-names = "sdhci"; 1114 power-domains = <&pd_core>; 1115 operating-points-v2 = <&sdmmc3_dvfs_opp_table>; 1116 status = "disabled"; 1117 }; 1118 1119 mmc@78000600 { 1120 compatible = "nvidia,tegra30-sdhci"; 1121 reg = <0x78000600 0x200>; 1122 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; 1124 clock-names = "sdhci"; 1125 resets = <&tegra_car 15>; 1126 reset-names = "sdhci"; 1127 status = "disabled"; 1128 }; 1129 1130 usb@7d000000 { 1131 compatible = "nvidia,tegra30-ehci"; 1132 reg = <0x7d000000 0x4000>; 1133 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1134 phy_type = "utmi"; 1135 clocks = <&tegra_car TEGRA30_CLK_USBD>; 1136 resets = <&tegra_car 22>; 1137 reset-names = "usb"; 1138 nvidia,needs-double-reset; 1139 nvidia,phy = <&phy1>; 1140 power-domains = <&pd_core>; 1141 operating-points-v2 = <&usbd_dvfs_opp_table>; 1142 status = "disabled"; 1143 }; 1144 1145 phy1: usb-phy@7d000000 { 1146 compatible = "nvidia,tegra30-usb-phy"; 1147 reg = <0x7d000000 0x4000>, 1148 <0x7d000000 0x4000>; 1149 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1150 phy_type = "utmi"; 1151 clocks = <&tegra_car TEGRA30_CLK_USBD>, 1152 <&tegra_car TEGRA30_CLK_PLL_U>, 1153 <&tegra_car TEGRA30_CLK_USBD>; 1154 clock-names = "reg", "pll_u", "utmi-pads"; 1155 resets = <&tegra_car 22>, <&tegra_car 22>; 1156 reset-names = "usb", "utmi-pads"; 1157 #phy-cells = <0>; 1158 nvidia,hssync-start-delay = <9>; 1159 nvidia,idle-wait-delay = <17>; 1160 nvidia,elastic-limit = <16>; 1161 nvidia,term-range-adj = <6>; 1162 nvidia,xcvr-setup = <51>; 1163 nvidia,xcvr-setup-use-fuses; 1164 nvidia,xcvr-lsfslew = <1>; 1165 nvidia,xcvr-lsrslew = <1>; 1166 nvidia,xcvr-hsslew = <32>; 1167 nvidia,hssquelch-level = <2>; 1168 nvidia,hsdiscon-level = <5>; 1169 nvidia,has-utmi-pad-registers; 1170 nvidia,pmc = <&tegra_pmc 0>; 1171 status = "disabled"; 1172 }; 1173 1174 usb@7d004000 { 1175 compatible = "nvidia,tegra30-ehci"; 1176 reg = <0x7d004000 0x4000>; 1177 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1178 phy_type = "utmi"; 1179 clocks = <&tegra_car TEGRA30_CLK_USB2>; 1180 resets = <&tegra_car 58>; 1181 reset-names = "usb"; 1182 nvidia,phy = <&phy2>; 1183 power-domains = <&pd_core>; 1184 operating-points-v2 = <&usb2_dvfs_opp_table>; 1185 status = "disabled"; 1186 }; 1187 1188 phy2: usb-phy@7d004000 { 1189 compatible = "nvidia,tegra30-usb-phy"; 1190 reg = <0x7d004000 0x4000>, 1191 <0x7d000000 0x4000>; 1192 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1193 phy_type = "utmi"; 1194 clocks = <&tegra_car TEGRA30_CLK_USB2>, 1195 <&tegra_car TEGRA30_CLK_PLL_U>, 1196 <&tegra_car TEGRA30_CLK_USBD>; 1197 clock-names = "reg", "pll_u", "utmi-pads"; 1198 resets = <&tegra_car 58>, <&tegra_car 22>; 1199 reset-names = "usb", "utmi-pads"; 1200 #phy-cells = <0>; 1201 nvidia,hssync-start-delay = <9>; 1202 nvidia,idle-wait-delay = <17>; 1203 nvidia,elastic-limit = <16>; 1204 nvidia,term-range-adj = <6>; 1205 nvidia,xcvr-setup = <51>; 1206 nvidia,xcvr-setup-use-fuses; 1207 nvidia,xcvr-lsfslew = <2>; 1208 nvidia,xcvr-lsrslew = <2>; 1209 nvidia,xcvr-hsslew = <32>; 1210 nvidia,hssquelch-level = <2>; 1211 nvidia,hsdiscon-level = <5>; 1212 nvidia,pmc = <&tegra_pmc 2>; 1213 status = "disabled"; 1214 }; 1215 1216 usb@7d008000 { 1217 compatible = "nvidia,tegra30-ehci"; 1218 reg = <0x7d008000 0x4000>; 1219 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1220 phy_type = "utmi"; 1221 clocks = <&tegra_car TEGRA30_CLK_USB3>; 1222 resets = <&tegra_car 59>; 1223 reset-names = "usb"; 1224 nvidia,phy = <&phy3>; 1225 power-domains = <&pd_core>; 1226 operating-points-v2 = <&usb3_dvfs_opp_table>; 1227 status = "disabled"; 1228 }; 1229 1230 phy3: usb-phy@7d008000 { 1231 compatible = "nvidia,tegra30-usb-phy"; 1232 reg = <0x7d008000 0x4000>, 1233 <0x7d000000 0x4000>; 1234 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1235 phy_type = "utmi"; 1236 clocks = <&tegra_car TEGRA30_CLK_USB3>, 1237 <&tegra_car TEGRA30_CLK_PLL_U>, 1238 <&tegra_car TEGRA30_CLK_USBD>; 1239 clock-names = "reg", "pll_u", "utmi-pads"; 1240 resets = <&tegra_car 59>, <&tegra_car 22>; 1241 reset-names = "usb", "utmi-pads"; 1242 #phy-cells = <0>; 1243 nvidia,hssync-start-delay = <0>; 1244 nvidia,idle-wait-delay = <17>; 1245 nvidia,elastic-limit = <16>; 1246 nvidia,term-range-adj = <6>; 1247 nvidia,xcvr-setup = <51>; 1248 nvidia,xcvr-setup-use-fuses; 1249 nvidia,xcvr-lsfslew = <2>; 1250 nvidia,xcvr-lsrslew = <2>; 1251 nvidia,xcvr-hsslew = <32>; 1252 nvidia,hssquelch-level = <2>; 1253 nvidia,hsdiscon-level = <5>; 1254 nvidia,pmc = <&tegra_pmc 1>; 1255 status = "disabled"; 1256 }; 1257 1258 cpus { 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 1262 cpu0: cpu@0 { 1263 device_type = "cpu"; 1264 compatible = "arm,cortex-a9"; 1265 reg = <0>; 1266 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1267 #cooling-cells = <2>; 1268 }; 1269 1270 cpu1: cpu@1 { 1271 device_type = "cpu"; 1272 compatible = "arm,cortex-a9"; 1273 reg = <1>; 1274 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1275 #cooling-cells = <2>; 1276 }; 1277 1278 cpu2: cpu@2 { 1279 device_type = "cpu"; 1280 compatible = "arm,cortex-a9"; 1281 reg = <2>; 1282 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1283 #cooling-cells = <2>; 1284 }; 1285 1286 cpu3: cpu@3 { 1287 device_type = "cpu"; 1288 compatible = "arm,cortex-a9"; 1289 reg = <3>; 1290 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; 1291 #cooling-cells = <2>; 1292 }; 1293 }; 1294 1295 pmu { 1296 compatible = "arm,cortex-a9-pmu"; 1297 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1301 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 1302 }; 1303 1304 thermal-zones { 1305 tsensor0-thermal { 1306 polling-delay-passive = <1000>; /* milliseconds */ 1307 polling-delay = <5000>; /* milliseconds */ 1308 1309 thermal-sensors = <&tsensor 0>; 1310 1311 trips { 1312 level1_trip: dvfs-alert { 1313 /* throttle at 80C until temperature drops to 79.8C */ 1314 temperature = <80000>; 1315 hysteresis = <200>; 1316 type = "passive"; 1317 }; 1318 1319 level2_trip: cpu-div2-throttle { 1320 /* hardware CPU x2 freq throttle at 85C */ 1321 temperature = <85000>; 1322 hysteresis = <200>; 1323 type = "hot"; 1324 }; 1325 1326 level3_trip: soc-critical { 1327 /* hardware shut down at 90C */ 1328 temperature = <90000>; 1329 hysteresis = <2000>; 1330 type = "critical"; 1331 }; 1332 }; 1333 1334 cooling-maps { 1335 map0 { 1336 trip = <&level1_trip>; 1337 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1338 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1339 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1340 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1341 <&actmon THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1342 }; 1343 }; 1344 }; 1345 1346 tsensor1-thermal { 1347 status = "disabled"; 1348 1349 polling-delay-passive = <1000>; /* milliseconds */ 1350 polling-delay = <0>; /* milliseconds */ 1351 1352 thermal-sensors = <&tsensor 1>; 1353 1354 trips { 1355 dvfs-alert { 1356 temperature = <80000>; 1357 hysteresis = <200>; 1358 type = "passive"; 1359 }; 1360 }; 1361 }; 1362 }; 1363}; 1364