1// SPDX-License-Identifier: GPL-2.0 2 3#include <dt-bindings/clock/tegra234-clock.h> 4#include <dt-bindings/gpio/tegra234-gpio.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/mailbox/tegra186-hsp.h> 7#include <dt-bindings/memory/tegra234-mc.h> 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9#include <dt-bindings/power/tegra234-powergate.h> 10#include <dt-bindings/reset/tegra234-reset.h> 11#include <dt-bindings/thermal/tegra234-bpmp-thermal.h> 12#include <dt-bindings/pinctrl/pinctrl-tegra.h> 13 14/ { 15 compatible = "nvidia,tegra234"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &gen1_i2c; 22 i2c1 = &gen2_i2c; 23 i2c2 = &cam_i2c; 24 i2c3 = &dp_aux_ch1_i2c; 25 i2c4 = &bpmp_i2c; 26 i2c5 = &dp_aux_ch0_i2c; 27 i2c6 = &dp_aux_ch2_i2c; 28 i2c7 = &gen8_i2c; 29 i2c8 = &dp_aux_ch3_i2c; 30 }; 31 32 bus@0 { 33 compatible = "simple-bus"; 34 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 38 39 misc@100000 { 40 compatible = "nvidia,tegra234-misc"; 41 reg = <0x0 0x00100000 0x0 0xf000>, 42 <0x0 0x0010f000 0x0 0x1000>; 43 status = "okay"; 44 }; 45 46 timer@2080000 { 47 compatible = "nvidia,tegra234-timer"; 48 reg = <0x0 0x02080000 0x0 0x00121000>; 49 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 65 status = "okay"; 66 }; 67 68 gpio: gpio@2200000 { 69 compatible = "nvidia,tegra234-gpio"; 70 reg-names = "security", "gpio"; 71 reg = <0x0 0x02200000 0x0 0x10000>, 72 <0x0 0x02210000 0x0 0x10000>; 73 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 101 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 121 #interrupt-cells = <2>; 122 interrupt-controller; 123 #gpio-cells = <2>; 124 gpio-controller; 125 gpio-ranges = <&pinmux 0 0 164>; 126 }; 127 128 pinmux: pinmux@2430000 { 129 compatible = "nvidia,tegra234-pinmux"; 130 reg = <0x0 0x2430000 0x0 0x19100>; 131 132 pex_rst_c4_in_state: pinmux-pex-rst-c4-in { 133 pex_rst { 134 nvidia,pins = "pex_l4_rst_n_pl1"; 135 nvidia,function = "rsvd1"; 136 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 137 nvidia,tristate = <TEGRA_PIN_ENABLE>; 138 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 139 }; 140 }; 141 142 pex_rst_c5_in_state: pinmux-pex-rst-c5-in { 143 pex_rst { 144 nvidia,pins = "pex_l5_rst_n_paf1"; 145 nvidia,function = "rsvd1"; 146 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 147 nvidia,tristate = <TEGRA_PIN_ENABLE>; 148 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 149 }; 150 }; 151 152 pex_rst_c6_in_state: pinmux-pex-rst-c6-in { 153 pex_rst { 154 nvidia,pins = "pex_l6_rst_n_paf3"; 155 nvidia,function = "rsvd1"; 156 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 157 nvidia,tristate = <TEGRA_PIN_ENABLE>; 158 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 159 }; 160 }; 161 162 pex_rst_c7_in_state: pinmux-pex-rst-c7-in { 163 pex_rst { 164 nvidia,pins = "pex_l7_rst_n_pag1"; 165 nvidia,function = "rsvd1"; 166 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 167 nvidia,tristate = <TEGRA_PIN_ENABLE>; 168 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 169 }; 170 }; 171 172 pex_rst_c10_in_state: pinmux-pex-rst-c10-in { 173 pex_rst { 174 nvidia,pins = "pex_l10_rst_n_pag7"; 175 nvidia,function = "rsvd1"; 176 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 177 nvidia,tristate = <TEGRA_PIN_ENABLE>; 178 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 179 }; 180 }; 181 }; 182 183 gpcdma: dma-controller@2600000 { 184 compatible = "nvidia,tegra234-gpcdma", 185 "nvidia,tegra186-gpcdma"; 186 reg = <0x0 0x2600000 0x0 0x210000>; 187 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 188 reset-names = "gpcdma"; 189 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 221 #dma-cells = <1>; 222 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 223 dma-channel-mask = <0xfffffffe>; 224 dma-coherent; 225 }; 226 227 aconnect@2900000 { 228 compatible = "nvidia,tegra234-aconnect", 229 "nvidia,tegra210-aconnect"; 230 clocks = <&bpmp TEGRA234_CLK_APE>, 231 <&bpmp TEGRA234_CLK_APB2APE>; 232 clock-names = "ape", "apb2ape"; 233 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 234 status = "disabled"; 235 236 #address-cells = <2>; 237 #size-cells = <2>; 238 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>; 239 240 tegra_ahub: ahub@2900800 { 241 compatible = "nvidia,tegra234-ahub"; 242 reg = <0x0 0x02900800 0x0 0x800>; 243 clocks = <&bpmp TEGRA234_CLK_AHUB>; 244 clock-names = "ahub"; 245 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 246 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 247 assigned-clock-rates = <81600000>; 248 status = "disabled"; 249 250 #address-cells = <2>; 251 #size-cells = <2>; 252 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; 253 254 tegra_i2s1: i2s@2901000 { 255 compatible = "nvidia,tegra234-i2s", 256 "nvidia,tegra210-i2s"; 257 reg = <0x0 0x2901000 0x0 0x100>; 258 clocks = <&bpmp TEGRA234_CLK_I2S1>, 259 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 260 clock-names = "i2s", "sync_input"; 261 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 262 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 263 assigned-clock-rates = <1536000>; 264 sound-name-prefix = "I2S1"; 265 status = "disabled"; 266 267 ports { 268 #address-cells = <1>; 269 #size-cells = <0>; 270 271 port@0 { 272 reg = <0>; 273 274 i2s1_cif: endpoint { 275 remote-endpoint = <&xbar_i2s1>; 276 }; 277 }; 278 279 i2s1_port: port@1 { 280 reg = <1>; 281 282 i2s1_dap: endpoint { 283 dai-format = "i2s"; 284 /* placeholder for external codec */ 285 }; 286 }; 287 }; 288 }; 289 290 tegra_i2s2: i2s@2901100 { 291 compatible = "nvidia,tegra234-i2s", 292 "nvidia,tegra210-i2s"; 293 reg = <0x0 0x2901100 0x0 0x100>; 294 clocks = <&bpmp TEGRA234_CLK_I2S2>, 295 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 296 clock-names = "i2s", "sync_input"; 297 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 298 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 299 assigned-clock-rates = <1536000>; 300 sound-name-prefix = "I2S2"; 301 status = "disabled"; 302 303 ports { 304 #address-cells = <1>; 305 #size-cells = <0>; 306 307 port@0 { 308 reg = <0>; 309 310 i2s2_cif: endpoint { 311 remote-endpoint = <&xbar_i2s2>; 312 }; 313 }; 314 315 i2s2_port: port@1 { 316 reg = <1>; 317 318 i2s2_dap: endpoint { 319 dai-format = "i2s"; 320 /* placeholder for external codec */ 321 }; 322 }; 323 }; 324 }; 325 326 tegra_i2s3: i2s@2901200 { 327 compatible = "nvidia,tegra234-i2s", 328 "nvidia,tegra210-i2s"; 329 reg = <0x0 0x2901200 0x0 0x100>; 330 clocks = <&bpmp TEGRA234_CLK_I2S3>, 331 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 332 clock-names = "i2s", "sync_input"; 333 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 334 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 335 assigned-clock-rates = <1536000>; 336 sound-name-prefix = "I2S3"; 337 status = "disabled"; 338 339 ports { 340 #address-cells = <1>; 341 #size-cells = <0>; 342 343 port@0 { 344 reg = <0>; 345 346 i2s3_cif: endpoint { 347 remote-endpoint = <&xbar_i2s3>; 348 }; 349 }; 350 351 i2s3_port: port@1 { 352 reg = <1>; 353 354 i2s3_dap: endpoint { 355 dai-format = "i2s"; 356 /* placeholder for external codec */ 357 }; 358 }; 359 }; 360 }; 361 362 tegra_i2s4: i2s@2901300 { 363 compatible = "nvidia,tegra234-i2s", 364 "nvidia,tegra210-i2s"; 365 reg = <0x0 0x2901300 0x0 0x100>; 366 clocks = <&bpmp TEGRA234_CLK_I2S4>, 367 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 368 clock-names = "i2s", "sync_input"; 369 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 370 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 371 assigned-clock-rates = <1536000>; 372 sound-name-prefix = "I2S4"; 373 status = "disabled"; 374 375 ports { 376 #address-cells = <1>; 377 #size-cells = <0>; 378 379 port@0 { 380 reg = <0>; 381 382 i2s4_cif: endpoint { 383 remote-endpoint = <&xbar_i2s4>; 384 }; 385 }; 386 387 i2s4_port: port@1 { 388 reg = <1>; 389 390 i2s4_dap: endpoint { 391 dai-format = "i2s"; 392 /* placeholder for external codec */ 393 }; 394 }; 395 }; 396 }; 397 398 tegra_i2s5: i2s@2901400 { 399 compatible = "nvidia,tegra234-i2s", 400 "nvidia,tegra210-i2s"; 401 reg = <0x0 0x2901400 0x0 0x100>; 402 clocks = <&bpmp TEGRA234_CLK_I2S5>, 403 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 404 clock-names = "i2s", "sync_input"; 405 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 406 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 407 assigned-clock-rates = <1536000>; 408 sound-name-prefix = "I2S5"; 409 status = "disabled"; 410 411 ports { 412 #address-cells = <1>; 413 #size-cells = <0>; 414 415 port@0 { 416 reg = <0>; 417 418 i2s5_cif: endpoint { 419 remote-endpoint = <&xbar_i2s5>; 420 }; 421 }; 422 423 i2s5_port: port@1 { 424 reg = <1>; 425 426 i2s5_dap: endpoint { 427 dai-format = "i2s"; 428 /* placeholder for external codec */ 429 }; 430 }; 431 }; 432 }; 433 434 tegra_i2s6: i2s@2901500 { 435 compatible = "nvidia,tegra234-i2s", 436 "nvidia,tegra210-i2s"; 437 reg = <0x0 0x2901500 0x0 0x100>; 438 clocks = <&bpmp TEGRA234_CLK_I2S6>, 439 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 440 clock-names = "i2s", "sync_input"; 441 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 442 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 443 assigned-clock-rates = <1536000>; 444 sound-name-prefix = "I2S6"; 445 status = "disabled"; 446 447 ports { 448 #address-cells = <1>; 449 #size-cells = <0>; 450 451 port@0 { 452 reg = <0>; 453 454 i2s6_cif: endpoint { 455 remote-endpoint = <&xbar_i2s6>; 456 }; 457 }; 458 459 i2s6_port: port@1 { 460 reg = <1>; 461 462 i2s6_dap: endpoint { 463 dai-format = "i2s"; 464 /* placeholder for external codec */ 465 }; 466 }; 467 }; 468 }; 469 470 tegra_sfc1: sfc@2902000 { 471 compatible = "nvidia,tegra234-sfc", 472 "nvidia,tegra210-sfc"; 473 reg = <0x0 0x2902000 0x0 0x200>; 474 sound-name-prefix = "SFC1"; 475 476 ports { 477 #address-cells = <1>; 478 #size-cells = <0>; 479 480 port@0 { 481 reg = <0>; 482 483 sfc1_cif_in: endpoint { 484 remote-endpoint = <&xbar_sfc1_in>; 485 }; 486 }; 487 488 sfc1_out_port: port@1 { 489 reg = <1>; 490 491 sfc1_cif_out: endpoint { 492 remote-endpoint = <&xbar_sfc1_out>; 493 }; 494 }; 495 }; 496 }; 497 498 tegra_sfc2: sfc@2902200 { 499 compatible = "nvidia,tegra234-sfc", 500 "nvidia,tegra210-sfc"; 501 reg = <0x0 0x2902200 0x0 0x200>; 502 sound-name-prefix = "SFC2"; 503 504 ports { 505 #address-cells = <1>; 506 #size-cells = <0>; 507 508 port@0 { 509 reg = <0>; 510 511 sfc2_cif_in: endpoint { 512 remote-endpoint = <&xbar_sfc2_in>; 513 }; 514 }; 515 516 sfc2_out_port: port@1 { 517 reg = <1>; 518 519 sfc2_cif_out: endpoint { 520 remote-endpoint = <&xbar_sfc2_out>; 521 }; 522 }; 523 }; 524 }; 525 526 tegra_sfc3: sfc@2902400 { 527 compatible = "nvidia,tegra234-sfc", 528 "nvidia,tegra210-sfc"; 529 reg = <0x0 0x2902400 0x0 0x200>; 530 sound-name-prefix = "SFC3"; 531 532 ports { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 536 port@0 { 537 reg = <0>; 538 539 sfc3_cif_in: endpoint { 540 remote-endpoint = <&xbar_sfc3_in>; 541 }; 542 }; 543 544 sfc3_out_port: port@1 { 545 reg = <1>; 546 547 sfc3_cif_out: endpoint { 548 remote-endpoint = <&xbar_sfc3_out>; 549 }; 550 }; 551 }; 552 }; 553 554 tegra_sfc4: sfc@2902600 { 555 compatible = "nvidia,tegra234-sfc", 556 "nvidia,tegra210-sfc"; 557 reg = <0x0 0x2902600 0x0 0x200>; 558 sound-name-prefix = "SFC4"; 559 560 ports { 561 #address-cells = <1>; 562 #size-cells = <0>; 563 564 port@0 { 565 reg = <0>; 566 567 sfc4_cif_in: endpoint { 568 remote-endpoint = <&xbar_sfc4_in>; 569 }; 570 }; 571 572 sfc4_out_port: port@1 { 573 reg = <1>; 574 575 sfc4_cif_out: endpoint { 576 remote-endpoint = <&xbar_sfc4_out>; 577 }; 578 }; 579 }; 580 }; 581 582 tegra_amx1: amx@2903000 { 583 compatible = "nvidia,tegra234-amx", 584 "nvidia,tegra194-amx"; 585 reg = <0x0 0x2903000 0x0 0x100>; 586 sound-name-prefix = "AMX1"; 587 588 ports { 589 #address-cells = <1>; 590 #size-cells = <0>; 591 592 port@0 { 593 reg = <0>; 594 595 amx1_in1: endpoint { 596 remote-endpoint = <&xbar_amx1_in1>; 597 }; 598 }; 599 600 port@1 { 601 reg = <1>; 602 603 amx1_in2: endpoint { 604 remote-endpoint = <&xbar_amx1_in2>; 605 }; 606 }; 607 608 port@2 { 609 reg = <2>; 610 611 amx1_in3: endpoint { 612 remote-endpoint = <&xbar_amx1_in3>; 613 }; 614 }; 615 616 port@3 { 617 reg = <3>; 618 619 amx1_in4: endpoint { 620 remote-endpoint = <&xbar_amx1_in4>; 621 }; 622 }; 623 624 amx1_out_port: port@4 { 625 reg = <4>; 626 627 amx1_out: endpoint { 628 remote-endpoint = <&xbar_amx1_out>; 629 }; 630 }; 631 }; 632 }; 633 634 tegra_amx2: amx@2903100 { 635 compatible = "nvidia,tegra234-amx", 636 "nvidia,tegra194-amx"; 637 reg = <0x0 0x2903100 0x0 0x100>; 638 sound-name-prefix = "AMX2"; 639 640 ports { 641 #address-cells = <1>; 642 #size-cells = <0>; 643 644 port@0 { 645 reg = <0>; 646 647 amx2_in1: endpoint { 648 remote-endpoint = <&xbar_amx2_in1>; 649 }; 650 }; 651 652 port@1 { 653 reg = <1>; 654 655 amx2_in2: endpoint { 656 remote-endpoint = <&xbar_amx2_in2>; 657 }; 658 }; 659 660 port@2 { 661 reg = <2>; 662 663 amx2_in3: endpoint { 664 remote-endpoint = <&xbar_amx2_in3>; 665 }; 666 }; 667 668 port@3 { 669 reg = <3>; 670 671 amx2_in4: endpoint { 672 remote-endpoint = <&xbar_amx2_in4>; 673 }; 674 }; 675 676 amx2_out_port: port@4 { 677 reg = <4>; 678 679 amx2_out: endpoint { 680 remote-endpoint = <&xbar_amx2_out>; 681 }; 682 }; 683 }; 684 }; 685 686 tegra_amx3: amx@2903200 { 687 compatible = "nvidia,tegra234-amx", 688 "nvidia,tegra194-amx"; 689 reg = <0x0 0x2903200 0x0 0x100>; 690 sound-name-prefix = "AMX3"; 691 692 ports { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 696 port@0 { 697 reg = <0>; 698 699 amx3_in1: endpoint { 700 remote-endpoint = <&xbar_amx3_in1>; 701 }; 702 }; 703 704 port@1 { 705 reg = <1>; 706 707 amx3_in2: endpoint { 708 remote-endpoint = <&xbar_amx3_in2>; 709 }; 710 }; 711 712 port@2 { 713 reg = <2>; 714 715 amx3_in3: endpoint { 716 remote-endpoint = <&xbar_amx3_in3>; 717 }; 718 }; 719 720 port@3 { 721 reg = <3>; 722 723 amx3_in4: endpoint { 724 remote-endpoint = <&xbar_amx3_in4>; 725 }; 726 }; 727 728 amx3_out_port: port@4 { 729 reg = <4>; 730 731 amx3_out: endpoint { 732 remote-endpoint = <&xbar_amx3_out>; 733 }; 734 }; 735 }; 736 }; 737 738 tegra_amx4: amx@2903300 { 739 compatible = "nvidia,tegra234-amx", 740 "nvidia,tegra194-amx"; 741 reg = <0x0 0x2903300 0x0 0x100>; 742 sound-name-prefix = "AMX4"; 743 744 ports { 745 #address-cells = <1>; 746 #size-cells = <0>; 747 748 port@0 { 749 reg = <0>; 750 751 amx4_in1: endpoint { 752 remote-endpoint = <&xbar_amx4_in1>; 753 }; 754 }; 755 756 port@1 { 757 reg = <1>; 758 759 amx4_in2: endpoint { 760 remote-endpoint = <&xbar_amx4_in2>; 761 }; 762 }; 763 764 port@2 { 765 reg = <2>; 766 767 amx4_in3: endpoint { 768 remote-endpoint = <&xbar_amx4_in3>; 769 }; 770 }; 771 772 port@3 { 773 reg = <3>; 774 775 amx4_in4: endpoint { 776 remote-endpoint = <&xbar_amx4_in4>; 777 }; 778 }; 779 780 amx4_out_port: port@4 { 781 reg = <4>; 782 783 amx4_out: endpoint { 784 remote-endpoint = <&xbar_amx4_out>; 785 }; 786 }; 787 }; 788 }; 789 790 tegra_adx1: adx@2903800 { 791 compatible = "nvidia,tegra234-adx", 792 "nvidia,tegra210-adx"; 793 reg = <0x0 0x2903800 0x0 0x100>; 794 sound-name-prefix = "ADX1"; 795 796 ports { 797 #address-cells = <1>; 798 #size-cells = <0>; 799 800 port@0 { 801 reg = <0>; 802 803 adx1_in: endpoint { 804 remote-endpoint = <&xbar_adx1_in>; 805 }; 806 }; 807 808 adx1_out1_port: port@1 { 809 reg = <1>; 810 811 adx1_out1: endpoint { 812 remote-endpoint = <&xbar_adx1_out1>; 813 }; 814 }; 815 816 adx1_out2_port: port@2 { 817 reg = <2>; 818 819 adx1_out2: endpoint { 820 remote-endpoint = <&xbar_adx1_out2>; 821 }; 822 }; 823 824 adx1_out3_port: port@3 { 825 reg = <3>; 826 827 adx1_out3: endpoint { 828 remote-endpoint = <&xbar_adx1_out3>; 829 }; 830 }; 831 832 adx1_out4_port: port@4 { 833 reg = <4>; 834 835 adx1_out4: endpoint { 836 remote-endpoint = <&xbar_adx1_out4>; 837 }; 838 }; 839 }; 840 }; 841 842 tegra_adx2: adx@2903900 { 843 compatible = "nvidia,tegra234-adx", 844 "nvidia,tegra210-adx"; 845 reg = <0x0 0x2903900 0x0 0x100>; 846 sound-name-prefix = "ADX2"; 847 848 ports { 849 #address-cells = <1>; 850 #size-cells = <0>; 851 852 port@0 { 853 reg = <0>; 854 855 adx2_in: endpoint { 856 remote-endpoint = <&xbar_adx2_in>; 857 }; 858 }; 859 860 adx2_out1_port: port@1 { 861 reg = <1>; 862 863 adx2_out1: endpoint { 864 remote-endpoint = <&xbar_adx2_out1>; 865 }; 866 }; 867 868 adx2_out2_port: port@2 { 869 reg = <2>; 870 871 adx2_out2: endpoint { 872 remote-endpoint = <&xbar_adx2_out2>; 873 }; 874 }; 875 876 adx2_out3_port: port@3 { 877 reg = <3>; 878 879 adx2_out3: endpoint { 880 remote-endpoint = <&xbar_adx2_out3>; 881 }; 882 }; 883 884 adx2_out4_port: port@4 { 885 reg = <4>; 886 887 adx2_out4: endpoint { 888 remote-endpoint = <&xbar_adx2_out4>; 889 }; 890 }; 891 }; 892 }; 893 894 tegra_adx3: adx@2903a00 { 895 compatible = "nvidia,tegra234-adx", 896 "nvidia,tegra210-adx"; 897 reg = <0x0 0x2903a00 0x0 0x100>; 898 sound-name-prefix = "ADX3"; 899 900 ports { 901 #address-cells = <1>; 902 #size-cells = <0>; 903 904 port@0 { 905 reg = <0>; 906 907 adx3_in: endpoint { 908 remote-endpoint = <&xbar_adx3_in>; 909 }; 910 }; 911 912 adx3_out1_port: port@1 { 913 reg = <1>; 914 915 adx3_out1: endpoint { 916 remote-endpoint = <&xbar_adx3_out1>; 917 }; 918 }; 919 920 adx3_out2_port: port@2 { 921 reg = <2>; 922 923 adx3_out2: endpoint { 924 remote-endpoint = <&xbar_adx3_out2>; 925 }; 926 }; 927 928 adx3_out3_port: port@3 { 929 reg = <3>; 930 931 adx3_out3: endpoint { 932 remote-endpoint = <&xbar_adx3_out3>; 933 }; 934 }; 935 936 adx3_out4_port: port@4 { 937 reg = <4>; 938 939 adx3_out4: endpoint { 940 remote-endpoint = <&xbar_adx3_out4>; 941 }; 942 }; 943 }; 944 }; 945 946 tegra_adx4: adx@2903b00 { 947 compatible = "nvidia,tegra234-adx", 948 "nvidia,tegra210-adx"; 949 reg = <0x0 0x2903b00 0x0 0x100>; 950 sound-name-prefix = "ADX4"; 951 952 ports { 953 #address-cells = <1>; 954 #size-cells = <0>; 955 956 port@0 { 957 reg = <0>; 958 959 adx4_in: endpoint { 960 remote-endpoint = <&xbar_adx4_in>; 961 }; 962 }; 963 964 adx4_out1_port: port@1 { 965 reg = <1>; 966 967 adx4_out1: endpoint { 968 remote-endpoint = <&xbar_adx4_out1>; 969 }; 970 }; 971 972 adx4_out2_port: port@2 { 973 reg = <2>; 974 975 adx4_out2: endpoint { 976 remote-endpoint = <&xbar_adx4_out2>; 977 }; 978 }; 979 980 adx4_out3_port: port@3 { 981 reg = <3>; 982 983 adx4_out3: endpoint { 984 remote-endpoint = <&xbar_adx4_out3>; 985 }; 986 }; 987 988 adx4_out4_port: port@4 { 989 reg = <4>; 990 991 adx4_out4: endpoint { 992 remote-endpoint = <&xbar_adx4_out4>; 993 }; 994 }; 995 }; 996 }; 997 998 999 tegra_dmic1: dmic@2904000 { 1000 compatible = "nvidia,tegra234-dmic", 1001 "nvidia,tegra210-dmic"; 1002 reg = <0x0 0x2904000 0x0 0x100>; 1003 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 1004 clock-names = "dmic"; 1005 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 1006 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1007 assigned-clock-rates = <3072000>; 1008 sound-name-prefix = "DMIC1"; 1009 status = "disabled"; 1010 1011 ports { 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 1015 port@0 { 1016 reg = <0>; 1017 1018 dmic1_cif: endpoint { 1019 remote-endpoint = <&xbar_dmic1>; 1020 }; 1021 }; 1022 1023 dmic1_port: port@1 { 1024 reg = <1>; 1025 1026 dmic1_dap: endpoint { 1027 /* placeholder for external codec */ 1028 }; 1029 }; 1030 }; 1031 }; 1032 1033 tegra_dmic2: dmic@2904100 { 1034 compatible = "nvidia,tegra234-dmic", 1035 "nvidia,tegra210-dmic"; 1036 reg = <0x0 0x2904100 0x0 0x100>; 1037 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 1038 clock-names = "dmic"; 1039 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 1040 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1041 assigned-clock-rates = <3072000>; 1042 sound-name-prefix = "DMIC2"; 1043 status = "disabled"; 1044 1045 ports { 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 1049 port@0 { 1050 reg = <0>; 1051 1052 dmic2_cif: endpoint { 1053 remote-endpoint = <&xbar_dmic2>; 1054 }; 1055 }; 1056 1057 dmic2_port: port@1 { 1058 reg = <1>; 1059 1060 dmic2_dap: endpoint { 1061 /* placeholder for external codec */ 1062 }; 1063 }; 1064 }; 1065 }; 1066 1067 tegra_dmic3: dmic@2904200 { 1068 compatible = "nvidia,tegra234-dmic", 1069 "nvidia,tegra210-dmic"; 1070 reg = <0x0 0x2904200 0x0 0x100>; 1071 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 1072 clock-names = "dmic"; 1073 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 1074 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1075 assigned-clock-rates = <3072000>; 1076 sound-name-prefix = "DMIC3"; 1077 status = "disabled"; 1078 1079 ports { 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 1083 port@0 { 1084 reg = <0>; 1085 1086 dmic3_cif: endpoint { 1087 remote-endpoint = <&xbar_dmic3>; 1088 }; 1089 }; 1090 1091 dmic3_port: port@1 { 1092 reg = <1>; 1093 1094 dmic3_dap: endpoint { 1095 /* placeholder for external codec */ 1096 }; 1097 }; 1098 }; 1099 }; 1100 1101 tegra_dmic4: dmic@2904300 { 1102 compatible = "nvidia,tegra234-dmic", 1103 "nvidia,tegra210-dmic"; 1104 reg = <0x0 0x2904300 0x0 0x100>; 1105 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 1106 clock-names = "dmic"; 1107 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 1108 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1109 assigned-clock-rates = <3072000>; 1110 sound-name-prefix = "DMIC4"; 1111 status = "disabled"; 1112 1113 ports { 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 1117 port@0 { 1118 reg = <0>; 1119 1120 dmic4_cif: endpoint { 1121 remote-endpoint = <&xbar_dmic4>; 1122 }; 1123 }; 1124 1125 dmic4_port: port@1 { 1126 reg = <1>; 1127 1128 dmic4_dap: endpoint { 1129 /* placeholder for external codec */ 1130 }; 1131 }; 1132 }; 1133 }; 1134 1135 tegra_dspk1: dspk@2905000 { 1136 compatible = "nvidia,tegra234-dspk", 1137 "nvidia,tegra186-dspk"; 1138 reg = <0x0 0x2905000 0x0 0x100>; 1139 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 1140 clock-names = "dspk"; 1141 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 1142 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1143 assigned-clock-rates = <12288000>; 1144 sound-name-prefix = "DSPK1"; 1145 status = "disabled"; 1146 1147 ports { 1148 #address-cells = <1>; 1149 #size-cells = <0>; 1150 1151 port@0 { 1152 reg = <0>; 1153 1154 dspk1_cif: endpoint { 1155 remote-endpoint = <&xbar_dspk1>; 1156 }; 1157 }; 1158 1159 dspk1_port: port@1 { 1160 reg = <1>; 1161 1162 dspk1_dap: endpoint { 1163 /* placeholder for external codec */ 1164 }; 1165 }; 1166 }; 1167 }; 1168 1169 tegra_dspk2: dspk@2905100 { 1170 compatible = "nvidia,tegra234-dspk", 1171 "nvidia,tegra186-dspk"; 1172 reg = <0x0 0x2905100 0x0 0x100>; 1173 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 1174 clock-names = "dspk"; 1175 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 1176 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1177 assigned-clock-rates = <12288000>; 1178 sound-name-prefix = "DSPK2"; 1179 status = "disabled"; 1180 1181 ports { 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 1185 port@0 { 1186 reg = <0>; 1187 1188 dspk2_cif: endpoint { 1189 remote-endpoint = <&xbar_dspk2>; 1190 }; 1191 }; 1192 1193 dspk2_port: port@1 { 1194 reg = <1>; 1195 1196 dspk2_dap: endpoint { 1197 /* placeholder for external codec */ 1198 }; 1199 }; 1200 }; 1201 }; 1202 1203 tegra_ope1: processing-engine@2908000 { 1204 compatible = "nvidia,tegra234-ope", 1205 "nvidia,tegra210-ope"; 1206 reg = <0x0 0x2908000 0x0 0x100>; 1207 sound-name-prefix = "OPE1"; 1208 1209 #address-cells = <2>; 1210 #size-cells = <2>; 1211 ranges; 1212 1213 equalizer@2908100 { 1214 compatible = "nvidia,tegra234-peq", 1215 "nvidia,tegra210-peq"; 1216 reg = <0x0 0x2908100 0x0 0x100>; 1217 }; 1218 1219 dynamic-range-compressor@2908200 { 1220 compatible = "nvidia,tegra234-mbdrc", 1221 "nvidia,tegra210-mbdrc"; 1222 reg = <0x0 0x2908200 0x0 0x200>; 1223 }; 1224 1225 ports { 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 1229 port@0 { 1230 reg = <0x0>; 1231 1232 ope1_cif_in_ep: endpoint { 1233 remote-endpoint = 1234 <&xbar_ope1_in_ep>; 1235 }; 1236 }; 1237 1238 ope1_out_port: port@1 { 1239 reg = <0x1>; 1240 1241 ope1_cif_out_ep: endpoint { 1242 remote-endpoint = 1243 <&xbar_ope1_out_ep>; 1244 }; 1245 }; 1246 }; 1247 }; 1248 1249 tegra_mvc1: mvc@290a000 { 1250 compatible = "nvidia,tegra234-mvc", 1251 "nvidia,tegra210-mvc"; 1252 reg = <0x0 0x290a000 0x0 0x200>; 1253 sound-name-prefix = "MVC1"; 1254 1255 ports { 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 1259 port@0 { 1260 reg = <0>; 1261 1262 mvc1_cif_in: endpoint { 1263 remote-endpoint = <&xbar_mvc1_in>; 1264 }; 1265 }; 1266 1267 mvc1_out_port: port@1 { 1268 reg = <1>; 1269 1270 mvc1_cif_out: endpoint { 1271 remote-endpoint = <&xbar_mvc1_out>; 1272 }; 1273 }; 1274 }; 1275 }; 1276 1277 tegra_mvc2: mvc@290a200 { 1278 compatible = "nvidia,tegra234-mvc", 1279 "nvidia,tegra210-mvc"; 1280 reg = <0x0 0x290a200 0x0 0x200>; 1281 sound-name-prefix = "MVC2"; 1282 1283 ports { 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 1287 port@0 { 1288 reg = <0>; 1289 1290 mvc2_cif_in: endpoint { 1291 remote-endpoint = <&xbar_mvc2_in>; 1292 }; 1293 }; 1294 1295 mvc2_out_port: port@1 { 1296 reg = <1>; 1297 1298 mvc2_cif_out: endpoint { 1299 remote-endpoint = <&xbar_mvc2_out>; 1300 }; 1301 }; 1302 }; 1303 }; 1304 1305 tegra_amixer: amixer@290bb00 { 1306 compatible = "nvidia,tegra234-amixer", 1307 "nvidia,tegra210-amixer"; 1308 reg = <0x0 0x290bb00 0x0 0x800>; 1309 sound-name-prefix = "MIXER1"; 1310 1311 ports { 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 1315 port@0 { 1316 reg = <0x0>; 1317 1318 mix_in1: endpoint { 1319 remote-endpoint = <&xbar_mix_in1>; 1320 }; 1321 }; 1322 1323 port@1 { 1324 reg = <0x1>; 1325 1326 mix_in2: endpoint { 1327 remote-endpoint = <&xbar_mix_in2>; 1328 }; 1329 }; 1330 1331 port@2 { 1332 reg = <0x2>; 1333 1334 mix_in3: endpoint { 1335 remote-endpoint = <&xbar_mix_in3>; 1336 }; 1337 }; 1338 1339 port@3 { 1340 reg = <0x3>; 1341 1342 mix_in4: endpoint { 1343 remote-endpoint = <&xbar_mix_in4>; 1344 }; 1345 }; 1346 1347 port@4 { 1348 reg = <0x4>; 1349 1350 mix_in5: endpoint { 1351 remote-endpoint = <&xbar_mix_in5>; 1352 }; 1353 }; 1354 1355 port@5 { 1356 reg = <0x5>; 1357 1358 mix_in6: endpoint { 1359 remote-endpoint = <&xbar_mix_in6>; 1360 }; 1361 }; 1362 1363 port@6 { 1364 reg = <0x6>; 1365 1366 mix_in7: endpoint { 1367 remote-endpoint = <&xbar_mix_in7>; 1368 }; 1369 }; 1370 1371 port@7 { 1372 reg = <0x7>; 1373 1374 mix_in8: endpoint { 1375 remote-endpoint = <&xbar_mix_in8>; 1376 }; 1377 }; 1378 1379 port@8 { 1380 reg = <0x8>; 1381 1382 mix_in9: endpoint { 1383 remote-endpoint = <&xbar_mix_in9>; 1384 }; 1385 }; 1386 1387 port@9 { 1388 reg = <0x9>; 1389 1390 mix_in10: endpoint { 1391 remote-endpoint = <&xbar_mix_in10>; 1392 }; 1393 }; 1394 1395 mix_out1_port: port@a { 1396 reg = <0xa>; 1397 1398 mix_out1: endpoint { 1399 remote-endpoint = <&xbar_mix_out1>; 1400 }; 1401 }; 1402 1403 mix_out2_port: port@b { 1404 reg = <0xb>; 1405 1406 mix_out2: endpoint { 1407 remote-endpoint = <&xbar_mix_out2>; 1408 }; 1409 }; 1410 1411 mix_out3_port: port@c { 1412 reg = <0xc>; 1413 1414 mix_out3: endpoint { 1415 remote-endpoint = <&xbar_mix_out3>; 1416 }; 1417 }; 1418 1419 mix_out4_port: port@d { 1420 reg = <0xd>; 1421 1422 mix_out4: endpoint { 1423 remote-endpoint = <&xbar_mix_out4>; 1424 }; 1425 }; 1426 1427 mix_out5_port: port@e { 1428 reg = <0xe>; 1429 1430 mix_out5: endpoint { 1431 remote-endpoint = <&xbar_mix_out5>; 1432 }; 1433 }; 1434 }; 1435 }; 1436 1437 tegra_admaif: admaif@290f000 { 1438 compatible = "nvidia,tegra234-admaif", 1439 "nvidia,tegra186-admaif"; 1440 reg = <0x0 0x0290f000 0x0 0x1000>; 1441 dmas = <&adma 1>, <&adma 1>, 1442 <&adma 2>, <&adma 2>, 1443 <&adma 3>, <&adma 3>, 1444 <&adma 4>, <&adma 4>, 1445 <&adma 5>, <&adma 5>, 1446 <&adma 6>, <&adma 6>, 1447 <&adma 7>, <&adma 7>, 1448 <&adma 8>, <&adma 8>, 1449 <&adma 9>, <&adma 9>, 1450 <&adma 10>, <&adma 10>, 1451 <&adma 11>, <&adma 11>, 1452 <&adma 12>, <&adma 12>, 1453 <&adma 13>, <&adma 13>, 1454 <&adma 14>, <&adma 14>, 1455 <&adma 15>, <&adma 15>, 1456 <&adma 16>, <&adma 16>, 1457 <&adma 17>, <&adma 17>, 1458 <&adma 18>, <&adma 18>, 1459 <&adma 19>, <&adma 19>, 1460 <&adma 20>, <&adma 20>; 1461 dma-names = "rx1", "tx1", 1462 "rx2", "tx2", 1463 "rx3", "tx3", 1464 "rx4", "tx4", 1465 "rx5", "tx5", 1466 "rx6", "tx6", 1467 "rx7", "tx7", 1468 "rx8", "tx8", 1469 "rx9", "tx9", 1470 "rx10", "tx10", 1471 "rx11", "tx11", 1472 "rx12", "tx12", 1473 "rx13", "tx13", 1474 "rx14", "tx14", 1475 "rx15", "tx15", 1476 "rx16", "tx16", 1477 "rx17", "tx17", 1478 "rx18", "tx18", 1479 "rx19", "tx19", 1480 "rx20", "tx20"; 1481 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 1482 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 1483 interconnect-names = "dma-mem", "write"; 1484 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 1485 1486 ports { 1487 #address-cells = <1>; 1488 #size-cells = <0>; 1489 1490 admaif0_port: port@0 { 1491 reg = <0x0>; 1492 1493 admaif0: endpoint { 1494 remote-endpoint = <&xbar_admaif0>; 1495 }; 1496 }; 1497 1498 admaif1_port: port@1 { 1499 reg = <0x1>; 1500 1501 admaif1: endpoint { 1502 remote-endpoint = <&xbar_admaif1>; 1503 }; 1504 }; 1505 1506 admaif2_port: port@2 { 1507 reg = <0x2>; 1508 1509 admaif2: endpoint { 1510 remote-endpoint = <&xbar_admaif2>; 1511 }; 1512 }; 1513 1514 admaif3_port: port@3 { 1515 reg = <0x3>; 1516 1517 admaif3: endpoint { 1518 remote-endpoint = <&xbar_admaif3>; 1519 }; 1520 }; 1521 1522 admaif4_port: port@4 { 1523 reg = <0x4>; 1524 1525 admaif4: endpoint { 1526 remote-endpoint = <&xbar_admaif4>; 1527 }; 1528 }; 1529 1530 admaif5_port: port@5 { 1531 reg = <0x5>; 1532 1533 admaif5: endpoint { 1534 remote-endpoint = <&xbar_admaif5>; 1535 }; 1536 }; 1537 1538 admaif6_port: port@6 { 1539 reg = <0x6>; 1540 1541 admaif6: endpoint { 1542 remote-endpoint = <&xbar_admaif6>; 1543 }; 1544 }; 1545 1546 admaif7_port: port@7 { 1547 reg = <0x7>; 1548 1549 admaif7: endpoint { 1550 remote-endpoint = <&xbar_admaif7>; 1551 }; 1552 }; 1553 1554 admaif8_port: port@8 { 1555 reg = <0x8>; 1556 1557 admaif8: endpoint { 1558 remote-endpoint = <&xbar_admaif8>; 1559 }; 1560 }; 1561 1562 admaif9_port: port@9 { 1563 reg = <0x9>; 1564 1565 admaif9: endpoint { 1566 remote-endpoint = <&xbar_admaif9>; 1567 }; 1568 }; 1569 1570 admaif10_port: port@a { 1571 reg = <0xa>; 1572 1573 admaif10: endpoint { 1574 remote-endpoint = <&xbar_admaif10>; 1575 }; 1576 }; 1577 1578 admaif11_port: port@b { 1579 reg = <0xb>; 1580 1581 admaif11: endpoint { 1582 remote-endpoint = <&xbar_admaif11>; 1583 }; 1584 }; 1585 1586 admaif12_port: port@c { 1587 reg = <0xc>; 1588 1589 admaif12: endpoint { 1590 remote-endpoint = <&xbar_admaif12>; 1591 }; 1592 }; 1593 1594 admaif13_port: port@d { 1595 reg = <0xd>; 1596 1597 admaif13: endpoint { 1598 remote-endpoint = <&xbar_admaif13>; 1599 }; 1600 }; 1601 1602 admaif14_port: port@e { 1603 reg = <0xe>; 1604 1605 admaif14: endpoint { 1606 remote-endpoint = <&xbar_admaif14>; 1607 }; 1608 }; 1609 1610 admaif15_port: port@f { 1611 reg = <0xf>; 1612 1613 admaif15: endpoint { 1614 remote-endpoint = <&xbar_admaif15>; 1615 }; 1616 }; 1617 1618 admaif16_port: port@10 { 1619 reg = <0x10>; 1620 1621 admaif16: endpoint { 1622 remote-endpoint = <&xbar_admaif16>; 1623 }; 1624 }; 1625 1626 admaif17_port: port@11 { 1627 reg = <0x11>; 1628 1629 admaif17: endpoint { 1630 remote-endpoint = <&xbar_admaif17>; 1631 }; 1632 }; 1633 1634 admaif18_port: port@12 { 1635 reg = <0x12>; 1636 1637 admaif18: endpoint { 1638 remote-endpoint = <&xbar_admaif18>; 1639 }; 1640 }; 1641 1642 admaif19_port: port@13 { 1643 reg = <0x13>; 1644 1645 admaif19: endpoint { 1646 remote-endpoint = <&xbar_admaif19>; 1647 }; 1648 }; 1649 }; 1650 }; 1651 1652 tegra_asrc: asrc@2910000 { 1653 compatible = "nvidia,tegra234-asrc", 1654 "nvidia,tegra186-asrc"; 1655 reg = <0x0 0x2910000 0x0 0x2000>; 1656 sound-name-prefix = "ASRC1"; 1657 1658 ports { 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 1662 port@0 { 1663 reg = <0x0>; 1664 1665 asrc_in1_ep: endpoint { 1666 remote-endpoint = 1667 <&xbar_asrc_in1_ep>; 1668 }; 1669 }; 1670 1671 port@1 { 1672 reg = <0x1>; 1673 1674 asrc_in2_ep: endpoint { 1675 remote-endpoint = 1676 <&xbar_asrc_in2_ep>; 1677 }; 1678 }; 1679 1680 port@2 { 1681 reg = <0x2>; 1682 1683 asrc_in3_ep: endpoint { 1684 remote-endpoint = 1685 <&xbar_asrc_in3_ep>; 1686 }; 1687 }; 1688 1689 port@3 { 1690 reg = <0x3>; 1691 1692 asrc_in4_ep: endpoint { 1693 remote-endpoint = 1694 <&xbar_asrc_in4_ep>; 1695 }; 1696 }; 1697 1698 port@4 { 1699 reg = <0x4>; 1700 1701 asrc_in5_ep: endpoint { 1702 remote-endpoint = 1703 <&xbar_asrc_in5_ep>; 1704 }; 1705 }; 1706 1707 port@5 { 1708 reg = <0x5>; 1709 1710 asrc_in6_ep: endpoint { 1711 remote-endpoint = 1712 <&xbar_asrc_in6_ep>; 1713 }; 1714 }; 1715 1716 port@6 { 1717 reg = <0x6>; 1718 1719 asrc_in7_ep: endpoint { 1720 remote-endpoint = 1721 <&xbar_asrc_in7_ep>; 1722 }; 1723 }; 1724 1725 asrc_out1_port: port@7 { 1726 reg = <0x7>; 1727 1728 asrc_out1_ep: endpoint { 1729 remote-endpoint = 1730 <&xbar_asrc_out1_ep>; 1731 }; 1732 }; 1733 1734 asrc_out2_port: port@8 { 1735 reg = <0x8>; 1736 1737 asrc_out2_ep: endpoint { 1738 remote-endpoint = 1739 <&xbar_asrc_out2_ep>; 1740 }; 1741 }; 1742 1743 asrc_out3_port: port@9 { 1744 reg = <0x9>; 1745 1746 asrc_out3_ep: endpoint { 1747 remote-endpoint = 1748 <&xbar_asrc_out3_ep>; 1749 }; 1750 }; 1751 1752 asrc_out4_port: port@a { 1753 reg = <0xa>; 1754 1755 asrc_out4_ep: endpoint { 1756 remote-endpoint = 1757 <&xbar_asrc_out4_ep>; 1758 }; 1759 }; 1760 1761 asrc_out5_port: port@b { 1762 reg = <0xb>; 1763 1764 asrc_out5_ep: endpoint { 1765 remote-endpoint = 1766 <&xbar_asrc_out5_ep>; 1767 }; 1768 }; 1769 1770 asrc_out6_port: port@c { 1771 reg = <0xc>; 1772 1773 asrc_out6_ep: endpoint { 1774 remote-endpoint = 1775 <&xbar_asrc_out6_ep>; 1776 }; 1777 }; 1778 }; 1779 }; 1780 1781 ports { 1782 #address-cells = <1>; 1783 #size-cells = <0>; 1784 1785 port@0 { 1786 reg = <0x0>; 1787 1788 xbar_admaif0: endpoint { 1789 remote-endpoint = <&admaif0>; 1790 }; 1791 }; 1792 1793 port@1 { 1794 reg = <0x1>; 1795 1796 xbar_admaif1: endpoint { 1797 remote-endpoint = <&admaif1>; 1798 }; 1799 }; 1800 1801 port@2 { 1802 reg = <0x2>; 1803 1804 xbar_admaif2: endpoint { 1805 remote-endpoint = <&admaif2>; 1806 }; 1807 }; 1808 1809 port@3 { 1810 reg = <0x3>; 1811 1812 xbar_admaif3: endpoint { 1813 remote-endpoint = <&admaif3>; 1814 }; 1815 }; 1816 1817 port@4 { 1818 reg = <0x4>; 1819 1820 xbar_admaif4: endpoint { 1821 remote-endpoint = <&admaif4>; 1822 }; 1823 }; 1824 1825 port@5 { 1826 reg = <0x5>; 1827 1828 xbar_admaif5: endpoint { 1829 remote-endpoint = <&admaif5>; 1830 }; 1831 }; 1832 1833 port@6 { 1834 reg = <0x6>; 1835 1836 xbar_admaif6: endpoint { 1837 remote-endpoint = <&admaif6>; 1838 }; 1839 }; 1840 1841 port@7 { 1842 reg = <0x7>; 1843 1844 xbar_admaif7: endpoint { 1845 remote-endpoint = <&admaif7>; 1846 }; 1847 }; 1848 1849 port@8 { 1850 reg = <0x8>; 1851 1852 xbar_admaif8: endpoint { 1853 remote-endpoint = <&admaif8>; 1854 }; 1855 }; 1856 1857 port@9 { 1858 reg = <0x9>; 1859 1860 xbar_admaif9: endpoint { 1861 remote-endpoint = <&admaif9>; 1862 }; 1863 }; 1864 1865 port@a { 1866 reg = <0xa>; 1867 1868 xbar_admaif10: endpoint { 1869 remote-endpoint = <&admaif10>; 1870 }; 1871 }; 1872 1873 port@b { 1874 reg = <0xb>; 1875 1876 xbar_admaif11: endpoint { 1877 remote-endpoint = <&admaif11>; 1878 }; 1879 }; 1880 1881 port@c { 1882 reg = <0xc>; 1883 1884 xbar_admaif12: endpoint { 1885 remote-endpoint = <&admaif12>; 1886 }; 1887 }; 1888 1889 port@d { 1890 reg = <0xd>; 1891 1892 xbar_admaif13: endpoint { 1893 remote-endpoint = <&admaif13>; 1894 }; 1895 }; 1896 1897 port@e { 1898 reg = <0xe>; 1899 1900 xbar_admaif14: endpoint { 1901 remote-endpoint = <&admaif14>; 1902 }; 1903 }; 1904 1905 port@f { 1906 reg = <0xf>; 1907 1908 xbar_admaif15: endpoint { 1909 remote-endpoint = <&admaif15>; 1910 }; 1911 }; 1912 1913 port@10 { 1914 reg = <0x10>; 1915 1916 xbar_admaif16: endpoint { 1917 remote-endpoint = <&admaif16>; 1918 }; 1919 }; 1920 1921 port@11 { 1922 reg = <0x11>; 1923 1924 xbar_admaif17: endpoint { 1925 remote-endpoint = <&admaif17>; 1926 }; 1927 }; 1928 1929 port@12 { 1930 reg = <0x12>; 1931 1932 xbar_admaif18: endpoint { 1933 remote-endpoint = <&admaif18>; 1934 }; 1935 }; 1936 1937 port@13 { 1938 reg = <0x13>; 1939 1940 xbar_admaif19: endpoint { 1941 remote-endpoint = <&admaif19>; 1942 }; 1943 }; 1944 1945 xbar_i2s1_port: port@14 { 1946 reg = <0x14>; 1947 1948 xbar_i2s1: endpoint { 1949 remote-endpoint = <&i2s1_cif>; 1950 }; 1951 }; 1952 1953 xbar_i2s2_port: port@15 { 1954 reg = <0x15>; 1955 1956 xbar_i2s2: endpoint { 1957 remote-endpoint = <&i2s2_cif>; 1958 }; 1959 }; 1960 1961 xbar_i2s3_port: port@16 { 1962 reg = <0x16>; 1963 1964 xbar_i2s3: endpoint { 1965 remote-endpoint = <&i2s3_cif>; 1966 }; 1967 }; 1968 1969 xbar_i2s4_port: port@17 { 1970 reg = <0x17>; 1971 1972 xbar_i2s4: endpoint { 1973 remote-endpoint = <&i2s4_cif>; 1974 }; 1975 }; 1976 1977 xbar_i2s5_port: port@18 { 1978 reg = <0x18>; 1979 1980 xbar_i2s5: endpoint { 1981 remote-endpoint = <&i2s5_cif>; 1982 }; 1983 }; 1984 1985 xbar_i2s6_port: port@19 { 1986 reg = <0x19>; 1987 1988 xbar_i2s6: endpoint { 1989 remote-endpoint = <&i2s6_cif>; 1990 }; 1991 }; 1992 1993 xbar_dmic1_port: port@1a { 1994 reg = <0x1a>; 1995 1996 xbar_dmic1: endpoint { 1997 remote-endpoint = <&dmic1_cif>; 1998 }; 1999 }; 2000 2001 xbar_dmic2_port: port@1b { 2002 reg = <0x1b>; 2003 2004 xbar_dmic2: endpoint { 2005 remote-endpoint = <&dmic2_cif>; 2006 }; 2007 }; 2008 2009 xbar_dmic3_port: port@1c { 2010 reg = <0x1c>; 2011 2012 xbar_dmic3: endpoint { 2013 remote-endpoint = <&dmic3_cif>; 2014 }; 2015 }; 2016 2017 xbar_dmic4_port: port@1d { 2018 reg = <0x1d>; 2019 2020 xbar_dmic4: endpoint { 2021 remote-endpoint = <&dmic4_cif>; 2022 }; 2023 }; 2024 2025 xbar_dspk1_port: port@1e { 2026 reg = <0x1e>; 2027 2028 xbar_dspk1: endpoint { 2029 remote-endpoint = <&dspk1_cif>; 2030 }; 2031 }; 2032 2033 xbar_dspk2_port: port@1f { 2034 reg = <0x1f>; 2035 2036 xbar_dspk2: endpoint { 2037 remote-endpoint = <&dspk2_cif>; 2038 }; 2039 }; 2040 2041 xbar_sfc1_in_port: port@20 { 2042 reg = <0x20>; 2043 2044 xbar_sfc1_in: endpoint { 2045 remote-endpoint = <&sfc1_cif_in>; 2046 }; 2047 }; 2048 2049 port@21 { 2050 reg = <0x21>; 2051 2052 xbar_sfc1_out: endpoint { 2053 remote-endpoint = <&sfc1_cif_out>; 2054 }; 2055 }; 2056 2057 xbar_sfc2_in_port: port@22 { 2058 reg = <0x22>; 2059 2060 xbar_sfc2_in: endpoint { 2061 remote-endpoint = <&sfc2_cif_in>; 2062 }; 2063 }; 2064 2065 port@23 { 2066 reg = <0x23>; 2067 2068 xbar_sfc2_out: endpoint { 2069 remote-endpoint = <&sfc2_cif_out>; 2070 }; 2071 }; 2072 2073 xbar_sfc3_in_port: port@24 { 2074 reg = <0x24>; 2075 2076 xbar_sfc3_in: endpoint { 2077 remote-endpoint = <&sfc3_cif_in>; 2078 }; 2079 }; 2080 2081 port@25 { 2082 reg = <0x25>; 2083 2084 xbar_sfc3_out: endpoint { 2085 remote-endpoint = <&sfc3_cif_out>; 2086 }; 2087 }; 2088 2089 xbar_sfc4_in_port: port@26 { 2090 reg = <0x26>; 2091 2092 xbar_sfc4_in: endpoint { 2093 remote-endpoint = <&sfc4_cif_in>; 2094 }; 2095 }; 2096 2097 port@27 { 2098 reg = <0x27>; 2099 2100 xbar_sfc4_out: endpoint { 2101 remote-endpoint = <&sfc4_cif_out>; 2102 }; 2103 }; 2104 2105 xbar_mvc1_in_port: port@28 { 2106 reg = <0x28>; 2107 2108 xbar_mvc1_in: endpoint { 2109 remote-endpoint = <&mvc1_cif_in>; 2110 }; 2111 }; 2112 2113 port@29 { 2114 reg = <0x29>; 2115 2116 xbar_mvc1_out: endpoint { 2117 remote-endpoint = <&mvc1_cif_out>; 2118 }; 2119 }; 2120 2121 xbar_mvc2_in_port: port@2a { 2122 reg = <0x2a>; 2123 2124 xbar_mvc2_in: endpoint { 2125 remote-endpoint = <&mvc2_cif_in>; 2126 }; 2127 }; 2128 2129 port@2b { 2130 reg = <0x2b>; 2131 2132 xbar_mvc2_out: endpoint { 2133 remote-endpoint = <&mvc2_cif_out>; 2134 }; 2135 }; 2136 2137 xbar_amx1_in1_port: port@2c { 2138 reg = <0x2c>; 2139 2140 xbar_amx1_in1: endpoint { 2141 remote-endpoint = <&amx1_in1>; 2142 }; 2143 }; 2144 2145 xbar_amx1_in2_port: port@2d { 2146 reg = <0x2d>; 2147 2148 xbar_amx1_in2: endpoint { 2149 remote-endpoint = <&amx1_in2>; 2150 }; 2151 }; 2152 2153 xbar_amx1_in3_port: port@2e { 2154 reg = <0x2e>; 2155 2156 xbar_amx1_in3: endpoint { 2157 remote-endpoint = <&amx1_in3>; 2158 }; 2159 }; 2160 2161 xbar_amx1_in4_port: port@2f { 2162 reg = <0x2f>; 2163 2164 xbar_amx1_in4: endpoint { 2165 remote-endpoint = <&amx1_in4>; 2166 }; 2167 }; 2168 2169 port@30 { 2170 reg = <0x30>; 2171 2172 xbar_amx1_out: endpoint { 2173 remote-endpoint = <&amx1_out>; 2174 }; 2175 }; 2176 2177 xbar_amx2_in1_port: port@31 { 2178 reg = <0x31>; 2179 2180 xbar_amx2_in1: endpoint { 2181 remote-endpoint = <&amx2_in1>; 2182 }; 2183 }; 2184 2185 xbar_amx2_in2_port: port@32 { 2186 reg = <0x32>; 2187 2188 xbar_amx2_in2: endpoint { 2189 remote-endpoint = <&amx2_in2>; 2190 }; 2191 }; 2192 2193 xbar_amx2_in3_port: port@33 { 2194 reg = <0x33>; 2195 2196 xbar_amx2_in3: endpoint { 2197 remote-endpoint = <&amx2_in3>; 2198 }; 2199 }; 2200 2201 xbar_amx2_in4_port: port@34 { 2202 reg = <0x34>; 2203 2204 xbar_amx2_in4: endpoint { 2205 remote-endpoint = <&amx2_in4>; 2206 }; 2207 }; 2208 2209 port@35 { 2210 reg = <0x35>; 2211 2212 xbar_amx2_out: endpoint { 2213 remote-endpoint = <&amx2_out>; 2214 }; 2215 }; 2216 2217 xbar_amx3_in1_port: port@36 { 2218 reg = <0x36>; 2219 2220 xbar_amx3_in1: endpoint { 2221 remote-endpoint = <&amx3_in1>; 2222 }; 2223 }; 2224 2225 xbar_amx3_in2_port: port@37 { 2226 reg = <0x37>; 2227 2228 xbar_amx3_in2: endpoint { 2229 remote-endpoint = <&amx3_in2>; 2230 }; 2231 }; 2232 2233 xbar_amx3_in3_port: port@38 { 2234 reg = <0x38>; 2235 2236 xbar_amx3_in3: endpoint { 2237 remote-endpoint = <&amx3_in3>; 2238 }; 2239 }; 2240 2241 xbar_amx3_in4_port: port@39 { 2242 reg = <0x39>; 2243 2244 xbar_amx3_in4: endpoint { 2245 remote-endpoint = <&amx3_in4>; 2246 }; 2247 }; 2248 2249 port@3a { 2250 reg = <0x3a>; 2251 2252 xbar_amx3_out: endpoint { 2253 remote-endpoint = <&amx3_out>; 2254 }; 2255 }; 2256 2257 xbar_amx4_in1_port: port@3b { 2258 reg = <0x3b>; 2259 2260 xbar_amx4_in1: endpoint { 2261 remote-endpoint = <&amx4_in1>; 2262 }; 2263 }; 2264 2265 xbar_amx4_in2_port: port@3c { 2266 reg = <0x3c>; 2267 2268 xbar_amx4_in2: endpoint { 2269 remote-endpoint = <&amx4_in2>; 2270 }; 2271 }; 2272 2273 xbar_amx4_in3_port: port@3d { 2274 reg = <0x3d>; 2275 2276 xbar_amx4_in3: endpoint { 2277 remote-endpoint = <&amx4_in3>; 2278 }; 2279 }; 2280 2281 xbar_amx4_in4_port: port@3e { 2282 reg = <0x3e>; 2283 2284 xbar_amx4_in4: endpoint { 2285 remote-endpoint = <&amx4_in4>; 2286 }; 2287 }; 2288 2289 port@3f { 2290 reg = <0x3f>; 2291 2292 xbar_amx4_out: endpoint { 2293 remote-endpoint = <&amx4_out>; 2294 }; 2295 }; 2296 2297 xbar_adx1_in_port: port@40 { 2298 reg = <0x40>; 2299 2300 xbar_adx1_in: endpoint { 2301 remote-endpoint = <&adx1_in>; 2302 }; 2303 }; 2304 2305 port@41 { 2306 reg = <0x41>; 2307 2308 xbar_adx1_out1: endpoint { 2309 remote-endpoint = <&adx1_out1>; 2310 }; 2311 }; 2312 2313 port@42 { 2314 reg = <0x42>; 2315 2316 xbar_adx1_out2: endpoint { 2317 remote-endpoint = <&adx1_out2>; 2318 }; 2319 }; 2320 2321 port@43 { 2322 reg = <0x43>; 2323 2324 xbar_adx1_out3: endpoint { 2325 remote-endpoint = <&adx1_out3>; 2326 }; 2327 }; 2328 2329 port@44 { 2330 reg = <0x44>; 2331 2332 xbar_adx1_out4: endpoint { 2333 remote-endpoint = <&adx1_out4>; 2334 }; 2335 }; 2336 2337 xbar_adx2_in_port: port@45 { 2338 reg = <0x45>; 2339 2340 xbar_adx2_in: endpoint { 2341 remote-endpoint = <&adx2_in>; 2342 }; 2343 }; 2344 2345 port@46 { 2346 reg = <0x46>; 2347 2348 xbar_adx2_out1: endpoint { 2349 remote-endpoint = <&adx2_out1>; 2350 }; 2351 }; 2352 2353 port@47 { 2354 reg = <0x47>; 2355 2356 xbar_adx2_out2: endpoint { 2357 remote-endpoint = <&adx2_out2>; 2358 }; 2359 }; 2360 2361 port@48 { 2362 reg = <0x48>; 2363 2364 xbar_adx2_out3: endpoint { 2365 remote-endpoint = <&adx2_out3>; 2366 }; 2367 }; 2368 2369 port@49 { 2370 reg = <0x49>; 2371 2372 xbar_adx2_out4: endpoint { 2373 remote-endpoint = <&adx2_out4>; 2374 }; 2375 }; 2376 2377 xbar_adx3_in_port: port@4a { 2378 reg = <0x4a>; 2379 2380 xbar_adx3_in: endpoint { 2381 remote-endpoint = <&adx3_in>; 2382 }; 2383 }; 2384 2385 port@4b { 2386 reg = <0x4b>; 2387 2388 xbar_adx3_out1: endpoint { 2389 remote-endpoint = <&adx3_out1>; 2390 }; 2391 }; 2392 2393 port@4c { 2394 reg = <0x4c>; 2395 2396 xbar_adx3_out2: endpoint { 2397 remote-endpoint = <&adx3_out2>; 2398 }; 2399 }; 2400 2401 port@4d { 2402 reg = <0x4d>; 2403 2404 xbar_adx3_out3: endpoint { 2405 remote-endpoint = <&adx3_out3>; 2406 }; 2407 }; 2408 2409 port@4e { 2410 reg = <0x4e>; 2411 2412 xbar_adx3_out4: endpoint { 2413 remote-endpoint = <&adx3_out4>; 2414 }; 2415 }; 2416 2417 xbar_adx4_in_port: port@4f { 2418 reg = <0x4f>; 2419 2420 xbar_adx4_in: endpoint { 2421 remote-endpoint = <&adx4_in>; 2422 }; 2423 }; 2424 2425 port@50 { 2426 reg = <0x50>; 2427 2428 xbar_adx4_out1: endpoint { 2429 remote-endpoint = <&adx4_out1>; 2430 }; 2431 }; 2432 2433 port@51 { 2434 reg = <0x51>; 2435 2436 xbar_adx4_out2: endpoint { 2437 remote-endpoint = <&adx4_out2>; 2438 }; 2439 }; 2440 2441 port@52 { 2442 reg = <0x52>; 2443 2444 xbar_adx4_out3: endpoint { 2445 remote-endpoint = <&adx4_out3>; 2446 }; 2447 }; 2448 2449 port@53 { 2450 reg = <0x53>; 2451 2452 xbar_adx4_out4: endpoint { 2453 remote-endpoint = <&adx4_out4>; 2454 }; 2455 }; 2456 2457 xbar_mix_in1_port: port@54 { 2458 reg = <0x54>; 2459 2460 xbar_mix_in1: endpoint { 2461 remote-endpoint = <&mix_in1>; 2462 }; 2463 }; 2464 2465 xbar_mix_in2_port: port@55 { 2466 reg = <0x55>; 2467 2468 xbar_mix_in2: endpoint { 2469 remote-endpoint = <&mix_in2>; 2470 }; 2471 }; 2472 2473 xbar_mix_in3_port: port@56 { 2474 reg = <0x56>; 2475 2476 xbar_mix_in3: endpoint { 2477 remote-endpoint = <&mix_in3>; 2478 }; 2479 }; 2480 2481 xbar_mix_in4_port: port@57 { 2482 reg = <0x57>; 2483 2484 xbar_mix_in4: endpoint { 2485 remote-endpoint = <&mix_in4>; 2486 }; 2487 }; 2488 2489 xbar_mix_in5_port: port@58 { 2490 reg = <0x58>; 2491 2492 xbar_mix_in5: endpoint { 2493 remote-endpoint = <&mix_in5>; 2494 }; 2495 }; 2496 2497 xbar_mix_in6_port: port@59 { 2498 reg = <0x59>; 2499 2500 xbar_mix_in6: endpoint { 2501 remote-endpoint = <&mix_in6>; 2502 }; 2503 }; 2504 2505 xbar_mix_in7_port: port@5a { 2506 reg = <0x5a>; 2507 2508 xbar_mix_in7: endpoint { 2509 remote-endpoint = <&mix_in7>; 2510 }; 2511 }; 2512 2513 xbar_mix_in8_port: port@5b { 2514 reg = <0x5b>; 2515 2516 xbar_mix_in8: endpoint { 2517 remote-endpoint = <&mix_in8>; 2518 }; 2519 }; 2520 2521 xbar_mix_in9_port: port@5c { 2522 reg = <0x5c>; 2523 2524 xbar_mix_in9: endpoint { 2525 remote-endpoint = <&mix_in9>; 2526 }; 2527 }; 2528 2529 xbar_mix_in10_port: port@5d { 2530 reg = <0x5d>; 2531 2532 xbar_mix_in10: endpoint { 2533 remote-endpoint = <&mix_in10>; 2534 }; 2535 }; 2536 2537 port@5e { 2538 reg = <0x5e>; 2539 2540 xbar_mix_out1: endpoint { 2541 remote-endpoint = <&mix_out1>; 2542 }; 2543 }; 2544 2545 port@5f { 2546 reg = <0x5f>; 2547 2548 xbar_mix_out2: endpoint { 2549 remote-endpoint = <&mix_out2>; 2550 }; 2551 }; 2552 2553 port@60 { 2554 reg = <0x60>; 2555 2556 xbar_mix_out3: endpoint { 2557 remote-endpoint = <&mix_out3>; 2558 }; 2559 }; 2560 2561 port@61 { 2562 reg = <0x61>; 2563 2564 xbar_mix_out4: endpoint { 2565 remote-endpoint = <&mix_out4>; 2566 }; 2567 }; 2568 2569 port@62 { 2570 reg = <0x62>; 2571 2572 xbar_mix_out5: endpoint { 2573 remote-endpoint = <&mix_out5>; 2574 }; 2575 }; 2576 2577 xbar_asrc_in1_port: port@63 { 2578 reg = <0x63>; 2579 2580 xbar_asrc_in1_ep: endpoint { 2581 remote-endpoint = <&asrc_in1_ep>; 2582 }; 2583 }; 2584 2585 port@64 { 2586 reg = <0x64>; 2587 2588 xbar_asrc_out1_ep: endpoint { 2589 remote-endpoint = <&asrc_out1_ep>; 2590 }; 2591 }; 2592 2593 xbar_asrc_in2_port: port@65 { 2594 reg = <0x65>; 2595 2596 xbar_asrc_in2_ep: endpoint { 2597 remote-endpoint = <&asrc_in2_ep>; 2598 }; 2599 }; 2600 2601 port@66 { 2602 reg = <0x66>; 2603 2604 xbar_asrc_out2_ep: endpoint { 2605 remote-endpoint = <&asrc_out2_ep>; 2606 }; 2607 }; 2608 2609 xbar_asrc_in3_port: port@67 { 2610 reg = <0x67>; 2611 2612 xbar_asrc_in3_ep: endpoint { 2613 remote-endpoint = <&asrc_in3_ep>; 2614 }; 2615 }; 2616 2617 port@68 { 2618 reg = <0x68>; 2619 2620 xbar_asrc_out3_ep: endpoint { 2621 remote-endpoint = <&asrc_out3_ep>; 2622 }; 2623 }; 2624 2625 xbar_asrc_in4_port: port@69 { 2626 reg = <0x69>; 2627 2628 xbar_asrc_in4_ep: endpoint { 2629 remote-endpoint = <&asrc_in4_ep>; 2630 }; 2631 }; 2632 2633 port@6a { 2634 reg = <0x6a>; 2635 2636 xbar_asrc_out4_ep: endpoint { 2637 remote-endpoint = <&asrc_out4_ep>; 2638 }; 2639 }; 2640 2641 xbar_asrc_in5_port: port@6b { 2642 reg = <0x6b>; 2643 2644 xbar_asrc_in5_ep: endpoint { 2645 remote-endpoint = <&asrc_in5_ep>; 2646 }; 2647 }; 2648 2649 port@6c { 2650 reg = <0x6c>; 2651 2652 xbar_asrc_out5_ep: endpoint { 2653 remote-endpoint = <&asrc_out5_ep>; 2654 }; 2655 }; 2656 2657 xbar_asrc_in6_port: port@6d { 2658 reg = <0x6d>; 2659 2660 xbar_asrc_in6_ep: endpoint { 2661 remote-endpoint = <&asrc_in6_ep>; 2662 }; 2663 }; 2664 2665 port@6e { 2666 reg = <0x6e>; 2667 2668 xbar_asrc_out6_ep: endpoint { 2669 remote-endpoint = <&asrc_out6_ep>; 2670 }; 2671 }; 2672 2673 xbar_asrc_in7_port: port@6f { 2674 reg = <0x6f>; 2675 2676 xbar_asrc_in7_ep: endpoint { 2677 remote-endpoint = <&asrc_in7_ep>; 2678 }; 2679 }; 2680 2681 xbar_ope1_in_port: port@70 { 2682 reg = <0x70>; 2683 2684 xbar_ope1_in_ep: endpoint { 2685 remote-endpoint = <&ope1_cif_in_ep>; 2686 }; 2687 }; 2688 2689 port@71 { 2690 reg = <0x71>; 2691 2692 xbar_ope1_out_ep: endpoint { 2693 remote-endpoint = <&ope1_cif_out_ep>; 2694 }; 2695 }; 2696 }; 2697 }; 2698 2699 adma: dma-controller@2930000 { 2700 compatible = "nvidia,tegra234-adma", 2701 "nvidia,tegra186-adma"; 2702 reg = <0x0 0x02930000 0x0 0x20000>; 2703 interrupt-parent = <&agic>; 2704 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 2706 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 2707 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2708 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2712 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 2721 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 2723 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 2724 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 2725 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 2726 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 2727 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 2728 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 2729 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 2730 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 2731 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 2732 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 2733 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 2734 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 2735 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2736 #dma-cells = <1>; 2737 clocks = <&bpmp TEGRA234_CLK_AHUB>; 2738 clock-names = "d_audio"; 2739 status = "disabled"; 2740 }; 2741 2742 agic: interrupt-controller@2a40000 { 2743 compatible = "nvidia,tegra234-agic", 2744 "nvidia,tegra210-agic"; 2745 #interrupt-cells = <3>; 2746 interrupt-controller; 2747 reg = <0x0 0x02a41000 0x0 0x1000>, 2748 <0x0 0x02a42000 0x0 0x2000>; 2749 interrupts = <GIC_SPI 145 2750 (GIC_CPU_MASK_SIMPLE(4) | 2751 IRQ_TYPE_LEVEL_HIGH)>; 2752 clocks = <&bpmp TEGRA234_CLK_APE>; 2753 clock-names = "clk"; 2754 status = "disabled"; 2755 }; 2756 }; 2757 2758 mc: memory-controller@2c00000 { 2759 compatible = "nvidia,tegra234-mc"; 2760 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ 2761 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/ 2762 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ 2763 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ 2764 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ 2765 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */ 2766 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */ 2767 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */ 2768 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */ 2769 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */ 2770 <0x0 0x01700000 0x0 0x10000>, /* MC8 */ 2771 <0x0 0x01710000 0x0 0x10000>, /* MC9 */ 2772 <0x0 0x01720000 0x0 0x10000>, /* MC10 */ 2773 <0x0 0x01730000 0x0 0x10000>, /* MC11 */ 2774 <0x0 0x01740000 0x0 0x10000>, /* MC12 */ 2775 <0x0 0x01750000 0x0 0x10000>, /* MC13 */ 2776 <0x0 0x01760000 0x0 0x10000>, /* MC14 */ 2777 <0x0 0x01770000 0x0 0x10000>; /* MC15 */ 2778 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 2779 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 2780 "ch11", "ch12", "ch13", "ch14", "ch15"; 2781 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2782 #interconnect-cells = <1>; 2783 status = "okay"; 2784 2785 #address-cells = <2>; 2786 #size-cells = <2>; 2787 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>, 2788 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>, 2789 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>; 2790 2791 /* 2792 * Bit 39 of addresses passing through the memory 2793 * controller selects the XBAR format used when memory 2794 * is accessed. This is used to transparently access 2795 * memory in the XBAR format used by the discrete GPU 2796 * (bit 39 set) or Tegra (bit 39 clear). 2797 * 2798 * As a consequence, the operating system must ensure 2799 * that bit 39 is never used implicitly, for example 2800 * via an I/O virtual address mapping of an IOMMU. If 2801 * devices require access to the XBAR switch, their 2802 * drivers must set this bit explicitly. 2803 * 2804 * Limit the DMA range for memory clients to [38:0]. 2805 */ 2806 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>; 2807 2808 emc: external-memory-controller@2c60000 { 2809 compatible = "nvidia,tegra234-emc"; 2810 reg = <0x0 0x02c60000 0x0 0x90000>, 2811 <0x0 0x01780000 0x0 0x80000>; 2812 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 2813 clocks = <&bpmp TEGRA234_CLK_EMC>; 2814 clock-names = "emc"; 2815 status = "okay"; 2816 2817 #interconnect-cells = <0>; 2818 2819 nvidia,bpmp = <&bpmp>; 2820 }; 2821 }; 2822 2823 uarta: serial@3100000 { 2824 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 2825 reg = <0x0 0x03100000 0x0 0x10000>; 2826 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2827 clocks = <&bpmp TEGRA234_CLK_UARTA>; 2828 resets = <&bpmp TEGRA234_RESET_UARTA>; 2829 dmas = <&gpcdma 8>, <&gpcdma 8>; 2830 dma-names = "rx", "tx"; 2831 status = "disabled"; 2832 }; 2833 2834 uarte: serial@3140000 { 2835 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 2836 reg = <0x0 0x03140000 0x0 0x10000>; 2837 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2838 clocks = <&bpmp TEGRA234_CLK_UARTE>; 2839 resets = <&bpmp TEGRA234_RESET_UARTE>; 2840 dmas = <&gpcdma 20>, <&gpcdma 20>; 2841 dma-names = "rx", "tx"; 2842 status = "disabled"; 2843 }; 2844 2845 gen1_i2c: i2c@3160000 { 2846 compatible = "nvidia,tegra194-i2c"; 2847 reg = <0x0 0x3160000 0x0 0x100>; 2848 status = "disabled"; 2849 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2850 #address-cells = <1>; 2851 #size-cells = <0>; 2852 clock-frequency = <400000>; 2853 clocks = <&bpmp TEGRA234_CLK_I2C1>, 2854 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2855 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 2856 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2857 clock-names = "div-clk", "parent"; 2858 resets = <&bpmp TEGRA234_RESET_I2C1>; 2859 reset-names = "i2c"; 2860 dmas = <&gpcdma 21>, <&gpcdma 21>; 2861 dma-names = "rx", "tx"; 2862 }; 2863 2864 cam_i2c: i2c@3180000 { 2865 compatible = "nvidia,tegra194-i2c"; 2866 reg = <0x0 0x3180000 0x0 0x100>; 2867 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 2868 #address-cells = <1>; 2869 #size-cells = <0>; 2870 status = "disabled"; 2871 clock-frequency = <400000>; 2872 clocks = <&bpmp TEGRA234_CLK_I2C3>, 2873 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2874 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 2875 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2876 clock-names = "div-clk", "parent"; 2877 resets = <&bpmp TEGRA234_RESET_I2C3>; 2878 reset-names = "i2c"; 2879 dmas = <&gpcdma 23>, <&gpcdma 23>; 2880 dma-names = "rx", "tx"; 2881 }; 2882 2883 dp_aux_ch1_i2c: i2c@3190000 { 2884 compatible = "nvidia,tegra194-i2c"; 2885 reg = <0x0 0x3190000 0x0 0x100>; 2886 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 2887 #address-cells = <1>; 2888 #size-cells = <0>; 2889 status = "disabled"; 2890 clock-frequency = <100000>; 2891 clocks = <&bpmp TEGRA234_CLK_I2C4>, 2892 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2893 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 2894 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2895 clock-names = "div-clk", "parent"; 2896 resets = <&bpmp TEGRA234_RESET_I2C4>; 2897 reset-names = "i2c"; 2898 dmas = <&gpcdma 26>, <&gpcdma 26>; 2899 dma-names = "rx", "tx"; 2900 }; 2901 2902 dp_aux_ch0_i2c: i2c@31b0000 { 2903 compatible = "nvidia,tegra194-i2c"; 2904 reg = <0x0 0x31b0000 0x0 0x100>; 2905 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2906 #address-cells = <1>; 2907 #size-cells = <0>; 2908 status = "disabled"; 2909 clock-frequency = <100000>; 2910 clocks = <&bpmp TEGRA234_CLK_I2C6>, 2911 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2912 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 2913 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2914 clock-names = "div-clk", "parent"; 2915 resets = <&bpmp TEGRA234_RESET_I2C6>; 2916 reset-names = "i2c"; 2917 dmas = <&gpcdma 30>, <&gpcdma 30>; 2918 dma-names = "rx", "tx"; 2919 }; 2920 2921 dp_aux_ch2_i2c: i2c@31c0000 { 2922 compatible = "nvidia,tegra194-i2c"; 2923 reg = <0x0 0x31c0000 0x0 0x100>; 2924 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2925 #address-cells = <1>; 2926 #size-cells = <0>; 2927 status = "disabled"; 2928 clock-frequency = <100000>; 2929 clocks = <&bpmp TEGRA234_CLK_I2C7>, 2930 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2931 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 2932 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2933 clock-names = "div-clk", "parent"; 2934 resets = <&bpmp TEGRA234_RESET_I2C7>; 2935 reset-names = "i2c"; 2936 dmas = <&gpcdma 27>, <&gpcdma 27>; 2937 dma-names = "rx", "tx"; 2938 }; 2939 2940 uarti: serial@31d0000 { 2941 compatible = "arm,sbsa-uart"; 2942 reg = <0x0 0x31d0000 0x0 0x10000>; 2943 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 2944 status = "disabled"; 2945 }; 2946 2947 dp_aux_ch3_i2c: i2c@31e0000 { 2948 compatible = "nvidia,tegra194-i2c"; 2949 reg = <0x0 0x31e0000 0x0 0x100>; 2950 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2951 #address-cells = <1>; 2952 #size-cells = <0>; 2953 status = "disabled"; 2954 clock-frequency = <100000>; 2955 clocks = <&bpmp TEGRA234_CLK_I2C9>, 2956 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2957 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 2958 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2959 clock-names = "div-clk", "parent"; 2960 resets = <&bpmp TEGRA234_RESET_I2C9>; 2961 reset-names = "i2c"; 2962 dmas = <&gpcdma 31>, <&gpcdma 31>; 2963 dma-names = "rx", "tx"; 2964 }; 2965 2966 spi@3210000 { 2967 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 2968 reg = <0x0 0x03210000 0x0 0x1000>; 2969 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2970 #address-cells = <1>; 2971 #size-cells = <0>; 2972 clocks = <&bpmp TEGRA234_CLK_SPI1>; 2973 assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>; 2974 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2975 clock-names = "spi"; 2976 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 2977 resets = <&bpmp TEGRA234_RESET_SPI1>; 2978 reset-names = "spi"; 2979 dmas = <&gpcdma 15>, <&gpcdma 15>; 2980 dma-names = "rx", "tx"; 2981 dma-coherent; 2982 status = "disabled"; 2983 }; 2984 2985 spi@3230000 { 2986 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 2987 reg = <0x0 0x03230000 0x0 0x1000>; 2988 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2989 #address-cells = <1>; 2990 #size-cells = <0>; 2991 clocks = <&bpmp TEGRA234_CLK_SPI3>; 2992 clock-names = "spi"; 2993 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 2994 assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>; 2995 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 2996 resets = <&bpmp TEGRA234_RESET_SPI3>; 2997 reset-names = "spi"; 2998 dmas = <&gpcdma 17>, <&gpcdma 17>; 2999 dma-names = "rx", "tx"; 3000 dma-coherent; 3001 status = "disabled"; 3002 }; 3003 3004 spi@3270000 { 3005 compatible = "nvidia,tegra234-qspi"; 3006 reg = <0x0 0x3270000 0x0 0x1000>; 3007 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 3008 #address-cells = <1>; 3009 #size-cells = <0>; 3010 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 3011 <&bpmp TEGRA234_CLK_QSPI0_PM>; 3012 clock-names = "qspi", "qspi_out"; 3013 resets = <&bpmp TEGRA234_RESET_QSPI0>; 3014 iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>; 3015 assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 3016 <&bpmp TEGRA234_CLK_QSPI0_PM>; 3017 assigned-clock-rates = <199999999 99999999>; 3018 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; 3019 status = "disabled"; 3020 }; 3021 3022 pwm1: pwm@3280000 { 3023 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3024 reg = <0x0 0x3280000 0x0 0x10000>; 3025 clocks = <&bpmp TEGRA234_CLK_PWM1>; 3026 resets = <&bpmp TEGRA234_RESET_PWM1>; 3027 reset-names = "pwm"; 3028 status = "disabled"; 3029 #pwm-cells = <2>; 3030 }; 3031 3032 pwm2: pwm@3290000 { 3033 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3034 reg = <0x0 0x3290000 0x0 0x10000>; 3035 clocks = <&bpmp TEGRA234_CLK_PWM2>; 3036 resets = <&bpmp TEGRA234_RESET_PWM2>; 3037 reset-names = "pwm"; 3038 status = "disabled"; 3039 #pwm-cells = <2>; 3040 }; 3041 3042 pwm3: pwm@32a0000 { 3043 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3044 reg = <0x0 0x32a0000 0x0 0x10000>; 3045 clocks = <&bpmp TEGRA234_CLK_PWM3>; 3046 resets = <&bpmp TEGRA234_RESET_PWM3>; 3047 reset-names = "pwm"; 3048 status = "disabled"; 3049 #pwm-cells = <2>; 3050 }; 3051 3052 pwm5: pwm@32c0000 { 3053 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3054 reg = <0x0 0x32c0000 0x0 0x10000>; 3055 clocks = <&bpmp TEGRA234_CLK_PWM5>; 3056 resets = <&bpmp TEGRA234_RESET_PWM5>; 3057 reset-names = "pwm"; 3058 status = "disabled"; 3059 #pwm-cells = <2>; 3060 }; 3061 3062 pwm6: pwm@32d0000 { 3063 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3064 reg = <0x0 0x32d0000 0x0 0x10000>; 3065 clocks = <&bpmp TEGRA234_CLK_PWM6>; 3066 resets = <&bpmp TEGRA234_RESET_PWM6>; 3067 reset-names = "pwm"; 3068 status = "disabled"; 3069 #pwm-cells = <2>; 3070 }; 3071 3072 pwm7: pwm@32e0000 { 3073 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3074 reg = <0x0 0x32e0000 0x0 0x10000>; 3075 clocks = <&bpmp TEGRA234_CLK_PWM7>; 3076 resets = <&bpmp TEGRA234_RESET_PWM7>; 3077 reset-names = "pwm"; 3078 status = "disabled"; 3079 #pwm-cells = <2>; 3080 }; 3081 3082 pwm8: pwm@32f0000 { 3083 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 3084 reg = <0x0 0x32f0000 0x0 0x10000>; 3085 clocks = <&bpmp TEGRA234_CLK_PWM8>; 3086 resets = <&bpmp TEGRA234_RESET_PWM8>; 3087 reset-names = "pwm"; 3088 status = "disabled"; 3089 #pwm-cells = <2>; 3090 }; 3091 3092 spi@3300000 { 3093 compatible = "nvidia,tegra234-qspi"; 3094 reg = <0x0 0x3300000 0x0 0x1000>; 3095 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 3096 #address-cells = <1>; 3097 #size-cells = <0>; 3098 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 3099 <&bpmp TEGRA234_CLK_QSPI1_PM>; 3100 clock-names = "qspi", "qspi_out"; 3101 resets = <&bpmp TEGRA234_RESET_QSPI1>; 3102 iommus = <&smmu_niso1 TEGRA234_SID_QSPI1>; 3103 assigned-clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 3104 <&bpmp TEGRA234_CLK_QSPI1_PM>; 3105 assigned-clock-rates = <199999999 99999999>; 3106 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; 3107 status = "disabled"; 3108 }; 3109 3110 mmc@3400000 { 3111 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 3112 reg = <0x0 0x03400000 0x0 0x20000>; 3113 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 3114 clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 3115 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 3116 clock-names = "sdhci", "tmclk"; 3117 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>, 3118 <&bpmp TEGRA234_CLK_PLLC4_MUXED>; 3119 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>, 3120 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>; 3121 resets = <&bpmp TEGRA234_RESET_SDMMC1>; 3122 reset-names = "sdhci"; 3123 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>, 3124 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>; 3125 interconnect-names = "dma-mem", "write"; 3126 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>; 3127 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8"; 3128 pinctrl-0 = <&sdmmc1_3v3>; 3129 pinctrl-1 = <&sdmmc1_1v8>; 3130 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>; 3131 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>; 3132 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>; 3133 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>; 3134 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>; 3135 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>; 3136 nvidia,default-tap = <14>; 3137 nvidia,default-trim = <0x8>; 3138 sd-uhs-sdr25; 3139 sd-uhs-sdr50; 3140 sd-uhs-ddr50; 3141 sd-uhs-sdr104; 3142 status = "disabled"; 3143 }; 3144 3145 mmc@3460000 { 3146 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 3147 reg = <0x0 0x03460000 0x0 0x20000>; 3148 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 3149 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 3150 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 3151 clock-names = "sdhci", "tmclk"; 3152 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 3153 <&bpmp TEGRA234_CLK_PLLC4>; 3154 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 3155 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 3156 reset-names = "sdhci"; 3157 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 3158 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 3159 interconnect-names = "dma-mem", "write"; 3160 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 3161 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 3162 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 3163 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 3164 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 3165 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 3166 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 3167 nvidia,default-tap = <0x8>; 3168 nvidia,default-trim = <0x14>; 3169 nvidia,dqs-trim = <40>; 3170 supports-cqe; 3171 status = "disabled"; 3172 }; 3173 3174 hda@3510000 { 3175 compatible = "nvidia,tegra234-hda"; 3176 reg = <0x0 0x3510000 0x0 0x10000>; 3177 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 3178 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 3179 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 3180 clock-names = "hda", "hda2codec_2x"; 3181 resets = <&bpmp TEGRA234_RESET_HDA>, 3182 <&bpmp TEGRA234_RESET_HDACODEC>; 3183 reset-names = "hda", "hda2codec_2x"; 3184 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 3185 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 3186 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 3187 interconnect-names = "dma-mem", "write"; 3188 iommus = <&smmu_niso0 TEGRA234_SID_HDA>; 3189 status = "disabled"; 3190 }; 3191 3192 xusb_padctl: padctl@3520000 { 3193 compatible = "nvidia,tegra234-xusb-padctl"; 3194 reg = <0x0 0x03520000 0x0 0x20000>, 3195 <0x0 0x03540000 0x0 0x10000>; 3196 reg-names = "padctl", "ao"; 3197 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 3198 3199 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>; 3200 reset-names = "padctl"; 3201 3202 status = "disabled"; 3203 3204 pads { 3205 usb2 { 3206 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>; 3207 clock-names = "trk"; 3208 3209 lanes { 3210 usb2-0 { 3211 nvidia,function = "xusb"; 3212 status = "disabled"; 3213 #phy-cells = <0>; 3214 }; 3215 3216 usb2-1 { 3217 nvidia,function = "xusb"; 3218 status = "disabled"; 3219 #phy-cells = <0>; 3220 }; 3221 3222 usb2-2 { 3223 nvidia,function = "xusb"; 3224 status = "disabled"; 3225 #phy-cells = <0>; 3226 }; 3227 3228 usb2-3 { 3229 nvidia,function = "xusb"; 3230 status = "disabled"; 3231 #phy-cells = <0>; 3232 }; 3233 }; 3234 }; 3235 3236 usb3 { 3237 lanes { 3238 usb3-0 { 3239 nvidia,function = "xusb"; 3240 status = "disabled"; 3241 #phy-cells = <0>; 3242 }; 3243 3244 usb3-1 { 3245 nvidia,function = "xusb"; 3246 status = "disabled"; 3247 #phy-cells = <0>; 3248 }; 3249 3250 usb3-2 { 3251 nvidia,function = "xusb"; 3252 status = "disabled"; 3253 #phy-cells = <0>; 3254 }; 3255 3256 usb3-3 { 3257 nvidia,function = "xusb"; 3258 status = "disabled"; 3259 #phy-cells = <0>; 3260 }; 3261 }; 3262 }; 3263 }; 3264 3265 ports { 3266 usb2-0 { 3267 status = "disabled"; 3268 }; 3269 3270 usb2-1 { 3271 status = "disabled"; 3272 }; 3273 3274 usb2-2 { 3275 status = "disabled"; 3276 }; 3277 3278 usb2-3 { 3279 status = "disabled"; 3280 }; 3281 3282 usb3-0 { 3283 status = "disabled"; 3284 }; 3285 3286 usb3-1 { 3287 status = "disabled"; 3288 }; 3289 3290 usb3-2 { 3291 status = "disabled"; 3292 }; 3293 3294 usb3-3 { 3295 status = "disabled"; 3296 }; 3297 }; 3298 }; 3299 3300 usb@3550000 { 3301 compatible = "nvidia,tegra234-xudc"; 3302 reg = <0x0 0x03550000 0x0 0x8000>, 3303 <0x0 0x03558000 0x0 0x8000>; 3304 reg-names = "base", "fpci"; 3305 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 3306 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>, 3307 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 3308 <&bpmp TEGRA234_CLK_XUSB_SS>, 3309 <&bpmp TEGRA234_CLK_XUSB_FS>; 3310 clock-names = "dev", "ss", "ss_src", "fs_src"; 3311 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>, 3312 <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>; 3313 interconnect-names = "dma-mem", "write"; 3314 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>; 3315 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>, 3316 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 3317 power-domain-names = "dev", "ss"; 3318 nvidia,xusb-padctl = <&xusb_padctl>; 3319 dma-coherent; 3320 status = "disabled"; 3321 }; 3322 3323 usb@3610000 { 3324 compatible = "nvidia,tegra234-xusb"; 3325 reg = <0x0 0x03610000 0x0 0x40000>, 3326 <0x0 0x03600000 0x0 0x10000>, 3327 <0x0 0x03650000 0x0 0x10000>; 3328 reg-names = "hcd", "fpci", "bar2"; 3329 3330 interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 3331 <&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 3332 <&pmc 76 IRQ_TYPE_LEVEL_HIGH>, 3333 <&pmc 77 IRQ_TYPE_LEVEL_HIGH>, 3334 <&pmc 78 IRQ_TYPE_LEVEL_HIGH>, 3335 <&pmc 79 IRQ_TYPE_LEVEL_HIGH>, 3336 <&pmc 80 IRQ_TYPE_LEVEL_HIGH>, 3337 <&pmc 81 IRQ_TYPE_LEVEL_HIGH>, 3338 <&pmc 82 IRQ_TYPE_LEVEL_HIGH>; 3339 3340 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 3341 <&bpmp TEGRA234_CLK_XUSB_FALCON>, 3342 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 3343 <&bpmp TEGRA234_CLK_XUSB_SS>, 3344 <&bpmp TEGRA234_CLK_CLK_M>, 3345 <&bpmp TEGRA234_CLK_XUSB_FS>, 3346 <&bpmp TEGRA234_CLK_UTMIP_PLL>, 3347 <&bpmp TEGRA234_CLK_CLK_M>, 3348 <&bpmp TEGRA234_CLK_PLLE>; 3349 clock-names = "xusb_host", "xusb_falcon_src", 3350 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 3351 "xusb_fs_src", "pll_u_480m", "clk_m", 3352 "pll_e"; 3353 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 3354 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 3355 interconnect-names = "dma-mem", "write"; 3356 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 3357 3358 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 3359 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 3360 power-domain-names = "xusb_host", "xusb_ss"; 3361 3362 nvidia,xusb-padctl = <&xusb_padctl>; 3363 dma-coherent; 3364 status = "disabled"; 3365 }; 3366 3367 fuse@3810000 { 3368 compatible = "nvidia,tegra234-efuse"; 3369 reg = <0x0 0x03810000 0x0 0x10000>; 3370 clocks = <&bpmp TEGRA234_CLK_FUSE>; 3371 clock-names = "fuse"; 3372 }; 3373 3374 hte_lic: hardware-timestamp@3aa0000 { 3375 compatible = "nvidia,tegra234-gte-lic"; 3376 reg = <0x0 0x3aa0000 0x0 0x10000>; 3377 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3378 nvidia,int-threshold = <1>; 3379 #timestamp-cells = <1>; 3380 }; 3381 3382 hsp_top0: hsp@3c00000 { 3383 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 3384 reg = <0x0 0x03c00000 0x0 0xa0000>; 3385 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 3394 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 3395 "shared3", "shared4", "shared5", "shared6", 3396 "shared7"; 3397 #mbox-cells = <2>; 3398 }; 3399 3400 p2u_hsio_0: phy@3e00000 { 3401 compatible = "nvidia,tegra234-p2u"; 3402 reg = <0x0 0x03e00000 0x0 0x10000>; 3403 reg-names = "ctl"; 3404 3405 #phy-cells = <0>; 3406 }; 3407 3408 p2u_hsio_1: phy@3e10000 { 3409 compatible = "nvidia,tegra234-p2u"; 3410 reg = <0x0 0x03e10000 0x0 0x10000>; 3411 reg-names = "ctl"; 3412 3413 #phy-cells = <0>; 3414 }; 3415 3416 p2u_hsio_2: phy@3e20000 { 3417 compatible = "nvidia,tegra234-p2u"; 3418 reg = <0x0 0x03e20000 0x0 0x10000>; 3419 reg-names = "ctl"; 3420 3421 #phy-cells = <0>; 3422 }; 3423 3424 p2u_hsio_3: phy@3e30000 { 3425 compatible = "nvidia,tegra234-p2u"; 3426 reg = <0x0 0x03e30000 0x0 0x10000>; 3427 reg-names = "ctl"; 3428 3429 #phy-cells = <0>; 3430 }; 3431 3432 p2u_hsio_4: phy@3e40000 { 3433 compatible = "nvidia,tegra234-p2u"; 3434 reg = <0x0 0x03e40000 0x0 0x10000>; 3435 reg-names = "ctl"; 3436 3437 #phy-cells = <0>; 3438 }; 3439 3440 p2u_hsio_5: phy@3e50000 { 3441 compatible = "nvidia,tegra234-p2u"; 3442 reg = <0x0 0x03e50000 0x0 0x10000>; 3443 reg-names = "ctl"; 3444 3445 #phy-cells = <0>; 3446 }; 3447 3448 p2u_hsio_6: phy@3e60000 { 3449 compatible = "nvidia,tegra234-p2u"; 3450 reg = <0x0 0x03e60000 0x0 0x10000>; 3451 reg-names = "ctl"; 3452 3453 #phy-cells = <0>; 3454 }; 3455 3456 p2u_hsio_7: phy@3e70000 { 3457 compatible = "nvidia,tegra234-p2u"; 3458 reg = <0x0 0x03e70000 0x0 0x10000>; 3459 reg-names = "ctl"; 3460 3461 #phy-cells = <0>; 3462 }; 3463 3464 p2u_nvhs_0: phy@3e90000 { 3465 compatible = "nvidia,tegra234-p2u"; 3466 reg = <0x0 0x03e90000 0x0 0x10000>; 3467 reg-names = "ctl"; 3468 3469 #phy-cells = <0>; 3470 }; 3471 3472 p2u_nvhs_1: phy@3ea0000 { 3473 compatible = "nvidia,tegra234-p2u"; 3474 reg = <0x0 0x03ea0000 0x0 0x10000>; 3475 reg-names = "ctl"; 3476 3477 #phy-cells = <0>; 3478 }; 3479 3480 p2u_nvhs_2: phy@3eb0000 { 3481 compatible = "nvidia,tegra234-p2u"; 3482 reg = <0x0 0x03eb0000 0x0 0x10000>; 3483 reg-names = "ctl"; 3484 3485 #phy-cells = <0>; 3486 }; 3487 3488 p2u_nvhs_3: phy@3ec0000 { 3489 compatible = "nvidia,tegra234-p2u"; 3490 reg = <0x0 0x03ec0000 0x0 0x10000>; 3491 reg-names = "ctl"; 3492 3493 #phy-cells = <0>; 3494 }; 3495 3496 p2u_nvhs_4: phy@3ed0000 { 3497 compatible = "nvidia,tegra234-p2u"; 3498 reg = <0x0 0x03ed0000 0x0 0x10000>; 3499 reg-names = "ctl"; 3500 3501 #phy-cells = <0>; 3502 }; 3503 3504 p2u_nvhs_5: phy@3ee0000 { 3505 compatible = "nvidia,tegra234-p2u"; 3506 reg = <0x0 0x03ee0000 0x0 0x10000>; 3507 reg-names = "ctl"; 3508 3509 #phy-cells = <0>; 3510 }; 3511 3512 p2u_nvhs_6: phy@3ef0000 { 3513 compatible = "nvidia,tegra234-p2u"; 3514 reg = <0x0 0x03ef0000 0x0 0x10000>; 3515 reg-names = "ctl"; 3516 3517 #phy-cells = <0>; 3518 }; 3519 3520 p2u_nvhs_7: phy@3f00000 { 3521 compatible = "nvidia,tegra234-p2u"; 3522 reg = <0x0 0x03f00000 0x0 0x10000>; 3523 reg-names = "ctl"; 3524 3525 #phy-cells = <0>; 3526 }; 3527 3528 p2u_gbe_0: phy@3f20000 { 3529 compatible = "nvidia,tegra234-p2u"; 3530 reg = <0x0 0x03f20000 0x0 0x10000>; 3531 reg-names = "ctl"; 3532 3533 #phy-cells = <0>; 3534 }; 3535 3536 p2u_gbe_1: phy@3f30000 { 3537 compatible = "nvidia,tegra234-p2u"; 3538 reg = <0x0 0x03f30000 0x0 0x10000>; 3539 reg-names = "ctl"; 3540 3541 #phy-cells = <0>; 3542 }; 3543 3544 p2u_gbe_2: phy@3f40000 { 3545 compatible = "nvidia,tegra234-p2u"; 3546 reg = <0x0 0x03f40000 0x0 0x10000>; 3547 reg-names = "ctl"; 3548 3549 #phy-cells = <0>; 3550 }; 3551 3552 p2u_gbe_3: phy@3f50000 { 3553 compatible = "nvidia,tegra234-p2u"; 3554 reg = <0x0 0x03f50000 0x0 0x10000>; 3555 reg-names = "ctl"; 3556 3557 #phy-cells = <0>; 3558 }; 3559 3560 p2u_gbe_4: phy@3f60000 { 3561 compatible = "nvidia,tegra234-p2u"; 3562 reg = <0x0 0x03f60000 0x0 0x10000>; 3563 reg-names = "ctl"; 3564 3565 #phy-cells = <0>; 3566 }; 3567 3568 p2u_gbe_5: phy@3f70000 { 3569 compatible = "nvidia,tegra234-p2u"; 3570 reg = <0x0 0x03f70000 0x0 0x10000>; 3571 reg-names = "ctl"; 3572 3573 #phy-cells = <0>; 3574 }; 3575 3576 p2u_gbe_6: phy@3f80000 { 3577 compatible = "nvidia,tegra234-p2u"; 3578 reg = <0x0 0x03f80000 0x0 0x10000>; 3579 reg-names = "ctl"; 3580 3581 #phy-cells = <0>; 3582 }; 3583 3584 p2u_gbe_7: phy@3f90000 { 3585 compatible = "nvidia,tegra234-p2u"; 3586 reg = <0x0 0x03f90000 0x0 0x10000>; 3587 reg-names = "ctl"; 3588 3589 #phy-cells = <0>; 3590 }; 3591 3592 ethernet@6800000 { 3593 compatible = "nvidia,tegra234-mgbe"; 3594 reg = <0x0 0x06800000 0x0 0x10000>, 3595 <0x0 0x06810000 0x0 0x10000>, 3596 <0x0 0x068a0000 0x0 0x10000>; 3597 reg-names = "hypervisor", "mac", "xpcs"; 3598 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 3599 interrupt-names = "common"; 3600 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>, 3601 <&bpmp TEGRA234_CLK_MGBE0_MAC>, 3602 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>, 3603 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>, 3604 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>, 3605 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>, 3606 <&bpmp TEGRA234_CLK_MGBE0_TX>, 3607 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>, 3608 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>, 3609 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, 3610 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, 3611 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; 3612 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 3613 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 3614 "rx-pcs", "tx-pcs"; 3615 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, 3616 <&bpmp TEGRA234_RESET_MGBE0_PCS>; 3617 reset-names = "mac", "pcs"; 3618 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>, 3619 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>; 3620 interconnect-names = "dma-mem", "write"; 3621 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>; 3622 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>; 3623 status = "disabled"; 3624 3625 snps,axi-config = <&mgbe0_axi_setup>; 3626 3627 mgbe0_axi_setup: stmmac-axi-config { 3628 snps,blen = <256 128 64 32>; 3629 snps,rd_osr_lmt = <63>; 3630 snps,wr_osr_lmt = <63>; 3631 }; 3632 }; 3633 3634 ethernet@6900000 { 3635 compatible = "nvidia,tegra234-mgbe"; 3636 reg = <0x0 0x06900000 0x0 0x10000>, 3637 <0x0 0x06910000 0x0 0x10000>, 3638 <0x0 0x069a0000 0x0 0x10000>; 3639 reg-names = "hypervisor", "mac", "xpcs"; 3640 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 3641 interrupt-names = "common"; 3642 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>, 3643 <&bpmp TEGRA234_CLK_MGBE1_MAC>, 3644 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>, 3645 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>, 3646 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>, 3647 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>, 3648 <&bpmp TEGRA234_CLK_MGBE1_TX>, 3649 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>, 3650 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>, 3651 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, 3652 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, 3653 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; 3654 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 3655 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 3656 "rx-pcs", "tx-pcs"; 3657 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, 3658 <&bpmp TEGRA234_RESET_MGBE1_PCS>; 3659 reset-names = "mac", "pcs"; 3660 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>, 3661 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>; 3662 interconnect-names = "dma-mem", "write"; 3663 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>; 3664 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>; 3665 status = "disabled"; 3666 3667 snps,axi-config = <&mgbe1_axi_setup>; 3668 3669 mgbe1_axi_setup: stmmac-axi-config { 3670 snps,blen = <256 128 64 32>; 3671 snps,rd_osr_lmt = <63>; 3672 snps,wr_osr_lmt = <63>; 3673 }; 3674 }; 3675 3676 ethernet@6a00000 { 3677 compatible = "nvidia,tegra234-mgbe"; 3678 reg = <0x0 0x06a00000 0x0 0x10000>, 3679 <0x0 0x06a10000 0x0 0x10000>, 3680 <0x0 0x06aa0000 0x0 0x10000>; 3681 reg-names = "hypervisor", "mac", "xpcs"; 3682 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 3683 interrupt-names = "common"; 3684 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>, 3685 <&bpmp TEGRA234_CLK_MGBE2_MAC>, 3686 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>, 3687 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>, 3688 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>, 3689 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>, 3690 <&bpmp TEGRA234_CLK_MGBE2_TX>, 3691 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>, 3692 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>, 3693 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, 3694 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, 3695 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; 3696 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 3697 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 3698 "rx-pcs", "tx-pcs"; 3699 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, 3700 <&bpmp TEGRA234_RESET_MGBE2_PCS>; 3701 reset-names = "mac", "pcs"; 3702 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>, 3703 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>; 3704 interconnect-names = "dma-mem", "write"; 3705 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>; 3706 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 3707 status = "disabled"; 3708 3709 snps,axi-config = <&mgbe2_axi_setup>; 3710 3711 mgbe2_axi_setup: stmmac-axi-config { 3712 snps,blen = <256 128 64 32>; 3713 snps,rd_osr_lmt = <63>; 3714 snps,wr_osr_lmt = <63>; 3715 }; 3716 }; 3717 3718 ethernet@6b00000 { 3719 compatible = "nvidia,tegra234-mgbe"; 3720 reg = <0x0 0x06b00000 0x0 0x10000>, 3721 <0x0 0x06b10000 0x0 0x10000>, 3722 <0x0 0x06ba0000 0x0 0x10000>; 3723 reg-names = "hypervisor", "mac", "xpcs"; 3724 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 3725 interrupt-names = "common"; 3726 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>, 3727 <&bpmp TEGRA234_CLK_MGBE3_MAC>, 3728 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>, 3729 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>, 3730 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>, 3731 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>, 3732 <&bpmp TEGRA234_CLK_MGBE3_TX>, 3733 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>, 3734 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>, 3735 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, 3736 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, 3737 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; 3738 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", 3739 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", 3740 "rx-pcs", "tx-pcs"; 3741 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, 3742 <&bpmp TEGRA234_RESET_MGBE3_PCS>; 3743 reset-names = "mac", "pcs"; 3744 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>, 3745 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>; 3746 interconnect-names = "dma-mem", "write"; 3747 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>; 3748 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>; 3749 status = "disabled"; 3750 }; 3751 3752 smmu_niso1: iommu@8000000 { 3753 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 3754 reg = <0x0 0x8000000 0x0 0x1000000>, 3755 <0x0 0x7000000 0x0 0x1000000>; 3756 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3787 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3788 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3789 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3790 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3793 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3794 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3795 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3796 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3797 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3798 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3799 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3810 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3811 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3812 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3813 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3814 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3815 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3816 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3817 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3818 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3819 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3820 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3821 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3822 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3823 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3824 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3825 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3826 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3827 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3828 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3829 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3830 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3831 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3832 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3833 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3834 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3835 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3836 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3837 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3838 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3839 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3840 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3841 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3857 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3858 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3859 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3862 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3864 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3865 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3867 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3868 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3869 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3870 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3871 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3872 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3873 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3874 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3875 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3876 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3877 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3878 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3879 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3880 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3881 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3882 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3883 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3884 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 3885 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 3886 stream-match-mask = <0x7f80>; 3887 #global-interrupts = <2>; 3888 #iommu-cells = <1>; 3889 3890 nvidia,memory-controller = <&mc>; 3891 status = "okay"; 3892 }; 3893 3894 sce-fabric@b600000 { 3895 compatible = "nvidia,tegra234-sce-fabric"; 3896 reg = <0x0 0xb600000 0x0 0x40000>; 3897 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 3898 status = "disabled"; 3899 }; 3900 3901 rce-fabric@be00000 { 3902 compatible = "nvidia,tegra234-rce-fabric"; 3903 reg = <0x0 0xbe00000 0x0 0x40000>; 3904 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 3905 status = "okay"; 3906 }; 3907 3908 hsp_aon: hsp@c150000 { 3909 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 3910 reg = <0x0 0x0c150000 0x0 0x90000>; 3911 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 3912 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 3913 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3914 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 3915 /* 3916 * Shared interrupt 0 is routed only to AON/SPE, so 3917 * we only have 4 shared interrupts for the CCPLEX. 3918 */ 3919 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 3920 #mbox-cells = <2>; 3921 }; 3922 3923 hte_aon: hardware-timestamp@c1e0000 { 3924 compatible = "nvidia,tegra234-gte-aon"; 3925 reg = <0x0 0xc1e0000 0x0 0x10000>; 3926 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3927 nvidia,int-threshold = <1>; 3928 nvidia,gpio-controller = <&gpio_aon>; 3929 #timestamp-cells = <1>; 3930 }; 3931 3932 gen2_i2c: i2c@c240000 { 3933 compatible = "nvidia,tegra194-i2c"; 3934 reg = <0x0 0xc240000 0x0 0x100>; 3935 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 3936 #address-cells = <1>; 3937 #size-cells = <0>; 3938 status = "disabled"; 3939 clock-frequency = <100000>; 3940 clocks = <&bpmp TEGRA234_CLK_I2C2>, 3941 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3942 clock-names = "div-clk", "parent"; 3943 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 3944 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3945 resets = <&bpmp TEGRA234_RESET_I2C2>; 3946 reset-names = "i2c"; 3947 dmas = <&gpcdma 22>, <&gpcdma 22>; 3948 dma-names = "rx", "tx"; 3949 }; 3950 3951 gen8_i2c: i2c@c250000 { 3952 compatible = "nvidia,tegra194-i2c"; 3953 reg = <0x0 0xc250000 0x0 0x100>; 3954 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3955 #address-cells = <1>; 3956 #size-cells = <0>; 3957 status = "disabled"; 3958 clock-frequency = <400000>; 3959 clocks = <&bpmp TEGRA234_CLK_I2C8>, 3960 <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3961 clock-names = "div-clk", "parent"; 3962 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 3963 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3964 resets = <&bpmp TEGRA234_RESET_I2C8>; 3965 reset-names = "i2c"; 3966 dmas = <&gpcdma 0>, <&gpcdma 0>; 3967 dma-names = "rx", "tx"; 3968 }; 3969 3970 spi@c260000 { 3971 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 3972 reg = <0x0 0x0c260000 0x0 0x1000>; 3973 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 3974 #address-cells = <1>; 3975 #size-cells = <0>; 3976 clocks = <&bpmp TEGRA234_CLK_SPI2>; 3977 clock-names = "spi"; 3978 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 3979 assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>; 3980 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 3981 resets = <&bpmp TEGRA234_RESET_SPI2>; 3982 reset-names = "spi"; 3983 dmas = <&gpcdma 16>, <&gpcdma 16>; 3984 dma-names = "rx", "tx"; 3985 dma-coherent; 3986 status = "disabled"; 3987 }; 3988 3989 rtc@c2a0000 { 3990 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 3991 reg = <0x0 0x0c2a0000 0x0 0x10000>; 3992 interrupt-parent = <&pmc>; 3993 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 3994 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 3995 clock-names = "rtc"; 3996 status = "disabled"; 3997 }; 3998 3999 gpio_aon: gpio@c2f0000 { 4000 compatible = "nvidia,tegra234-gpio-aon"; 4001 reg-names = "security", "gpio"; 4002 reg = <0x0 0x0c2f0000 0x0 0x1000>, 4003 <0x0 0x0c2f1000 0x0 0x1000>; 4004 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 4005 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 4006 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 4007 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 4008 #interrupt-cells = <2>; 4009 interrupt-controller; 4010 #gpio-cells = <2>; 4011 gpio-controller; 4012 gpio-ranges = <&pinmux_aon 0 0 32>; 4013 }; 4014 4015 pinmux_aon: pinmux@c300000 { 4016 compatible = "nvidia,tegra234-pinmux-aon"; 4017 reg = <0x0 0xc300000 0x0 0x4000>; 4018 }; 4019 4020 pwm4: pwm@c340000 { 4021 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm"; 4022 reg = <0x0 0xc340000 0x0 0x10000>; 4023 clocks = <&bpmp TEGRA234_CLK_PWM4>; 4024 resets = <&bpmp TEGRA234_RESET_PWM4>; 4025 reset-names = "pwm"; 4026 status = "disabled"; 4027 #pwm-cells = <2>; 4028 }; 4029 4030 pmc: pmc@c360000 { 4031 compatible = "nvidia,tegra234-pmc"; 4032 reg = <0x0 0x0c360000 0x0 0x10000>, 4033 <0x0 0x0c370000 0x0 0x10000>, 4034 <0x0 0x0c380000 0x0 0x10000>, 4035 <0x0 0x0c390000 0x0 0x10000>, 4036 <0x0 0x0c3a0000 0x0 0x10000>; 4037 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 4038 4039 #interrupt-cells = <2>; 4040 interrupt-controller; 4041 4042 sdmmc1_1v8: sdmmc1-1v8 { 4043 pins = "sdmmc1-hv"; 4044 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 4045 }; 4046 4047 sdmmc1_3v3: sdmmc1-3v3 { 4048 pins = "sdmmc1-hv"; 4049 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 4050 }; 4051 4052 sdmmc3_1v8: sdmmc3-1v8 { 4053 pins = "sdmmc3-hv"; 4054 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 4055 }; 4056 4057 sdmmc3_3v3: sdmmc3-3v3 { 4058 pins = "sdmmc3-hv"; 4059 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 4060 }; 4061 }; 4062 4063 aon-fabric@c600000 { 4064 compatible = "nvidia,tegra234-aon-fabric"; 4065 reg = <0x0 0xc600000 0x0 0x40000>; 4066 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 4067 status = "okay"; 4068 }; 4069 4070 bpmp-fabric@d600000 { 4071 compatible = "nvidia,tegra234-bpmp-fabric"; 4072 reg = <0x0 0xd600000 0x0 0x40000>; 4073 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4074 status = "okay"; 4075 }; 4076 4077 dce-fabric@de00000 { 4078 compatible = "nvidia,tegra234-dce-fabric"; 4079 reg = <0x0 0xde00000 0x0 0x40000>; 4080 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 4081 status = "okay"; 4082 }; 4083 4084 ccplex@e000000 { 4085 compatible = "nvidia,tegra234-ccplex-cluster"; 4086 reg = <0x0 0x0e000000 0x0 0x5ffff>; 4087 nvidia,bpmp = <&bpmp>; 4088 status = "okay"; 4089 }; 4090 4091 gic: interrupt-controller@f400000 { 4092 compatible = "arm,gic-v3"; 4093 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */ 4094 <0x0 0x0f440000 0x0 0x200000>; /* GICR */ 4095 interrupt-parent = <&gic>; 4096 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 4097 4098 #redistributor-regions = <1>; 4099 #interrupt-cells = <3>; 4100 interrupt-controller; 4101 4102 #address-cells = <0>; 4103 }; 4104 4105 smmu_iso: iommu@10000000 { 4106 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 4107 reg = <0x0 0x10000000 0x0 0x1000000>; 4108 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4138 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4140 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4142 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4143 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4144 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4145 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4146 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4147 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4148 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4149 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4150 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4151 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4152 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4153 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4154 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4155 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4156 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4157 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4158 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4160 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4161 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4162 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4163 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4164 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4165 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4166 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4167 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4168 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4169 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4170 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4172 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4173 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4174 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4175 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4176 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4178 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4179 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4180 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4181 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4182 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4183 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4184 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4185 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4186 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4187 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4188 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4190 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4191 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4195 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4198 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4199 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4200 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4201 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4202 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4203 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4204 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4205 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4206 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4207 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4208 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4209 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4210 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4211 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4212 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4213 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4214 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4215 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4216 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4217 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4218 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4219 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4220 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4221 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4222 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4223 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4224 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4225 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4228 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4229 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4230 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4231 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4232 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4233 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4234 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4235 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4236 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 4237 stream-match-mask = <0x7f80>; 4238 #global-interrupts = <1>; 4239 #iommu-cells = <1>; 4240 4241 nvidia,memory-controller = <&mc>; 4242 status = "okay"; 4243 }; 4244 4245 smmu_niso0: iommu@12000000 { 4246 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 4247 reg = <0x0 0x12000000 0x0 0x1000000>, 4248 <0x0 0x11000000 0x0 0x1000000>; 4249 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4250 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 4251 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4252 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 4253 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4254 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4255 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4256 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4257 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4258 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4259 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4260 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4261 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4262 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4263 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4264 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4265 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4266 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4267 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4268 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4269 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4270 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4271 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4272 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4273 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4274 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4275 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4276 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4277 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4278 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4279 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4280 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4281 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4282 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4283 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4284 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4285 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4286 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4287 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4288 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4289 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4290 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4291 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4292 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4293 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4294 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4299 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4300 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4303 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4304 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4305 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4306 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4307 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4308 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4309 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4311 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4312 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4313 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4315 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4316 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4317 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4318 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4319 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4320 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4321 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4322 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4323 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4324 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4325 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4326 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4327 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4328 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4329 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4330 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4331 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4332 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4333 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4334 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4335 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4336 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4337 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4340 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4341 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4342 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4354 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4357 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4360 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4361 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4362 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4363 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4364 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4365 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4366 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4367 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4368 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4369 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4370 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4371 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4372 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4373 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4374 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4375 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4376 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4377 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4378 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 4379 stream-match-mask = <0x7f80>; 4380 #global-interrupts = <2>; 4381 #iommu-cells = <1>; 4382 4383 nvidia,memory-controller = <&mc>; 4384 status = "okay"; 4385 }; 4386 4387 cbb-fabric@13a00000 { 4388 compatible = "nvidia,tegra234-cbb-fabric"; 4389 reg = <0x0 0x13a00000 0x0 0x400000>; 4390 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 4391 status = "okay"; 4392 }; 4393 4394 host1x@13e00000 { 4395 compatible = "nvidia,tegra234-host1x"; 4396 reg = <0x0 0x13e00000 0x0 0x10000>, 4397 <0x0 0x13e10000 0x0 0x10000>, 4398 <0x0 0x13e40000 0x0 0x10000>; 4399 reg-names = "common", "hypervisor", "vm"; 4400 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4401 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 4402 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 4403 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 4404 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 4405 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 4406 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 4407 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 4408 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 4409 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 4410 "syncpt5", "syncpt6", "syncpt7", "host1x"; 4411 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 4412 clock-names = "host1x"; 4413 4414 #address-cells = <2>; 4415 #size-cells = <2>; 4416 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>; 4417 4418 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 4419 interconnect-names = "dma-mem"; 4420 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 4421 dma-coherent; 4422 4423 /* Context isolation domains */ 4424 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>, 4425 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>, 4426 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>, 4427 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>, 4428 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>, 4429 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>, 4430 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>, 4431 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>, 4432 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>, 4433 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>, 4434 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>, 4435 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>, 4436 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>, 4437 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>, 4438 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>, 4439 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>; 4440 4441 vic@15340000 { 4442 compatible = "nvidia,tegra234-vic"; 4443 reg = <0x0 0x15340000 0x0 0x00040000>; 4444 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 4445 clocks = <&bpmp TEGRA234_CLK_VIC>; 4446 clock-names = "vic"; 4447 resets = <&bpmp TEGRA234_RESET_VIC>; 4448 reset-names = "vic"; 4449 4450 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 4451 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 4452 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 4453 interconnect-names = "dma-mem", "write"; 4454 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 4455 dma-coherent; 4456 }; 4457 4458 nvdec@15480000 { 4459 compatible = "nvidia,tegra234-nvdec"; 4460 reg = <0x0 0x15480000 0x0 0x00040000>; 4461 clocks = <&bpmp TEGRA234_CLK_NVDEC>, 4462 <&bpmp TEGRA234_CLK_FUSE>, 4463 <&bpmp TEGRA234_CLK_TSEC_PKA>; 4464 clock-names = "nvdec", "fuse", "tsec_pka"; 4465 resets = <&bpmp TEGRA234_RESET_NVDEC>; 4466 reset-names = "nvdec"; 4467 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>; 4468 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>, 4469 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>; 4470 interconnect-names = "dma-mem", "write"; 4471 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>; 4472 dma-coherent; 4473 4474 nvidia,memory-controller = <&mc>; 4475 4476 /* 4477 * Placeholder values that firmware needs to update with the real 4478 * offsets parsed from the microcode headers. 4479 */ 4480 nvidia,bl-manifest-offset = <0>; 4481 nvidia,bl-data-offset = <0>; 4482 nvidia,bl-code-offset = <0>; 4483 nvidia,os-manifest-offset = <0>; 4484 nvidia,os-data-offset = <0>; 4485 nvidia,os-code-offset = <0>; 4486 4487 /* 4488 * Firmware needs to set this to "okay" once the above values have 4489 * been updated. 4490 */ 4491 status = "disabled"; 4492 }; 4493 4494 crypto@15820000 { 4495 compatible = "nvidia,tegra234-se-aes"; 4496 reg = <0x00 0x15820000 0x00 0x10000>; 4497 clocks = <&bpmp TEGRA234_CLK_SE>; 4498 iommus = <&smmu_niso1 TEGRA234_SID_SES_SE1>; 4499 dma-coherent; 4500 }; 4501 4502 crypto@15840000 { 4503 compatible = "nvidia,tegra234-se-hash"; 4504 reg = <0x00 0x15840000 0x00 0x10000>; 4505 clocks = <&bpmp TEGRA234_CLK_SE>; 4506 iommus = <&smmu_niso1 TEGRA234_SID_SES_SE2>; 4507 dma-coherent; 4508 }; 4509 }; 4510 4511 pcie@140a0000 { 4512 compatible = "nvidia,tegra234-pcie"; 4513 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>; 4514 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */ 4515 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */ 4516 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4517 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4518 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4519 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4520 4521 #address-cells = <3>; 4522 #size-cells = <2>; 4523 device_type = "pci"; 4524 num-lanes = <4>; 4525 num-viewport = <8>; 4526 linux,pci-domain = <8>; 4527 4528 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>; 4529 clock-names = "core"; 4530 4531 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>, 4532 <&bpmp TEGRA234_RESET_PEX2_CORE_8>; 4533 reset-names = "apb", "core"; 4534 4535 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4536 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4537 interrupt-names = "intr", "msi"; 4538 4539 #interrupt-cells = <1>; 4540 interrupt-map-mask = <0 0 0 0>; 4541 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 4542 4543 nvidia,bpmp = <&bpmp 8>; 4544 4545 nvidia,aspm-cmrt-us = <60>; 4546 nvidia,aspm-pwr-on-t-us = <20>; 4547 nvidia,aspm-l0s-entrance-latency-us = <3>; 4548 4549 bus-range = <0x0 0xff>; 4550 4551 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 4552 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4553 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4554 4555 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>, 4556 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>; 4557 interconnect-names = "dma-mem", "write"; 4558 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>; 4559 iommu-map-mask = <0x0>; 4560 dma-coherent; 4561 4562 status = "disabled"; 4563 }; 4564 4565 pcie@140c0000 { 4566 compatible = "nvidia,tegra234-pcie"; 4567 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>; 4568 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */ 4569 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */ 4570 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4571 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4572 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4573 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4574 4575 #address-cells = <3>; 4576 #size-cells = <2>; 4577 device_type = "pci"; 4578 num-lanes = <4>; 4579 num-viewport = <8>; 4580 linux,pci-domain = <9>; 4581 4582 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>; 4583 clock-names = "core"; 4584 4585 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>, 4586 <&bpmp TEGRA234_RESET_PEX2_CORE_9>; 4587 reset-names = "apb", "core"; 4588 4589 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4590 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4591 interrupt-names = "intr", "msi"; 4592 4593 #interrupt-cells = <1>; 4594 interrupt-map-mask = <0 0 0 0>; 4595 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 4596 4597 nvidia,bpmp = <&bpmp 9>; 4598 4599 nvidia,aspm-cmrt-us = <60>; 4600 nvidia,aspm-pwr-on-t-us = <20>; 4601 nvidia,aspm-l0s-entrance-latency-us = <3>; 4602 4603 bus-range = <0x0 0xff>; 4604 4605 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */ 4606 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4607 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4608 4609 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>, 4610 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>; 4611 interconnect-names = "dma-mem", "write"; 4612 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>; 4613 iommu-map-mask = <0x0>; 4614 dma-coherent; 4615 4616 status = "disabled"; 4617 }; 4618 4619 pcie@140e0000 { 4620 compatible = "nvidia,tegra234-pcie"; 4621 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 4622 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 4623 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */ 4624 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4625 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4626 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4627 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4628 4629 #address-cells = <3>; 4630 #size-cells = <2>; 4631 device_type = "pci"; 4632 num-lanes = <4>; 4633 num-viewport = <8>; 4634 linux,pci-domain = <10>; 4635 4636 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 4637 clock-names = "core"; 4638 4639 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 4640 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 4641 reset-names = "apb", "core"; 4642 4643 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4644 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4645 interrupt-names = "intr", "msi"; 4646 4647 #interrupt-cells = <1>; 4648 interrupt-map-mask = <0 0 0 0>; 4649 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 4650 4651 nvidia,bpmp = <&bpmp 10>; 4652 4653 nvidia,aspm-cmrt-us = <60>; 4654 nvidia,aspm-pwr-on-t-us = <20>; 4655 nvidia,aspm-l0s-entrance-latency-us = <3>; 4656 4657 bus-range = <0x0 0xff>; 4658 4659 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 4660 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4661 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4662 4663 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 4664 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 4665 interconnect-names = "dma-mem", "write"; 4666 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 4667 iommu-map-mask = <0x0>; 4668 dma-coherent; 4669 4670 status = "disabled"; 4671 }; 4672 4673 pcie-ep@140e0000 { 4674 compatible = "nvidia,tegra234-pcie-ep"; 4675 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>; 4676 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */ 4677 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4678 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */ 4679 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 4680 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 4681 4682 num-lanes = <4>; 4683 4684 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>; 4685 clock-names = "core"; 4686 4687 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>, 4688 <&bpmp TEGRA234_RESET_PEX2_CORE_10>; 4689 reset-names = "apb", "core"; 4690 4691 pinctrl-names = "default"; 4692 pinctrl-0 = <&pex_rst_c10_in_state>; 4693 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 4694 interrupt-names = "intr"; 4695 4696 nvidia,bpmp = <&bpmp 10>; 4697 4698 nvidia,enable-ext-refclk; 4699 nvidia,aspm-cmrt-us = <60>; 4700 nvidia,aspm-pwr-on-t-us = <20>; 4701 nvidia,aspm-l0s-entrance-latency-us = <3>; 4702 4703 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, 4704 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; 4705 interconnect-names = "dma-mem", "write"; 4706 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>; 4707 iommu-map-mask = <0x0>; 4708 dma-coherent; 4709 4710 status = "disabled"; 4711 }; 4712 4713 pcie@14100000 { 4714 compatible = "nvidia,tegra234-pcie"; 4715 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 4716 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */ 4717 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */ 4718 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4719 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4720 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */ 4721 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4722 4723 #address-cells = <3>; 4724 #size-cells = <2>; 4725 device_type = "pci"; 4726 num-lanes = <1>; 4727 num-viewport = <8>; 4728 linux,pci-domain = <1>; 4729 4730 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>; 4731 clock-names = "core"; 4732 4733 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>, 4734 <&bpmp TEGRA234_RESET_PEX0_CORE_1>; 4735 reset-names = "apb", "core"; 4736 4737 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4738 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4739 interrupt-names = "intr", "msi"; 4740 4741 #interrupt-cells = <1>; 4742 interrupt-map-mask = <0 0 0 0>; 4743 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 4744 4745 nvidia,bpmp = <&bpmp 1>; 4746 4747 nvidia,aspm-cmrt-us = <60>; 4748 nvidia,aspm-pwr-on-t-us = <20>; 4749 nvidia,aspm-l0s-entrance-latency-us = <3>; 4750 4751 bus-range = <0x0 0xff>; 4752 4753 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 4754 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4755 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4756 4757 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>, 4758 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>; 4759 interconnect-names = "dma-mem", "write"; 4760 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>; 4761 iommu-map-mask = <0x0>; 4762 dma-coherent; 4763 4764 status = "disabled"; 4765 }; 4766 4767 pcie@14120000 { 4768 compatible = "nvidia,tegra234-pcie"; 4769 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 4770 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */ 4771 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */ 4772 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4773 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4774 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */ 4775 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4776 4777 #address-cells = <3>; 4778 #size-cells = <2>; 4779 device_type = "pci"; 4780 num-lanes = <1>; 4781 num-viewport = <8>; 4782 linux,pci-domain = <2>; 4783 4784 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>; 4785 clock-names = "core"; 4786 4787 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>, 4788 <&bpmp TEGRA234_RESET_PEX0_CORE_2>; 4789 reset-names = "apb", "core"; 4790 4791 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4792 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4793 interrupt-names = "intr", "msi"; 4794 4795 #interrupt-cells = <1>; 4796 interrupt-map-mask = <0 0 0 0>; 4797 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 4798 4799 nvidia,bpmp = <&bpmp 2>; 4800 4801 nvidia,aspm-cmrt-us = <60>; 4802 nvidia,aspm-pwr-on-t-us = <20>; 4803 nvidia,aspm-l0s-entrance-latency-us = <3>; 4804 4805 bus-range = <0x0 0xff>; 4806 4807 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 4808 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4809 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4810 4811 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>, 4812 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>; 4813 interconnect-names = "dma-mem", "write"; 4814 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>; 4815 iommu-map-mask = <0x0>; 4816 dma-coherent; 4817 4818 status = "disabled"; 4819 }; 4820 4821 pcie@14140000 { 4822 compatible = "nvidia,tegra234-pcie"; 4823 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>; 4824 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */ 4825 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */ 4826 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4827 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4828 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4829 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4830 4831 #address-cells = <3>; 4832 #size-cells = <2>; 4833 device_type = "pci"; 4834 num-lanes = <1>; 4835 num-viewport = <8>; 4836 linux,pci-domain = <3>; 4837 4838 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>; 4839 clock-names = "core"; 4840 4841 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>, 4842 <&bpmp TEGRA234_RESET_PEX0_CORE_3>; 4843 reset-names = "apb", "core"; 4844 4845 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4846 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4847 interrupt-names = "intr", "msi"; 4848 4849 #interrupt-cells = <1>; 4850 interrupt-map-mask = <0 0 0 0>; 4851 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 4852 4853 nvidia,bpmp = <&bpmp 3>; 4854 4855 nvidia,aspm-cmrt-us = <60>; 4856 nvidia,aspm-pwr-on-t-us = <20>; 4857 nvidia,aspm-l0s-entrance-latency-us = <3>; 4858 4859 bus-range = <0x0 0xff>; 4860 4861 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ 4862 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4863 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4864 4865 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, 4866 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>; 4867 interconnect-names = "dma-mem", "write"; 4868 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>; 4869 iommu-map-mask = <0x0>; 4870 dma-coherent; 4871 4872 status = "disabled"; 4873 }; 4874 4875 pcie@14160000 { 4876 compatible = "nvidia,tegra234-pcie"; 4877 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 4878 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */ 4879 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */ 4880 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4881 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4882 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4883 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4884 4885 #address-cells = <3>; 4886 #size-cells = <2>; 4887 device_type = "pci"; 4888 num-lanes = <4>; 4889 num-viewport = <8>; 4890 linux,pci-domain = <4>; 4891 4892 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 4893 clock-names = "core"; 4894 4895 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 4896 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 4897 reset-names = "apb", "core"; 4898 4899 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4900 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4901 interrupt-names = "intr", "msi"; 4902 4903 #interrupt-cells = <1>; 4904 interrupt-map-mask = <0 0 0 0>; 4905 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 4906 4907 nvidia,bpmp = <&bpmp 4>; 4908 4909 nvidia,aspm-cmrt-us = <60>; 4910 nvidia,aspm-pwr-on-t-us = <20>; 4911 nvidia,aspm-l0s-entrance-latency-us = <3>; 4912 4913 bus-range = <0x0 0xff>; 4914 4915 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 4916 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 4917 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 4918 4919 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 4920 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 4921 interconnect-names = "dma-mem", "write"; 4922 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>; 4923 iommu-map-mask = <0x0>; 4924 dma-coherent; 4925 4926 status = "disabled"; 4927 }; 4928 4929 pcie-ep@14160000 { 4930 compatible = "nvidia,tegra234-pcie-ep"; 4931 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>; 4932 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 4933 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 4934 0x00 0x36080000 0x0 0x00040000 /* DBI space (256K) */ 4935 0x21 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 4936 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 4937 num-lanes = <4>; 4938 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>; 4939 clock-names = "core"; 4940 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>, 4941 <&bpmp TEGRA234_RESET_PEX0_CORE_4>; 4942 reset-names = "apb", "core"; 4943 4944 pinctrl-names = "default"; 4945 pinctrl-0 = <&pex_rst_c4_in_state>; 4946 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 4947 interrupt-names = "intr"; 4948 nvidia,bpmp = <&bpmp 4>; 4949 nvidia,enable-ext-refclk; 4950 nvidia,aspm-cmrt-us = <60>; 4951 nvidia,aspm-pwr-on-t-us = <20>; 4952 nvidia,aspm-l0s-entrance-latency-us = <3>; 4953 4954 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, 4955 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; 4956 interconnect-names = "dma-mem", "write"; 4957 iommus = <&smmu_niso0 TEGRA234_SID_PCIE4>; 4958 dma-coherent; 4959 status = "disabled"; 4960 }; 4961 4962 pcie@14180000 { 4963 compatible = "nvidia,tegra234-pcie"; 4964 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>; 4965 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */ 4966 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */ 4967 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 4968 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */ 4969 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 4970 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 4971 4972 #address-cells = <3>; 4973 #size-cells = <2>; 4974 device_type = "pci"; 4975 num-lanes = <4>; 4976 num-viewport = <8>; 4977 linux,pci-domain = <0>; 4978 4979 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>; 4980 clock-names = "core"; 4981 4982 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>, 4983 <&bpmp TEGRA234_RESET_PEX0_CORE_0>; 4984 reset-names = "apb", "core"; 4985 4986 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 4987 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 4988 interrupt-names = "intr", "msi"; 4989 4990 #interrupt-cells = <1>; 4991 interrupt-map-mask = <0 0 0 0>; 4992 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 4993 4994 nvidia,bpmp = <&bpmp 0>; 4995 4996 nvidia,aspm-cmrt-us = <60>; 4997 nvidia,aspm-pwr-on-t-us = <20>; 4998 nvidia,aspm-l0s-entrance-latency-us = <3>; 4999 5000 bus-range = <0x0 0xff>; 5001 5002 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 5003 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 5004 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 5005 5006 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>, 5007 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>; 5008 interconnect-names = "dma-mem", "write"; 5009 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>; 5010 iommu-map-mask = <0x0>; 5011 dma-coherent; 5012 5013 status = "disabled"; 5014 }; 5015 5016 pcie@141a0000 { 5017 compatible = "nvidia,tegra234-pcie"; 5018 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 5019 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 5020 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */ 5021 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5022 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 5023 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 5024 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 5025 5026 #address-cells = <3>; 5027 #size-cells = <2>; 5028 device_type = "pci"; 5029 num-lanes = <8>; 5030 num-viewport = <8>; 5031 linux,pci-domain = <5>; 5032 5033 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 5034 clock-names = "core"; 5035 5036 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 5037 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 5038 reset-names = "apb", "core"; 5039 5040 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 5041 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 5042 interrupt-names = "intr", "msi"; 5043 5044 #interrupt-cells = <1>; 5045 interrupt-map-mask = <0 0 0 0>; 5046 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 5047 5048 nvidia,bpmp = <&bpmp 5>; 5049 5050 nvidia,aspm-cmrt-us = <60>; 5051 nvidia,aspm-pwr-on-t-us = <20>; 5052 nvidia,aspm-l0s-entrance-latency-us = <3>; 5053 5054 bus-range = <0x0 0xff>; 5055 5056 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */ 5057 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 5058 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 5059 5060 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 5061 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 5062 interconnect-names = "dma-mem", "write"; 5063 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 5064 iommu-map-mask = <0x0>; 5065 dma-coherent; 5066 5067 status = "disabled"; 5068 }; 5069 5070 pcie-ep@141a0000 { 5071 compatible = "nvidia,tegra234-pcie-ep"; 5072 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 5073 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 5074 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5075 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 5076 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 5077 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 5078 5079 num-lanes = <8>; 5080 5081 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 5082 clock-names = "core"; 5083 5084 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 5085 <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 5086 reset-names = "apb", "core"; 5087 5088 pinctrl-names = "default"; 5089 pinctrl-0 = <&pex_rst_c5_in_state>; 5090 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 5091 interrupt-names = "intr"; 5092 5093 nvidia,bpmp = <&bpmp 5>; 5094 5095 nvidia,enable-ext-refclk; 5096 nvidia,aspm-cmrt-us = <60>; 5097 nvidia,aspm-pwr-on-t-us = <20>; 5098 nvidia,aspm-l0s-entrance-latency-us = <3>; 5099 5100 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, 5101 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; 5102 interconnect-names = "dma-mem", "write"; 5103 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>; 5104 iommu-map-mask = <0x0>; 5105 dma-coherent; 5106 5107 status = "disabled"; 5108 }; 5109 5110 pcie@141c0000 { 5111 compatible = "nvidia,tegra234-pcie"; 5112 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 5113 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 5114 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */ 5115 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5116 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */ 5117 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 5118 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 5119 5120 #address-cells = <3>; 5121 #size-cells = <2>; 5122 device_type = "pci"; 5123 num-lanes = <4>; 5124 num-viewport = <8>; 5125 linux,pci-domain = <6>; 5126 5127 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 5128 clock-names = "core"; 5129 5130 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 5131 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 5132 reset-names = "apb", "core"; 5133 5134 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 5135 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 5136 interrupt-names = "intr", "msi"; 5137 5138 #interrupt-cells = <1>; 5139 interrupt-map-mask = <0 0 0 0>; 5140 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 5141 5142 nvidia,bpmp = <&bpmp 6>; 5143 5144 nvidia,aspm-cmrt-us = <60>; 5145 nvidia,aspm-pwr-on-t-us = <20>; 5146 nvidia,aspm-l0s-entrance-latency-us = <3>; 5147 5148 bus-range = <0x0 0xff>; 5149 5150 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */ 5151 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 5152 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 5153 5154 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 5155 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 5156 interconnect-names = "dma-mem", "write"; 5157 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 5158 iommu-map-mask = <0x0>; 5159 dma-coherent; 5160 5161 status = "disabled"; 5162 }; 5163 5164 pcie-ep@141c0000 { 5165 compatible = "nvidia,tegra234-pcie-ep"; 5166 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>; 5167 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */ 5168 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5169 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */ 5170 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */ 5171 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 5172 5173 num-lanes = <4>; 5174 5175 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>; 5176 clock-names = "core"; 5177 5178 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>, 5179 <&bpmp TEGRA234_RESET_PEX1_CORE_6>; 5180 reset-names = "apb", "core"; 5181 5182 pinctrl-names = "default"; 5183 pinctrl-0 = <&pex_rst_c6_in_state>; 5184 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 5185 interrupt-names = "intr"; 5186 5187 nvidia,bpmp = <&bpmp 6>; 5188 5189 nvidia,enable-ext-refclk; 5190 nvidia,aspm-cmrt-us = <60>; 5191 nvidia,aspm-pwr-on-t-us = <20>; 5192 nvidia,aspm-l0s-entrance-latency-us = <3>; 5193 5194 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, 5195 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; 5196 interconnect-names = "dma-mem", "write"; 5197 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>; 5198 iommu-map-mask = <0x0>; 5199 dma-coherent; 5200 5201 status = "disabled"; 5202 }; 5203 5204 pcie@141e0000 { 5205 compatible = "nvidia,tegra234-pcie"; 5206 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 5207 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 5208 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */ 5209 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5210 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */ 5211 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */ 5212 reg-names = "appl", "config", "atu_dma", "dbi", "ecam"; 5213 5214 #address-cells = <3>; 5215 #size-cells = <2>; 5216 device_type = "pci"; 5217 num-lanes = <8>; 5218 num-viewport = <8>; 5219 linux,pci-domain = <7>; 5220 5221 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 5222 clock-names = "core"; 5223 5224 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 5225 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 5226 reset-names = "apb", "core"; 5227 5228 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 5229 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 5230 interrupt-names = "intr", "msi"; 5231 5232 #interrupt-cells = <1>; 5233 interrupt-map-mask = <0 0 0 0>; 5234 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 5235 5236 nvidia,bpmp = <&bpmp 7>; 5237 5238 nvidia,aspm-cmrt-us = <60>; 5239 nvidia,aspm-pwr-on-t-us = <20>; 5240 nvidia,aspm-l0s-entrance-latency-us = <3>; 5241 5242 bus-range = <0x0 0xff>; 5243 5244 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */ 5245 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ 5246 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ 5247 5248 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 5249 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 5250 interconnect-names = "dma-mem", "write"; 5251 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 5252 iommu-map-mask = <0x0>; 5253 dma-coherent; 5254 5255 status = "disabled"; 5256 }; 5257 5258 pcie-ep@141e0000 { 5259 compatible = "nvidia,tegra234-pcie-ep"; 5260 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>; 5261 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */ 5262 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 5263 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */ 5264 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 5265 reg-names = "appl", "atu_dma", "dbi", "addr_space"; 5266 5267 num-lanes = <8>; 5268 5269 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>; 5270 clock-names = "core"; 5271 5272 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>, 5273 <&bpmp TEGRA234_RESET_PEX2_CORE_7>; 5274 reset-names = "apb", "core"; 5275 5276 pinctrl-names = "default"; 5277 pinctrl-0 = <&pex_rst_c7_in_state>; 5278 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 5279 interrupt-names = "intr"; 5280 5281 nvidia,bpmp = <&bpmp 7>; 5282 5283 nvidia,enable-ext-refclk; 5284 nvidia,aspm-cmrt-us = <60>; 5285 nvidia,aspm-pwr-on-t-us = <20>; 5286 nvidia,aspm-l0s-entrance-latency-us = <3>; 5287 5288 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, 5289 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; 5290 interconnect-names = "dma-mem", "write"; 5291 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>; 5292 iommu-map-mask = <0x0>; 5293 dma-coherent; 5294 5295 status = "disabled"; 5296 }; 5297 }; 5298 5299 sram@40000000 { 5300 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 5301 reg = <0x0 0x40000000 0x0 0x80000>; 5302 5303 #address-cells = <1>; 5304 #size-cells = <1>; 5305 ranges = <0x0 0x0 0x40000000 0x80000>; 5306 5307 no-memory-wc; 5308 5309 cpu_bpmp_tx: sram@70000 { 5310 reg = <0x70000 0x1000>; 5311 label = "cpu-bpmp-tx"; 5312 pool; 5313 }; 5314 5315 cpu_bpmp_rx: sram@71000 { 5316 reg = <0x71000 0x1000>; 5317 label = "cpu-bpmp-rx"; 5318 pool; 5319 }; 5320 }; 5321 5322 bpmp: bpmp { 5323 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 5324 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 5325 TEGRA_HSP_DB_MASTER_BPMP>; 5326 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 5327 #clock-cells = <1>; 5328 #reset-cells = <1>; 5329 #power-domain-cells = <1>; 5330 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 5331 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 5332 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 5333 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 5334 interconnect-names = "read", "write", "dma-mem", "dma-write"; 5335 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 5336 5337 bpmp_i2c: i2c { 5338 compatible = "nvidia,tegra186-bpmp-i2c"; 5339 nvidia,bpmp-bus-id = <5>; 5340 #address-cells = <1>; 5341 #size-cells = <0>; 5342 }; 5343 5344 bpmp_thermal: thermal { 5345 compatible = "nvidia,tegra186-bpmp-thermal"; 5346 #thermal-sensor-cells = <1>; 5347 }; 5348 }; 5349 5350 cpus { 5351 #address-cells = <1>; 5352 #size-cells = <0>; 5353 5354 cpu0_0: cpu@0 { 5355 compatible = "arm,cortex-a78"; 5356 device_type = "cpu"; 5357 reg = <0x00000>; 5358 5359 enable-method = "psci"; 5360 5361 operating-points-v2 = <&cl0_opp_tbl>; 5362 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 5363 5364 i-cache-size = <65536>; 5365 i-cache-line-size = <64>; 5366 i-cache-sets = <256>; 5367 d-cache-size = <65536>; 5368 d-cache-line-size = <64>; 5369 d-cache-sets = <256>; 5370 next-level-cache = <&l2c0_0>; 5371 }; 5372 5373 cpu0_1: cpu@100 { 5374 compatible = "arm,cortex-a78"; 5375 device_type = "cpu"; 5376 reg = <0x00100>; 5377 5378 enable-method = "psci"; 5379 5380 operating-points-v2 = <&cl0_opp_tbl>; 5381 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 5382 5383 i-cache-size = <65536>; 5384 i-cache-line-size = <64>; 5385 i-cache-sets = <256>; 5386 d-cache-size = <65536>; 5387 d-cache-line-size = <64>; 5388 d-cache-sets = <256>; 5389 next-level-cache = <&l2c0_1>; 5390 }; 5391 5392 cpu0_2: cpu@200 { 5393 compatible = "arm,cortex-a78"; 5394 device_type = "cpu"; 5395 reg = <0x00200>; 5396 5397 enable-method = "psci"; 5398 5399 operating-points-v2 = <&cl0_opp_tbl>; 5400 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 5401 5402 i-cache-size = <65536>; 5403 i-cache-line-size = <64>; 5404 i-cache-sets = <256>; 5405 d-cache-size = <65536>; 5406 d-cache-line-size = <64>; 5407 d-cache-sets = <256>; 5408 next-level-cache = <&l2c0_2>; 5409 }; 5410 5411 cpu0_3: cpu@300 { 5412 compatible = "arm,cortex-a78"; 5413 device_type = "cpu"; 5414 reg = <0x00300>; 5415 5416 enable-method = "psci"; 5417 5418 operating-points-v2 = <&cl0_opp_tbl>; 5419 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>; 5420 5421 i-cache-size = <65536>; 5422 i-cache-line-size = <64>; 5423 i-cache-sets = <256>; 5424 d-cache-size = <65536>; 5425 d-cache-line-size = <64>; 5426 d-cache-sets = <256>; 5427 next-level-cache = <&l2c0_3>; 5428 }; 5429 5430 cpu1_0: cpu@10000 { 5431 compatible = "arm,cortex-a78"; 5432 device_type = "cpu"; 5433 reg = <0x10000>; 5434 5435 enable-method = "psci"; 5436 5437 operating-points-v2 = <&cl1_opp_tbl>; 5438 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 5439 5440 i-cache-size = <65536>; 5441 i-cache-line-size = <64>; 5442 i-cache-sets = <256>; 5443 d-cache-size = <65536>; 5444 d-cache-line-size = <64>; 5445 d-cache-sets = <256>; 5446 next-level-cache = <&l2c1_0>; 5447 }; 5448 5449 cpu1_1: cpu@10100 { 5450 compatible = "arm,cortex-a78"; 5451 device_type = "cpu"; 5452 reg = <0x10100>; 5453 5454 enable-method = "psci"; 5455 5456 operating-points-v2 = <&cl1_opp_tbl>; 5457 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 5458 5459 i-cache-size = <65536>; 5460 i-cache-line-size = <64>; 5461 i-cache-sets = <256>; 5462 d-cache-size = <65536>; 5463 d-cache-line-size = <64>; 5464 d-cache-sets = <256>; 5465 next-level-cache = <&l2c1_1>; 5466 }; 5467 5468 cpu1_2: cpu@10200 { 5469 compatible = "arm,cortex-a78"; 5470 device_type = "cpu"; 5471 reg = <0x10200>; 5472 5473 enable-method = "psci"; 5474 5475 operating-points-v2 = <&cl1_opp_tbl>; 5476 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 5477 5478 i-cache-size = <65536>; 5479 i-cache-line-size = <64>; 5480 i-cache-sets = <256>; 5481 d-cache-size = <65536>; 5482 d-cache-line-size = <64>; 5483 d-cache-sets = <256>; 5484 next-level-cache = <&l2c1_2>; 5485 }; 5486 5487 cpu1_3: cpu@10300 { 5488 compatible = "arm,cortex-a78"; 5489 device_type = "cpu"; 5490 reg = <0x10300>; 5491 5492 enable-method = "psci"; 5493 5494 operating-points-v2 = <&cl1_opp_tbl>; 5495 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>; 5496 5497 i-cache-size = <65536>; 5498 i-cache-line-size = <64>; 5499 i-cache-sets = <256>; 5500 d-cache-size = <65536>; 5501 d-cache-line-size = <64>; 5502 d-cache-sets = <256>; 5503 next-level-cache = <&l2c1_3>; 5504 }; 5505 5506 cpu2_0: cpu@20000 { 5507 compatible = "arm,cortex-a78"; 5508 device_type = "cpu"; 5509 reg = <0x20000>; 5510 5511 enable-method = "psci"; 5512 5513 operating-points-v2 = <&cl2_opp_tbl>; 5514 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 5515 5516 i-cache-size = <65536>; 5517 i-cache-line-size = <64>; 5518 i-cache-sets = <256>; 5519 d-cache-size = <65536>; 5520 d-cache-line-size = <64>; 5521 d-cache-sets = <256>; 5522 next-level-cache = <&l2c2_0>; 5523 }; 5524 5525 cpu2_1: cpu@20100 { 5526 compatible = "arm,cortex-a78"; 5527 device_type = "cpu"; 5528 reg = <0x20100>; 5529 5530 enable-method = "psci"; 5531 5532 operating-points-v2 = <&cl2_opp_tbl>; 5533 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 5534 5535 i-cache-size = <65536>; 5536 i-cache-line-size = <64>; 5537 i-cache-sets = <256>; 5538 d-cache-size = <65536>; 5539 d-cache-line-size = <64>; 5540 d-cache-sets = <256>; 5541 next-level-cache = <&l2c2_1>; 5542 }; 5543 5544 cpu2_2: cpu@20200 { 5545 compatible = "arm,cortex-a78"; 5546 device_type = "cpu"; 5547 reg = <0x20200>; 5548 5549 enable-method = "psci"; 5550 5551 operating-points-v2 = <&cl2_opp_tbl>; 5552 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 5553 5554 i-cache-size = <65536>; 5555 i-cache-line-size = <64>; 5556 i-cache-sets = <256>; 5557 d-cache-size = <65536>; 5558 d-cache-line-size = <64>; 5559 d-cache-sets = <256>; 5560 next-level-cache = <&l2c2_2>; 5561 }; 5562 5563 cpu2_3: cpu@20300 { 5564 compatible = "arm,cortex-a78"; 5565 device_type = "cpu"; 5566 reg = <0x20300>; 5567 5568 enable-method = "psci"; 5569 5570 operating-points-v2 = <&cl2_opp_tbl>; 5571 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>; 5572 5573 i-cache-size = <65536>; 5574 i-cache-line-size = <64>; 5575 i-cache-sets = <256>; 5576 d-cache-size = <65536>; 5577 d-cache-line-size = <64>; 5578 d-cache-sets = <256>; 5579 next-level-cache = <&l2c2_3>; 5580 }; 5581 5582 cpu-map { 5583 cluster0 { 5584 core0 { 5585 cpu = <&cpu0_0>; 5586 }; 5587 5588 core1 { 5589 cpu = <&cpu0_1>; 5590 }; 5591 5592 core2 { 5593 cpu = <&cpu0_2>; 5594 }; 5595 5596 core3 { 5597 cpu = <&cpu0_3>; 5598 }; 5599 }; 5600 5601 cluster1 { 5602 core0 { 5603 cpu = <&cpu1_0>; 5604 }; 5605 5606 core1 { 5607 cpu = <&cpu1_1>; 5608 }; 5609 5610 core2 { 5611 cpu = <&cpu1_2>; 5612 }; 5613 5614 core3 { 5615 cpu = <&cpu1_3>; 5616 }; 5617 }; 5618 5619 cluster2 { 5620 core0 { 5621 cpu = <&cpu2_0>; 5622 }; 5623 5624 core1 { 5625 cpu = <&cpu2_1>; 5626 }; 5627 5628 core2 { 5629 cpu = <&cpu2_2>; 5630 }; 5631 5632 core3 { 5633 cpu = <&cpu2_3>; 5634 }; 5635 }; 5636 }; 5637 5638 l2c0_0: l2-cache00 { 5639 compatible = "cache"; 5640 cache-size = <262144>; 5641 cache-line-size = <64>; 5642 cache-sets = <512>; 5643 cache-unified; 5644 cache-level = <2>; 5645 next-level-cache = <&l3c0>; 5646 }; 5647 5648 l2c0_1: l2-cache01 { 5649 compatible = "cache"; 5650 cache-size = <262144>; 5651 cache-line-size = <64>; 5652 cache-sets = <512>; 5653 cache-unified; 5654 cache-level = <2>; 5655 next-level-cache = <&l3c0>; 5656 }; 5657 5658 l2c0_2: l2-cache02 { 5659 compatible = "cache"; 5660 cache-size = <262144>; 5661 cache-line-size = <64>; 5662 cache-sets = <512>; 5663 cache-unified; 5664 cache-level = <2>; 5665 next-level-cache = <&l3c0>; 5666 }; 5667 5668 l2c0_3: l2-cache03 { 5669 compatible = "cache"; 5670 cache-size = <262144>; 5671 cache-line-size = <64>; 5672 cache-sets = <512>; 5673 cache-unified; 5674 cache-level = <2>; 5675 next-level-cache = <&l3c0>; 5676 }; 5677 5678 l2c1_0: l2-cache10 { 5679 compatible = "cache"; 5680 cache-size = <262144>; 5681 cache-line-size = <64>; 5682 cache-sets = <512>; 5683 cache-unified; 5684 cache-level = <2>; 5685 next-level-cache = <&l3c1>; 5686 }; 5687 5688 l2c1_1: l2-cache11 { 5689 compatible = "cache"; 5690 cache-size = <262144>; 5691 cache-line-size = <64>; 5692 cache-sets = <512>; 5693 cache-unified; 5694 cache-level = <2>; 5695 next-level-cache = <&l3c1>; 5696 }; 5697 5698 l2c1_2: l2-cache12 { 5699 compatible = "cache"; 5700 cache-size = <262144>; 5701 cache-line-size = <64>; 5702 cache-sets = <512>; 5703 cache-unified; 5704 cache-level = <2>; 5705 next-level-cache = <&l3c1>; 5706 }; 5707 5708 l2c1_3: l2-cache13 { 5709 compatible = "cache"; 5710 cache-size = <262144>; 5711 cache-line-size = <64>; 5712 cache-sets = <512>; 5713 cache-unified; 5714 cache-level = <2>; 5715 next-level-cache = <&l3c1>; 5716 }; 5717 5718 l2c2_0: l2-cache20 { 5719 compatible = "cache"; 5720 cache-size = <262144>; 5721 cache-line-size = <64>; 5722 cache-sets = <512>; 5723 cache-unified; 5724 cache-level = <2>; 5725 next-level-cache = <&l3c2>; 5726 }; 5727 5728 l2c2_1: l2-cache21 { 5729 compatible = "cache"; 5730 cache-size = <262144>; 5731 cache-line-size = <64>; 5732 cache-sets = <512>; 5733 cache-unified; 5734 cache-level = <2>; 5735 next-level-cache = <&l3c2>; 5736 }; 5737 5738 l2c2_2: l2-cache22 { 5739 compatible = "cache"; 5740 cache-size = <262144>; 5741 cache-line-size = <64>; 5742 cache-sets = <512>; 5743 cache-unified; 5744 cache-level = <2>; 5745 next-level-cache = <&l3c2>; 5746 }; 5747 5748 l2c2_3: l2-cache23 { 5749 compatible = "cache"; 5750 cache-size = <262144>; 5751 cache-line-size = <64>; 5752 cache-sets = <512>; 5753 cache-unified; 5754 cache-level = <2>; 5755 next-level-cache = <&l3c2>; 5756 }; 5757 5758 l3c0: l3-cache0 { 5759 compatible = "cache"; 5760 cache-unified; 5761 cache-size = <2097152>; 5762 cache-line-size = <64>; 5763 cache-sets = <2048>; 5764 cache-level = <3>; 5765 }; 5766 5767 l3c1: l3-cache1 { 5768 compatible = "cache"; 5769 cache-unified; 5770 cache-size = <2097152>; 5771 cache-line-size = <64>; 5772 cache-sets = <2048>; 5773 cache-level = <3>; 5774 }; 5775 5776 l3c2: l3-cache2 { 5777 compatible = "cache"; 5778 cache-unified; 5779 cache-size = <2097152>; 5780 cache-line-size = <64>; 5781 cache-sets = <2048>; 5782 cache-level = <3>; 5783 }; 5784 }; 5785 5786 dsu-pmu0 { 5787 compatible = "arm,dsu-pmu"; 5788 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>; 5789 cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>; 5790 }; 5791 5792 dsu-pmu1 { 5793 compatible = "arm,dsu-pmu"; 5794 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 5795 cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>; 5796 }; 5797 5798 dsu-pmu2 { 5799 compatible = "arm,dsu-pmu"; 5800 interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 5801 cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>; 5802 }; 5803 5804 pmu { 5805 compatible = "arm,cortex-a78-pmu"; 5806 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 5807 status = "okay"; 5808 }; 5809 5810 psci { 5811 compatible = "arm,psci-1.0"; 5812 status = "okay"; 5813 method = "smc"; 5814 }; 5815 5816 tcu: serial { 5817 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 5818 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 5819 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 5820 mbox-names = "rx", "tx"; 5821 status = "disabled"; 5822 }; 5823 5824 sound { 5825 status = "disabled"; 5826 5827 clocks = <&bpmp TEGRA234_CLK_PLLA>, 5828 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 5829 clock-names = "pll_a", "plla_out0"; 5830 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 5831 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 5832 <&bpmp TEGRA234_CLK_AUD_MCLK>; 5833 assigned-clock-parents = <0>, 5834 <&bpmp TEGRA234_CLK_PLLA>, 5835 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 5836 }; 5837 5838 thermal-zones { 5839 cpu-thermal { 5840 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>; 5841 status = "disabled"; 5842 }; 5843 5844 gpu-thermal { 5845 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>; 5846 status = "disabled"; 5847 }; 5848 5849 cv0-thermal { 5850 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>; 5851 status = "disabled"; 5852 }; 5853 5854 cv1-thermal { 5855 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>; 5856 status = "disabled"; 5857 }; 5858 5859 cv2-thermal { 5860 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>; 5861 status = "disabled"; 5862 }; 5863 5864 soc0-thermal { 5865 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>; 5866 status = "disabled"; 5867 }; 5868 5869 soc1-thermal { 5870 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>; 5871 status = "disabled"; 5872 }; 5873 5874 soc2-thermal { 5875 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>; 5876 status = "disabled"; 5877 }; 5878 5879 tj-thermal { 5880 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>; 5881 status = "disabled"; 5882 }; 5883 }; 5884 5885 timer { 5886 compatible = "arm,armv8-timer"; 5887 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 5888 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 5889 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 5890 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 5891 interrupt-parent = <&gic>; 5892 always-on; 5893 }; 5894 5895 cl0_opp_tbl: opp-table-cluster0 { 5896 compatible = "operating-points-v2"; 5897 opp-shared; 5898 5899 cl0_ch1_opp1: opp-115200000 { 5900 opp-hz = /bits/ 64 <115200000>; 5901 opp-peak-kBps = <816000>; 5902 }; 5903 5904 cl0_ch1_opp2: opp-192000000 { 5905 opp-hz = /bits/ 64 <192000000>; 5906 opp-peak-kBps = <816000>; 5907 }; 5908 5909 cl0_ch1_opp3: opp-268800000 { 5910 opp-hz = /bits/ 64 <268800000>; 5911 opp-peak-kBps = <816000>; 5912 }; 5913 5914 cl0_ch1_opp4: opp-345600000 { 5915 opp-hz = /bits/ 64 <345600000>; 5916 opp-peak-kBps = <816000>; 5917 }; 5918 5919 cl0_ch1_opp5: opp-422400000 { 5920 opp-hz = /bits/ 64 <422400000>; 5921 opp-peak-kBps = <816000>; 5922 }; 5923 5924 cl0_ch1_opp6: opp-499200000 { 5925 opp-hz = /bits/ 64 <499200000>; 5926 opp-peak-kBps = <816000>; 5927 }; 5928 5929 cl0_ch1_opp7: opp-576000000 { 5930 opp-hz = /bits/ 64 <576000000>; 5931 opp-peak-kBps = <816000>; 5932 }; 5933 5934 cl0_ch1_opp8: opp-652800000 { 5935 opp-hz = /bits/ 64 <652800000>; 5936 opp-peak-kBps = <816000>; 5937 }; 5938 5939 cl0_ch1_opp9: opp-729600000 { 5940 opp-hz = /bits/ 64 <729600000>; 5941 opp-peak-kBps = <816000>; 5942 }; 5943 5944 cl0_ch1_opp10: opp-806400000 { 5945 opp-hz = /bits/ 64 <806400000>; 5946 opp-peak-kBps = <816000>; 5947 }; 5948 5949 cl0_ch1_opp11: opp-883200000 { 5950 opp-hz = /bits/ 64 <883200000>; 5951 opp-peak-kBps = <816000>; 5952 }; 5953 5954 cl0_ch1_opp12: opp-960000000 { 5955 opp-hz = /bits/ 64 <960000000>; 5956 opp-peak-kBps = <816000>; 5957 }; 5958 5959 cl0_ch1_opp13: opp-1036800000 { 5960 opp-hz = /bits/ 64 <1036800000>; 5961 opp-peak-kBps = <816000>; 5962 }; 5963 5964 cl0_ch1_opp14: opp-1113600000 { 5965 opp-hz = /bits/ 64 <1113600000>; 5966 opp-peak-kBps = <1632000>; 5967 }; 5968 5969 cl0_ch1_opp15: opp-1190400000 { 5970 opp-hz = /bits/ 64 <1190400000>; 5971 opp-peak-kBps = <1632000>; 5972 }; 5973 5974 cl0_ch1_opp16: opp-1267200000 { 5975 opp-hz = /bits/ 64 <1267200000>; 5976 opp-peak-kBps = <1632000>; 5977 }; 5978 5979 cl0_ch1_opp17: opp-1344000000 { 5980 opp-hz = /bits/ 64 <1344000000>; 5981 opp-peak-kBps = <1632000>; 5982 }; 5983 5984 cl0_ch1_opp18: opp-1420800000 { 5985 opp-hz = /bits/ 64 <1420800000>; 5986 opp-peak-kBps = <1632000>; 5987 }; 5988 5989 cl0_ch1_opp19: opp-1497600000 { 5990 opp-hz = /bits/ 64 <1497600000>; 5991 opp-peak-kBps = <3200000>; 5992 }; 5993 5994 cl0_ch1_opp20: opp-1574400000 { 5995 opp-hz = /bits/ 64 <1574400000>; 5996 opp-peak-kBps = <3200000>; 5997 }; 5998 5999 cl0_ch1_opp21: opp-1651200000 { 6000 opp-hz = /bits/ 64 <1651200000>; 6001 opp-peak-kBps = <3200000>; 6002 }; 6003 6004 cl0_ch1_opp22: opp-1728000000 { 6005 opp-hz = /bits/ 64 <1728000000>; 6006 opp-peak-kBps = <3200000>; 6007 }; 6008 6009 cl0_ch1_opp23: opp-1804800000 { 6010 opp-hz = /bits/ 64 <1804800000>; 6011 opp-peak-kBps = <3200000>; 6012 }; 6013 6014 cl0_ch1_opp24: opp-1881600000 { 6015 opp-hz = /bits/ 64 <1881600000>; 6016 opp-peak-kBps = <3200000>; 6017 }; 6018 6019 cl0_ch1_opp25: opp-1958400000 { 6020 opp-hz = /bits/ 64 <1958400000>; 6021 opp-peak-kBps = <3200000>; 6022 }; 6023 6024 cl0_ch1_opp26: opp-2035200000 { 6025 opp-hz = /bits/ 64 <2035200000>; 6026 opp-peak-kBps = <3200000>; 6027 }; 6028 6029 cl0_ch1_opp27: opp-2112000000 { 6030 opp-hz = /bits/ 64 <2112000000>; 6031 opp-peak-kBps = <6400000>; 6032 }; 6033 6034 cl0_ch1_opp28: opp-2188800000 { 6035 opp-hz = /bits/ 64 <2188800000>; 6036 opp-peak-kBps = <6400000>; 6037 }; 6038 6039 cl0_ch1_opp29: opp-2201600000 { 6040 opp-hz = /bits/ 64 <2201600000>; 6041 opp-peak-kBps = <6400000>; 6042 }; 6043 }; 6044 6045 cl1_opp_tbl: opp-table-cluster1 { 6046 compatible = "operating-points-v2"; 6047 opp-shared; 6048 6049 cl1_ch1_opp1: opp-115200000 { 6050 opp-hz = /bits/ 64 <115200000>; 6051 opp-peak-kBps = <816000>; 6052 }; 6053 6054 cl1_ch1_opp2: opp-192000000 { 6055 opp-hz = /bits/ 64 <192000000>; 6056 opp-peak-kBps = <816000>; 6057 }; 6058 6059 cl1_ch1_opp3: opp-268800000 { 6060 opp-hz = /bits/ 64 <268800000>; 6061 opp-peak-kBps = <816000>; 6062 }; 6063 6064 cl1_ch1_opp4: opp-345600000 { 6065 opp-hz = /bits/ 64 <345600000>; 6066 opp-peak-kBps = <816000>; 6067 }; 6068 6069 cl1_ch1_opp5: opp-422400000 { 6070 opp-hz = /bits/ 64 <422400000>; 6071 opp-peak-kBps = <816000>; 6072 }; 6073 6074 cl1_ch1_opp6: opp-499200000 { 6075 opp-hz = /bits/ 64 <499200000>; 6076 opp-peak-kBps = <816000>; 6077 }; 6078 6079 cl1_ch1_opp7: opp-576000000 { 6080 opp-hz = /bits/ 64 <576000000>; 6081 opp-peak-kBps = <816000>; 6082 }; 6083 6084 cl1_ch1_opp8: opp-652800000 { 6085 opp-hz = /bits/ 64 <652800000>; 6086 opp-peak-kBps = <816000>; 6087 }; 6088 6089 cl1_ch1_opp9: opp-729600000 { 6090 opp-hz = /bits/ 64 <729600000>; 6091 opp-peak-kBps = <816000>; 6092 }; 6093 6094 cl1_ch1_opp10: opp-806400000 { 6095 opp-hz = /bits/ 64 <806400000>; 6096 opp-peak-kBps = <816000>; 6097 }; 6098 6099 cl1_ch1_opp11: opp-883200000 { 6100 opp-hz = /bits/ 64 <883200000>; 6101 opp-peak-kBps = <816000>; 6102 }; 6103 6104 cl1_ch1_opp12: opp-960000000 { 6105 opp-hz = /bits/ 64 <960000000>; 6106 opp-peak-kBps = <816000>; 6107 }; 6108 6109 cl1_ch1_opp13: opp-1036800000 { 6110 opp-hz = /bits/ 64 <1036800000>; 6111 opp-peak-kBps = <816000>; 6112 }; 6113 6114 cl1_ch1_opp14: opp-1113600000 { 6115 opp-hz = /bits/ 64 <1113600000>; 6116 opp-peak-kBps = <1632000>; 6117 }; 6118 6119 cl1_ch1_opp15: opp-1190400000 { 6120 opp-hz = /bits/ 64 <1190400000>; 6121 opp-peak-kBps = <1632000>; 6122 }; 6123 6124 cl1_ch1_opp16: opp-1267200000 { 6125 opp-hz = /bits/ 64 <1267200000>; 6126 opp-peak-kBps = <1632000>; 6127 }; 6128 6129 cl1_ch1_opp17: opp-1344000000 { 6130 opp-hz = /bits/ 64 <1344000000>; 6131 opp-peak-kBps = <1632000>; 6132 }; 6133 6134 cl1_ch1_opp18: opp-1420800000 { 6135 opp-hz = /bits/ 64 <1420800000>; 6136 opp-peak-kBps = <1632000>; 6137 }; 6138 6139 cl1_ch1_opp19: opp-1497600000 { 6140 opp-hz = /bits/ 64 <1497600000>; 6141 opp-peak-kBps = <3200000>; 6142 }; 6143 6144 cl1_ch1_opp20: opp-1574400000 { 6145 opp-hz = /bits/ 64 <1574400000>; 6146 opp-peak-kBps = <3200000>; 6147 }; 6148 6149 cl1_ch1_opp21: opp-1651200000 { 6150 opp-hz = /bits/ 64 <1651200000>; 6151 opp-peak-kBps = <3200000>; 6152 }; 6153 6154 cl1_ch1_opp22: opp-1728000000 { 6155 opp-hz = /bits/ 64 <1728000000>; 6156 opp-peak-kBps = <3200000>; 6157 }; 6158 6159 cl1_ch1_opp23: opp-1804800000 { 6160 opp-hz = /bits/ 64 <1804800000>; 6161 opp-peak-kBps = <3200000>; 6162 }; 6163 6164 cl1_ch1_opp24: opp-1881600000 { 6165 opp-hz = /bits/ 64 <1881600000>; 6166 opp-peak-kBps = <3200000>; 6167 }; 6168 6169 cl1_ch1_opp25: opp-1958400000 { 6170 opp-hz = /bits/ 64 <1958400000>; 6171 opp-peak-kBps = <3200000>; 6172 }; 6173 6174 cl1_ch1_opp26: opp-2035200000 { 6175 opp-hz = /bits/ 64 <2035200000>; 6176 opp-peak-kBps = <3200000>; 6177 }; 6178 6179 cl1_ch1_opp27: opp-2112000000 { 6180 opp-hz = /bits/ 64 <2112000000>; 6181 opp-peak-kBps = <6400000>; 6182 }; 6183 6184 cl1_ch1_opp28: opp-2188800000 { 6185 opp-hz = /bits/ 64 <2188800000>; 6186 opp-peak-kBps = <6400000>; 6187 }; 6188 6189 cl1_ch1_opp29: opp-2201600000 { 6190 opp-hz = /bits/ 64 <2201600000>; 6191 opp-peak-kBps = <6400000>; 6192 }; 6193 }; 6194 6195 cl2_opp_tbl: opp-table-cluster2 { 6196 compatible = "operating-points-v2"; 6197 opp-shared; 6198 6199 cl2_ch1_opp1: opp-115200000 { 6200 opp-hz = /bits/ 64 <115200000>; 6201 opp-peak-kBps = <816000>; 6202 }; 6203 6204 cl2_ch1_opp2: opp-192000000 { 6205 opp-hz = /bits/ 64 <192000000>; 6206 opp-peak-kBps = <816000>; 6207 }; 6208 6209 cl2_ch1_opp3: opp-268800000 { 6210 opp-hz = /bits/ 64 <268800000>; 6211 opp-peak-kBps = <816000>; 6212 }; 6213 6214 cl2_ch1_opp4: opp-345600000 { 6215 opp-hz = /bits/ 64 <345600000>; 6216 opp-peak-kBps = <816000>; 6217 }; 6218 6219 cl2_ch1_opp5: opp-422400000 { 6220 opp-hz = /bits/ 64 <422400000>; 6221 opp-peak-kBps = <816000>; 6222 }; 6223 6224 cl2_ch1_opp6: opp-499200000 { 6225 opp-hz = /bits/ 64 <499200000>; 6226 opp-peak-kBps = <816000>; 6227 }; 6228 6229 cl2_ch1_opp7: opp-576000000 { 6230 opp-hz = /bits/ 64 <576000000>; 6231 opp-peak-kBps = <816000>; 6232 }; 6233 6234 cl2_ch1_opp8: opp-652800000 { 6235 opp-hz = /bits/ 64 <652800000>; 6236 opp-peak-kBps = <816000>; 6237 }; 6238 6239 cl2_ch1_opp9: opp-729600000 { 6240 opp-hz = /bits/ 64 <729600000>; 6241 opp-peak-kBps = <816000>; 6242 }; 6243 6244 cl2_ch1_opp10: opp-806400000 { 6245 opp-hz = /bits/ 64 <806400000>; 6246 opp-peak-kBps = <816000>; 6247 }; 6248 6249 cl2_ch1_opp11: opp-883200000 { 6250 opp-hz = /bits/ 64 <883200000>; 6251 opp-peak-kBps = <816000>; 6252 }; 6253 6254 cl2_ch1_opp12: opp-960000000 { 6255 opp-hz = /bits/ 64 <960000000>; 6256 opp-peak-kBps = <816000>; 6257 }; 6258 6259 cl2_ch1_opp13: opp-1036800000 { 6260 opp-hz = /bits/ 64 <1036800000>; 6261 opp-peak-kBps = <816000>; 6262 }; 6263 6264 cl2_ch1_opp14: opp-1113600000 { 6265 opp-hz = /bits/ 64 <1113600000>; 6266 opp-peak-kBps = <1632000>; 6267 }; 6268 6269 cl2_ch1_opp15: opp-1190400000 { 6270 opp-hz = /bits/ 64 <1190400000>; 6271 opp-peak-kBps = <1632000>; 6272 }; 6273 6274 cl2_ch1_opp16: opp-1267200000 { 6275 opp-hz = /bits/ 64 <1267200000>; 6276 opp-peak-kBps = <1632000>; 6277 }; 6278 6279 cl2_ch1_opp17: opp-1344000000 { 6280 opp-hz = /bits/ 64 <1344000000>; 6281 opp-peak-kBps = <1632000>; 6282 }; 6283 6284 cl2_ch1_opp18: opp-1420800000 { 6285 opp-hz = /bits/ 64 <1420800000>; 6286 opp-peak-kBps = <1632000>; 6287 }; 6288 6289 cl2_ch1_opp19: opp-1497600000 { 6290 opp-hz = /bits/ 64 <1497600000>; 6291 opp-peak-kBps = <3200000>; 6292 }; 6293 6294 cl2_ch1_opp20: opp-1574400000 { 6295 opp-hz = /bits/ 64 <1574400000>; 6296 opp-peak-kBps = <3200000>; 6297 }; 6298 6299 cl2_ch1_opp21: opp-1651200000 { 6300 opp-hz = /bits/ 64 <1651200000>; 6301 opp-peak-kBps = <3200000>; 6302 }; 6303 6304 cl2_ch1_opp22: opp-1728000000 { 6305 opp-hz = /bits/ 64 <1728000000>; 6306 opp-peak-kBps = <3200000>; 6307 }; 6308 6309 cl2_ch1_opp23: opp-1804800000 { 6310 opp-hz = /bits/ 64 <1804800000>; 6311 opp-peak-kBps = <3200000>; 6312 }; 6313 6314 cl2_ch1_opp24: opp-1881600000 { 6315 opp-hz = /bits/ 64 <1881600000>; 6316 opp-peak-kBps = <3200000>; 6317 }; 6318 6319 cl2_ch1_opp25: opp-1958400000 { 6320 opp-hz = /bits/ 64 <1958400000>; 6321 opp-peak-kBps = <3200000>; 6322 }; 6323 6324 cl2_ch1_opp26: opp-2035200000 { 6325 opp-hz = /bits/ 64 <2035200000>; 6326 opp-peak-kBps = <3200000>; 6327 }; 6328 6329 cl2_ch1_opp27: opp-2112000000 { 6330 opp-hz = /bits/ 64 <2112000000>; 6331 opp-peak-kBps = <6400000>; 6332 }; 6333 6334 cl2_ch1_opp28: opp-2188800000 { 6335 opp-hz = /bits/ 64 <2188800000>; 6336 opp-peak-kBps = <6400000>; 6337 }; 6338 6339 cl2_ch1_opp29: opp-2201600000 { 6340 opp-hz = /bits/ 64 <2201600000>; 6341 opp-peak-kBps = <6400000>; 6342 }; 6343 }; 6344}; 6345