1 /* SPDX-License-Identifier: GPL-2.0-only 2 * SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION. All rights reserved. 3 * 4 * tegra210_amx.h - Definitions for Tegra210 AMX driver 5 * 6 */ 7 8 #ifndef __TEGRA210_AMX_H__ 9 #define __TEGRA210_AMX_H__ 10 11 /* Register offsets from TEGRA210_AMX*_BASE */ 12 #define TEGRA210_AMX_RX_STATUS 0x0c 13 #define TEGRA210_AMX_RX_INT_STATUS 0x10 14 #define TEGRA210_AMX_RX_INT_MASK 0x14 15 #define TEGRA210_AMX_RX_INT_SET 0x18 16 #define TEGRA210_AMX_RX_INT_CLEAR 0x1c 17 #define TEGRA210_AMX_RX1_CIF_CTRL 0x20 18 #define TEGRA210_AMX_RX2_CIF_CTRL 0x24 19 #define TEGRA210_AMX_RX3_CIF_CTRL 0x28 20 #define TEGRA210_AMX_RX4_CIF_CTRL 0x2c 21 #define TEGRA210_AMX_TX_STATUS 0x4c 22 #define TEGRA210_AMX_TX_INT_STATUS 0x50 23 #define TEGRA210_AMX_TX_INT_MASK 0x54 24 #define TEGRA210_AMX_TX_INT_SET 0x58 25 #define TEGRA210_AMX_TX_INT_CLEAR 0x5c 26 #define TEGRA210_AMX_TX_CIF_CTRL 0x60 27 #define TEGRA210_AMX_ENABLE 0x80 28 #define TEGRA210_AMX_SOFT_RESET 0x84 29 #define TEGRA210_AMX_CG 0x88 30 #define TEGRA210_AMX_STATUS 0x8c 31 #define TEGRA210_AMX_INT_STATUS 0x90 32 #define TEGRA210_AMX_CTRL 0xa4 33 #define TEGRA210_AMX_OUT_BYTE_EN0 0xa8 34 #define TEGRA210_AMX_CYA 0xb0 35 #define TEGRA210_AMX_CFG_RAM_CTRL 0xb8 36 #define TEGRA210_AMX_CFG_RAM_DATA 0xbc 37 38 #define TEGRA194_AMX_RX1_FRAME_PERIOD 0xc0 39 #define TEGRA194_AMX_RX4_FRAME_PERIOD 0xcc 40 #define TEGRA194_AMX_RX4_LAST_FRAME_PERIOD 0xdc 41 42 #define TEGRA264_AMX_STREAMS_AUTO_DISABLE 0xb8 43 #define TEGRA264_AMX_CFG_RAM_CTRL 0xc0 44 #define TEGRA264_AMX_CFG_RAM_DATA 0xc4 45 #define TEGRA264_AMX_RX1_FRAME_PERIOD 0xc8 46 #define TEGRA264_AMX_RX4_FRAME_PERIOD 0xd4 47 #define TEGRA264_AMX_RX4_LAST_FRAME_PERIOD 0xe4 48 49 /* Fields in TEGRA210_AMX_ENABLE */ 50 #define TEGRA210_AMX_ENABLE_SHIFT 0 51 52 /* Fields in TEGRA210_AMX_CTRL */ 53 #define TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT 14 54 #define TEGRA210_AMX_CTRL_MSTR_RX_NUM_MASK (3 << TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT) 55 56 #define TEGRA210_AMX_CTRL_RX_DEP_SHIFT 12 57 #define TEGRA210_AMX_CTRL_RX_DEP_MASK (3 << TEGRA210_AMX_CTRL_RX_DEP_SHIFT) 58 59 /* Fields in TEGRA210_AMX_CFG_RAM_CTRL */ 60 #define TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT 14 61 #define TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT) 62 63 #define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13 64 #define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT) 65 66 #define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 12 67 #define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT) 68 69 #define TEGRA210_AMX_CFG_CTRL_RAM_ADDR_SHIFT 0 70 71 /* Fields in TEGRA210_AMX_SOFT_RESET */ 72 #define TEGRA210_AMX_SOFT_RESET_SOFT_EN 1 73 #define TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK TEGRA210_AMX_SOFT_RESET_SOFT_EN 74 75 #define TEGRA210_AMX_AUDIOCIF_CH_STRIDE 4 76 #define TEGRA210_AMX_RAM_DEPTH 16 77 #define TEGRA210_AMX_MAP_STREAM_NUM_SHIFT 6 78 #define TEGRA210_AMX_MAP_WORD_NUM_SHIFT 2 79 #define TEGRA210_AMX_MAP_BYTE_NUM_SHIFT 0 80 #define TEGRA210_AMX_BYTE_MASK_COUNT 2 81 #define TEGRA210_AMX_MAX_CHANNEL 16 82 #define TEGRA210_AMX_AUTO_DISABLE_OFFSET 0 83 84 #define TEGRA264_AMX_RAM_DEPTH 32 85 #define TEGRA264_AMX_BYTE_MASK_COUNT 4 86 #define TEGRA264_AMX_MAX_CHANNEL 32 87 #define TEGRA264_AMX_AUTO_DISABLE_OFFSET 8 88 #define TEGRA_AMX_OUT_DAI_ID 4 89 90 enum { 91 TEGRA210_AMX_WAIT_ON_ALL, 92 TEGRA210_AMX_WAIT_ON_ANY, 93 }; 94 95 struct tegra210_amx_soc_data { 96 const struct regmap_config *regmap_conf; 97 bool auto_disable; 98 const struct snd_kcontrol_new *controls; 99 unsigned int num_controls; 100 unsigned int max_ch; 101 unsigned int ram_depth; 102 unsigned int byte_mask_size; 103 unsigned int reg_offset; 104 }; 105 106 struct tegra210_amx { 107 const struct tegra210_amx_soc_data *soc_data; 108 unsigned int *map; 109 unsigned int *byte_mask; 110 struct regmap *regmap; 111 }; 112 113 #endif 114