1 // SPDX-License-Identifier: GPL-2.0-only
2 // SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES.
3 // All rights reserved.
4 //
5 // tegra210_amx.c - Tegra210 AMX driver
6
7 #include <linux/bits.h>
8 #include <linux/clk.h>
9 #include <linux/device.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <sound/core.h>
16 #include <sound/pcm.h>
17 #include <sound/pcm_params.h>
18 #include <sound/soc.h>
19
20 #include "tegra210_amx.h"
21 #include "tegra_cif.h"
22
23 /*
24 * The counter is in terms of AHUB clock cycles. If a frame is not
25 * received within these clock cycles, the AMX input channel gets
26 * automatically disabled. For now the counter is calculated as a
27 * function of sample rate (8 kHz) and AHUB clock (49.152 MHz).
28 * If later an accurate number is needed, the counter needs to be
29 * calculated at runtime.
30 *
31 * count = ahub_clk / sample_rate
32 */
33 #define TEGRA194_MAX_FRAME_IDLE_COUNT 0x1800
34
35 #define AMX_CH_REG(id, reg) ((reg) + ((id) * TEGRA210_AMX_AUDIOCIF_CH_STRIDE))
36
37 static const struct reg_default tegra210_amx_reg_defaults[] = {
38 { TEGRA210_AMX_RX_INT_MASK, 0x0000000f},
39 { TEGRA210_AMX_RX1_CIF_CTRL, 0x00007000},
40 { TEGRA210_AMX_RX2_CIF_CTRL, 0x00007000},
41 { TEGRA210_AMX_RX3_CIF_CTRL, 0x00007000},
42 { TEGRA210_AMX_RX4_CIF_CTRL, 0x00007000},
43 { TEGRA210_AMX_TX_INT_MASK, 0x00000001},
44 { TEGRA210_AMX_TX_CIF_CTRL, 0x00007000},
45 { TEGRA210_AMX_CG, 0x1},
46 { TEGRA210_AMX_CFG_RAM_CTRL, 0x00004000},
47 };
48
49 static const struct reg_default tegra264_amx_reg_defaults[] = {
50 { TEGRA210_AMX_RX_INT_MASK, 0x0000000f},
51 { TEGRA210_AMX_RX1_CIF_CTRL, 0x00003800},
52 { TEGRA210_AMX_RX2_CIF_CTRL, 0x00003800},
53 { TEGRA210_AMX_RX3_CIF_CTRL, 0x00003800},
54 { TEGRA210_AMX_RX4_CIF_CTRL, 0x00003800},
55 { TEGRA210_AMX_TX_INT_MASK, 0x00000001},
56 { TEGRA210_AMX_TX_CIF_CTRL, 0x00003800},
57 { TEGRA210_AMX_CG, 0x1},
58 { TEGRA264_AMX_CFG_RAM_CTRL, 0x00004000},
59 };
60
tegra210_amx_write_map_ram(struct tegra210_amx * amx)61 static void tegra210_amx_write_map_ram(struct tegra210_amx *amx)
62 {
63 const unsigned int bits_per_mask = BITS_PER_TYPE(*amx->byte_mask);
64 int i;
65
66 memset(amx->byte_mask, 0,
67 amx->soc_data->byte_mask_size * sizeof(*amx->byte_mask));
68
69 regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_CTRL + amx->soc_data->reg_offset,
70 TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN |
71 TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN |
72 TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE);
73
74 for (i = 0; i < amx->soc_data->ram_depth; i++) {
75 u32 word = 0;
76 int b;
77
78 for (b = 0; b < TEGRA_AMX_SLOTS_PER_WORD; b++) {
79 unsigned int slot = i * TEGRA_AMX_SLOTS_PER_WORD + b;
80 u16 val = amx->map[slot];
81
82 if (val >= 256)
83 continue;
84
85 word |= (u32)val << (b * BITS_PER_BYTE);
86 amx->byte_mask[slot / bits_per_mask] |=
87 1U << (slot % bits_per_mask);
88 }
89 regmap_write(amx->regmap, TEGRA210_AMX_CFG_RAM_DATA + amx->soc_data->reg_offset,
90 word);
91 }
92
93 for (i = 0; i < amx->soc_data->byte_mask_size; i++)
94 regmap_write(amx->regmap,
95 TEGRA210_AMX_OUT_BYTE_EN0 + (i * TEGRA210_AMX_AUDIOCIF_CH_STRIDE),
96 amx->byte_mask[i]);
97 }
98
tegra210_amx_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)99 static int tegra210_amx_startup(struct snd_pcm_substream *substream,
100 struct snd_soc_dai *dai)
101 {
102 struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);
103 unsigned int val;
104 int err;
105
106 /* Ensure if AMX is disabled */
107 err = regmap_read_poll_timeout(amx->regmap, TEGRA210_AMX_STATUS, val,
108 !(val & 0x1), 10, 10000);
109 if (err < 0) {
110 dev_err(dai->dev, "failed to stop AMX, err = %d\n", err);
111 return err;
112 }
113
114 /*
115 * Soft Reset: Below performs module soft reset which clears
116 * all FSM logic, flushes flow control of FIFO and resets the
117 * state register. It also brings module back to disabled
118 * state (without flushing the data in the pipe).
119 */
120 regmap_update_bits(amx->regmap, TEGRA210_AMX_SOFT_RESET,
121 TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK,
122 TEGRA210_AMX_SOFT_RESET_SOFT_EN);
123
124 err = regmap_read_poll_timeout(amx->regmap, TEGRA210_AMX_SOFT_RESET,
125 val, !(val & 0x1), 10, 10000);
126 if (err < 0) {
127 dev_err(dai->dev, "failed to reset AMX, err = %d\n", err);
128 return err;
129 }
130
131 return 0;
132 }
133
tegra210_amx_runtime_suspend(struct device * dev)134 static int tegra210_amx_runtime_suspend(struct device *dev)
135 {
136 struct tegra210_amx *amx = dev_get_drvdata(dev);
137
138 regcache_cache_only(amx->regmap, true);
139 regcache_mark_dirty(amx->regmap);
140
141 return 0;
142 }
143
tegra210_amx_runtime_resume(struct device * dev)144 static int tegra210_amx_runtime_resume(struct device *dev)
145 {
146 struct tegra210_amx *amx = dev_get_drvdata(dev);
147
148 regcache_cache_only(amx->regmap, false);
149 regcache_sync(amx->regmap);
150
151 regmap_update_bits(amx->regmap,
152 TEGRA210_AMX_CTRL,
153 TEGRA210_AMX_CTRL_RX_DEP_MASK,
154 TEGRA210_AMX_WAIT_ON_ANY << TEGRA210_AMX_CTRL_RX_DEP_SHIFT);
155
156 tegra210_amx_write_map_ram(amx);
157
158 return 0;
159 }
160
tegra210_amx_set_audio_cif(struct snd_soc_dai * dai,struct snd_pcm_hw_params * params,unsigned int reg)161 static int tegra210_amx_set_audio_cif(struct snd_soc_dai *dai,
162 struct snd_pcm_hw_params *params,
163 unsigned int reg)
164 {
165 struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);
166 int channels, audio_bits;
167 struct tegra_cif_conf cif_conf;
168
169 memset(&cif_conf, 0, sizeof(struct tegra_cif_conf));
170
171 channels = params_channels(params);
172
173 switch (params_format(params)) {
174 case SNDRV_PCM_FORMAT_S8:
175 audio_bits = TEGRA_ACIF_BITS_8;
176 break;
177 case SNDRV_PCM_FORMAT_S16_LE:
178 audio_bits = TEGRA_ACIF_BITS_16;
179 break;
180 case SNDRV_PCM_FORMAT_S24_LE:
181 case SNDRV_PCM_FORMAT_S32_LE:
182 audio_bits = TEGRA_ACIF_BITS_32;
183 break;
184 default:
185 dev_err(dai->dev, "unsupported format: %d\n",
186 params_format(params));
187 return -EINVAL;
188 }
189
190 cif_conf.audio_ch = channels;
191 cif_conf.client_ch = channels;
192 cif_conf.audio_bits = audio_bits;
193 cif_conf.client_bits = audio_bits;
194
195 if (amx->soc_data->max_ch == TEGRA264_AMX_MAX_CHANNEL)
196 tegra264_set_cif(amx->regmap, reg, &cif_conf);
197 else
198 tegra_set_cif(amx->regmap, reg, &cif_conf);
199
200 return 0;
201 }
202
tegra210_amx_in_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)203 static int tegra210_amx_in_hw_params(struct snd_pcm_substream *substream,
204 struct snd_pcm_hw_params *params,
205 struct snd_soc_dai *dai)
206 {
207 struct tegra210_amx *amx = snd_soc_dai_get_drvdata(dai);
208
209 if (amx->soc_data->auto_disable) {
210 regmap_write(amx->regmap,
211 AMX_CH_REG(dai->id, TEGRA194_AMX_RX1_FRAME_PERIOD +
212 amx->soc_data->reg_offset),
213 TEGRA194_MAX_FRAME_IDLE_COUNT);
214 regmap_write(amx->regmap, TEGRA210_AMX_CYA + amx->soc_data->reg_offset, 1);
215 }
216
217 return tegra210_amx_set_audio_cif(dai, params,
218 AMX_CH_REG(dai->id, TEGRA210_AMX_RX1_CIF_CTRL));
219 }
220
tegra210_amx_out_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)221 static int tegra210_amx_out_hw_params(struct snd_pcm_substream *substream,
222 struct snd_pcm_hw_params *params,
223 struct snd_soc_dai *dai)
224 {
225 return tegra210_amx_set_audio_cif(dai, params,
226 TEGRA210_AMX_TX_CIF_CTRL);
227 }
228
tegra210_amx_get_byte_map(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)229 static int tegra210_amx_get_byte_map(struct snd_kcontrol *kcontrol,
230 struct snd_ctl_elem_value *ucontrol)
231 {
232 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
233 struct soc_mixer_control *mc =
234 (struct soc_mixer_control *)kcontrol->private_value;
235 struct tegra210_amx *amx = snd_soc_component_get_drvdata(cmpnt);
236
237 ucontrol->value.integer.value[0] = amx->map[mc->reg];
238
239 return 0;
240 }
241
tegra210_amx_put_byte_map(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)242 static int tegra210_amx_put_byte_map(struct snd_kcontrol *kcontrol,
243 struct snd_ctl_elem_value *ucontrol)
244 {
245 struct soc_mixer_control *mc =
246 (struct soc_mixer_control *)kcontrol->private_value;
247 struct snd_soc_component *cmpnt = snd_kcontrol_chip(kcontrol);
248 struct tegra210_amx *amx = snd_soc_component_get_drvdata(cmpnt);
249 unsigned int value = ucontrol->value.integer.value[0];
250
251 /*
252 * Match the previous behaviour: any value outside [0, 255] is
253 * treated as the "disabled" sentinel (256). Negative values from
254 * userspace fold in through the unsigned cast and are caught here.
255 */
256 if (value > 255)
257 value = 256;
258
259 if (amx->map[mc->reg] == value)
260 return 0;
261
262 amx->map[mc->reg] = value;
263
264 return 1;
265 }
266
267 static const struct snd_soc_dai_ops tegra210_amx_out_dai_ops = {
268 .hw_params = tegra210_amx_out_hw_params,
269 .startup = tegra210_amx_startup,
270 };
271
272 static const struct snd_soc_dai_ops tegra210_amx_in_dai_ops = {
273 .hw_params = tegra210_amx_in_hw_params,
274 };
275
276 #define IN_DAI(id) \
277 { \
278 .name = "AMX-RX-CIF" #id, \
279 .playback = { \
280 .stream_name = "RX" #id "-CIF-Playback",\
281 .channels_min = 1, \
282 .channels_max = 16, \
283 .rates = SNDRV_PCM_RATE_8000_192000, \
284 .formats = SNDRV_PCM_FMTBIT_S8 | \
285 SNDRV_PCM_FMTBIT_S16_LE | \
286 SNDRV_PCM_FMTBIT_S24_LE | \
287 SNDRV_PCM_FMTBIT_S32_LE, \
288 }, \
289 .capture = { \
290 .stream_name = "RX" #id "-CIF-Capture", \
291 .channels_min = 1, \
292 .channels_max = 16, \
293 .rates = SNDRV_PCM_RATE_8000_192000, \
294 .formats = SNDRV_PCM_FMTBIT_S8 | \
295 SNDRV_PCM_FMTBIT_S16_LE | \
296 SNDRV_PCM_FMTBIT_S24_LE | \
297 SNDRV_PCM_FMTBIT_S32_LE, \
298 }, \
299 .ops = &tegra210_amx_in_dai_ops, \
300 }
301
302 #define OUT_DAI \
303 { \
304 .name = "AMX-TX-CIF", \
305 .playback = { \
306 .stream_name = "TX-CIF-Playback", \
307 .channels_min = 1, \
308 .channels_max = 16, \
309 .rates = SNDRV_PCM_RATE_8000_192000, \
310 .formats = SNDRV_PCM_FMTBIT_S8 | \
311 SNDRV_PCM_FMTBIT_S16_LE | \
312 SNDRV_PCM_FMTBIT_S24_LE | \
313 SNDRV_PCM_FMTBIT_S32_LE, \
314 }, \
315 .capture = { \
316 .stream_name = "TX-CIF-Capture", \
317 .channels_min = 1, \
318 .channels_max = 16, \
319 .rates = SNDRV_PCM_RATE_8000_192000, \
320 .formats = SNDRV_PCM_FMTBIT_S8 | \
321 SNDRV_PCM_FMTBIT_S16_LE | \
322 SNDRV_PCM_FMTBIT_S24_LE | \
323 SNDRV_PCM_FMTBIT_S32_LE, \
324 }, \
325 .ops = &tegra210_amx_out_dai_ops, \
326 }
327
328 static struct snd_soc_dai_driver tegra210_amx_dais[] = {
329 IN_DAI(1),
330 IN_DAI(2),
331 IN_DAI(3),
332 IN_DAI(4),
333 OUT_DAI,
334 };
335
336 static const struct snd_soc_dapm_widget tegra210_amx_widgets[] = {
337 SND_SOC_DAPM_AIF_IN("RX1", NULL, 0, TEGRA210_AMX_CTRL, 0, 0),
338 SND_SOC_DAPM_AIF_IN("RX2", NULL, 0, TEGRA210_AMX_CTRL, 1, 0),
339 SND_SOC_DAPM_AIF_IN("RX3", NULL, 0, TEGRA210_AMX_CTRL, 2, 0),
340 SND_SOC_DAPM_AIF_IN("RX4", NULL, 0, TEGRA210_AMX_CTRL, 3, 0),
341 SND_SOC_DAPM_AIF_OUT("TX", NULL, 0, TEGRA210_AMX_ENABLE,
342 TEGRA210_AMX_ENABLE_SHIFT, 0),
343 };
344
345 #define STREAM_ROUTES(id, sname) \
346 { "RX" #id " XBAR-" sname, NULL, "RX" #id " XBAR-TX" }, \
347 { "RX" #id "-CIF-" sname, NULL, "RX" #id " XBAR-" sname },\
348 { "RX" #id, NULL, "RX" #id "-CIF-" sname }, \
349 { "TX", NULL, "RX" #id }, \
350 { "TX-CIF-" sname, NULL, "TX" }, \
351 { "XBAR-" sname, NULL, "TX-CIF-" sname }, \
352 { "XBAR-RX", NULL, "XBAR-" sname }
353
354 #define AMX_ROUTES(id) \
355 STREAM_ROUTES(id, "Playback"), \
356 STREAM_ROUTES(id, "Capture")
357
358 static const struct snd_soc_dapm_route tegra210_amx_routes[] = {
359 AMX_ROUTES(1),
360 AMX_ROUTES(2),
361 AMX_ROUTES(3),
362 AMX_ROUTES(4),
363 };
364
365 #define TEGRA210_AMX_BYTE_MAP_CTRL(reg) \
366 SOC_SINGLE_EXT("Byte Map " #reg, reg, 0, 256, 0, \
367 tegra210_amx_get_byte_map, \
368 tegra210_amx_put_byte_map)
369
370 static struct snd_kcontrol_new tegra210_amx_controls[] = {
371 TEGRA210_AMX_BYTE_MAP_CTRL(0),
372 TEGRA210_AMX_BYTE_MAP_CTRL(1),
373 TEGRA210_AMX_BYTE_MAP_CTRL(2),
374 TEGRA210_AMX_BYTE_MAP_CTRL(3),
375 TEGRA210_AMX_BYTE_MAP_CTRL(4),
376 TEGRA210_AMX_BYTE_MAP_CTRL(5),
377 TEGRA210_AMX_BYTE_MAP_CTRL(6),
378 TEGRA210_AMX_BYTE_MAP_CTRL(7),
379 TEGRA210_AMX_BYTE_MAP_CTRL(8),
380 TEGRA210_AMX_BYTE_MAP_CTRL(9),
381 TEGRA210_AMX_BYTE_MAP_CTRL(10),
382 TEGRA210_AMX_BYTE_MAP_CTRL(11),
383 TEGRA210_AMX_BYTE_MAP_CTRL(12),
384 TEGRA210_AMX_BYTE_MAP_CTRL(13),
385 TEGRA210_AMX_BYTE_MAP_CTRL(14),
386 TEGRA210_AMX_BYTE_MAP_CTRL(15),
387 TEGRA210_AMX_BYTE_MAP_CTRL(16),
388 TEGRA210_AMX_BYTE_MAP_CTRL(17),
389 TEGRA210_AMX_BYTE_MAP_CTRL(18),
390 TEGRA210_AMX_BYTE_MAP_CTRL(19),
391 TEGRA210_AMX_BYTE_MAP_CTRL(20),
392 TEGRA210_AMX_BYTE_MAP_CTRL(21),
393 TEGRA210_AMX_BYTE_MAP_CTRL(22),
394 TEGRA210_AMX_BYTE_MAP_CTRL(23),
395 TEGRA210_AMX_BYTE_MAP_CTRL(24),
396 TEGRA210_AMX_BYTE_MAP_CTRL(25),
397 TEGRA210_AMX_BYTE_MAP_CTRL(26),
398 TEGRA210_AMX_BYTE_MAP_CTRL(27),
399 TEGRA210_AMX_BYTE_MAP_CTRL(28),
400 TEGRA210_AMX_BYTE_MAP_CTRL(29),
401 TEGRA210_AMX_BYTE_MAP_CTRL(30),
402 TEGRA210_AMX_BYTE_MAP_CTRL(31),
403 TEGRA210_AMX_BYTE_MAP_CTRL(32),
404 TEGRA210_AMX_BYTE_MAP_CTRL(33),
405 TEGRA210_AMX_BYTE_MAP_CTRL(34),
406 TEGRA210_AMX_BYTE_MAP_CTRL(35),
407 TEGRA210_AMX_BYTE_MAP_CTRL(36),
408 TEGRA210_AMX_BYTE_MAP_CTRL(37),
409 TEGRA210_AMX_BYTE_MAP_CTRL(38),
410 TEGRA210_AMX_BYTE_MAP_CTRL(39),
411 TEGRA210_AMX_BYTE_MAP_CTRL(40),
412 TEGRA210_AMX_BYTE_MAP_CTRL(41),
413 TEGRA210_AMX_BYTE_MAP_CTRL(42),
414 TEGRA210_AMX_BYTE_MAP_CTRL(43),
415 TEGRA210_AMX_BYTE_MAP_CTRL(44),
416 TEGRA210_AMX_BYTE_MAP_CTRL(45),
417 TEGRA210_AMX_BYTE_MAP_CTRL(46),
418 TEGRA210_AMX_BYTE_MAP_CTRL(47),
419 TEGRA210_AMX_BYTE_MAP_CTRL(48),
420 TEGRA210_AMX_BYTE_MAP_CTRL(49),
421 TEGRA210_AMX_BYTE_MAP_CTRL(50),
422 TEGRA210_AMX_BYTE_MAP_CTRL(51),
423 TEGRA210_AMX_BYTE_MAP_CTRL(52),
424 TEGRA210_AMX_BYTE_MAP_CTRL(53),
425 TEGRA210_AMX_BYTE_MAP_CTRL(54),
426 TEGRA210_AMX_BYTE_MAP_CTRL(55),
427 TEGRA210_AMX_BYTE_MAP_CTRL(56),
428 TEGRA210_AMX_BYTE_MAP_CTRL(57),
429 TEGRA210_AMX_BYTE_MAP_CTRL(58),
430 TEGRA210_AMX_BYTE_MAP_CTRL(59),
431 TEGRA210_AMX_BYTE_MAP_CTRL(60),
432 TEGRA210_AMX_BYTE_MAP_CTRL(61),
433 TEGRA210_AMX_BYTE_MAP_CTRL(62),
434 TEGRA210_AMX_BYTE_MAP_CTRL(63),
435 };
436
437 static struct snd_kcontrol_new tegra264_amx_controls[] = {
438 TEGRA210_AMX_BYTE_MAP_CTRL(64),
439 TEGRA210_AMX_BYTE_MAP_CTRL(65),
440 TEGRA210_AMX_BYTE_MAP_CTRL(66),
441 TEGRA210_AMX_BYTE_MAP_CTRL(67),
442 TEGRA210_AMX_BYTE_MAP_CTRL(68),
443 TEGRA210_AMX_BYTE_MAP_CTRL(69),
444 TEGRA210_AMX_BYTE_MAP_CTRL(70),
445 TEGRA210_AMX_BYTE_MAP_CTRL(71),
446 TEGRA210_AMX_BYTE_MAP_CTRL(72),
447 TEGRA210_AMX_BYTE_MAP_CTRL(73),
448 TEGRA210_AMX_BYTE_MAP_CTRL(74),
449 TEGRA210_AMX_BYTE_MAP_CTRL(75),
450 TEGRA210_AMX_BYTE_MAP_CTRL(76),
451 TEGRA210_AMX_BYTE_MAP_CTRL(77),
452 TEGRA210_AMX_BYTE_MAP_CTRL(78),
453 TEGRA210_AMX_BYTE_MAP_CTRL(79),
454 TEGRA210_AMX_BYTE_MAP_CTRL(80),
455 TEGRA210_AMX_BYTE_MAP_CTRL(81),
456 TEGRA210_AMX_BYTE_MAP_CTRL(82),
457 TEGRA210_AMX_BYTE_MAP_CTRL(83),
458 TEGRA210_AMX_BYTE_MAP_CTRL(84),
459 TEGRA210_AMX_BYTE_MAP_CTRL(85),
460 TEGRA210_AMX_BYTE_MAP_CTRL(86),
461 TEGRA210_AMX_BYTE_MAP_CTRL(87),
462 TEGRA210_AMX_BYTE_MAP_CTRL(88),
463 TEGRA210_AMX_BYTE_MAP_CTRL(89),
464 TEGRA210_AMX_BYTE_MAP_CTRL(90),
465 TEGRA210_AMX_BYTE_MAP_CTRL(91),
466 TEGRA210_AMX_BYTE_MAP_CTRL(92),
467 TEGRA210_AMX_BYTE_MAP_CTRL(93),
468 TEGRA210_AMX_BYTE_MAP_CTRL(94),
469 TEGRA210_AMX_BYTE_MAP_CTRL(95),
470 TEGRA210_AMX_BYTE_MAP_CTRL(96),
471 TEGRA210_AMX_BYTE_MAP_CTRL(97),
472 TEGRA210_AMX_BYTE_MAP_CTRL(98),
473 TEGRA210_AMX_BYTE_MAP_CTRL(99),
474 TEGRA210_AMX_BYTE_MAP_CTRL(100),
475 TEGRA210_AMX_BYTE_MAP_CTRL(101),
476 TEGRA210_AMX_BYTE_MAP_CTRL(102),
477 TEGRA210_AMX_BYTE_MAP_CTRL(103),
478 TEGRA210_AMX_BYTE_MAP_CTRL(104),
479 TEGRA210_AMX_BYTE_MAP_CTRL(105),
480 TEGRA210_AMX_BYTE_MAP_CTRL(106),
481 TEGRA210_AMX_BYTE_MAP_CTRL(107),
482 TEGRA210_AMX_BYTE_MAP_CTRL(108),
483 TEGRA210_AMX_BYTE_MAP_CTRL(109),
484 TEGRA210_AMX_BYTE_MAP_CTRL(110),
485 TEGRA210_AMX_BYTE_MAP_CTRL(111),
486 TEGRA210_AMX_BYTE_MAP_CTRL(112),
487 TEGRA210_AMX_BYTE_MAP_CTRL(113),
488 TEGRA210_AMX_BYTE_MAP_CTRL(114),
489 TEGRA210_AMX_BYTE_MAP_CTRL(115),
490 TEGRA210_AMX_BYTE_MAP_CTRL(116),
491 TEGRA210_AMX_BYTE_MAP_CTRL(117),
492 TEGRA210_AMX_BYTE_MAP_CTRL(118),
493 TEGRA210_AMX_BYTE_MAP_CTRL(119),
494 TEGRA210_AMX_BYTE_MAP_CTRL(120),
495 TEGRA210_AMX_BYTE_MAP_CTRL(121),
496 TEGRA210_AMX_BYTE_MAP_CTRL(122),
497 TEGRA210_AMX_BYTE_MAP_CTRL(123),
498 TEGRA210_AMX_BYTE_MAP_CTRL(124),
499 TEGRA210_AMX_BYTE_MAP_CTRL(125),
500 TEGRA210_AMX_BYTE_MAP_CTRL(126),
501 TEGRA210_AMX_BYTE_MAP_CTRL(127),
502 };
503
tegra210_amx_component_probe(struct snd_soc_component * component)504 static int tegra210_amx_component_probe(struct snd_soc_component *component)
505 {
506 struct tegra210_amx *amx = snd_soc_component_get_drvdata(component);
507
508 if (amx->soc_data->num_controls)
509 return snd_soc_add_component_controls(component, amx->soc_data->controls,
510 amx->soc_data->num_controls);
511
512 return 0;
513 }
514
515 static const struct snd_soc_component_driver tegra210_amx_cmpnt = {
516 .probe = tegra210_amx_component_probe,
517 .dapm_widgets = tegra210_amx_widgets,
518 .num_dapm_widgets = ARRAY_SIZE(tegra210_amx_widgets),
519 .dapm_routes = tegra210_amx_routes,
520 .num_dapm_routes = ARRAY_SIZE(tegra210_amx_routes),
521 .controls = tegra210_amx_controls,
522 .num_controls = ARRAY_SIZE(tegra210_amx_controls),
523 };
524
tegra210_amx_wr_reg(struct device * dev,unsigned int reg)525 static bool tegra210_amx_wr_reg(struct device *dev, unsigned int reg)
526 {
527 switch (reg) {
528 case TEGRA210_AMX_RX_INT_MASK ... TEGRA210_AMX_RX4_CIF_CTRL:
529 case TEGRA210_AMX_TX_INT_MASK ... TEGRA210_AMX_CG:
530 case TEGRA210_AMX_CTRL ... TEGRA210_AMX_CYA:
531 case TEGRA210_AMX_CFG_RAM_CTRL ... TEGRA210_AMX_CFG_RAM_DATA:
532 return true;
533 default:
534 return false;
535 }
536 }
537
tegra194_amx_wr_reg(struct device * dev,unsigned int reg)538 static bool tegra194_amx_wr_reg(struct device *dev, unsigned int reg)
539 {
540 switch (reg) {
541 case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD:
542 return true;
543 default:
544 return tegra210_amx_wr_reg(dev, reg);
545 }
546 }
547
tegra264_amx_wr_reg(struct device * dev,unsigned int reg)548 static bool tegra264_amx_wr_reg(struct device *dev,
549 unsigned int reg)
550 {
551 switch (reg) {
552 case TEGRA210_AMX_RX_INT_MASK ... TEGRA210_AMX_RX4_CIF_CTRL:
553 case TEGRA210_AMX_TX_INT_MASK ... TEGRA210_AMX_TX_CIF_CTRL:
554 case TEGRA210_AMX_ENABLE ... TEGRA210_AMX_CG:
555 case TEGRA210_AMX_CTRL ... TEGRA264_AMX_STREAMS_AUTO_DISABLE:
556 case TEGRA264_AMX_CFG_RAM_CTRL ... TEGRA264_AMX_CFG_RAM_DATA:
557 case TEGRA264_AMX_RX1_FRAME_PERIOD ... TEGRA264_AMX_RX4_FRAME_PERIOD:
558 return true;
559 default:
560 return false;
561 }
562 }
563
tegra210_amx_rd_reg(struct device * dev,unsigned int reg)564 static bool tegra210_amx_rd_reg(struct device *dev, unsigned int reg)
565 {
566 switch (reg) {
567 case TEGRA210_AMX_RX_STATUS ... TEGRA210_AMX_CFG_RAM_DATA:
568 return true;
569 default:
570 return false;
571 }
572 }
573
tegra194_amx_rd_reg(struct device * dev,unsigned int reg)574 static bool tegra194_amx_rd_reg(struct device *dev, unsigned int reg)
575 {
576 switch (reg) {
577 case TEGRA194_AMX_RX1_FRAME_PERIOD ... TEGRA194_AMX_RX4_FRAME_PERIOD:
578 return true;
579 default:
580 return tegra210_amx_rd_reg(dev, reg);
581 }
582 }
583
tegra264_amx_rd_reg(struct device * dev,unsigned int reg)584 static bool tegra264_amx_rd_reg(struct device *dev,
585 unsigned int reg)
586 {
587 switch (reg) {
588 case TEGRA210_AMX_RX_STATUS ... TEGRA210_AMX_RX4_CIF_CTRL:
589 case TEGRA210_AMX_TX_STATUS ... TEGRA210_AMX_TX_CIF_CTRL:
590 case TEGRA210_AMX_ENABLE ... TEGRA210_AMX_INT_STATUS:
591 case TEGRA210_AMX_CTRL ... TEGRA264_AMX_CFG_RAM_DATA:
592 case TEGRA264_AMX_RX1_FRAME_PERIOD ... TEGRA264_AMX_RX4_FRAME_PERIOD:
593 return true;
594 default:
595 return false;
596 }
597 }
598
tegra210_amx_volatile_reg(struct device * dev,unsigned int reg)599 static bool tegra210_amx_volatile_reg(struct device *dev, unsigned int reg)
600 {
601 switch (reg) {
602 case TEGRA210_AMX_RX_STATUS:
603 case TEGRA210_AMX_RX_INT_STATUS:
604 case TEGRA210_AMX_RX_INT_SET:
605 case TEGRA210_AMX_TX_STATUS:
606 case TEGRA210_AMX_TX_INT_STATUS:
607 case TEGRA210_AMX_TX_INT_SET:
608 case TEGRA210_AMX_SOFT_RESET:
609 case TEGRA210_AMX_STATUS:
610 case TEGRA210_AMX_INT_STATUS:
611 case TEGRA210_AMX_CFG_RAM_CTRL:
612 case TEGRA210_AMX_CFG_RAM_DATA:
613 return true;
614 default:
615 break;
616 }
617
618 return false;
619 }
620
tegra264_amx_volatile_reg(struct device * dev,unsigned int reg)621 static bool tegra264_amx_volatile_reg(struct device *dev,
622 unsigned int reg)
623 {
624 switch (reg) {
625 case TEGRA210_AMX_RX_STATUS:
626 case TEGRA210_AMX_RX_INT_STATUS:
627 case TEGRA210_AMX_RX_INT_SET:
628 case TEGRA210_AMX_TX_STATUS:
629 case TEGRA210_AMX_TX_INT_STATUS:
630 case TEGRA210_AMX_TX_INT_SET:
631 case TEGRA210_AMX_SOFT_RESET:
632 case TEGRA210_AMX_STATUS:
633 case TEGRA210_AMX_INT_STATUS:
634 case TEGRA264_AMX_CFG_RAM_CTRL:
635 case TEGRA264_AMX_CFG_RAM_DATA:
636 return true;
637 default:
638 break;
639 }
640
641 return false;
642 }
643
644 static const struct regmap_config tegra210_amx_regmap_config = {
645 .reg_bits = 32,
646 .reg_stride = 4,
647 .val_bits = 32,
648 .max_register = TEGRA210_AMX_CFG_RAM_DATA,
649 .writeable_reg = tegra210_amx_wr_reg,
650 .readable_reg = tegra210_amx_rd_reg,
651 .volatile_reg = tegra210_amx_volatile_reg,
652 .reg_defaults = tegra210_amx_reg_defaults,
653 .num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults),
654 .reg_default_cb = regmap_default_zero_cb,
655 .cache_type = REGCACHE_FLAT,
656 };
657
658 static const struct regmap_config tegra194_amx_regmap_config = {
659 .reg_bits = 32,
660 .reg_stride = 4,
661 .val_bits = 32,
662 .max_register = TEGRA194_AMX_RX4_LAST_FRAME_PERIOD,
663 .writeable_reg = tegra194_amx_wr_reg,
664 .readable_reg = tegra194_amx_rd_reg,
665 .volatile_reg = tegra210_amx_volatile_reg,
666 .reg_defaults = tegra210_amx_reg_defaults,
667 .num_reg_defaults = ARRAY_SIZE(tegra210_amx_reg_defaults),
668 .reg_default_cb = regmap_default_zero_cb,
669 .cache_type = REGCACHE_FLAT,
670 };
671
672 static const struct regmap_config tegra264_amx_regmap_config = {
673 .reg_bits = 32,
674 .reg_stride = 4,
675 .val_bits = 32,
676 .max_register = TEGRA264_AMX_RX4_LAST_FRAME_PERIOD,
677 .writeable_reg = tegra264_amx_wr_reg,
678 .readable_reg = tegra264_amx_rd_reg,
679 .volatile_reg = tegra264_amx_volatile_reg,
680 .reg_defaults = tegra264_amx_reg_defaults,
681 .num_reg_defaults = ARRAY_SIZE(tegra264_amx_reg_defaults),
682 .reg_default_cb = regmap_default_zero_cb,
683 .cache_type = REGCACHE_FLAT,
684 };
685
686 static const struct tegra210_amx_soc_data soc_data_tegra210 = {
687 .regmap_conf = &tegra210_amx_regmap_config,
688 .max_ch = TEGRA210_AMX_MAX_CHANNEL,
689 .ram_depth = TEGRA210_AMX_RAM_DEPTH,
690 .byte_mask_size = TEGRA210_AMX_BYTE_MASK_COUNT,
691 .reg_offset = TEGRA210_AMX_AUTO_DISABLE_OFFSET,
692 };
693
694 static const struct tegra210_amx_soc_data soc_data_tegra194 = {
695 .regmap_conf = &tegra194_amx_regmap_config,
696 .auto_disable = true,
697 .max_ch = TEGRA210_AMX_MAX_CHANNEL,
698 .ram_depth = TEGRA210_AMX_RAM_DEPTH,
699 .byte_mask_size = TEGRA210_AMX_BYTE_MASK_COUNT,
700 .reg_offset = TEGRA210_AMX_AUTO_DISABLE_OFFSET,
701 };
702
703 static const struct tegra210_amx_soc_data soc_data_tegra264 = {
704 .regmap_conf = &tegra264_amx_regmap_config,
705 .auto_disable = true,
706 .max_ch = TEGRA264_AMX_MAX_CHANNEL,
707 .ram_depth = TEGRA264_AMX_RAM_DEPTH,
708 .byte_mask_size = TEGRA264_AMX_BYTE_MASK_COUNT,
709 .reg_offset = TEGRA264_AMX_AUTO_DISABLE_OFFSET,
710 .controls = tegra264_amx_controls,
711 .num_controls = ARRAY_SIZE(tegra264_amx_controls),
712 };
713
714 static const struct of_device_id tegra210_amx_of_match[] = {
715 { .compatible = "nvidia,tegra210-amx", .data = &soc_data_tegra210 },
716 { .compatible = "nvidia,tegra194-amx", .data = &soc_data_tegra194 },
717 { .compatible = "nvidia,tegra264-amx", .data = &soc_data_tegra264 },
718 {},
719 };
720 MODULE_DEVICE_TABLE(of, tegra210_amx_of_match);
721
tegra210_amx_platform_probe(struct platform_device * pdev)722 static int tegra210_amx_platform_probe(struct platform_device *pdev)
723 {
724 struct device *dev = &pdev->dev;
725 struct tegra210_amx *amx;
726 void __iomem *regs;
727 int err, i;
728
729 amx = devm_kzalloc(dev, sizeof(*amx), GFP_KERNEL);
730 if (!amx)
731 return -ENOMEM;
732
733 amx->soc_data = device_get_match_data(dev);
734
735 dev_set_drvdata(dev, amx);
736
737 regs = devm_platform_ioremap_resource(pdev, 0);
738 if (IS_ERR(regs))
739 return PTR_ERR(regs);
740
741 amx->regmap = devm_regmap_init_mmio(dev, regs,
742 amx->soc_data->regmap_conf);
743 if (IS_ERR(amx->regmap))
744 return dev_err_probe(dev, PTR_ERR(amx->regmap),
745 "regmap init failed\n");
746
747 regcache_cache_only(amx->regmap, true);
748
749 amx->map = devm_kcalloc(dev,
750 amx->soc_data->ram_depth * TEGRA_AMX_SLOTS_PER_WORD,
751 sizeof(*amx->map), GFP_KERNEL);
752 if (!amx->map)
753 return -ENOMEM;
754
755 amx->byte_mask = devm_kcalloc(dev, amx->soc_data->byte_mask_size,
756 sizeof(*amx->byte_mask), GFP_KERNEL);
757 if (!amx->byte_mask)
758 return -ENOMEM;
759
760 /* Initialise all byte map slots as disabled (value 256). */
761 for (i = 0; i < amx->soc_data->ram_depth * TEGRA_AMX_SLOTS_PER_WORD; i++)
762 amx->map[i] = 256;
763
764 tegra210_amx_dais[TEGRA_AMX_OUT_DAI_ID].capture.channels_max =
765 amx->soc_data->max_ch;
766
767 err = devm_snd_soc_register_component(dev, &tegra210_amx_cmpnt,
768 tegra210_amx_dais,
769 ARRAY_SIZE(tegra210_amx_dais));
770 if (err)
771 return dev_err_probe(dev, err,
772 "can't register AMX component\n");
773
774 pm_runtime_enable(dev);
775
776 return 0;
777 }
778
tegra210_amx_platform_remove(struct platform_device * pdev)779 static void tegra210_amx_platform_remove(struct platform_device *pdev)
780 {
781 pm_runtime_disable(&pdev->dev);
782 }
783
784 static const struct dev_pm_ops tegra210_amx_pm_ops = {
785 RUNTIME_PM_OPS(tegra210_amx_runtime_suspend,
786 tegra210_amx_runtime_resume, NULL)
787 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
788 };
789
790 static struct platform_driver tegra210_amx_driver = {
791 .driver = {
792 .name = "tegra210-amx",
793 .of_match_table = tegra210_amx_of_match,
794 .pm = pm_ptr(&tegra210_amx_pm_ops),
795 },
796 .probe = tegra210_amx_platform_probe,
797 .remove = tegra210_amx_platform_remove,
798 };
799 module_platform_driver(tegra210_amx_driver);
800
801 MODULE_AUTHOR("Songhee Baek <sbaek@nvidia.com>");
802 MODULE_DESCRIPTION("Tegra210 AMX ASoC driver");
803 MODULE_LICENSE("GPL v2");
804