1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12/ { 13 compatible = "nvidia,tegra210"; 14 interrupt-parent = <&lic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 pcie@1003000 { 19 compatible = "nvidia,tegra210-pcie"; 20 device_type = "pci"; 21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 24 reg-names = "pads", "afi", "cs"; 25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 27 interrupt-names = "intr", "msi"; 28 29 #interrupt-cells = <1>; 30 interrupt-map-mask = <0 0 0 0>; 31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 32 33 bus-range = <0x00 0xff>; 34 #address-cells = <3>; 35 #size-cells = <2>; 36 37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 42 43 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 44 <&tegra_car TEGRA210_CLK_AFI>, 45 <&tegra_car TEGRA210_CLK_PLL_E>, 46 <&tegra_car TEGRA210_CLK_CML0>; 47 clock-names = "pex", "afi", "pll_e", "cml"; 48 resets = <&tegra_car 70>, 49 <&tegra_car 72>, 50 <&tegra_car 74>; 51 reset-names = "pex", "afi", "pcie_x"; 52 53 pinctrl-names = "default", "idle"; 54 pinctrl-0 = <&pex_dpd_disable>; 55 pinctrl-1 = <&pex_dpd_enable>; 56 57 status = "disabled"; 58 59 pci@1,0 { 60 device_type = "pci"; 61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 62 reg = <0x000800 0 0 0 0>; 63 bus-range = <0x00 0xff>; 64 status = "disabled"; 65 66 #address-cells = <3>; 67 #size-cells = <2>; 68 ranges; 69 70 nvidia,num-lanes = <4>; 71 }; 72 73 pci@2,0 { 74 device_type = "pci"; 75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 76 reg = <0x001000 0 0 0 0>; 77 bus-range = <0x00 0xff>; 78 status = "disabled"; 79 80 #address-cells = <3>; 81 #size-cells = <2>; 82 ranges; 83 84 nvidia,num-lanes = <1>; 85 }; 86 }; 87 88 host1x@50000000 { 89 compatible = "nvidia,tegra210-host1x"; 90 reg = <0x0 0x50000000 0x0 0x00034000>; 91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 93 interrupt-names = "syncpt", "host1x"; 94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 95 clock-names = "host1x"; 96 resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; 97 reset-names = "host1x", "mc"; 98 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 103 104 iommus = <&mc TEGRA_SWGROUP_HC>; 105 106 dpaux1: dpaux@54040000 { 107 compatible = "nvidia,tegra210-dpaux"; 108 reg = <0x0 0x54040000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 111 <&tegra_car TEGRA210_CLK_PLL_DP>; 112 clock-names = "dpaux", "parent"; 113 resets = <&tegra_car 207>; 114 reset-names = "dpaux"; 115 power-domains = <&pd_sor>; 116 status = "disabled"; 117 118 state_dpaux1_aux: pinmux-aux { 119 groups = "dpaux-io"; 120 function = "aux"; 121 }; 122 123 state_dpaux1_i2c: pinmux-i2c { 124 groups = "dpaux-io"; 125 function = "i2c"; 126 }; 127 128 state_dpaux1_off: pinmux-off { 129 groups = "dpaux-io"; 130 function = "off"; 131 }; 132 133 i2c-bus { 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 }; 138 139 vi@54080000 { 140 compatible = "nvidia,tegra210-vi"; 141 reg = <0x0 0x54080000 0x0 0x700>; 142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 146 147 clocks = <&tegra_car TEGRA210_CLK_VI>; 148 power-domains = <&pd_venc>; 149 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 ranges = <0x0 0x0 0x54080000 0x2000>; 154 155 csi@838 { 156 compatible = "nvidia,tegra210-csi"; 157 reg = <0x838 0x1300>; 158 status = "disabled"; 159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 160 <&tegra_car TEGRA210_CLK_CILCD>, 161 <&tegra_car TEGRA210_CLK_CILE>, 162 <&tegra_car TEGRA210_CLK_CSI_TPG>; 163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 164 <&tegra_car TEGRA210_CLK_PLL_P>, 165 <&tegra_car TEGRA210_CLK_PLL_P>; 166 assigned-clock-rates = <102000000>, 167 <102000000>, 168 <102000000>, 169 <972000000>; 170 171 clocks = <&tegra_car TEGRA210_CLK_CSI>, 172 <&tegra_car TEGRA210_CLK_CILAB>, 173 <&tegra_car TEGRA210_CLK_CILCD>, 174 <&tegra_car TEGRA210_CLK_CILE>, 175 <&tegra_car TEGRA210_CLK_CSI_TPG>; 176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 177 power-domains = <&pd_sor>; 178 }; 179 }; 180 181 tsec@54100000 { 182 compatible = "nvidia,tegra210-tsec"; 183 reg = <0x0 0x54100000 0x0 0x00040000>; 184 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&tegra_car TEGRA210_CLK_TSEC>; 186 clock-names = "tsec"; 187 resets = <&tegra_car 83>; 188 reset-names = "tsec"; 189 status = "disabled"; 190 }; 191 192 dc@54200000 { 193 compatible = "nvidia,tegra210-dc"; 194 reg = <0x0 0x54200000 0x0 0x00040000>; 195 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 197 clock-names = "dc"; 198 resets = <&tegra_car 27>; 199 reset-names = "dc"; 200 201 iommus = <&mc TEGRA_SWGROUP_DC>; 202 203 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 204 nvidia,head = <0>; 205 }; 206 207 dc@54240000 { 208 compatible = "nvidia,tegra210-dc"; 209 reg = <0x0 0x54240000 0x0 0x00040000>; 210 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 212 clock-names = "dc"; 213 resets = <&tegra_car 26>; 214 reset-names = "dc"; 215 216 iommus = <&mc TEGRA_SWGROUP_DCB>; 217 218 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 219 nvidia,head = <1>; 220 }; 221 222 dsia: dsi@54300000 { 223 compatible = "nvidia,tegra210-dsi"; 224 reg = <0x0 0x54300000 0x0 0x00040000>; 225 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 226 <&tegra_car TEGRA210_CLK_DSIALP>, 227 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 228 clock-names = "dsi", "lp", "parent"; 229 resets = <&tegra_car 48>; 230 reset-names = "dsi"; 231 power-domains = <&pd_sor>; 232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 233 234 status = "disabled"; 235 236 #address-cells = <1>; 237 #size-cells = <0>; 238 }; 239 240 vic@54340000 { 241 compatible = "nvidia,tegra210-vic"; 242 reg = <0x0 0x54340000 0x0 0x00040000>; 243 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 245 clock-names = "vic"; 246 resets = <&tegra_car 178>; 247 reset-names = "vic"; 248 249 iommus = <&mc TEGRA_SWGROUP_VIC>; 250 power-domains = <&pd_vic>; 251 }; 252 253 nvjpg@54380000 { 254 compatible = "nvidia,tegra210-nvjpg"; 255 reg = <0x0 0x54380000 0x0 0x00040000>; 256 status = "disabled"; 257 }; 258 259 dsib: dsi@54400000 { 260 compatible = "nvidia,tegra210-dsi"; 261 reg = <0x0 0x54400000 0x0 0x00040000>; 262 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 263 <&tegra_car TEGRA210_CLK_DSIBLP>, 264 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 265 clock-names = "dsi", "lp", "parent"; 266 resets = <&tegra_car 82>; 267 reset-names = "dsi"; 268 power-domains = <&pd_sor>; 269 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 270 271 status = "disabled"; 272 273 #address-cells = <1>; 274 #size-cells = <0>; 275 }; 276 277 nvdec@54480000 { 278 compatible = "nvidia,tegra210-nvdec"; 279 reg = <0x0 0x54480000 0x0 0x00040000>; 280 status = "disabled"; 281 }; 282 283 nvenc@544c0000 { 284 compatible = "nvidia,tegra210-nvenc"; 285 reg = <0x0 0x544c0000 0x0 0x00040000>; 286 status = "disabled"; 287 }; 288 289 tsec@54500000 { 290 compatible = "nvidia,tegra210-tsec"; 291 reg = <0x0 0x54500000 0x0 0x00040000>; 292 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 293 clocks = <&tegra_car TEGRA210_CLK_TSECB>; 294 clock-names = "tsec"; 295 resets = <&tegra_car 206>; 296 reset-names = "tsec"; 297 status = "disabled"; 298 }; 299 300 sor0: sor@54540000 { 301 compatible = "nvidia,tegra210-sor"; 302 reg = <0x0 0x54540000 0x0 0x00040000>; 303 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 305 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 306 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 307 <&tegra_car TEGRA210_CLK_PLL_DP>, 308 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 309 clock-names = "sor", "out", "parent", "dp", "safe"; 310 resets = <&tegra_car 182>; 311 reset-names = "sor"; 312 pinctrl-0 = <&state_dpaux_aux>; 313 pinctrl-1 = <&state_dpaux_i2c>; 314 pinctrl-2 = <&state_dpaux_off>; 315 pinctrl-names = "aux", "i2c", "off"; 316 power-domains = <&pd_sor>; 317 status = "disabled"; 318 }; 319 320 sor1: sor@54580000 { 321 compatible = "nvidia,tegra210-sor1"; 322 reg = <0x0 0x54580000 0x0 0x00040000>; 323 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 325 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 326 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 327 <&tegra_car TEGRA210_CLK_PLL_DP>, 328 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 329 clock-names = "sor", "out", "parent", "dp", "safe"; 330 resets = <&tegra_car 183>; 331 reset-names = "sor"; 332 pinctrl-0 = <&state_dpaux1_aux>; 333 pinctrl-1 = <&state_dpaux1_i2c>; 334 pinctrl-2 = <&state_dpaux1_off>; 335 pinctrl-names = "aux", "i2c", "off"; 336 power-domains = <&pd_sor>; 337 status = "disabled"; 338 }; 339 340 dpaux: dpaux@545c0000 { 341 compatible = "nvidia,tegra210-dpaux"; 342 reg = <0x0 0x545c0000 0x0 0x00040000>; 343 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 345 <&tegra_car TEGRA210_CLK_PLL_DP>; 346 clock-names = "dpaux", "parent"; 347 resets = <&tegra_car 181>; 348 reset-names = "dpaux"; 349 power-domains = <&pd_sor>; 350 status = "disabled"; 351 352 state_dpaux_aux: pinmux-aux { 353 groups = "dpaux-io"; 354 function = "aux"; 355 }; 356 357 state_dpaux_i2c: pinmux-i2c { 358 groups = "dpaux-io"; 359 function = "i2c"; 360 }; 361 362 state_dpaux_off: pinmux-off { 363 groups = "dpaux-io"; 364 function = "off"; 365 }; 366 367 i2c-bus { 368 #address-cells = <1>; 369 #size-cells = <0>; 370 }; 371 }; 372 373 isp@54600000 { 374 compatible = "nvidia,tegra210-isp"; 375 reg = <0x0 0x54600000 0x0 0x00040000>; 376 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 378 resets = <&tegra_car 23>; 379 reset-names = "isp"; 380 status = "disabled"; 381 }; 382 383 isp@54680000 { 384 compatible = "nvidia,tegra210-isp"; 385 reg = <0x0 0x54680000 0x0 0x00040000>; 386 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 388 resets = <&tegra_car 3>; 389 reset-names = "isp"; 390 status = "disabled"; 391 }; 392 393 i2c@546c0000 { 394 compatible = "nvidia,tegra210-i2c-vi"; 395 reg = <0x0 0x546c0000 0x0 0x00040000>; 396 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 398 <&tegra_car TEGRA210_CLK_I2CSLOW>; 399 clock-names = "div-clk", "slow"; 400 resets = <&tegra_car 208>; 401 reset-names = "i2c"; 402 power-domains = <&pd_venc>; 403 status = "disabled"; 404 405 #address-cells = <1>; 406 #size-cells = <0>; 407 }; 408 }; 409 410 gic: interrupt-controller@50041000 { 411 compatible = "arm,gic-400"; 412 #interrupt-cells = <3>; 413 interrupt-controller; 414 reg = <0x0 0x50041000 0x0 0x1000>, 415 <0x0 0x50042000 0x0 0x2000>, 416 <0x0 0x50044000 0x0 0x2000>, 417 <0x0 0x50046000 0x0 0x2000>; 418 interrupts = <GIC_PPI 9 419 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 420 interrupt-parent = <&gic>; 421 }; 422 423 gpu@57000000 { 424 compatible = "nvidia,gm20b"; 425 reg = <0x0 0x57000000 0x0 0x01000000>, 426 <0x0 0x58000000 0x0 0x01000000>; 427 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 429 interrupt-names = "stall", "nonstall"; 430 clocks = <&tegra_car TEGRA210_CLK_GPU>, 431 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 432 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 433 clock-names = "gpu", "pwr", "ref"; 434 resets = <&tegra_car 184>; 435 reset-names = "gpu"; 436 437 iommus = <&mc TEGRA_SWGROUP_GPU>; 438 439 status = "disabled"; 440 }; 441 442 lic: interrupt-controller@60004000 { 443 compatible = "nvidia,tegra210-ictlr"; 444 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 445 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 446 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 447 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 448 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 449 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 450 interrupt-controller; 451 #interrupt-cells = <3>; 452 interrupt-parent = <&gic>; 453 }; 454 455 timer@60005000 { 456 compatible = "nvidia,tegra210-timer"; 457 reg = <0x0 0x60005000 0x0 0x400>; 458 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 473 clock-names = "timer"; 474 }; 475 476 tegra_car: clock@60006000 { 477 compatible = "nvidia,tegra210-car"; 478 reg = <0x0 0x60006000 0x0 0x1000>; 479 #clock-cells = <1>; 480 #reset-cells = <1>; 481 }; 482 483 flow-controller@60007000 { 484 compatible = "nvidia,tegra210-flowctrl"; 485 reg = <0x0 0x60007000 0x0 0x1000>; 486 }; 487 488 gpio: gpio@6000d000 { 489 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 490 reg = <0x0 0x6000d000 0x0 0x1000>; 491 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 499 #gpio-cells = <2>; 500 gpio-controller; 501 #interrupt-cells = <2>; 502 interrupt-controller; 503 }; 504 505 apbdma: dma@60020000 { 506 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 507 reg = <0x0 0x60020000 0x0 0x1400>; 508 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 541 clock-names = "dma"; 542 resets = <&tegra_car 34>; 543 reset-names = "dma"; 544 #dma-cells = <1>; 545 }; 546 547 apbmisc@70000800 { 548 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 549 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 550 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 551 }; 552 553 pinmux: pinmux@700008d4 { 554 compatible = "nvidia,tegra210-pinmux"; 555 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 556 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 557 558 sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { 559 sdmmc1 { 560 nvidia,pins = "drive_sdmmc1"; 561 nvidia,pull-down-strength = <0x4>; 562 nvidia,pull-up-strength = <0x3>; 563 }; 564 }; 565 566 sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { 567 sdmmc1 { 568 nvidia,pins = "drive_sdmmc1"; 569 nvidia,pull-down-strength = <0x8>; 570 nvidia,pull-up-strength = <0x8>; 571 }; 572 }; 573 574 sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv { 575 sdmmc2 { 576 nvidia,pins = "drive_sdmmc2"; 577 nvidia,pull-down-strength = <0x10>; 578 nvidia,pull-up-strength = <0x10>; 579 }; 580 }; 581 582 sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { 583 sdmmc3 { 584 nvidia,pins = "drive_sdmmc3"; 585 nvidia,pull-down-strength = <0x4>; 586 nvidia,pull-up-strength = <0x3>; 587 }; 588 }; 589 590 sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { 591 sdmmc3 { 592 nvidia,pins = "drive_sdmmc3"; 593 nvidia,pull-down-strength = <0x8>; 594 nvidia,pull-up-strength = <0x8>; 595 }; 596 }; 597 598 sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv { 599 sdmmc4 { 600 nvidia,pins = "drive_sdmmc4"; 601 nvidia,pull-down-strength = <0x10>; 602 nvidia,pull-up-strength = <0x10>; 603 }; 604 }; 605 }; 606 607 /* 608 * There are two serial driver i.e. 8250 based simple serial 609 * driver and APB DMA based serial driver for higher baudrate 610 * and performance. To enable the 8250 based driver, the compatible 611 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 612 * the APB DMA based serial driver, the compatible is 613 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 614 */ 615 uarta: serial@70006000 { 616 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 617 reg = <0x0 0x70006000 0x0 0x40>; 618 reg-shift = <2>; 619 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 621 resets = <&tegra_car 6>; 622 dmas = <&apbdma 8>, <&apbdma 8>; 623 dma-names = "rx", "tx"; 624 status = "disabled"; 625 }; 626 627 uartb: serial@70006040 { 628 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 629 reg = <0x0 0x70006040 0x0 0x40>; 630 reg-shift = <2>; 631 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 633 resets = <&tegra_car 7>; 634 dmas = <&apbdma 9>, <&apbdma 9>; 635 dma-names = "rx", "tx"; 636 status = "disabled"; 637 }; 638 639 uartc: serial@70006200 { 640 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 641 reg = <0x0 0x70006200 0x0 0x40>; 642 reg-shift = <2>; 643 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 645 resets = <&tegra_car 55>; 646 dmas = <&apbdma 10>, <&apbdma 10>; 647 dma-names = "rx", "tx"; 648 status = "disabled"; 649 }; 650 651 uartd: serial@70006300 { 652 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 653 reg = <0x0 0x70006300 0x0 0x40>; 654 reg-shift = <2>; 655 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 657 resets = <&tegra_car 65>; 658 dmas = <&apbdma 19>, <&apbdma 19>; 659 dma-names = "rx", "tx"; 660 status = "disabled"; 661 }; 662 663 pwm: pwm@7000a000 { 664 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 665 reg = <0x0 0x7000a000 0x0 0x100>; 666 #pwm-cells = <2>; 667 clocks = <&tegra_car TEGRA210_CLK_PWM>; 668 resets = <&tegra_car 17>; 669 reset-names = "pwm"; 670 status = "disabled"; 671 }; 672 673 i2c@7000c000 { 674 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 675 reg = <0x0 0x7000c000 0x0 0x100>; 676 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 677 #address-cells = <1>; 678 #size-cells = <0>; 679 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 680 clock-names = "div-clk"; 681 resets = <&tegra_car 12>; 682 reset-names = "i2c"; 683 dmas = <&apbdma 21>, <&apbdma 21>; 684 dma-names = "rx", "tx"; 685 status = "disabled"; 686 }; 687 688 i2c@7000c400 { 689 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 690 reg = <0x0 0x7000c400 0x0 0x100>; 691 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 695 clock-names = "div-clk"; 696 resets = <&tegra_car 54>; 697 reset-names = "i2c"; 698 dmas = <&apbdma 22>, <&apbdma 22>; 699 dma-names = "rx", "tx"; 700 status = "disabled"; 701 }; 702 703 i2c@7000c500 { 704 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 705 reg = <0x0 0x7000c500 0x0 0x100>; 706 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 710 clock-names = "div-clk"; 711 resets = <&tegra_car 67>; 712 reset-names = "i2c"; 713 dmas = <&apbdma 23>, <&apbdma 23>; 714 dma-names = "rx", "tx"; 715 status = "disabled"; 716 }; 717 718 i2c@7000c700 { 719 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 720 reg = <0x0 0x7000c700 0x0 0x100>; 721 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 725 clock-names = "div-clk"; 726 resets = <&tegra_car 103>; 727 reset-names = "i2c"; 728 dmas = <&apbdma 26>, <&apbdma 26>; 729 dma-names = "rx", "tx"; 730 pinctrl-0 = <&state_dpaux1_i2c>; 731 pinctrl-1 = <&state_dpaux1_off>; 732 pinctrl-names = "default", "idle"; 733 status = "disabled"; 734 }; 735 736 i2c@7000d000 { 737 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 738 reg = <0x0 0x7000d000 0x0 0x100>; 739 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 740 #address-cells = <1>; 741 #size-cells = <0>; 742 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 743 clock-names = "div-clk"; 744 resets = <&tegra_car 47>; 745 reset-names = "i2c"; 746 dmas = <&apbdma 24>, <&apbdma 24>; 747 dma-names = "rx", "tx"; 748 status = "disabled"; 749 }; 750 751 i2c@7000d100 { 752 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 753 reg = <0x0 0x7000d100 0x0 0x100>; 754 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 758 clock-names = "div-clk"; 759 resets = <&tegra_car 166>; 760 reset-names = "i2c"; 761 dmas = <&apbdma 30>, <&apbdma 30>; 762 dma-names = "rx", "tx"; 763 pinctrl-0 = <&state_dpaux_i2c>; 764 pinctrl-1 = <&state_dpaux_off>; 765 pinctrl-names = "default", "idle"; 766 status = "disabled"; 767 }; 768 769 spi@7000d400 { 770 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 771 reg = <0x0 0x7000d400 0x0 0x200>; 772 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 776 clock-names = "spi"; 777 resets = <&tegra_car 41>; 778 reset-names = "spi"; 779 dmas = <&apbdma 15>, <&apbdma 15>; 780 dma-names = "rx", "tx"; 781 status = "disabled"; 782 }; 783 784 spi@7000d600 { 785 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 786 reg = <0x0 0x7000d600 0x0 0x200>; 787 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 791 clock-names = "spi"; 792 resets = <&tegra_car 44>; 793 reset-names = "spi"; 794 dmas = <&apbdma 16>, <&apbdma 16>; 795 dma-names = "rx", "tx"; 796 status = "disabled"; 797 }; 798 799 spi@7000d800 { 800 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 801 reg = <0x0 0x7000d800 0x0 0x200>; 802 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 806 clock-names = "spi"; 807 resets = <&tegra_car 46>; 808 reset-names = "spi"; 809 dmas = <&apbdma 17>, <&apbdma 17>; 810 dma-names = "rx", "tx"; 811 status = "disabled"; 812 }; 813 814 spi@7000da00 { 815 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 816 reg = <0x0 0x7000da00 0x0 0x200>; 817 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 821 clock-names = "spi"; 822 resets = <&tegra_car 68>; 823 reset-names = "spi"; 824 dmas = <&apbdma 18>, <&apbdma 18>; 825 dma-names = "rx", "tx"; 826 status = "disabled"; 827 }; 828 829 rtc@7000e000 { 830 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 831 reg = <0x0 0x7000e000 0x0 0x100>; 832 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 833 interrupt-parent = <&tegra_pmc>; 834 clocks = <&tegra_car TEGRA210_CLK_RTC>; 835 clock-names = "rtc"; 836 }; 837 838 tegra_pmc: pmc@7000e400 { 839 compatible = "nvidia,tegra210-pmc"; 840 reg = <0x0 0x7000e400 0x0 0x400>; 841 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 842 clock-names = "pclk", "clk32k_in"; 843 #clock-cells = <1>; 844 #interrupt-cells = <2>; 845 interrupt-controller; 846 847 pinmux { 848 pex_dpd_disable: pex-dpd-disable { 849 pins = "pex-bias", "pex-clk1", "pex-clk2"; 850 low-power-disable; 851 }; 852 853 pex_dpd_enable: pex-dpd-enable { 854 pins = "pex-bias", "pex-clk1", "pex-clk2"; 855 low-power-enable; 856 }; 857 858 sdmmc1_1v8: sdmmc1-1v8 { 859 pins = "sdmmc1"; 860 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 861 }; 862 863 sdmmc1_3v3: sdmmc1-3v3 { 864 pins = "sdmmc1"; 865 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 866 }; 867 868 sdmmc3_1v8: sdmmc3-1v8 { 869 pins = "sdmmc3"; 870 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 871 }; 872 873 sdmmc3_3v3: sdmmc3-3v3 { 874 pins = "sdmmc3"; 875 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 876 }; 877 878 gpio_1v8: gpio-1v8 { 879 pins = "gpio"; 880 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 881 }; 882 883 gpio_3v3: gpio-3v3 { 884 pins = "gpio"; 885 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 886 }; 887 }; 888 889 powergates { 890 pd_audio: aud { 891 clocks = <&tegra_car TEGRA210_CLK_APE>, 892 <&tegra_car TEGRA210_CLK_APB2APE>; 893 resets = <&tegra_car 198>; 894 #power-domain-cells = <0>; 895 }; 896 897 pd_sor: sor { 898 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 899 <&tegra_car TEGRA210_CLK_SOR1>, 900 <&tegra_car TEGRA210_CLK_CILAB>, 901 <&tegra_car TEGRA210_CLK_CILCD>, 902 <&tegra_car TEGRA210_CLK_CILE>, 903 <&tegra_car TEGRA210_CLK_DSIA>, 904 <&tegra_car TEGRA210_CLK_DSIB>, 905 <&tegra_car TEGRA210_CLK_DPAUX>, 906 <&tegra_car TEGRA210_CLK_DPAUX1>, 907 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 908 resets = <&tegra_car TEGRA210_CLK_SOR0>, 909 <&tegra_car TEGRA210_CLK_SOR1>, 910 <&tegra_car TEGRA210_CLK_DSIA>, 911 <&tegra_car TEGRA210_CLK_DSIB>, 912 <&tegra_car TEGRA210_CLK_DPAUX>, 913 <&tegra_car TEGRA210_CLK_DPAUX1>, 914 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 915 #power-domain-cells = <0>; 916 }; 917 918 pd_venc: venc { 919 clocks = <&tegra_car TEGRA210_CLK_VI>, 920 <&tegra_car TEGRA210_CLK_CSI>; 921 resets = <&mc TEGRA210_MC_RESET_VI>, 922 <&tegra_car 20>, 923 <&tegra_car 52>; 924 #power-domain-cells = <0>; 925 }; 926 927 pd_vic: vic { 928 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 929 resets = <&tegra_car 178>; 930 #power-domain-cells = <0>; 931 }; 932 933 pd_xusbss: xusba { 934 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 935 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 936 #power-domain-cells = <0>; 937 }; 938 939 pd_xusbdev: xusbb { 940 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 941 resets = <&tegra_car 95>; 942 #power-domain-cells = <0>; 943 }; 944 945 pd_xusbhost: xusbc { 946 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 947 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 948 #power-domain-cells = <0>; 949 }; 950 }; 951 }; 952 953 fuse@7000f800 { 954 compatible = "nvidia,tegra210-efuse"; 955 reg = <0x0 0x7000f800 0x0 0x400>; 956 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 957 clock-names = "fuse"; 958 resets = <&tegra_car 39>; 959 reset-names = "fuse"; 960 }; 961 962 cec@70015000 { 963 compatible = "nvidia,tegra210-cec"; 964 reg = <0x0 0x070015000 0x0 0x1000>; 965 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&tegra_car TEGRA210_CLK_CEC>; 967 clock-names = "cec"; 968 status = "disabled"; 969 }; 970 971 mc: memory-controller@70019000 { 972 compatible = "nvidia,tegra210-mc"; 973 reg = <0x0 0x70019000 0x0 0x1000>; 974 clocks = <&tegra_car TEGRA210_CLK_MC>; 975 clock-names = "mc"; 976 977 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 978 979 #iommu-cells = <1>; 980 #reset-cells = <1>; 981 }; 982 983 emc: external-memory-controller@7001b000 { 984 compatible = "nvidia,tegra210-emc"; 985 reg = <0x0 0x7001b000 0x0 0x1000>, 986 <0x0 0x7001e000 0x0 0x1000>, 987 <0x0 0x7001f000 0x0 0x1000>; 988 clocks = <&tegra_car TEGRA210_CLK_EMC>; 989 clock-names = "emc"; 990 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 991 nvidia,memory-controller = <&mc>; 992 #cooling-cells = <2>; 993 }; 994 995 sata@70020000 { 996 compatible = "nvidia,tegra210-ahci"; 997 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 998 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 999 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 1000 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&tegra_car TEGRA210_CLK_SATA>, 1002 <&tegra_car TEGRA210_CLK_SATA_OOB>; 1003 clock-names = "sata", "sata-oob"; 1004 resets = <&tegra_car 124>, 1005 <&tegra_car 129>, 1006 <&tegra_car 123>; 1007 reset-names = "sata", "sata-cold", "sata-oob"; 1008 status = "disabled"; 1009 }; 1010 1011 hda@70030000 { 1012 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 1013 reg = <0x0 0x70030000 0x0 0x10000>; 1014 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&tegra_car TEGRA210_CLK_HDA>, 1016 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 1017 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 1018 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1019 resets = <&tegra_car 125>, /* hda */ 1020 <&tegra_car 128>, /* hda2hdmi */ 1021 <&tegra_car 111>; /* hda2codec_2x */ 1022 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1023 power-domains = <&pd_sor>; 1024 status = "disabled"; 1025 }; 1026 1027 usb@70090000 { 1028 compatible = "nvidia,tegra210-xusb"; 1029 reg = <0x0 0x70090000 0x0 0x8000>, 1030 <0x0 0x70098000 0x0 0x1000>, 1031 <0x0 0x70099000 0x0 0x1000>; 1032 reg-names = "hcd", "fpci", "ipfs"; 1033 1034 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1036 1037 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1038 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1039 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1040 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1041 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1042 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1043 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1044 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1045 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1046 <&tegra_car TEGRA210_CLK_CLK_M>, 1047 <&tegra_car TEGRA210_CLK_PLL_E>; 1048 clock-names = "xusb_host", "xusb_host_src", 1049 "xusb_falcon_src", "xusb_ss", 1050 "xusb_ss_div2", "xusb_ss_src", 1051 "xusb_hs_src", "xusb_fs_src", 1052 "pll_u_480m", "clk_m", "pll_e"; 1053 resets = <&tegra_car 89>, <&tegra_car 156>, 1054 <&tegra_car 143>; 1055 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1056 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1057 power-domain-names = "xusb_host", "xusb_ss"; 1058 1059 nvidia,xusb-padctl = <&padctl>; 1060 1061 status = "disabled"; 1062 }; 1063 1064 padctl: padctl@7009f000 { 1065 compatible = "nvidia,tegra210-xusb-padctl"; 1066 reg = <0x0 0x7009f000 0x0 0x1000>; 1067 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1068 resets = <&tegra_car 142>; 1069 reset-names = "padctl"; 1070 nvidia,pmc = <&tegra_pmc>; 1071 1072 status = "disabled"; 1073 1074 pads { 1075 usb2 { 1076 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1077 clock-names = "trk"; 1078 status = "disabled"; 1079 1080 lanes { 1081 usb2-0 { 1082 status = "disabled"; 1083 #phy-cells = <0>; 1084 }; 1085 1086 usb2-1 { 1087 status = "disabled"; 1088 #phy-cells = <0>; 1089 }; 1090 1091 usb2-2 { 1092 status = "disabled"; 1093 #phy-cells = <0>; 1094 }; 1095 1096 usb2-3 { 1097 status = "disabled"; 1098 #phy-cells = <0>; 1099 }; 1100 }; 1101 }; 1102 1103 hsic { 1104 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1105 clock-names = "trk"; 1106 status = "disabled"; 1107 1108 lanes { 1109 hsic-0 { 1110 status = "disabled"; 1111 #phy-cells = <0>; 1112 }; 1113 1114 hsic-1 { 1115 status = "disabled"; 1116 #phy-cells = <0>; 1117 }; 1118 }; 1119 }; 1120 1121 pcie { 1122 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1123 clock-names = "pll"; 1124 resets = <&tegra_car 205>; 1125 reset-names = "phy"; 1126 status = "disabled"; 1127 1128 lanes { 1129 pcie-0 { 1130 status = "disabled"; 1131 #phy-cells = <0>; 1132 }; 1133 1134 pcie-1 { 1135 status = "disabled"; 1136 #phy-cells = <0>; 1137 }; 1138 1139 pcie-2 { 1140 status = "disabled"; 1141 #phy-cells = <0>; 1142 }; 1143 1144 pcie-3 { 1145 status = "disabled"; 1146 #phy-cells = <0>; 1147 }; 1148 1149 pcie-4 { 1150 status = "disabled"; 1151 #phy-cells = <0>; 1152 }; 1153 1154 pcie-5 { 1155 status = "disabled"; 1156 #phy-cells = <0>; 1157 }; 1158 1159 pcie-6 { 1160 status = "disabled"; 1161 #phy-cells = <0>; 1162 }; 1163 }; 1164 }; 1165 1166 sata { 1167 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1168 clock-names = "pll"; 1169 resets = <&tegra_car 204>; 1170 reset-names = "phy"; 1171 status = "disabled"; 1172 1173 lanes { 1174 sata-0 { 1175 status = "disabled"; 1176 #phy-cells = <0>; 1177 }; 1178 }; 1179 }; 1180 }; 1181 1182 ports { 1183 usb2-0 { 1184 status = "disabled"; 1185 }; 1186 1187 usb2-1 { 1188 status = "disabled"; 1189 }; 1190 1191 usb2-2 { 1192 status = "disabled"; 1193 }; 1194 1195 usb2-3 { 1196 status = "disabled"; 1197 }; 1198 1199 hsic-0 { 1200 status = "disabled"; 1201 }; 1202 1203 usb3-0 { 1204 status = "disabled"; 1205 }; 1206 1207 usb3-1 { 1208 status = "disabled"; 1209 }; 1210 1211 usb3-2 { 1212 status = "disabled"; 1213 }; 1214 1215 usb3-3 { 1216 status = "disabled"; 1217 }; 1218 }; 1219 }; 1220 1221 mmc@700b0000 { 1222 compatible = "nvidia,tegra210-sdhci"; 1223 reg = <0x0 0x700b0000 0x0 0x200>; 1224 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1225 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 1226 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1227 clock-names = "sdhci", "tmclk"; 1228 resets = <&tegra_car 14>; 1229 reset-names = "sdhci"; 1230 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1231 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1232 pinctrl-0 = <&sdmmc1_3v3>; 1233 pinctrl-1 = <&sdmmc1_1v8>; 1234 pinctrl-2 = <&sdmmc1_3v3_drv>; 1235 pinctrl-3 = <&sdmmc1_1v8_drv>; 1236 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1237 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1238 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1239 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1240 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x0>; 1241 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x0>; 1242 nvidia,default-tap = <0x2>; 1243 nvidia,default-trim = <0x4>; 1244 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1245 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1246 <&tegra_car TEGRA210_CLK_PLL_C4>; 1247 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1248 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1249 status = "disabled"; 1250 }; 1251 1252 mmc@700b0200 { 1253 compatible = "nvidia,tegra210-sdhci"; 1254 reg = <0x0 0x700b0200 0x0 0x200>; 1255 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1256 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, 1257 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1258 clock-names = "sdhci", "tmclk"; 1259 resets = <&tegra_car 9>; 1260 reset-names = "sdhci"; 1261 pinctrl-names = "sdmmc-1v8-drv"; 1262 pinctrl-0 = <&sdmmc2_1v8_drv>; 1263 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1264 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1265 nvidia,default-tap = <0x8>; 1266 nvidia,default-trim = <0x0>; 1267 status = "disabled"; 1268 }; 1269 1270 mmc@700b0400 { 1271 compatible = "nvidia,tegra210-sdhci"; 1272 reg = <0x0 0x700b0400 0x0 0x200>; 1273 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, 1275 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1276 clock-names = "sdhci", "tmclk"; 1277 resets = <&tegra_car 69>; 1278 reset-names = "sdhci"; 1279 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1280 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1281 pinctrl-0 = <&sdmmc3_3v3>; 1282 pinctrl-1 = <&sdmmc3_1v8>; 1283 pinctrl-2 = <&sdmmc3_3v3_drv>; 1284 pinctrl-3 = <&sdmmc3_1v8_drv>; 1285 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1286 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1287 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1288 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1289 nvidia,default-tap = <0x3>; 1290 nvidia,default-trim = <0x3>; 1291 status = "disabled"; 1292 }; 1293 1294 mmc@700b0600 { 1295 compatible = "nvidia,tegra210-sdhci"; 1296 reg = <0x0 0x700b0600 0x0 0x200>; 1297 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1298 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1299 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1300 clock-names = "sdhci", "tmclk"; 1301 resets = <&tegra_car 15>; 1302 reset-names = "sdhci"; 1303 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1304 pinctrl-0 = <&sdmmc4_1v8_drv>; 1305 pinctrl-1 = <&sdmmc4_1v8_drv>; 1306 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1307 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1308 nvidia,default-tap = <0x8>; 1309 nvidia,default-trim = <0x0>; 1310 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1311 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1312 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1313 nvidia,dqs-trim = <40>; 1314 mmc-hs400-1_8v; 1315 status = "disabled"; 1316 }; 1317 1318 usb@700d0000 { 1319 compatible = "nvidia,tegra210-xudc"; 1320 reg = <0x0 0x700d0000 0x0 0x8000>, 1321 <0x0 0x700d8000 0x0 0x1000>, 1322 <0x0 0x700d9000 0x0 0x1000>; 1323 reg-names = "base", "fpci", "ipfs"; 1324 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1325 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1326 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1327 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1328 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1329 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1330 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1331 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1332 power-domain-names = "dev", "ss"; 1333 nvidia,xusb-padctl = <&padctl>; 1334 status = "disabled"; 1335 }; 1336 1337 soctherm: thermal-sensor@700e2000 { 1338 compatible = "nvidia,tegra210-soctherm"; 1339 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1340 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1341 reg-names = "soctherm-reg", "car-reg"; 1342 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1344 interrupt-names = "thermal", "edp"; 1345 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1346 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1347 clock-names = "tsensor", "soctherm"; 1348 resets = <&tegra_car 78>; 1349 reset-names = "soctherm"; 1350 #thermal-sensor-cells = <1>; 1351 1352 throttle-cfgs { 1353 throttle_heavy: heavy { 1354 nvidia,priority = <100>; 1355 nvidia,cpu-throt-percent = <85>; 1356 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 1357 1358 #cooling-cells = <2>; 1359 }; 1360 }; 1361 }; 1362 1363 mipi: mipi@700e3000 { 1364 compatible = "nvidia,tegra210-mipi"; 1365 reg = <0x0 0x700e3000 0x0 0x100>; 1366 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1367 clock-names = "mipi-cal"; 1368 power-domains = <&pd_sor>; 1369 #nvidia,mipi-calibrate-cells = <1>; 1370 }; 1371 1372 dfll: clock@70110000 { 1373 compatible = "nvidia,tegra210-dfll"; 1374 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1375 <0 0x70110000 0 0x100>, /* I2C output control */ 1376 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1377 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1378 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1379 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1380 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1381 <&tegra_car TEGRA210_CLK_I2C5>; 1382 clock-names = "soc", "ref", "i2c"; 1383 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, 1384 <&tegra_car 155>; 1385 reset-names = "dvco", "dfll"; 1386 #clock-cells = <0>; 1387 clock-output-names = "dfllCPU_out"; 1388 status = "disabled"; 1389 }; 1390 1391 aconnect@702c0000 { 1392 compatible = "nvidia,tegra210-aconnect"; 1393 clocks = <&tegra_car TEGRA210_CLK_APE>, 1394 <&tegra_car TEGRA210_CLK_APB2APE>; 1395 clock-names = "ape", "apb2ape"; 1396 power-domains = <&pd_audio>; 1397 #address-cells = <1>; 1398 #size-cells = <1>; 1399 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1400 status = "disabled"; 1401 1402 tegra_ahub: ahub@702d0800 { 1403 compatible = "nvidia,tegra210-ahub"; 1404 reg = <0x702d0800 0x800>; 1405 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1406 clock-names = "ahub"; 1407 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1408 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>; 1409 assigned-clock-rates = <81600000>; 1410 #address-cells = <1>; 1411 #size-cells = <1>; 1412 ranges = <0x702d0000 0x702d0000 0x0000e400>; 1413 status = "disabled"; 1414 1415 tegra_admaif: admaif@702d0000 { 1416 compatible = "nvidia,tegra210-admaif"; 1417 reg = <0x702d0000 0x800>; 1418 dmas = <&adma 1>, <&adma 1>, 1419 <&adma 2>, <&adma 2>, 1420 <&adma 3>, <&adma 3>, 1421 <&adma 4>, <&adma 4>, 1422 <&adma 5>, <&adma 5>, 1423 <&adma 6>, <&adma 6>, 1424 <&adma 7>, <&adma 7>, 1425 <&adma 8>, <&adma 8>, 1426 <&adma 9>, <&adma 9>, 1427 <&adma 10>, <&adma 10>; 1428 dma-names = "rx1", "tx1", 1429 "rx2", "tx2", 1430 "rx3", "tx3", 1431 "rx4", "tx4", 1432 "rx5", "tx5", 1433 "rx6", "tx6", 1434 "rx7", "tx7", 1435 "rx8", "tx8", 1436 "rx9", "tx9", 1437 "rx10", "tx10"; 1438 status = "disabled"; 1439 1440 ports { 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 1444 admaif1_port: port@0 { 1445 reg = <0>; 1446 1447 admaif1_ep: endpoint { 1448 remote-endpoint = <&xbar_admaif1_ep>; 1449 }; 1450 }; 1451 1452 admaif2_port: port@1 { 1453 reg = <1>; 1454 1455 admaif2_ep: endpoint { 1456 remote-endpoint = <&xbar_admaif2_ep>; 1457 }; 1458 }; 1459 1460 admaif3_port: port@2 { 1461 reg = <2>; 1462 1463 admaif3_ep: endpoint { 1464 remote-endpoint = <&xbar_admaif3_ep>; 1465 }; 1466 }; 1467 1468 admaif4_port: port@3 { 1469 reg = <3>; 1470 1471 admaif4_ep: endpoint { 1472 remote-endpoint = <&xbar_admaif4_ep>; 1473 }; 1474 }; 1475 1476 admaif5_port: port@4 { 1477 reg = <4>; 1478 1479 admaif5_ep: endpoint { 1480 remote-endpoint = <&xbar_admaif5_ep>; 1481 }; 1482 }; 1483 1484 admaif6_port: port@5 { 1485 reg = <5>; 1486 1487 admaif6_ep: endpoint { 1488 remote-endpoint = <&xbar_admaif6_ep>; 1489 }; 1490 }; 1491 1492 admaif7_port: port@6 { 1493 reg = <6>; 1494 1495 admaif7_ep: endpoint { 1496 remote-endpoint = <&xbar_admaif7_ep>; 1497 }; 1498 }; 1499 1500 admaif8_port: port@7 { 1501 reg = <7>; 1502 1503 admaif8_ep: endpoint { 1504 remote-endpoint = <&xbar_admaif8_ep>; 1505 }; 1506 }; 1507 1508 admaif9_port: port@8 { 1509 reg = <8>; 1510 1511 admaif9_ep: endpoint { 1512 remote-endpoint = <&xbar_admaif9_ep>; 1513 }; 1514 }; 1515 1516 admaif10_port: port@9 { 1517 reg = <9>; 1518 1519 admaif10_ep: endpoint { 1520 remote-endpoint = <&xbar_admaif10_ep>; 1521 }; 1522 }; 1523 }; 1524 }; 1525 1526 tegra_i2s1: i2s@702d1000 { 1527 compatible = "nvidia,tegra210-i2s"; 1528 reg = <0x702d1000 0x100>; 1529 clocks = <&tegra_car TEGRA210_CLK_I2S0>, 1530 <&tegra_car TEGRA210_CLK_I2S0_SYNC>; 1531 clock-names = "i2s", "sync_input"; 1532 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 1533 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1534 assigned-clock-rates = <1536000>; 1535 sound-name-prefix = "I2S1"; 1536 status = "disabled"; 1537 }; 1538 1539 tegra_i2s2: i2s@702d1100 { 1540 compatible = "nvidia,tegra210-i2s"; 1541 reg = <0x702d1100 0x100>; 1542 clocks = <&tegra_car TEGRA210_CLK_I2S1>, 1543 <&tegra_car TEGRA210_CLK_I2S1_SYNC>; 1544 clock-names = "i2s", "sync_input"; 1545 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; 1546 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1547 assigned-clock-rates = <1536000>; 1548 sound-name-prefix = "I2S2"; 1549 status = "disabled"; 1550 }; 1551 1552 tegra_i2s3: i2s@702d1200 { 1553 compatible = "nvidia,tegra210-i2s"; 1554 reg = <0x702d1200 0x100>; 1555 clocks = <&tegra_car TEGRA210_CLK_I2S2>, 1556 <&tegra_car TEGRA210_CLK_I2S2_SYNC>; 1557 clock-names = "i2s", "sync_input"; 1558 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; 1559 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1560 assigned-clock-rates = <1536000>; 1561 sound-name-prefix = "I2S3"; 1562 status = "disabled"; 1563 }; 1564 1565 tegra_i2s4: i2s@702d1300 { 1566 compatible = "nvidia,tegra210-i2s"; 1567 reg = <0x702d1300 0x100>; 1568 clocks = <&tegra_car TEGRA210_CLK_I2S3>, 1569 <&tegra_car TEGRA210_CLK_I2S3_SYNC>; 1570 clock-names = "i2s", "sync_input"; 1571 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; 1572 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1573 assigned-clock-rates = <1536000>; 1574 sound-name-prefix = "I2S4"; 1575 status = "disabled"; 1576 }; 1577 1578 tegra_i2s5: i2s@702d1400 { 1579 compatible = "nvidia,tegra210-i2s"; 1580 reg = <0x702d1400 0x100>; 1581 clocks = <&tegra_car TEGRA210_CLK_I2S4>, 1582 <&tegra_car TEGRA210_CLK_I2S4_SYNC>; 1583 clock-names = "i2s", "sync_input"; 1584 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; 1585 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1586 assigned-clock-rates = <1536000>; 1587 sound-name-prefix = "I2S5"; 1588 status = "disabled"; 1589 }; 1590 1591 tegra_sfc1: sfc@702d2000 { 1592 compatible = "nvidia,tegra210-sfc"; 1593 reg = <0x702d2000 0x200>; 1594 sound-name-prefix = "SFC1"; 1595 status = "disabled"; 1596 }; 1597 1598 tegra_sfc2: sfc@702d2200 { 1599 compatible = "nvidia,tegra210-sfc"; 1600 reg = <0x702d2200 0x200>; 1601 sound-name-prefix = "SFC2"; 1602 status = "disabled"; 1603 }; 1604 1605 tegra_sfc3: sfc@702d2400 { 1606 compatible = "nvidia,tegra210-sfc"; 1607 reg = <0x702d2400 0x200>; 1608 sound-name-prefix = "SFC3"; 1609 status = "disabled"; 1610 }; 1611 1612 tegra_sfc4: sfc@702d2600 { 1613 compatible = "nvidia,tegra210-sfc"; 1614 reg = <0x702d2600 0x200>; 1615 sound-name-prefix = "SFC4"; 1616 status = "disabled"; 1617 }; 1618 1619 tegra_amx1: amx@702d3000 { 1620 compatible = "nvidia,tegra210-amx"; 1621 reg = <0x702d3000 0x100>; 1622 sound-name-prefix = "AMX1"; 1623 status = "disabled"; 1624 }; 1625 1626 tegra_amx2: amx@702d3100 { 1627 compatible = "nvidia,tegra210-amx"; 1628 reg = <0x702d3100 0x100>; 1629 sound-name-prefix = "AMX2"; 1630 status = "disabled"; 1631 }; 1632 1633 tegra_adx1: adx@702d3800 { 1634 compatible = "nvidia,tegra210-adx"; 1635 reg = <0x702d3800 0x100>; 1636 sound-name-prefix = "ADX1"; 1637 status = "disabled"; 1638 }; 1639 1640 tegra_adx2: adx@702d3900 { 1641 compatible = "nvidia,tegra210-adx"; 1642 reg = <0x702d3900 0x100>; 1643 sound-name-prefix = "ADX2"; 1644 status = "disabled"; 1645 }; 1646 1647 tegra_dmic1: dmic@702d4000 { 1648 compatible = "nvidia,tegra210-dmic"; 1649 reg = <0x702d4000 0x100>; 1650 clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1651 clock-names = "dmic"; 1652 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1653 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1654 assigned-clock-rates = <3072000>; 1655 sound-name-prefix = "DMIC1"; 1656 status = "disabled"; 1657 }; 1658 1659 tegra_dmic2: dmic@702d4100 { 1660 compatible = "nvidia,tegra210-dmic"; 1661 reg = <0x702d4100 0x100>; 1662 clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1663 clock-names = "dmic"; 1664 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1665 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1666 assigned-clock-rates = <3072000>; 1667 sound-name-prefix = "DMIC2"; 1668 status = "disabled"; 1669 }; 1670 1671 tegra_dmic3: dmic@702d4200 { 1672 compatible = "nvidia,tegra210-dmic"; 1673 reg = <0x702d4200 0x100>; 1674 clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1675 clock-names = "dmic"; 1676 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1677 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1678 assigned-clock-rates = <3072000>; 1679 sound-name-prefix = "DMIC3"; 1680 status = "disabled"; 1681 }; 1682 1683 tegra_ope1: processing-engine@702d8000 { 1684 compatible = "nvidia,tegra210-ope"; 1685 reg = <0x702d8000 0x100>; 1686 #address-cells = <1>; 1687 #size-cells = <1>; 1688 ranges; 1689 sound-name-prefix = "OPE1"; 1690 status = "disabled"; 1691 1692 equalizer@702d8100 { 1693 compatible = "nvidia,tegra210-peq"; 1694 reg = <0x702d8100 0x100>; 1695 }; 1696 1697 dynamic-range-compressor@702d8200 { 1698 compatible = "nvidia,tegra210-mbdrc"; 1699 reg = <0x702d8200 0x200>; 1700 }; 1701 }; 1702 1703 tegra_ope2: processing-engine@702d8400 { 1704 compatible = "nvidia,tegra210-ope"; 1705 reg = <0x702d8400 0x100>; 1706 #address-cells = <1>; 1707 #size-cells = <1>; 1708 ranges; 1709 sound-name-prefix = "OPE2"; 1710 status = "disabled"; 1711 1712 equalizer@702d8500 { 1713 compatible = "nvidia,tegra210-peq"; 1714 reg = <0x702d8500 0x100>; 1715 }; 1716 1717 dynamic-range-compressor@702d8600 { 1718 compatible = "nvidia,tegra210-mbdrc"; 1719 reg = <0x702d8600 0x200>; 1720 }; 1721 }; 1722 1723 tegra_mvc1: mvc@702da000 { 1724 compatible = "nvidia,tegra210-mvc"; 1725 reg = <0x702da000 0x200>; 1726 sound-name-prefix = "MVC1"; 1727 status = "disabled"; 1728 }; 1729 1730 tegra_mvc2: mvc@702da200 { 1731 compatible = "nvidia,tegra210-mvc"; 1732 reg = <0x702da200 0x200>; 1733 sound-name-prefix = "MVC2"; 1734 status = "disabled"; 1735 }; 1736 1737 tegra_amixer: amixer@702dbb00 { 1738 compatible = "nvidia,tegra210-amixer"; 1739 reg = <0x702dbb00 0x800>; 1740 sound-name-prefix = "MIXER1"; 1741 status = "disabled"; 1742 }; 1743 1744 ports { 1745 #address-cells = <1>; 1746 #size-cells = <0>; 1747 1748 port@0 { 1749 reg = <0x0>; 1750 1751 xbar_admaif1_ep: endpoint { 1752 remote-endpoint = <&admaif1_ep>; 1753 }; 1754 }; 1755 1756 port@1 { 1757 reg = <0x1>; 1758 1759 xbar_admaif2_ep: endpoint { 1760 remote-endpoint = <&admaif2_ep>; 1761 }; 1762 }; 1763 1764 port@2 { 1765 reg = <0x2>; 1766 1767 xbar_admaif3_ep: endpoint { 1768 remote-endpoint = <&admaif3_ep>; 1769 }; 1770 }; 1771 1772 port@3 { 1773 reg = <0x3>; 1774 1775 xbar_admaif4_ep: endpoint { 1776 remote-endpoint = <&admaif4_ep>; 1777 }; 1778 }; 1779 1780 port@4 { 1781 reg = <0x4>; 1782 xbar_admaif5_ep: endpoint { 1783 remote-endpoint = <&admaif5_ep>; 1784 }; 1785 }; 1786 port@5 { 1787 reg = <0x5>; 1788 1789 xbar_admaif6_ep: endpoint { 1790 remote-endpoint = <&admaif6_ep>; 1791 }; 1792 }; 1793 1794 port@6 { 1795 reg = <0x6>; 1796 1797 xbar_admaif7_ep: endpoint { 1798 remote-endpoint = <&admaif7_ep>; 1799 }; 1800 }; 1801 1802 port@7 { 1803 reg = <0x7>; 1804 1805 xbar_admaif8_ep: endpoint { 1806 remote-endpoint = <&admaif8_ep>; 1807 }; 1808 }; 1809 1810 port@8 { 1811 reg = <0x8>; 1812 1813 xbar_admaif9_ep: endpoint { 1814 remote-endpoint = <&admaif9_ep>; 1815 }; 1816 }; 1817 1818 port@9 { 1819 reg = <0x9>; 1820 1821 xbar_admaif10_ep: endpoint { 1822 remote-endpoint = <&admaif10_ep>; 1823 }; 1824 }; 1825 }; 1826 }; 1827 1828 adma: dma-controller@702e2000 { 1829 compatible = "nvidia,tegra210-adma"; 1830 reg = <0x702e2000 0x2000>; 1831 interrupt-parent = <&agic>; 1832 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1854 #dma-cells = <1>; 1855 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1856 clock-names = "d_audio"; 1857 status = "disabled"; 1858 }; 1859 1860 agic: interrupt-controller@702f9000 { 1861 compatible = "nvidia,tegra210-agic"; 1862 #interrupt-cells = <3>; 1863 interrupt-controller; 1864 reg = <0x702f9000 0x1000>, 1865 <0x702fa000 0x2000>; 1866 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1867 clocks = <&tegra_car TEGRA210_CLK_APE>; 1868 clock-names = "clk"; 1869 status = "disabled"; 1870 }; 1871 }; 1872 1873 spi@70410000 { 1874 compatible = "nvidia,tegra210-qspi"; 1875 reg = <0x0 0x70410000 0x0 0x1000>; 1876 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 clocks = <&tegra_car TEGRA210_CLK_QSPI>, 1880 <&tegra_car TEGRA210_CLK_QSPI_PM>; 1881 clock-names = "qspi", "qspi_out"; 1882 resets = <&tegra_car 211>; 1883 dmas = <&apbdma 5>, <&apbdma 5>; 1884 dma-names = "rx", "tx"; 1885 status = "disabled"; 1886 }; 1887 1888 usb@7d000000 { 1889 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1890 reg = <0x0 0x7d000000 0x0 0x4000>; 1891 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1892 phy_type = "utmi"; 1893 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1894 clock-names = "usb"; 1895 resets = <&tegra_car 22>; 1896 reset-names = "usb"; 1897 nvidia,phy = <&phy1>; 1898 status = "disabled"; 1899 }; 1900 1901 phy1: usb-phy@7d000000 { 1902 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1903 reg = <0x0 0x7d000000 0x0 0x4000>, 1904 <0x0 0x7d000000 0x0 0x4000>; 1905 phy_type = "utmi"; 1906 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1907 <&tegra_car TEGRA210_CLK_PLL_U>, 1908 <&tegra_car TEGRA210_CLK_USBD>; 1909 clock-names = "reg", "pll_u", "utmi-pads"; 1910 resets = <&tegra_car 22>, <&tegra_car 22>; 1911 reset-names = "usb", "utmi-pads"; 1912 nvidia,hssync-start-delay = <0>; 1913 nvidia,idle-wait-delay = <17>; 1914 nvidia,elastic-limit = <16>; 1915 nvidia,term-range-adj = <6>; 1916 nvidia,xcvr-setup = <9>; 1917 nvidia,xcvr-lsfslew = <0>; 1918 nvidia,xcvr-lsrslew = <3>; 1919 nvidia,hssquelch-level = <2>; 1920 nvidia,hsdiscon-level = <5>; 1921 nvidia,xcvr-hsslew = <12>; 1922 nvidia,has-utmi-pad-registers; 1923 status = "disabled"; 1924 }; 1925 1926 usb@7d004000 { 1927 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1928 reg = <0x0 0x7d004000 0x0 0x4000>; 1929 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1930 phy_type = "utmi"; 1931 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1932 clock-names = "usb"; 1933 resets = <&tegra_car 58>; 1934 reset-names = "usb"; 1935 nvidia,phy = <&phy2>; 1936 status = "disabled"; 1937 }; 1938 1939 phy2: usb-phy@7d004000 { 1940 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1941 reg = <0x0 0x7d004000 0x0 0x4000>, 1942 <0x0 0x7d000000 0x0 0x4000>; 1943 phy_type = "utmi"; 1944 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1945 <&tegra_car TEGRA210_CLK_PLL_U>, 1946 <&tegra_car TEGRA210_CLK_USBD>; 1947 clock-names = "reg", "pll_u", "utmi-pads"; 1948 resets = <&tegra_car 58>, <&tegra_car 22>; 1949 reset-names = "usb", "utmi-pads"; 1950 nvidia,hssync-start-delay = <0>; 1951 nvidia,idle-wait-delay = <17>; 1952 nvidia,elastic-limit = <16>; 1953 nvidia,term-range-adj = <6>; 1954 nvidia,xcvr-setup = <9>; 1955 nvidia,xcvr-lsfslew = <0>; 1956 nvidia,xcvr-lsrslew = <3>; 1957 nvidia,hssquelch-level = <2>; 1958 nvidia,hsdiscon-level = <5>; 1959 nvidia,xcvr-hsslew = <12>; 1960 status = "disabled"; 1961 }; 1962 1963 cpus { 1964 #address-cells = <1>; 1965 #size-cells = <0>; 1966 1967 cpu@0 { 1968 device_type = "cpu"; 1969 compatible = "arm,cortex-a57"; 1970 reg = <0>; 1971 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 1972 <&tegra_car TEGRA210_CLK_PLL_X>, 1973 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 1974 <&dfll>; 1975 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 1976 clock-latency = <300000>; 1977 cpu-idle-states = <&CPU_SLEEP>; 1978 next-level-cache = <&L2>; 1979 }; 1980 1981 cpu@1 { 1982 device_type = "cpu"; 1983 compatible = "arm,cortex-a57"; 1984 reg = <1>; 1985 cpu-idle-states = <&CPU_SLEEP>; 1986 next-level-cache = <&L2>; 1987 }; 1988 1989 cpu@2 { 1990 device_type = "cpu"; 1991 compatible = "arm,cortex-a57"; 1992 reg = <2>; 1993 cpu-idle-states = <&CPU_SLEEP>; 1994 next-level-cache = <&L2>; 1995 }; 1996 1997 cpu@3 { 1998 device_type = "cpu"; 1999 compatible = "arm,cortex-a57"; 2000 reg = <3>; 2001 cpu-idle-states = <&CPU_SLEEP>; 2002 next-level-cache = <&L2>; 2003 }; 2004 2005 idle-states { 2006 entry-method = "psci"; 2007 2008 CPU_SLEEP: cpu-sleep { 2009 compatible = "arm,idle-state"; 2010 arm,psci-suspend-param = <0x40000007>; 2011 entry-latency-us = <100>; 2012 exit-latency-us = <30>; 2013 min-residency-us = <1000>; 2014 wakeup-latency-us = <130>; 2015 idle-state-name = "cpu-sleep"; 2016 status = "disabled"; 2017 }; 2018 }; 2019 2020 L2: l2-cache { 2021 compatible = "cache"; 2022 cache-level = <2>; 2023 cache-unified; 2024 }; 2025 }; 2026 2027 pmu { 2028 compatible = "arm,cortex-a57-pmu"; 2029 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2033 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 2034 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 2035 }; 2036 2037 sound { 2038 status = "disabled"; 2039 2040 clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2041 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2042 clock-names = "pll_a", "plla_out0"; 2043 2044 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2045 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, 2046 <&tegra_car TEGRA210_CLK_EXTERN1>; 2047 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2048 assigned-clock-rates = <368640000>, <49152000>, <12288000>; 2049 }; 2050 2051 thermal-zones { 2052 cpu-thermal { 2053 polling-delay-passive = <1000>; 2054 polling-delay = <0>; 2055 2056 thermal-sensors = 2057 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 2058 2059 trips { 2060 cpu-shutdown-trip { 2061 temperature = <102500>; 2062 hysteresis = <0>; 2063 type = "critical"; 2064 }; 2065 2066 cpu_throttle_trip: throttle-trip { 2067 temperature = <98500>; 2068 hysteresis = <1000>; 2069 type = "hot"; 2070 }; 2071 }; 2072 2073 cooling-maps { 2074 map0 { 2075 trip = <&cpu_throttle_trip>; 2076 cooling-device = <&throttle_heavy 1 1>; 2077 }; 2078 }; 2079 }; 2080 2081 mem-thermal { 2082 polling-delay-passive = <0>; 2083 polling-delay = <0>; 2084 2085 thermal-sensors = 2086 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 2087 2088 trips { 2089 dram_nominal: mem-nominal-trip { 2090 temperature = <50000>; 2091 hysteresis = <1000>; 2092 type = "passive"; 2093 }; 2094 2095 dram_throttle: mem-throttle-trip { 2096 temperature = <70000>; 2097 hysteresis = <1000>; 2098 type = "active"; 2099 }; 2100 2101 mem-hot-trip { 2102 temperature = <100000>; 2103 hysteresis = <1000>; 2104 type = "hot"; 2105 }; 2106 2107 mem-shutdown-trip { 2108 temperature = <103000>; 2109 hysteresis = <0>; 2110 type = "critical"; 2111 }; 2112 }; 2113 2114 cooling-maps { 2115 dram-passive { 2116 cooling-device = <&emc 0 0>; 2117 trip = <&dram_nominal>; 2118 }; 2119 2120 dram-active { 2121 cooling-device = <&emc 1 1>; 2122 trip = <&dram_throttle>; 2123 }; 2124 }; 2125 }; 2126 2127 gpu-thermal { 2128 polling-delay-passive = <1000>; 2129 polling-delay = <0>; 2130 2131 thermal-sensors = 2132 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 2133 2134 trips { 2135 gpu-shutdown-trip { 2136 temperature = <103000>; 2137 hysteresis = <0>; 2138 type = "critical"; 2139 }; 2140 2141 gpu_throttle_trip: throttle-trip { 2142 temperature = <100000>; 2143 hysteresis = <1000>; 2144 type = "hot"; 2145 }; 2146 }; 2147 2148 cooling-maps { 2149 map0 { 2150 trip = <&gpu_throttle_trip>; 2151 cooling-device = <&throttle_heavy 1 1>; 2152 }; 2153 }; 2154 }; 2155 2156 pllx-thermal { 2157 polling-delay-passive = <0>; 2158 polling-delay = <0>; 2159 2160 thermal-sensors = 2161 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 2162 2163 trips { 2164 pllx-shutdown-trip { 2165 temperature = <103000>; 2166 hysteresis = <0>; 2167 type = "critical"; 2168 }; 2169 2170 pllx-throttle-trip { 2171 temperature = <100000>; 2172 hysteresis = <1000>; 2173 type = "hot"; 2174 }; 2175 }; 2176 2177 cooling-maps { 2178 /* 2179 * There are currently no cooling maps, 2180 * because there are no cooling devices. 2181 */ 2182 }; 2183 }; 2184 }; 2185 2186 timer { 2187 compatible = "arm,armv8-timer"; 2188 interrupts = <GIC_PPI 13 2189 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2190 <GIC_PPI 14 2191 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2192 <GIC_PPI 11 2193 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2194 <GIC_PPI 10 2195 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2196 interrupt-parent = <&gic>; 2197 arm,no-tick-in-suspend; 2198 }; 2199}; 2200