1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/reset/tegra124-car.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11#include "tegra124-peripherals-opp.dtsi" 12 13/ { 14 compatible = "nvidia,tegra124"; 15 interrupt-parent = <&lic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 memory@80000000 { 20 device_type = "memory"; 21 reg = <0x0 0x80000000 0x0 0x0>; 22 }; 23 24 pcie@1003000 { 25 compatible = "nvidia,tegra124-pcie"; 26 device_type = "pci"; 27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 30 reg-names = "pads", "afi", "cs"; 31 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 32 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 33 interrupt-names = "intr", "msi"; 34 35 #interrupt-cells = <1>; 36 interrupt-map-mask = <0 0 0 0>; 37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 38 39 bus-range = <0x00 0xff>; 40 #address-cells = <3>; 41 #size-cells = <2>; 42 43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 46 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 47 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 48 49 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 50 <&tegra_car TEGRA124_CLK_AFI>, 51 <&tegra_car TEGRA124_CLK_PLL_E>, 52 <&tegra_car TEGRA124_CLK_CML0>; 53 clock-names = "pex", "afi", "pll_e", "cml"; 54 resets = <&tegra_car 70>, 55 <&tegra_car 72>, 56 <&tegra_car 74>; 57 reset-names = "pex", "afi", "pcie_x"; 58 status = "disabled"; 59 60 pci@1,0 { 61 device_type = "pci"; 62 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 63 reg = <0x000800 0 0 0 0>; 64 bus-range = <0x00 0xff>; 65 status = "disabled"; 66 67 #address-cells = <3>; 68 #size-cells = <2>; 69 ranges; 70 71 nvidia,num-lanes = <2>; 72 }; 73 74 pci@2,0 { 75 device_type = "pci"; 76 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 77 reg = <0x001000 0 0 0 0>; 78 bus-range = <0x00 0xff>; 79 status = "disabled"; 80 81 #address-cells = <3>; 82 #size-cells = <2>; 83 ranges; 84 85 nvidia,num-lanes = <1>; 86 }; 87 }; 88 89 host1x@50000000 { 90 compatible = "nvidia,tegra124-host1x"; 91 reg = <0x0 0x50000000 0x0 0x00034000>; 92 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 93 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 94 interrupt-names = "syncpt", "host1x"; 95 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 96 clock-names = "host1x"; 97 resets = <&tegra_car 28>, <&mc TEGRA124_MC_RESET_HC>; 98 reset-names = "host1x", "mc"; 99 iommus = <&mc TEGRA_SWGROUP_HC>; 100 101 #address-cells = <2>; 102 #size-cells = <2>; 103 104 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 105 106 dc@54200000 { 107 compatible = "nvidia,tegra124-dc"; 108 reg = <0x0 0x54200000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA124_CLK_DISP1>; 111 clock-names = "dc"; 112 resets = <&tegra_car 27>; 113 reset-names = "dc"; 114 115 iommus = <&mc TEGRA_SWGROUP_DC>; 116 117 nvidia,head = <0>; 118 119 interconnects = <&mc TEGRA124_MC_DISPLAY0A &emc>, 120 <&mc TEGRA124_MC_DISPLAY0B &emc>, 121 <&mc TEGRA124_MC_DISPLAY0C &emc>, 122 <&mc TEGRA124_MC_DISPLAYHC &emc>, 123 <&mc TEGRA124_MC_DISPLAYD &emc>, 124 <&mc TEGRA124_MC_DISPLAYT &emc>; 125 interconnect-names = "wina", 126 "winb", 127 "winc", 128 "cursor", 129 "wind", 130 "wint"; 131 }; 132 133 dc@54240000 { 134 compatible = "nvidia,tegra124-dc"; 135 reg = <0x0 0x54240000 0x0 0x00040000>; 136 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&tegra_car TEGRA124_CLK_DISP2>; 138 clock-names = "dc"; 139 resets = <&tegra_car 26>; 140 reset-names = "dc"; 141 142 iommus = <&mc TEGRA_SWGROUP_DCB>; 143 144 nvidia,head = <1>; 145 146 interconnects = <&mc TEGRA124_MC_DISPLAY0AB &emc>, 147 <&mc TEGRA124_MC_DISPLAY0BB &emc>, 148 <&mc TEGRA124_MC_DISPLAY0CB &emc>, 149 <&mc TEGRA124_MC_DISPLAYHCB &emc>; 150 interconnect-names = "wina", 151 "winb", 152 "winc", 153 "cursor"; 154 }; 155 156 hdmi: hdmi@54280000 { 157 compatible = "nvidia,tegra124-hdmi"; 158 reg = <0x0 0x54280000 0x0 0x00040000>; 159 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 161 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 162 clock-names = "hdmi", "parent"; 163 resets = <&tegra_car 51>; 164 reset-names = "hdmi"; 165 status = "disabled"; 166 }; 167 168 dsia: dsi@54300000 { 169 compatible = "nvidia,tegra124-dsi"; 170 reg = <0x0 0x54300000 0x0 0x00040000>; 171 clocks = <&tegra_car TEGRA124_CLK_DSIA>, 172 <&tegra_car TEGRA124_CLK_DSIALP>, 173 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; 174 clock-names = "dsi", "lp", "parent"; 175 resets = <&tegra_car 48>; 176 reset-names = "dsi"; 177 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ 178 status = "disabled"; 179 180 #address-cells = <1>; 181 #size-cells = <0>; 182 }; 183 184 vic@54340000 { 185 compatible = "nvidia,tegra124-vic"; 186 reg = <0x0 0x54340000 0x0 0x00040000>; 187 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&tegra_car TEGRA124_CLK_VIC03>; 189 clock-names = "vic"; 190 resets = <&tegra_car 178>; 191 reset-names = "vic"; 192 193 iommus = <&mc TEGRA_SWGROUP_VIC>; 194 }; 195 196 dsib: dsi@54400000 { 197 compatible = "nvidia,tegra124-dsi"; 198 reg = <0x0 0x54400000 0x0 0x00040000>; 199 clocks = <&tegra_car TEGRA124_CLK_DSIB>, 200 <&tegra_car TEGRA124_CLK_DSIBLP>, 201 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; 202 clock-names = "dsi", "lp", "parent"; 203 resets = <&tegra_car 82>; 204 reset-names = "dsi"; 205 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ 206 status = "disabled"; 207 208 #address-cells = <1>; 209 #size-cells = <0>; 210 }; 211 212 sor@54540000 { 213 compatible = "nvidia,tegra124-sor"; 214 reg = <0x0 0x54540000 0x0 0x00040000>; 215 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 217 <&tegra_car TEGRA124_CLK_SOR0_OUT>, 218 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 219 <&tegra_car TEGRA124_CLK_PLL_DP>, 220 <&tegra_car TEGRA124_CLK_CLK_M>; 221 clock-names = "sor", "out", "parent", "dp", "safe"; 222 resets = <&tegra_car 182>; 223 reset-names = "sor"; 224 status = "disabled"; 225 }; 226 227 dpaux: dpaux@545c0000 { 228 compatible = "nvidia,tegra124-dpaux"; 229 reg = <0x0 0x545c0000 0x0 0x00040000>; 230 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 232 <&tegra_car TEGRA124_CLK_PLL_DP>; 233 clock-names = "dpaux", "parent"; 234 resets = <&tegra_car 181>; 235 reset-names = "dpaux"; 236 status = "disabled"; 237 238 i2c-bus { 239 #address-cells = <1>; 240 #size-cells = <0>; 241 }; 242 }; 243 }; 244 245 gic: interrupt-controller@50041000 { 246 compatible = "arm,cortex-a15-gic"; 247 #interrupt-cells = <3>; 248 interrupt-controller; 249 reg = <0x0 0x50041000 0x0 0x1000>, 250 <0x0 0x50042000 0x0 0x1000>, 251 <0x0 0x50044000 0x0 0x2000>, 252 <0x0 0x50046000 0x0 0x2000>; 253 interrupts = <GIC_PPI 9 254 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 255 interrupt-parent = <&gic>; 256 }; 257 258 gpu@57000000 { 259 compatible = "nvidia,gk20a"; 260 reg = <0x0 0x57000000 0x0 0x01000000>, 261 <0x0 0x58000000 0x0 0x01000000>; 262 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 264 interrupt-names = "stall", "nonstall"; 265 clocks = <&tegra_car TEGRA124_CLK_GPU>, 266 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 267 clock-names = "gpu", "pwr"; 268 resets = <&tegra_car 184>; 269 reset-names = "gpu"; 270 271 iommus = <&mc TEGRA_SWGROUP_GPU>; 272 273 status = "disabled"; 274 }; 275 276 lic: interrupt-controller@60004000 { 277 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 278 reg = <0x0 0x60004000 0x0 0x100>, 279 <0x0 0x60004100 0x0 0x100>, 280 <0x0 0x60004200 0x0 0x100>, 281 <0x0 0x60004300 0x0 0x100>, 282 <0x0 0x60004400 0x0 0x100>; 283 interrupt-controller; 284 #interrupt-cells = <3>; 285 interrupt-parent = <&gic>; 286 }; 287 288 timer@60005000 { 289 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; 290 reg = <0x0 0x60005000 0x0 0x400>; 291 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 298 }; 299 300 tegra_car: clock@60006000 { 301 compatible = "nvidia,tegra124-car"; 302 reg = <0x0 0x60006000 0x0 0x1000>; 303 #clock-cells = <1>; 304 #reset-cells = <1>; 305 nvidia,external-memory-controller = <&emc>; 306 }; 307 308 flow-controller@60007000 { 309 compatible = "nvidia,tegra124-flowctrl"; 310 reg = <0x0 0x60007000 0x0 0x1000>; 311 }; 312 313 actmon: actmon@6000c800 { 314 compatible = "nvidia,tegra124-actmon"; 315 reg = <0x0 0x6000c800 0x0 0x400>; 316 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 318 <&tegra_car TEGRA124_CLK_EMC>; 319 clock-names = "actmon", "emc"; 320 resets = <&tegra_car 119>; 321 reset-names = "actmon"; 322 operating-points-v2 = <&emc_bw_dfs_opp_table>; 323 interconnects = <&mc TEGRA124_MC_MPCORER &emc>; 324 interconnect-names = "cpu-read"; 325 #cooling-cells = <2>; 326 }; 327 328 gpio: gpio@6000d000 { 329 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 330 reg = <0x0 0x6000d000 0x0 0x1000>; 331 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 339 #gpio-cells = <2>; 340 gpio-controller; 341 #interrupt-cells = <2>; 342 interrupt-controller; 343 gpio-ranges = <&pinmux 0 0 251>; 344 }; 345 346 apbdma: dma@60020000 { 347 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 348 reg = <0x0 0x60020000 0x0 0x1400>; 349 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 382 resets = <&tegra_car 34>; 383 reset-names = "dma"; 384 #dma-cells = <1>; 385 }; 386 387 apbmisc@70000800 { 388 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 389 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 390 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 391 }; 392 393 pinmux: pinmux@70000868 { 394 compatible = "nvidia,tegra124-pinmux"; 395 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 396 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 397 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 398 }; 399 400 /* 401 * There are two serial driver i.e. 8250 based simple serial 402 * driver and APB DMA based serial driver for higher baudrate 403 * and performace. To enable the 8250 based driver, the compatible 404 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 405 * the APB DMA based serial driver, the compatible is 406 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 407 */ 408 uarta: serial@70006000 { 409 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 410 reg = <0x0 0x70006000 0x0 0x40>; 411 reg-shift = <2>; 412 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 414 resets = <&tegra_car 6>; 415 dmas = <&apbdma 8>, <&apbdma 8>; 416 dma-names = "rx", "tx"; 417 status = "disabled"; 418 }; 419 420 uartb: serial@70006040 { 421 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 422 reg = <0x0 0x70006040 0x0 0x40>; 423 reg-shift = <2>; 424 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 426 resets = <&tegra_car 7>; 427 dmas = <&apbdma 9>, <&apbdma 9>; 428 dma-names = "rx", "tx"; 429 status = "disabled"; 430 }; 431 432 uartc: serial@70006200 { 433 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 434 reg = <0x0 0x70006200 0x0 0x40>; 435 reg-shift = <2>; 436 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 438 resets = <&tegra_car 55>; 439 dmas = <&apbdma 10>, <&apbdma 10>; 440 dma-names = "rx", "tx"; 441 status = "disabled"; 442 }; 443 444 uartd: serial@70006300 { 445 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 446 reg = <0x0 0x70006300 0x0 0x40>; 447 reg-shift = <2>; 448 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 450 resets = <&tegra_car 65>; 451 dmas = <&apbdma 19>, <&apbdma 19>; 452 dma-names = "rx", "tx"; 453 status = "disabled"; 454 }; 455 456 pwm: pwm@7000a000 { 457 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 458 reg = <0x0 0x7000a000 0x0 0x100>; 459 #pwm-cells = <2>; 460 clocks = <&tegra_car TEGRA124_CLK_PWM>; 461 resets = <&tegra_car 17>; 462 reset-names = "pwm"; 463 status = "disabled"; 464 }; 465 466 i2c@7000c000 { 467 compatible = "nvidia,tegra124-i2c"; 468 reg = <0x0 0x7000c000 0x0 0x100>; 469 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 473 clock-names = "div-clk"; 474 resets = <&tegra_car 12>; 475 reset-names = "i2c"; 476 dmas = <&apbdma 21>, <&apbdma 21>; 477 dma-names = "rx", "tx"; 478 status = "disabled"; 479 }; 480 481 i2c@7000c400 { 482 compatible = "nvidia,tegra124-i2c"; 483 reg = <0x0 0x7000c400 0x0 0x100>; 484 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 488 clock-names = "div-clk"; 489 resets = <&tegra_car 54>; 490 reset-names = "i2c"; 491 dmas = <&apbdma 22>, <&apbdma 22>; 492 dma-names = "rx", "tx"; 493 status = "disabled"; 494 }; 495 496 i2c@7000c500 { 497 compatible = "nvidia,tegra124-i2c"; 498 reg = <0x0 0x7000c500 0x0 0x100>; 499 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 503 clock-names = "div-clk"; 504 resets = <&tegra_car 67>; 505 reset-names = "i2c"; 506 dmas = <&apbdma 23>, <&apbdma 23>; 507 dma-names = "rx", "tx"; 508 status = "disabled"; 509 }; 510 511 i2c@7000c700 { 512 compatible = "nvidia,tegra124-i2c"; 513 reg = <0x0 0x7000c700 0x0 0x100>; 514 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 518 clock-names = "div-clk"; 519 resets = <&tegra_car 103>; 520 reset-names = "i2c"; 521 dmas = <&apbdma 26>, <&apbdma 26>; 522 dma-names = "rx", "tx"; 523 status = "disabled"; 524 }; 525 526 i2c@7000d000 { 527 compatible = "nvidia,tegra124-i2c"; 528 reg = <0x0 0x7000d000 0x0 0x100>; 529 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 533 clock-names = "div-clk"; 534 resets = <&tegra_car 47>; 535 reset-names = "i2c"; 536 dmas = <&apbdma 24>, <&apbdma 24>; 537 dma-names = "rx", "tx"; 538 status = "disabled"; 539 }; 540 541 i2c@7000d100 { 542 compatible = "nvidia,tegra124-i2c"; 543 reg = <0x0 0x7000d100 0x0 0x100>; 544 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 548 clock-names = "div-clk"; 549 resets = <&tegra_car 166>; 550 reset-names = "i2c"; 551 dmas = <&apbdma 30>, <&apbdma 30>; 552 dma-names = "rx", "tx"; 553 status = "disabled"; 554 }; 555 556 spi@7000d400 { 557 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 558 reg = <0x0 0x7000d400 0x0 0x200>; 559 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 563 clock-names = "spi"; 564 resets = <&tegra_car 41>; 565 reset-names = "spi"; 566 dmas = <&apbdma 15>, <&apbdma 15>; 567 dma-names = "rx", "tx"; 568 status = "disabled"; 569 }; 570 571 spi@7000d600 { 572 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 573 reg = <0x0 0x7000d600 0x0 0x200>; 574 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 578 clock-names = "spi"; 579 resets = <&tegra_car 44>; 580 reset-names = "spi"; 581 dmas = <&apbdma 16>, <&apbdma 16>; 582 dma-names = "rx", "tx"; 583 status = "disabled"; 584 }; 585 586 spi@7000d800 { 587 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 588 reg = <0x0 0x7000d800 0x0 0x200>; 589 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 593 clock-names = "spi"; 594 resets = <&tegra_car 46>; 595 reset-names = "spi"; 596 dmas = <&apbdma 17>, <&apbdma 17>; 597 dma-names = "rx", "tx"; 598 status = "disabled"; 599 }; 600 601 spi@7000da00 { 602 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 603 reg = <0x0 0x7000da00 0x0 0x200>; 604 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 608 clock-names = "spi"; 609 resets = <&tegra_car 68>; 610 reset-names = "spi"; 611 dmas = <&apbdma 18>, <&apbdma 18>; 612 dma-names = "rx", "tx"; 613 status = "disabled"; 614 }; 615 616 spi@7000dc00 { 617 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 618 reg = <0x0 0x7000dc00 0x0 0x200>; 619 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 623 clock-names = "spi"; 624 resets = <&tegra_car 104>; 625 reset-names = "spi"; 626 dmas = <&apbdma 27>, <&apbdma 27>; 627 dma-names = "rx", "tx"; 628 status = "disabled"; 629 }; 630 631 spi@7000de00 { 632 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 633 reg = <0x0 0x7000de00 0x0 0x200>; 634 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 638 clock-names = "spi"; 639 resets = <&tegra_car 105>; 640 reset-names = "spi"; 641 dmas = <&apbdma 28>, <&apbdma 28>; 642 dma-names = "rx", "tx"; 643 status = "disabled"; 644 }; 645 646 rtc@7000e000 { 647 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 648 reg = <0x0 0x7000e000 0x0 0x100>; 649 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&tegra_car TEGRA124_CLK_RTC>; 651 }; 652 653 tegra_pmc: pmc@7000e400 { 654 compatible = "nvidia,tegra124-pmc"; 655 reg = <0x0 0x7000e400 0x0 0x400>; 656 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 657 clock-names = "pclk", "clk32k_in"; 658 #clock-cells = <1>; 659 }; 660 661 fuse@7000f800 { 662 compatible = "nvidia,tegra124-efuse"; 663 reg = <0x0 0x7000f800 0x0 0x400>; 664 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 665 clock-names = "fuse"; 666 resets = <&tegra_car 39>; 667 reset-names = "fuse"; 668 }; 669 670 cec@70015000 { 671 compatible = "nvidia,tegra124-cec"; 672 reg = <0x0 0x70015000 0x0 0x00001000>; 673 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&tegra_car TEGRA124_CLK_CEC>; 675 clock-names = "cec"; 676 status = "disabled"; 677 hdmi-phandle = <&hdmi>; 678 }; 679 680 mc: memory-controller@70019000 { 681 compatible = "nvidia,tegra124-mc"; 682 reg = <0x0 0x70019000 0x0 0x1000>; 683 clocks = <&tegra_car TEGRA124_CLK_MC>; 684 clock-names = "mc"; 685 686 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 687 688 #iommu-cells = <1>; 689 #reset-cells = <1>; 690 #interconnect-cells = <1>; 691 }; 692 693 emc: external-memory-controller@7001b000 { 694 compatible = "nvidia,tegra124-emc"; 695 reg = <0x0 0x7001b000 0x0 0x1000>; 696 clocks = <&tegra_car TEGRA124_CLK_EMC>; 697 clock-names = "emc"; 698 699 nvidia,memory-controller = <&mc>; 700 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 701 702 #interconnect-cells = <0>; 703 }; 704 705 sata@70020000 { 706 compatible = "nvidia,tegra124-ahci"; 707 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 708 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 709 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 710 clocks = <&tegra_car TEGRA124_CLK_SATA>, 711 <&tegra_car TEGRA124_CLK_SATA_OOB>; 712 clock-names = "sata", "sata-oob"; 713 resets = <&tegra_car 124>, 714 <&tegra_car 129>, 715 <&tegra_car 123>; 716 reset-names = "sata", "sata-cold", "sata-oob"; 717 status = "disabled"; 718 }; 719 720 hda@70030000 { 721 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; 722 reg = <0x0 0x70030000 0x0 0x10000>; 723 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&tegra_car TEGRA124_CLK_HDA>, 725 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 726 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 727 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 728 resets = <&tegra_car 125>, /* hda */ 729 <&tegra_car 128>, /* hda2hdmi */ 730 <&tegra_car 111>; /* hda2codec_2x */ 731 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 732 status = "disabled"; 733 }; 734 735 usb@70090000 { 736 compatible = "nvidia,tegra124-xusb"; 737 reg = <0x0 0x70090000 0x0 0x8000>, 738 <0x0 0x70098000 0x0 0x1000>, 739 <0x0 0x70099000 0x0 0x1000>; 740 reg-names = "hcd", "fpci", "ipfs"; 741 742 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 744 745 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 746 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 747 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 748 <&tegra_car TEGRA124_CLK_XUSB_SS>, 749 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 750 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 751 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 752 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 753 <&tegra_car TEGRA124_CLK_PLL_U_480M>, 754 <&tegra_car TEGRA124_CLK_CLK_M>, 755 <&tegra_car TEGRA124_CLK_PLL_E>; 756 clock-names = "xusb_host", "xusb_host_src", 757 "xusb_falcon_src", "xusb_ss", 758 "xusb_ss_div2", "xusb_ss_src", 759 "xusb_hs_src", "xusb_fs_src", 760 "pll_u_480m", "clk_m", "pll_e"; 761 resets = <&tegra_car 89>, <&tegra_car 156>, 762 <&tegra_car 143>; 763 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 764 765 nvidia,xusb-padctl = <&padctl>; 766 767 status = "disabled"; 768 }; 769 770 padctl: padctl@7009f000 { 771 compatible = "nvidia,tegra124-xusb-padctl"; 772 reg = <0x0 0x7009f000 0x0 0x1000>; 773 resets = <&tegra_car 142>; 774 reset-names = "padctl"; 775 776 pads { 777 usb2 { 778 status = "disabled"; 779 780 lanes { 781 usb2-0 { 782 status = "disabled"; 783 #phy-cells = <0>; 784 }; 785 786 usb2-1 { 787 status = "disabled"; 788 #phy-cells = <0>; 789 }; 790 791 usb2-2 { 792 status = "disabled"; 793 #phy-cells = <0>; 794 }; 795 }; 796 }; 797 798 ulpi { 799 status = "disabled"; 800 801 lanes { 802 ulpi-0 { 803 status = "disabled"; 804 #phy-cells = <0>; 805 }; 806 }; 807 }; 808 809 hsic { 810 status = "disabled"; 811 812 lanes { 813 hsic-0 { 814 status = "disabled"; 815 #phy-cells = <0>; 816 }; 817 818 hsic-1 { 819 status = "disabled"; 820 #phy-cells = <0>; 821 }; 822 }; 823 }; 824 825 pcie { 826 status = "disabled"; 827 828 lanes { 829 pcie-0 { 830 status = "disabled"; 831 #phy-cells = <0>; 832 }; 833 834 pcie-1 { 835 status = "disabled"; 836 #phy-cells = <0>; 837 }; 838 839 pcie-2 { 840 status = "disabled"; 841 #phy-cells = <0>; 842 }; 843 844 pcie-3 { 845 status = "disabled"; 846 #phy-cells = <0>; 847 }; 848 849 pcie-4 { 850 status = "disabled"; 851 #phy-cells = <0>; 852 }; 853 }; 854 }; 855 856 sata { 857 status = "disabled"; 858 859 lanes { 860 sata-0 { 861 status = "disabled"; 862 #phy-cells = <0>; 863 }; 864 }; 865 }; 866 }; 867 868 ports { 869 usb2-0 { 870 status = "disabled"; 871 }; 872 873 usb2-1 { 874 status = "disabled"; 875 }; 876 877 usb2-2 { 878 status = "disabled"; 879 }; 880 881 ulpi-0 { 882 status = "disabled"; 883 }; 884 885 hsic-0 { 886 status = "disabled"; 887 }; 888 889 hsic-1 { 890 status = "disabled"; 891 }; 892 893 usb3-0 { 894 status = "disabled"; 895 }; 896 897 usb3-1 { 898 status = "disabled"; 899 }; 900 }; 901 }; 902 903 mmc@700b0000 { 904 compatible = "nvidia,tegra124-sdhci"; 905 reg = <0x0 0x700b0000 0x0 0x200>; 906 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 908 clock-names = "sdhci"; 909 resets = <&tegra_car 14>; 910 reset-names = "sdhci"; 911 status = "disabled"; 912 }; 913 914 mmc@700b0200 { 915 compatible = "nvidia,tegra124-sdhci"; 916 reg = <0x0 0x700b0200 0x0 0x200>; 917 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 919 clock-names = "sdhci"; 920 resets = <&tegra_car 9>; 921 reset-names = "sdhci"; 922 status = "disabled"; 923 }; 924 925 mmc@700b0400 { 926 compatible = "nvidia,tegra124-sdhci"; 927 reg = <0x0 0x700b0400 0x0 0x200>; 928 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 930 clock-names = "sdhci"; 931 resets = <&tegra_car 69>; 932 reset-names = "sdhci"; 933 status = "disabled"; 934 }; 935 936 mmc@700b0600 { 937 compatible = "nvidia,tegra124-sdhci"; 938 reg = <0x0 0x700b0600 0x0 0x200>; 939 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 940 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 941 clock-names = "sdhci"; 942 resets = <&tegra_car 15>; 943 reset-names = "sdhci"; 944 status = "disabled"; 945 }; 946 947 soctherm: thermal-sensor@700e2000 { 948 compatible = "nvidia,tegra124-soctherm"; 949 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 950 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 951 reg-names = "soctherm-reg", "car-reg"; 952 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 954 interrupt-names = "thermal", "edp"; 955 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 956 <&tegra_car TEGRA124_CLK_SOC_THERM>; 957 clock-names = "tsensor", "soctherm"; 958 resets = <&tegra_car 78>; 959 reset-names = "soctherm"; 960 #thermal-sensor-cells = <1>; 961 962 throttle-cfgs { 963 throttle_heavy: heavy { 964 nvidia,priority = <100>; 965 nvidia,cpu-throt-percent = <85>; 966 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 967 968 #cooling-cells = <2>; 969 }; 970 }; 971 }; 972 973 mipi: mipi@700e3000 { 974 compatible = "nvidia,tegra124-mipi"; 975 reg = <0x0 0x700e3000 0x0 0x100>; 976 clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>; 977 clock-names = "mipi-cal"; 978 #nvidia,mipi-calibrate-cells = <1>; 979 }; 980 981 dfll: clock@70110000 { 982 compatible = "nvidia,tegra124-dfll"; 983 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 984 <0 0x70110000 0 0x100>, /* I2C output control */ 985 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 986 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 987 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, 989 <&tegra_car TEGRA124_CLK_DFLL_REF>, 990 <&tegra_car TEGRA124_CLK_I2C5>; 991 clock-names = "soc", "ref", "i2c"; 992 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; 993 reset-names = "dvco"; 994 #clock-cells = <0>; 995 clock-output-names = "dfllCPU_out"; 996 nvidia,sample-rate = <12500>; 997 nvidia,droop-ctrl = <0x00000f00>; 998 nvidia,force-mode = <1>; 999 nvidia,cf = <10>; 1000 nvidia,ci = <0>; 1001 nvidia,cg = <2>; 1002 status = "disabled"; 1003 }; 1004 1005 ahub@70300000 { 1006 compatible = "nvidia,tegra124-ahub"; 1007 reg = <0x0 0x70300000 0x0 0x200>, 1008 <0x0 0x70300800 0x0 0x800>, 1009 <0x0 0x70300200 0x0 0x600>; 1010 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 1012 <&tegra_car TEGRA124_CLK_APBIF>; 1013 clock-names = "d_audio", "apbif"; 1014 resets = <&tegra_car 106>, /* d_audio */ 1015 <&tegra_car 107>, /* apbif */ 1016 <&tegra_car 30>, /* i2s0 */ 1017 <&tegra_car 11>, /* i2s1 */ 1018 <&tegra_car 18>, /* i2s2 */ 1019 <&tegra_car 101>, /* i2s3 */ 1020 <&tegra_car 102>, /* i2s4 */ 1021 <&tegra_car 108>, /* dam0 */ 1022 <&tegra_car 109>, /* dam1 */ 1023 <&tegra_car 110>, /* dam2 */ 1024 <&tegra_car 10>, /* spdif */ 1025 <&tegra_car 153>, /* amx */ 1026 <&tegra_car 185>, /* amx1 */ 1027 <&tegra_car 154>, /* adx */ 1028 <&tegra_car 180>, /* adx1 */ 1029 <&tegra_car 186>, /* afc0 */ 1030 <&tegra_car 187>, /* afc1 */ 1031 <&tegra_car 188>, /* afc2 */ 1032 <&tegra_car 189>, /* afc3 */ 1033 <&tegra_car 190>, /* afc4 */ 1034 <&tegra_car 191>; /* afc5 */ 1035 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 1036 "i2s3", "i2s4", "dam0", "dam1", "dam2", 1037 "spdif", "amx", "amx1", "adx", "adx1", 1038 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 1039 dmas = <&apbdma 1>, <&apbdma 1>, 1040 <&apbdma 2>, <&apbdma 2>, 1041 <&apbdma 3>, <&apbdma 3>, 1042 <&apbdma 4>, <&apbdma 4>, 1043 <&apbdma 6>, <&apbdma 6>, 1044 <&apbdma 7>, <&apbdma 7>, 1045 <&apbdma 12>, <&apbdma 12>, 1046 <&apbdma 13>, <&apbdma 13>, 1047 <&apbdma 14>, <&apbdma 14>, 1048 <&apbdma 29>, <&apbdma 29>; 1049 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 1050 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 1051 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 1052 "rx9", "tx9"; 1053 ranges; 1054 #address-cells = <2>; 1055 #size-cells = <2>; 1056 1057 tegra_i2s0: i2s@70301000 { 1058 compatible = "nvidia,tegra124-i2s"; 1059 reg = <0x0 0x70301000 0x0 0x100>; 1060 nvidia,ahub-cif-ids = <4 4>; 1061 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 1062 resets = <&tegra_car 30>; 1063 reset-names = "i2s"; 1064 status = "disabled"; 1065 }; 1066 1067 tegra_i2s1: i2s@70301100 { 1068 compatible = "nvidia,tegra124-i2s"; 1069 reg = <0x0 0x70301100 0x0 0x100>; 1070 nvidia,ahub-cif-ids = <5 5>; 1071 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 1072 resets = <&tegra_car 11>; 1073 reset-names = "i2s"; 1074 status = "disabled"; 1075 }; 1076 1077 tegra_i2s2: i2s@70301200 { 1078 compatible = "nvidia,tegra124-i2s"; 1079 reg = <0x0 0x70301200 0x0 0x100>; 1080 nvidia,ahub-cif-ids = <6 6>; 1081 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 1082 resets = <&tegra_car 18>; 1083 reset-names = "i2s"; 1084 status = "disabled"; 1085 }; 1086 1087 tegra_i2s3: i2s@70301300 { 1088 compatible = "nvidia,tegra124-i2s"; 1089 reg = <0x0 0x70301300 0x0 0x100>; 1090 nvidia,ahub-cif-ids = <7 7>; 1091 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 1092 resets = <&tegra_car 101>; 1093 reset-names = "i2s"; 1094 status = "disabled"; 1095 }; 1096 1097 tegra_i2s4: i2s@70301400 { 1098 compatible = "nvidia,tegra124-i2s"; 1099 reg = <0x0 0x70301400 0x0 0x100>; 1100 nvidia,ahub-cif-ids = <8 8>; 1101 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 1102 resets = <&tegra_car 102>; 1103 reset-names = "i2s"; 1104 status = "disabled"; 1105 }; 1106 }; 1107 1108 usb@7d000000 { 1109 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1110 reg = <0x0 0x7d000000 0x0 0x4000>; 1111 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1112 phy_type = "utmi"; 1113 clocks = <&tegra_car TEGRA124_CLK_USBD>; 1114 resets = <&tegra_car 22>; 1115 reset-names = "usb"; 1116 nvidia,phy = <&phy1>; 1117 status = "disabled"; 1118 }; 1119 1120 phy1: usb-phy@7d000000 { 1121 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1122 reg = <0x0 0x7d000000 0x0 0x4000>, 1123 <0x0 0x7d000000 0x0 0x4000>; 1124 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1125 phy_type = "utmi"; 1126 clocks = <&tegra_car TEGRA124_CLK_USBD>, 1127 <&tegra_car TEGRA124_CLK_PLL_U>, 1128 <&tegra_car TEGRA124_CLK_USBD>; 1129 clock-names = "reg", "pll_u", "utmi-pads"; 1130 resets = <&tegra_car 22>, <&tegra_car 22>; 1131 reset-names = "usb", "utmi-pads"; 1132 #phy-cells = <0>; 1133 nvidia,hssync-start-delay = <0>; 1134 nvidia,idle-wait-delay = <17>; 1135 nvidia,elastic-limit = <16>; 1136 nvidia,term-range-adj = <6>; 1137 nvidia,xcvr-setup = <9>; 1138 nvidia,xcvr-lsfslew = <0>; 1139 nvidia,xcvr-lsrslew = <3>; 1140 nvidia,hssquelch-level = <2>; 1141 nvidia,hsdiscon-level = <5>; 1142 nvidia,xcvr-hsslew = <12>; 1143 nvidia,has-utmi-pad-registers; 1144 nvidia,pmc = <&tegra_pmc 0>; 1145 status = "disabled"; 1146 }; 1147 1148 usb@7d004000 { 1149 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1150 reg = <0x0 0x7d004000 0x0 0x4000>; 1151 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1152 phy_type = "utmi"; 1153 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1154 resets = <&tegra_car 58>; 1155 reset-names = "usb"; 1156 nvidia,phy = <&phy2>; 1157 status = "disabled"; 1158 }; 1159 1160 phy2: usb-phy@7d004000 { 1161 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1162 reg = <0x0 0x7d004000 0x0 0x4000>, 1163 <0x0 0x7d000000 0x0 0x4000>; 1164 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1165 phy_type = "utmi"; 1166 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1167 <&tegra_car TEGRA124_CLK_PLL_U>, 1168 <&tegra_car TEGRA124_CLK_USBD>; 1169 clock-names = "reg", "pll_u", "utmi-pads"; 1170 resets = <&tegra_car 58>, <&tegra_car 22>; 1171 reset-names = "usb", "utmi-pads"; 1172 #phy-cells = <0>; 1173 nvidia,hssync-start-delay = <0>; 1174 nvidia,idle-wait-delay = <17>; 1175 nvidia,elastic-limit = <16>; 1176 nvidia,term-range-adj = <6>; 1177 nvidia,xcvr-setup = <9>; 1178 nvidia,xcvr-lsfslew = <0>; 1179 nvidia,xcvr-lsrslew = <3>; 1180 nvidia,hssquelch-level = <2>; 1181 nvidia,hsdiscon-level = <5>; 1182 nvidia,xcvr-hsslew = <12>; 1183 nvidia,pmc = <&tegra_pmc 1>; 1184 status = "disabled"; 1185 }; 1186 1187 usb@7d008000 { 1188 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1189 reg = <0x0 0x7d008000 0x0 0x4000>; 1190 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1191 phy_type = "utmi"; 1192 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1193 resets = <&tegra_car 59>; 1194 reset-names = "usb"; 1195 nvidia,phy = <&phy3>; 1196 status = "disabled"; 1197 }; 1198 1199 phy3: usb-phy@7d008000 { 1200 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1201 reg = <0x0 0x7d008000 0x0 0x4000>, 1202 <0x0 0x7d000000 0x0 0x4000>; 1203 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1204 phy_type = "utmi"; 1205 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1206 <&tegra_car TEGRA124_CLK_PLL_U>, 1207 <&tegra_car TEGRA124_CLK_USBD>; 1208 clock-names = "reg", "pll_u", "utmi-pads"; 1209 resets = <&tegra_car 59>, <&tegra_car 22>; 1210 reset-names = "usb", "utmi-pads"; 1211 #phy-cells = <0>; 1212 nvidia,hssync-start-delay = <0>; 1213 nvidia,idle-wait-delay = <17>; 1214 nvidia,elastic-limit = <16>; 1215 nvidia,term-range-adj = <6>; 1216 nvidia,xcvr-setup = <9>; 1217 nvidia,xcvr-lsfslew = <0>; 1218 nvidia,xcvr-lsrslew = <3>; 1219 nvidia,hssquelch-level = <2>; 1220 nvidia,hsdiscon-level = <5>; 1221 nvidia,xcvr-hsslew = <12>; 1222 nvidia,pmc = <&tegra_pmc 2>; 1223 status = "disabled"; 1224 }; 1225 1226 cpus { 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 1230 cpu@0 { 1231 device_type = "cpu"; 1232 compatible = "arm,cortex-a15"; 1233 reg = <0>; 1234 1235 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, 1236 <&tegra_car TEGRA124_CLK_CCLK_LP>, 1237 <&tegra_car TEGRA124_CLK_PLL_X>, 1238 <&tegra_car TEGRA124_CLK_PLL_P>, 1239 <&dfll>; 1240 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; 1241 /* FIXME: what's the actual transition time? */ 1242 clock-latency = <300000>; 1243 }; 1244 1245 cpu@1 { 1246 device_type = "cpu"; 1247 compatible = "arm,cortex-a15"; 1248 reg = <1>; 1249 }; 1250 1251 cpu@2 { 1252 device_type = "cpu"; 1253 compatible = "arm,cortex-a15"; 1254 reg = <2>; 1255 }; 1256 1257 cpu@3 { 1258 device_type = "cpu"; 1259 compatible = "arm,cortex-a15"; 1260 reg = <3>; 1261 }; 1262 }; 1263 1264 pmu { 1265 compatible = "arm,cortex-a15-pmu"; 1266 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1270 interrupt-affinity = <&{/cpus/cpu@0}>, 1271 <&{/cpus/cpu@1}>, 1272 <&{/cpus/cpu@2}>, 1273 <&{/cpus/cpu@3}>; 1274 }; 1275 1276 thermal-zones { 1277 cpu-thermal { 1278 polling-delay-passive = <1000>; 1279 polling-delay = <1000>; 1280 1281 thermal-sensors = 1282 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1283 1284 trips { 1285 cpu-shutdown-trip { 1286 temperature = <103000>; 1287 hysteresis = <0>; 1288 type = "critical"; 1289 }; 1290 cpu_throttle_trip: throttle-trip { 1291 temperature = <100000>; 1292 hysteresis = <1000>; 1293 type = "hot"; 1294 }; 1295 }; 1296 1297 cooling-maps { 1298 map0 { 1299 trip = <&cpu_throttle_trip>; 1300 cooling-device = <&throttle_heavy 1 1>; 1301 }; 1302 }; 1303 }; 1304 1305 mem-thermal { 1306 polling-delay-passive = <1000>; 1307 polling-delay = <1000>; 1308 1309 thermal-sensors = 1310 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1311 1312 trips { 1313 mem-shutdown-trip { 1314 temperature = <103000>; 1315 hysteresis = <0>; 1316 type = "critical"; 1317 }; 1318 mem-throttle-trip { 1319 temperature = <99000>; 1320 hysteresis = <1000>; 1321 type = "hot"; 1322 }; 1323 }; 1324 1325 cooling-maps { 1326 /* 1327 * There are currently no cooling maps, 1328 * because there are no cooling devices. 1329 */ 1330 }; 1331 }; 1332 1333 gpu-thermal { 1334 polling-delay-passive = <1000>; 1335 polling-delay = <1000>; 1336 1337 thermal-sensors = 1338 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1339 1340 trips { 1341 gpu-shutdown-trip { 1342 temperature = <101000>; 1343 hysteresis = <0>; 1344 type = "critical"; 1345 }; 1346 gpu_throttle_trip: throttle-trip { 1347 temperature = <99000>; 1348 hysteresis = <1000>; 1349 type = "hot"; 1350 }; 1351 }; 1352 1353 cooling-maps { 1354 map0 { 1355 trip = <&gpu_throttle_trip>; 1356 cooling-device = <&throttle_heavy 1 1>; 1357 }; 1358 }; 1359 }; 1360 1361 pllx-thermal { 1362 polling-delay-passive = <1000>; 1363 polling-delay = <1000>; 1364 1365 thermal-sensors = 1366 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1367 1368 trips { 1369 pllx-shutdown-trip { 1370 temperature = <103000>; 1371 hysteresis = <0>; 1372 type = "critical"; 1373 }; 1374 pllx-throttle-trip { 1375 temperature = <99000>; 1376 hysteresis = <1000>; 1377 type = "hot"; 1378 }; 1379 }; 1380 1381 cooling-maps { 1382 /* 1383 * There are currently no cooling maps, 1384 * because there are no cooling devices. 1385 */ 1386 }; 1387 }; 1388 }; 1389 1390 timer { 1391 compatible = "arm,armv7-timer"; 1392 interrupts = <GIC_PPI 13 1393 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1394 <GIC_PPI 14 1395 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1396 <GIC_PPI 11 1397 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1398 <GIC_PPI 10 1399 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1400 interrupt-parent = <&gic>; 1401 }; 1402}; 1403