1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Apple T8010 "A10" SoC 4 * 5 * Other names: H9P, "Cayman" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "apple,hurricane-zephyr"; 33 reg = <0x0 0x0>; 34 cpu-release-addr = <0 0>; /* To be filled by loader */ 35 operating-points-v2 = <&fusion_opp>; 36 performance-domains = <&cpufreq>; 37 enable-method = "spin-table"; 38 device_type = "cpu"; 39 next-level-cache = <&l2_cache>; 40 i-cache-size = <0x10000>; /* P-core */ 41 d-cache-size = <0x10000>; /* P-core */ 42 }; 43 44 cpu1: cpu@1 { 45 compatible = "apple,hurricane-zephyr"; 46 reg = <0x0 0x1>; 47 cpu-release-addr = <0 0>; /* To be filled by loader */ 48 operating-points-v2 = <&fusion_opp>; 49 performance-domains = <&cpufreq>; 50 enable-method = "spin-table"; 51 device_type = "cpu"; 52 next-level-cache = <&l2_cache>; 53 i-cache-size = <0x10000>; /* P-core */ 54 d-cache-size = <0x10000>; /* P-core */ 55 }; 56 57 l2_cache: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 cache-unified; 61 cache-size = <0x300000>; /* P-cluster */ 62 }; 63 }; 64 65 fusion_opp: opp-table { 66 compatible = "operating-points-v2"; 67 68 /* 69 * Apple Fusion Architecture: Hardware big.LITTLE switcher 70 * that use p-state transitions to switch between cores. 71 * Only one type of core can be active at a given time. 72 * 73 * The E-core frequencies are adjusted so performance scales 74 * linearly with reported clock speed. 75 */ 76 77 opp01 { 78 opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ 79 opp-level = <1>; 80 clock-latency-ns = <11000>; 81 }; 82 opp02 { 83 opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ 84 opp-level = <2>; 85 clock-latency-ns = <49000>; 86 }; 87 opp03 { 88 opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */ 89 opp-level = <3>; 90 clock-latency-ns = <13000>; 91 }; 92 opp04 { 93 opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */ 94 opp-level = <4>; 95 clock-latency-ns = <18000>; 96 }; 97 opp05 { 98 opp-hz = /bits/ 64 <756000000>; 99 opp-level = <5>; 100 clock-latency-ns = <35000>; 101 }; 102 opp06 { 103 opp-hz = /bits/ 64 <1056000000>; 104 opp-level = <6>; 105 clock-latency-ns = <31000>; 106 }; 107 opp07 { 108 opp-hz = /bits/ 64 <1356000000>; 109 opp-level = <7>; 110 clock-latency-ns = <37000>; 111 }; 112 opp08 { 113 opp-hz = /bits/ 64 <1644000000>; 114 opp-level = <8>; 115 clock-latency-ns = <39500>; 116 }; 117 hurricane_opp09: opp09 { 118 opp-hz = /bits/ 64 <1944000000>; 119 opp-level = <9>; 120 clock-latency-ns = <46000>; 121 status = "disabled"; /* Not available on N112 */ 122 }; 123 hurricane_opp10: opp10 { 124 opp-hz = /bits/ 64 <2244000000>; 125 opp-level = <10>; 126 clock-latency-ns = <56000>; 127 status = "disabled"; /* Not available on N112 */ 128 }; 129#if 0 130 /* Not available until CPU deep sleep is implemented */ 131 hurricane_opp11: opp11 { 132 opp-hz = /bits/ 64 <2340000000>; 133 opp-level = <11>; 134 clock-latency-ns = <56000>; 135 turbo-mode; 136 status = "disabled"; /* Not available on N112 */ 137 }; 138#endif 139 }; 140 141 soc { 142 compatible = "simple-bus"; 143 #address-cells = <2>; 144 #size-cells = <2>; 145 nonposted-mmio; 146 ranges; 147 148 cpufreq: performance-controller@202f20000 { 149 compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 150 reg = <0x2 0x02f20000 0 0x1000>; 151 #performance-domain-cells = <0>; 152 }; 153 154 serial0: serial@20a0c0000 { 155 compatible = "apple,s5l-uart"; 156 reg = <0x2 0x0a0c0000 0x0 0x4000>; 157 reg-io-width = <4>; 158 interrupt-parent = <&aic>; 159 interrupts = <AIC_IRQ 218 IRQ_TYPE_LEVEL_HIGH>; 160 /* Use the bootloader-enabled clocks for now. */ 161 clocks = <&clkref>, <&clkref>; 162 clock-names = "uart", "clk_uart_baud0"; 163 power-domains = <&ps_uart0>; 164 status = "disabled"; 165 }; 166 167 pmgr: power-management@20e000000 { 168 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 169 #address-cells = <1>; 170 #size-cells = <1>; 171 172 reg = <0x2 0xe000000 0 0x8c000>; 173 }; 174 175 aic: interrupt-controller@20e100000 { 176 compatible = "apple,t8010-aic", "apple,aic"; 177 reg = <0x2 0x0e100000 0x0 0x100000>; 178 #interrupt-cells = <3>; 179 interrupt-controller; 180 power-domains = <&ps_aic>; 181 }; 182 183 dwi_bl: backlight@20e200080 { 184 compatible = "apple,t8010-dwi-bl", "apple,dwi-bl"; 185 reg = <0x2 0x0e200080 0x0 0x8>; 186 power-domains = <&ps_dwi>; 187 status = "disabled"; 188 }; 189 190 pinctrl_ap: pinctrl@20f100000 { 191 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 192 reg = <0x2 0x0f100000 0x0 0x100000>; 193 power-domains = <&ps_gpio>; 194 195 gpio-controller; 196 #gpio-cells = <2>; 197 gpio-ranges = <&pinctrl_ap 0 0 208>; 198 apple,npins = <208>; 199 200 interrupt-controller; 201 #interrupt-cells = <2>; 202 interrupt-parent = <&aic>; 203 interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, 204 <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, 205 <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, 206 <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 207 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 208 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 209 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; 210 }; 211 212 pinctrl_aop: pinctrl@2100f0000 { 213 compatible = "apple,t8010-pinctrl", "apple,pinctrl"; 214 reg = <0x2 0x100f0000 0x0 0x100000>; 215 power-domains = <&ps_aop_gpio>; 216 217 gpio-controller; 218 #gpio-cells = <2>; 219 gpio-ranges = <&pinctrl_aop 0 0 42>; 220 apple,npins = <42>; 221 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 interrupt-parent = <&aic>; 225 interrupts = <AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH>, 226 <AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH>, 227 <AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH>, 228 <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>, 229 <AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH>, 230 <AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH>, 231 <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>; 232 }; 233 234 pmgr_mini: power-management@210200000 { 235 compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 236 #address-cells = <1>; 237 #size-cells = <1>; 238 239 reg = <0x2 0x10200000 0 0x84000>; 240 }; 241 242 wdt: watchdog@2102b0000 { 243 compatible = "apple,t8010-wdt", "apple,wdt"; 244 reg = <0x2 0x102b0000 0x0 0x4000>; 245 clocks = <&clkref>; 246 interrupt-parent = <&aic>; 247 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 248 }; 249 }; 250 251 timer { 252 compatible = "arm,armv8-timer"; 253 interrupt-parent = <&aic>; 254 interrupt-names = "phys", "virt"; 255 /* Note that A10 doesn't actually have a hypervisor (EL2 is not implemented). */ 256 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 257 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 258 }; 259}; 260 261#include "t8010-pmgr.dtsi" 262