1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T7001 "A8X" SoC 4 * 5 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 6 * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts. 7 */ 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/apple-aic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/pinctrl/apple.h> 13 14/ { 15 interrupt-parent = <&aic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 serial0 = &serial0; 21 }; 22 23 clkref: clock-ref { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <24000000>; 27 clock-output-names = "clkref"; 28 }; 29 30 cpus { 31 #address-cells = <2>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 compatible = "apple,typhoon"; 36 reg = <0x0 0x0>; 37 cpu-release-addr = <0 0>; /* To be filled in by loader */ 38 performance-domains = <&cpufreq>; 39 operating-points-v2 = <&typhoon_opp>; 40 enable-method = "spin-table"; 41 device_type = "cpu"; 42 next-level-cache = <&l2_cache>; 43 i-cache-size = <0x10000>; 44 d-cache-size = <0x10000>; 45 }; 46 47 cpu1: cpu@1 { 48 compatible = "apple,typhoon"; 49 reg = <0x0 0x1>; 50 cpu-release-addr = <0 0>; /* To be filled in by loader */ 51 performance-domains = <&cpufreq>; 52 operating-points-v2 = <&typhoon_opp>; 53 enable-method = "spin-table"; 54 device_type = "cpu"; 55 next-level-cache = <&l2_cache>; 56 i-cache-size = <0x10000>; 57 d-cache-size = <0x10000>; 58 }; 59 60 cpu2: cpu@2 { 61 compatible = "apple,typhoon"; 62 reg = <0x0 0x2>; 63 cpu-release-addr = <0 0>; /* To be filled by loader */ 64 performance-domains = <&cpufreq>; 65 operating-points-v2 = <&typhoon_opp>; 66 enable-method = "spin-table"; 67 device_type = "cpu"; 68 next-level-cache = <&l2_cache>; 69 i-cache-size = <0x10000>; 70 d-cache-size = <0x10000>; 71 }; 72 73 l2_cache: l2-cache { 74 compatible = "cache"; 75 cache-level = <2>; 76 cache-unified; 77 cache-size = <0x200000>; 78 }; 79 }; 80 81 typhoon_opp: opp-table { 82 compatible = "operating-points-v2"; 83 84 opp01 { 85 opp-hz = /bits/ 64 <300000000>; 86 opp-level = <1>; 87 clock-latency-ns = <300>; 88 }; 89 opp02 { 90 opp-hz = /bits/ 64 <396000000>; 91 opp-level = <2>; 92 clock-latency-ns = <49000>; 93 }; 94 opp03 { 95 opp-hz = /bits/ 64 <600000000>; 96 opp-level = <3>; 97 clock-latency-ns = <31000>; 98 }; 99 opp04 { 100 opp-hz = /bits/ 64 <840000000>; 101 opp-level = <4>; 102 clock-latency-ns = <32000>; 103 }; 104 opp05 { 105 opp-hz = /bits/ 64 <1128000000>; 106 opp-level = <5>; 107 clock-latency-ns = <32000>; 108 }; 109 opp06 { 110 opp-hz = /bits/ 64 <1392000000>; 111 opp-level = <6>; 112 clock-latency-ns = <37000>; 113 }; 114 opp07 { 115 opp-hz = /bits/ 64 <1512000000>; 116 opp-level = <7>; 117 clock-latency-ns = <41000>; 118 }; 119 }; 120 121 soc { 122 compatible = "simple-bus"; 123 #address-cells = <2>; 124 #size-cells = <2>; 125 nonposted-mmio; 126 ranges; 127 128 cpufreq: performance-controller@202220000 { 129 compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq"; 130 reg = <0x2 0x02220000 0 0x1000>; 131 #performance-domain-cells = <0>; 132 }; 133 134 serial0: serial@20a0c0000 { 135 compatible = "apple,s5l-uart"; 136 reg = <0x2 0x0a0c0000 0x0 0x4000>; 137 reg-io-width = <4>; 138 interrupt-parent = <&aic>; 139 interrupts = <AIC_IRQ 158 IRQ_TYPE_LEVEL_HIGH>; 140 /* Use the bootloader-enabled clocks for now. */ 141 clocks = <&clkref>, <&clkref>; 142 clock-names = "uart", "clk_uart_baud0"; 143 power-domains = <&ps_uart0>; 144 status = "disabled"; 145 }; 146 147 pmgr: power-management@20e000000 { 148 compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 149 #address-cells = <1>; 150 #size-cells = <1>; 151 152 reg = <0x2 0xe000000 0 0x24000>; 153 }; 154 155 wdt: watchdog@20e027000 { 156 compatible = "apple,t7000-wdt", "apple,wdt"; 157 reg = <0x2 0x0e027000 0x0 0x1000>; 158 clocks = <&clkref>; 159 interrupt-parent = <&aic>; 160 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 161 }; 162 163 aic: interrupt-controller@20e100000 { 164 compatible = "apple,t7000-aic", "apple,aic"; 165 reg = <0x2 0x0e100000 0x0 0x100000>; 166 #interrupt-cells = <3>; 167 interrupt-controller; 168 power-domains = <&ps_aic>; 169 }; 170 171 pinctrl: pinctrl@20e300000 { 172 compatible = "apple,t7000-pinctrl", "apple,pinctrl"; 173 reg = <0x2 0x0e300000 0x0 0x100000>; 174 power-domains = <&ps_gpio>; 175 176 gpio-controller; 177 #gpio-cells = <2>; 178 gpio-ranges = <&pinctrl 0 0 184>; 179 apple,npins = <184>; 180 181 interrupt-controller; 182 #interrupt-cells = <2>; 183 interrupt-parent = <&aic>; 184 interrupts = <AIC_IRQ 62 IRQ_TYPE_LEVEL_HIGH>, 185 <AIC_IRQ 63 IRQ_TYPE_LEVEL_HIGH>, 186 <AIC_IRQ 64 IRQ_TYPE_LEVEL_HIGH>, 187 <AIC_IRQ 65 IRQ_TYPE_LEVEL_HIGH>, 188 <AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH>, 189 <AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH>, 190 <AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH>; 191 }; 192 }; 193 194 timer { 195 compatible = "arm,armv8-timer"; 196 interrupt-parent = <&aic>; 197 interrupt-names = "phys", "virt"; 198 /* Note that A8X doesn't actually have a hypervisor (EL2 is not implemented). */ 199 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 200 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 201 }; 202}; 203 204#include "t7001-pmgr.dtsi" 205