xref: /linux/arch/arm/boot/dts/allwinner/sun5i.dtsi (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1/*
2 * Copyright 2012-2015 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 *  a) This library is free software; you can redistribute it and/or
12 *     modify it under the terms of the GNU General Public License as
13 *     published by the Free Software Foundation; either version 2 of the
14 *     License, or (at your option) any later version.
15 *
16 *     This library is distributed in the hope that it will be useful,
17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 *     GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 *  b) Permission is hereby granted, free of charge, to any person
24 *     obtaining a copy of this software and associated documentation
25 *     files (the "Software"), to deal in the Software without
26 *     restriction, including without limitation the rights to use,
27 *     copy, modify, merge, publish, distribute, sublicense, and/or
28 *     sell copies of the Software, and to permit persons to whom the
29 *     Software is furnished to do so, subject to the following
30 *     conditions:
31 *
32 *     The above copyright notice and this permission notice shall be
33 *     included in all copies or substantial portions of the Software.
34 *
35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 *     OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include <dt-bindings/clock/sun5i-ccu.h>
46#include <dt-bindings/dma/sun4i-a10.h>
47#include <dt-bindings/reset/sun5i-ccu.h>
48
49/ {
50	interrupt-parent = <&intc>;
51	#address-cells = <1>;
52	#size-cells = <1>;
53
54	cpus {
55		#address-cells = <1>;
56		#size-cells = <0>;
57
58		cpu0: cpu@0 {
59			device_type = "cpu";
60			compatible = "arm,cortex-a8";
61			reg = <0x0>;
62			clocks = <&ccu CLK_CPU>;
63		};
64	};
65
66	chosen {
67		#address-cells = <1>;
68		#size-cells = <1>;
69		ranges;
70
71		framebuffer-lcd0 {
72			compatible = "allwinner,simple-framebuffer",
73				     "simple-framebuffer";
74			allwinner,pipeline = "de_be0-lcd0";
75			clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
76				 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
77			status = "disabled";
78		};
79
80		framebuffer-lcd0-tve0 {
81			compatible = "allwinner,simple-framebuffer",
82				     "simple-framebuffer";
83			allwinner,pipeline = "de_be0-lcd0-tve0";
84			clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
85				 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
86				 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
87			status = "disabled";
88		};
89	};
90
91	clocks {
92		#address-cells = <1>;
93		#size-cells = <1>;
94		ranges;
95
96		osc24M: clk-24M {
97			#clock-cells = <0>;
98			compatible = "fixed-clock";
99			clock-frequency = <24000000>;
100			clock-output-names = "osc24M";
101		};
102
103		osc32k: clk-32k {
104			#clock-cells = <0>;
105			compatible = "fixed-clock";
106			clock-frequency = <32768>;
107			clock-output-names = "osc32k";
108		};
109	};
110
111	reserved-memory {
112		#address-cells = <1>;
113		#size-cells = <1>;
114		ranges;
115
116		/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
117		default-pool {
118			compatible = "shared-dma-pool";
119			size = <0x6000000>;
120			alloc-ranges = <0x40000000 0x10000000>;
121			reusable;
122			linux,cma-default;
123		};
124	};
125
126	soc {
127		compatible = "simple-bus";
128		#address-cells = <1>;
129		#size-cells = <1>;
130		dma-ranges;
131		ranges;
132
133		system-control@1c00000 {
134			compatible = "allwinner,sun5i-a13-system-control";
135			reg = <0x01c00000 0x30>;
136			#address-cells = <1>;
137			#size-cells = <1>;
138			ranges;
139
140			sram_a: sram@0 {
141				compatible = "mmio-sram";
142				reg = <0x00000000 0xc000>;
143				#address-cells = <1>;
144				#size-cells = <1>;
145				ranges = <0 0x00000000 0xc000>;
146
147				emac_sram: sram-section@8000 {
148					compatible = "allwinner,sun5i-a13-sram-a3-a4",
149						     "allwinner,sun4i-a10-sram-a3-a4";
150					reg = <0x8000 0x4000>;
151					status = "disabled";
152				};
153			};
154
155			sram_d: sram@10000 {
156				compatible = "mmio-sram";
157				reg = <0x00010000 0x1000>;
158				#address-cells = <1>;
159				#size-cells = <1>;
160				ranges = <0 0x00010000 0x1000>;
161
162				otg_sram: sram-section@0 {
163					compatible = "allwinner,sun5i-a13-sram-d",
164						     "allwinner,sun4i-a10-sram-d";
165					reg = <0x0000 0x1000>;
166					status = "disabled";
167				};
168			};
169
170			sram_c: sram@1d00000 {
171				compatible = "mmio-sram";
172				reg = <0x01d00000 0xd0000>;
173				#address-cells = <1>;
174				#size-cells = <1>;
175				ranges = <0 0x01d00000 0xd0000>;
176
177				ve_sram: sram-section@0 {
178					compatible = "allwinner,sun5i-a13-sram-c1",
179						     "allwinner,sun4i-a10-sram-c1";
180					reg = <0x000000 0x80000>;
181				};
182			};
183		};
184
185		mbus: dram-controller@1c01000 {
186			compatible = "allwinner,sun5i-a13-mbus";
187			reg = <0x01c01000 0x1000>;
188			clocks = <&ccu CLK_MBUS>;
189			#address-cells = <1>;
190			#size-cells = <1>;
191			dma-ranges = <0x00000000 0x40000000 0x20000000>;
192			#interconnect-cells = <1>;
193		};
194
195		dma: dma-controller@1c02000 {
196			compatible = "allwinner,sun4i-a10-dma";
197			reg = <0x01c02000 0x1000>;
198			interrupts = <27>;
199			clocks = <&ccu CLK_AHB_DMA>;
200			#dma-cells = <2>;
201		};
202
203		nfc: nand-controller@1c03000 {
204			compatible = "allwinner,sun4i-a10-nand";
205			reg = <0x01c03000 0x1000>;
206			interrupts = <37>;
207			clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
208			clock-names = "ahb", "mod";
209			dmas = <&dma SUN4I_DMA_DEDICATED 3>;
210			dma-names = "rxtx";
211			status = "disabled";
212			#address-cells = <1>;
213			#size-cells = <0>;
214		};
215
216		spi0: spi@1c05000 {
217			compatible = "allwinner,sun4i-a10-spi";
218			reg = <0x01c05000 0x1000>;
219			interrupts = <10>;
220			clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
221			clock-names = "ahb", "mod";
222			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
223			       <&dma SUN4I_DMA_DEDICATED 26>;
224			dma-names = "rx", "tx";
225			status = "disabled";
226			#address-cells = <1>;
227			#size-cells = <0>;
228		};
229
230		spi1: spi@1c06000 {
231			compatible = "allwinner,sun4i-a10-spi";
232			reg = <0x01c06000 0x1000>;
233			interrupts = <11>;
234			clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
235			clock-names = "ahb", "mod";
236			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
237			       <&dma SUN4I_DMA_DEDICATED 8>;
238			dma-names = "rx", "tx";
239			status = "disabled";
240			#address-cells = <1>;
241			#size-cells = <0>;
242		};
243
244		tve0: tv-encoder@1c0a000 {
245			compatible = "allwinner,sun4i-a10-tv-encoder";
246			reg = <0x01c0a000 0x1000>;
247			clocks = <&ccu CLK_AHB_TVE>;
248			resets = <&ccu RST_TVE>;
249			status = "disabled";
250
251			port {
252
253				tve0_in_tcon0: endpoint {
254					remote-endpoint = <&tcon0_out_tve0>;
255				};
256			};
257		};
258
259		emac: ethernet@1c0b000 {
260			compatible = "allwinner,sun4i-a10-emac";
261			reg = <0x01c0b000 0x1000>;
262			interrupts = <55>;
263			clocks = <&ccu CLK_AHB_EMAC>;
264			allwinner,sram = <&emac_sram 1>;
265			status = "disabled";
266		};
267
268		mdio: mdio@1c0b080 {
269			compatible = "allwinner,sun4i-a10-mdio";
270			reg = <0x01c0b080 0x14>;
271			status = "disabled";
272			#address-cells = <1>;
273			#size-cells = <0>;
274		};
275
276		tcon0: lcd-controller@1c0c000 {
277			compatible = "allwinner,sun5i-a13-tcon";
278			reg = <0x01c0c000 0x1000>;
279			interrupts = <44>;
280			dmas = <&dma SUN4I_DMA_DEDICATED 14>;
281			resets = <&ccu RST_LCD>;
282			reset-names = "lcd";
283			clocks = <&ccu CLK_AHB_LCD>,
284				 <&ccu CLK_TCON_CH0>,
285				 <&ccu CLK_TCON_CH1>;
286			clock-names = "ahb",
287				      "tcon-ch0",
288				      "tcon-ch1";
289			clock-output-names = "tcon-data-clock";
290			#clock-cells = <0>;
291			status = "disabled";
292
293			ports {
294				#address-cells = <1>;
295				#size-cells = <0>;
296
297				tcon0_in: port@0 {
298					reg = <0>;
299
300					tcon0_in_be0: endpoint {
301						remote-endpoint = <&be0_out_tcon0>;
302					};
303				};
304
305				tcon0_out: port@1 {
306					#address-cells = <1>;
307					#size-cells = <0>;
308					reg = <1>;
309
310					tcon0_out_tve0: endpoint@1 {
311						reg = <1>;
312						remote-endpoint = <&tve0_in_tcon0>;
313						allwinner,tcon-channel = <1>;
314					};
315				};
316			};
317		};
318
319		video-codec@1c0e000 {
320			compatible = "allwinner,sun5i-a13-video-engine";
321			reg = <0x01c0e000 0x1000>;
322			clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
323				 <&ccu CLK_DRAM_VE>;
324			clock-names = "ahb", "mod", "ram";
325			resets = <&ccu RST_VE>;
326			interrupts = <53>;
327			allwinner,sram = <&ve_sram 1>;
328		};
329
330		mmc0: mmc@1c0f000 {
331			compatible = "allwinner,sun5i-a13-mmc";
332			reg = <0x01c0f000 0x1000>;
333			clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
334			clock-names = "ahb", "mmc";
335			interrupts = <32>;
336			pinctrl-names = "default";
337			pinctrl-0 = <&mmc0_pins>;
338			status = "disabled";
339			#address-cells = <1>;
340			#size-cells = <0>;
341		};
342
343		mmc1: mmc@1c10000 {
344			compatible = "allwinner,sun5i-a13-mmc";
345			reg = <0x01c10000 0x1000>;
346			clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
347			clock-names = "ahb", "mmc";
348			interrupts = <33>;
349			status = "disabled";
350			#address-cells = <1>;
351			#size-cells = <0>;
352		};
353
354		mmc2: mmc@1c11000 {
355			compatible = "allwinner,sun5i-a13-mmc";
356			reg = <0x01c11000 0x1000>;
357			clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
358			clock-names = "ahb", "mmc";
359			interrupts = <34>;
360			status = "disabled";
361			#address-cells = <1>;
362			#size-cells = <0>;
363		};
364
365		usb_otg: usb@1c13000 {
366			compatible = "allwinner,sun4i-a10-musb";
367			reg = <0x01c13000 0x0400>;
368			clocks = <&ccu CLK_AHB_OTG>;
369			interrupts = <38>;
370			interrupt-names = "mc";
371			phys = <&usbphy 0>;
372			phy-names = "usb";
373			extcon = <&usbphy 0>;
374			allwinner,sram = <&otg_sram 1>;
375			dr_mode = "otg";
376			status = "disabled";
377		};
378
379		usbphy: phy@1c13400 {
380			#phy-cells = <1>;
381			compatible = "allwinner,sun5i-a13-usb-phy";
382			reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
383			reg-names = "phy_ctrl", "pmu1";
384			clocks = <&ccu CLK_USB_PHY0>;
385			clock-names = "usb_phy";
386			resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
387			reset-names = "usb0_reset", "usb1_reset";
388			status = "disabled";
389		};
390
391		ehci0: usb@1c14000 {
392			compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
393			reg = <0x01c14000 0x100>;
394			interrupts = <39>;
395			clocks = <&ccu CLK_AHB_EHCI>;
396			phys = <&usbphy 1>;
397			phy-names = "usb";
398			status = "disabled";
399		};
400
401		ohci0: usb@1c14400 {
402			compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
403			reg = <0x01c14400 0x100>;
404			interrupts = <40>;
405			clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
406			phys = <&usbphy 1>;
407			phy-names = "usb";
408			status = "disabled";
409		};
410
411		crypto: crypto-engine@1c15000 {
412			compatible = "allwinner,sun5i-a13-crypto",
413				     "allwinner,sun4i-a10-crypto";
414			reg = <0x01c15000 0x1000>;
415			interrupts = <54>;
416			clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
417			clock-names = "ahb", "mod";
418		};
419
420		spi2: spi@1c17000 {
421			compatible = "allwinner,sun4i-a10-spi";
422			reg = <0x01c17000 0x1000>;
423			interrupts = <12>;
424			clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
425			clock-names = "ahb", "mod";
426			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
427			       <&dma SUN4I_DMA_DEDICATED 28>;
428			dma-names = "rx", "tx";
429			status = "disabled";
430			#address-cells = <1>;
431			#size-cells = <0>;
432		};
433
434		ccu: clock@1c20000 {
435			reg = <0x01c20000 0x400>;
436			clocks = <&osc24M>, <&osc32k>;
437			clock-names = "hosc", "losc";
438			#clock-cells = <1>;
439			#reset-cells = <1>;
440		};
441
442		intc: interrupt-controller@1c20400 {
443			compatible = "allwinner,sun4i-a10-ic";
444			reg = <0x01c20400 0x400>;
445			interrupt-controller;
446			#interrupt-cells = <1>;
447		};
448
449		pio: pinctrl@1c20800 {
450			reg = <0x01c20800 0x400>;
451			interrupts = <28>;
452			clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
453			clock-names = "apb", "hosc", "losc";
454			gpio-controller;
455			interrupt-controller;
456			#interrupt-cells = <3>;
457			#gpio-cells = <3>;
458
459			emac_pd_pins: emac-pd-pins {
460				pins = "PD6", "PD7", "PD10",
461				       "PD11", "PD12", "PD13", "PD14",
462				       "PD15", "PD18", "PD19", "PD20",
463				       "PD21", "PD22", "PD23", "PD24",
464				       "PD25", "PD26", "PD27";
465				function = "emac";
466			};
467
468			i2c0_pins: i2c0-pins {
469				pins = "PB0", "PB1";
470				function = "i2c0";
471			};
472
473			i2c1_pins: i2c1-pins {
474				pins = "PB15", "PB16";
475				function = "i2c1";
476			};
477
478			i2c2_pins: i2c2-pins {
479				pins = "PB17", "PB18";
480				function = "i2c2";
481			};
482
483			ir0_rx_pin: ir0-rx-pin {
484				pins = "PB4";
485				function = "ir0";
486			};
487
488			lcd_rgb565_pins: lcd-rgb565-pins {
489				pins = "PD3", "PD4", "PD5", "PD6", "PD7",
490						 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
491						 "PD19", "PD20", "PD21", "PD22", "PD23",
492						 "PD24", "PD25", "PD26", "PD27";
493				function = "lcd0";
494			};
495
496			lcd_rgb666_pins: lcd-rgb666-pins {
497				pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
498				       "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
499				       "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
500				       "PD24", "PD25", "PD26", "PD27";
501				function = "lcd0";
502			};
503
504			mmc0_pins: mmc0-pins {
505				pins = "PF0", "PF1", "PF2", "PF3",
506				       "PF4", "PF5";
507				function = "mmc0";
508				drive-strength = <30>;
509				bias-pull-up;
510			};
511
512			mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
513				pins = "PC6", "PC7", "PC8", "PC9",
514				       "PC10", "PC11";
515				function = "mmc2";
516				drive-strength = <30>;
517				bias-pull-up;
518			};
519
520			/omit-if-no-ref/
521			mmc2_4bit_pe_pins: mmc2-4bit-pe-pins {
522				pins = "PE4", "PE5", "PE6", "PE7",
523				       "PE8", "PE9";
524				function = "mmc2";
525				drive-strength = <30>;
526				bias-pull-up;
527			};
528
529			mmc2_8bit_pins: mmc2-8bit-pins {
530				pins = "PC6", "PC7", "PC8", "PC9",
531				       "PC10", "PC11", "PC12", "PC13",
532				       "PC14", "PC15";
533				function = "mmc2";
534				drive-strength = <30>;
535				bias-pull-up;
536			};
537
538			nand_pins: nand-pins {
539				pins = "PC0", "PC1", "PC2",
540				       "PC5", "PC8", "PC9", "PC10",
541				       "PC11", "PC12", "PC13", "PC14",
542				       "PC15";
543				function = "nand0";
544			};
545
546			nand_cs0_pin: nand-cs0-pin {
547				pins = "PC4";
548				function = "nand0";
549			};
550
551			nand_rb0_pin: nand-rb0-pin {
552				pins = "PC6";
553				function = "nand0";
554			};
555
556			pwm0_pin: pwm0-pin {
557				pins = "PB2";
558				function = "pwm";
559			};
560
561			spi2_pe_pins: spi2-pe-pins {
562				pins = "PE1", "PE2", "PE3";
563				function = "spi2";
564			};
565
566			spi2_cs0_pe_pin: spi2-cs0-pe-pin {
567				pins = "PE0";
568				function = "spi2";
569			};
570
571			uart1_pe_pins: uart1-pe-pins {
572				pins = "PE10", "PE11";
573				function = "uart1";
574			};
575
576			uart1_pg_pins: uart1-pg-pins {
577				pins = "PG3", "PG4";
578				function = "uart1";
579			};
580
581			uart2_pd_pins: uart2-pd-pins {
582				pins = "PD2", "PD3";
583				function = "uart2";
584			};
585
586			uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
587				pins = "PD4", "PD5";
588				function = "uart2";
589			};
590
591			uart3_pg_pins: uart3-pg-pins {
592				pins = "PG9", "PG10";
593				function = "uart3";
594			};
595
596			uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
597				pins = "PG11", "PG12";
598				function = "uart3";
599			};
600		};
601
602		timer@1c20c00 {
603			compatible = "allwinner,sun4i-a10-timer";
604			reg = <0x01c20c00 0x90>;
605			interrupts = <22>,
606				     <23>,
607				     <24>,
608				     <25>,
609				     <67>,
610				     <68>;
611			clocks = <&ccu CLK_HOSC>;
612		};
613
614		wdt: watchdog@1c20c90 {
615			compatible = "allwinner,sun4i-a10-wdt";
616			reg = <0x01c20c90 0x10>;
617			interrupts = <24>;
618			clocks = <&osc24M>;
619		};
620
621		ir0: ir@1c21800 {
622			compatible = "allwinner,sun4i-a10-ir";
623			clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
624			clock-names = "apb", "ir";
625			interrupts = <5>;
626			reg = <0x01c21800 0x40>;
627			status = "disabled";
628		};
629
630		lradc: lradc@1c22800 {
631			compatible = "allwinner,sun4i-a10-lradc-keys";
632			reg = <0x01c22800 0x100>;
633			interrupts = <31>;
634			status = "disabled";
635		};
636
637		codec: codec@1c22c00 {
638			#sound-dai-cells = <0>;
639			compatible = "allwinner,sun4i-a10-codec";
640			reg = <0x01c22c00 0x40>;
641			interrupts = <30>;
642			clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
643			clock-names = "apb", "codec";
644			dmas = <&dma SUN4I_DMA_NORMAL 19>,
645			       <&dma SUN4I_DMA_NORMAL 19>;
646			dma-names = "rx", "tx";
647			status = "disabled";
648		};
649
650		sid: eeprom@1c23800 {
651			compatible = "allwinner,sun4i-a10-sid";
652			reg = <0x01c23800 0x10>;
653		};
654
655		rtp: rtp@1c25000 {
656			compatible = "allwinner,sun5i-a13-ts";
657			reg = <0x01c25000 0x100>;
658			interrupts = <29>;
659			#thermal-sensor-cells = <0>;
660		};
661
662		uart0: serial@1c28000 {
663			compatible = "snps,dw-apb-uart";
664			reg = <0x01c28000 0x400>;
665			interrupts = <1>;
666			reg-shift = <2>;
667			reg-io-width = <4>;
668			clocks = <&ccu CLK_APB1_UART0>;
669			status = "disabled";
670		};
671
672		uart1: serial@1c28400 {
673			compatible = "snps,dw-apb-uart";
674			reg = <0x01c28400 0x400>;
675			interrupts = <2>;
676			reg-shift = <2>;
677			reg-io-width = <4>;
678			clocks = <&ccu CLK_APB1_UART1>;
679			status = "disabled";
680		};
681
682		uart2: serial@1c28800 {
683			compatible = "snps,dw-apb-uart";
684			reg = <0x01c28800 0x400>;
685			interrupts = <3>;
686			reg-shift = <2>;
687			reg-io-width = <4>;
688			clocks = <&ccu CLK_APB1_UART2>;
689			status = "disabled";
690		};
691
692		uart3: serial@1c28c00 {
693			compatible = "snps,dw-apb-uart";
694			reg = <0x01c28c00 0x400>;
695			interrupts = <4>;
696			reg-shift = <2>;
697			reg-io-width = <4>;
698			clocks = <&ccu CLK_APB1_UART3>;
699			status = "disabled";
700		};
701
702		i2c0: i2c@1c2ac00 {
703			compatible = "allwinner,sun4i-a10-i2c";
704			reg = <0x01c2ac00 0x400>;
705			interrupts = <7>;
706			clocks = <&ccu CLK_APB1_I2C0>;
707			pinctrl-names = "default";
708			pinctrl-0 = <&i2c0_pins>;
709			status = "disabled";
710			#address-cells = <1>;
711			#size-cells = <0>;
712		};
713
714		i2c1: i2c@1c2b000 {
715			compatible = "allwinner,sun4i-a10-i2c";
716			reg = <0x01c2b000 0x400>;
717			interrupts = <8>;
718			clocks = <&ccu CLK_APB1_I2C1>;
719			pinctrl-names = "default";
720			pinctrl-0 = <&i2c1_pins>;
721			status = "disabled";
722			#address-cells = <1>;
723			#size-cells = <0>;
724		};
725
726		i2c2: i2c@1c2b400 {
727			compatible = "allwinner,sun4i-a10-i2c";
728			reg = <0x01c2b400 0x400>;
729			interrupts = <9>;
730			clocks = <&ccu CLK_APB1_I2C2>;
731			pinctrl-names = "default";
732			pinctrl-0 = <&i2c2_pins>;
733			status = "disabled";
734			#address-cells = <1>;
735			#size-cells = <0>;
736		};
737
738		mali: gpu@1c40000 {
739			compatible = "allwinner,sun4i-a10-mali", "arm,mali-400";
740			reg = <0x01c40000 0x10000>;
741			interrupts = <69>, <70>, <71>, <72>,  <73>;
742			interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pmu";
743			clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
744			clock-names = "bus", "core";
745			resets = <&ccu RST_GPU>;
746			assigned-clocks = <&ccu CLK_GPU>;
747			assigned-clock-rates = <320000000>;
748		};
749
750		timer@1c60000 {
751			compatible = "allwinner,sun5i-a13-hstimer";
752			reg = <0x01c60000 0x1000>;
753			interrupts = <82>, <83>;
754			clocks = <&ccu CLK_AHB_HSTIMER>;
755		};
756
757		fe0: display-frontend@1e00000 {
758			compatible = "allwinner,sun5i-a13-display-frontend";
759			reg = <0x01e00000 0x20000>;
760			interrupts = <47>;
761			clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
762				 <&ccu CLK_DRAM_DE_FE>;
763			clock-names = "ahb", "mod",
764				      "ram";
765			resets = <&ccu RST_DE_FE>;
766			interconnects = <&mbus 19>;
767			interconnect-names = "dma-mem";
768			status = "disabled";
769
770			ports {
771				#address-cells = <1>;
772				#size-cells = <0>;
773
774				fe0_out: port@1 {
775					reg = <1>;
776
777					fe0_out_be0: endpoint {
778						remote-endpoint = <&be0_in_fe0>;
779					};
780				};
781			};
782		};
783
784		be0: display-backend@1e60000 {
785			compatible = "allwinner,sun5i-a13-display-backend";
786			reg = <0x01e60000 0x10000>;
787			interrupts = <47>;
788			clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
789				 <&ccu CLK_DRAM_DE_BE>;
790			clock-names = "ahb", "mod",
791				      "ram";
792			resets = <&ccu RST_DE_BE>;
793			interconnects = <&mbus 18>;
794			interconnect-names = "dma-mem";
795			status = "disabled";
796
797			ports {
798				#address-cells = <1>;
799				#size-cells = <0>;
800
801				be0_in: port@0 {
802					reg = <0>;
803
804					be0_in_fe0: endpoint {
805						remote-endpoint = <&fe0_out_be0>;
806					};
807				};
808
809				be0_out: port@1 {
810					reg = <1>;
811
812					be0_out_tcon0: endpoint {
813						remote-endpoint = <&tcon0_in_be0>;
814					};
815				};
816			};
817		};
818	};
819};
820