1/* 2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include "../armv7-m.dtsi" 44#include <dt-bindings/clock/stm32h7-clks.h> 45#include <dt-bindings/mfd/stm32h7-rcc.h> 46#include <dt-bindings/interrupt-controller/irq.h> 47 48/ { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 52 clocks { 53 clk_hse: clk-hse { 54 #clock-cells = <0>; 55 compatible = "fixed-clock"; 56 clock-frequency = <0>; 57 }; 58 59 clk_lse: clk-lse { 60 #clock-cells = <0>; 61 compatible = "fixed-clock"; 62 clock-frequency = <32768>; 63 }; 64 65 clk_i2s: i2s_ckin { 66 #clock-cells = <0>; 67 compatible = "fixed-clock"; 68 clock-frequency = <0>; 69 }; 70 }; 71 72 soc { 73 timer5: timer@40000c00 { 74 compatible = "st,stm32-timer"; 75 reg = <0x40000c00 0x400>; 76 interrupts = <50>; 77 clocks = <&rcc TIM5_CK>; 78 }; 79 80 lptimer1: timer@40002400 { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 compatible = "st,stm32-lptimer"; 84 reg = <0x40002400 0x400>; 85 clocks = <&rcc LPTIM1_CK>; 86 clock-names = "mux"; 87 status = "disabled"; 88 89 pwm { 90 compatible = "st,stm32-pwm-lp"; 91 #pwm-cells = <3>; 92 status = "disabled"; 93 }; 94 95 trigger@0 { 96 compatible = "st,stm32-lptimer-trigger"; 97 reg = <0>; 98 status = "disabled"; 99 }; 100 101 counter { 102 compatible = "st,stm32-lptimer-counter"; 103 status = "disabled"; 104 }; 105 }; 106 107 spi2: spi@40003800 { 108 #address-cells = <1>; 109 #size-cells = <0>; 110 compatible = "st,stm32h7-spi"; 111 reg = <0x40003800 0x400>; 112 interrupts = <36>; 113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>; 114 clocks = <&rcc SPI2_CK>; 115 status = "disabled"; 116 117 }; 118 119 spi3: spi@40003c00 { 120 #address-cells = <1>; 121 #size-cells = <0>; 122 compatible = "st,stm32h7-spi"; 123 reg = <0x40003c00 0x400>; 124 interrupts = <51>; 125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>; 126 clocks = <&rcc SPI3_CK>; 127 status = "disabled"; 128 }; 129 130 usart2: serial@40004400 { 131 compatible = "st,stm32h7-uart"; 132 reg = <0x40004400 0x400>; 133 interrupts = <38>; 134 status = "disabled"; 135 clocks = <&rcc USART2_CK>; 136 }; 137 138 usart3: serial@40004800 { 139 compatible = "st,stm32h7-uart"; 140 reg = <0x40004800 0x400>; 141 interrupts = <39>; 142 status = "disabled"; 143 clocks = <&rcc USART3_CK>; 144 }; 145 146 uart4: serial@40004c00 { 147 compatible = "st,stm32h7-uart"; 148 reg = <0x40004c00 0x400>; 149 interrupts = <52>; 150 status = "disabled"; 151 clocks = <&rcc UART4_CK>; 152 }; 153 154 i2c1: i2c@40005400 { 155 compatible = "st,stm32f7-i2c"; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 reg = <0x40005400 0x400>; 159 interrupts = <31>, 160 <32>; 161 resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; 162 clocks = <&rcc I2C1_CK>; 163 status = "disabled"; 164 }; 165 166 i2c2: i2c@40005800 { 167 compatible = "st,stm32f7-i2c"; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 reg = <0x40005800 0x400>; 171 interrupts = <33>, 172 <34>; 173 resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; 174 clocks = <&rcc I2C2_CK>; 175 status = "disabled"; 176 }; 177 178 i2c3: i2c@40005c00 { 179 compatible = "st,stm32f7-i2c"; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 reg = <0x40005C00 0x400>; 183 interrupts = <72>, 184 <73>; 185 resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; 186 clocks = <&rcc I2C3_CK>; 187 status = "disabled"; 188 }; 189 190 dac: dac@40007400 { 191 compatible = "st,stm32h7-dac-core"; 192 reg = <0x40007400 0x400>; 193 clocks = <&rcc DAC12_CK>; 194 clock-names = "pclk"; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 status = "disabled"; 198 199 dac1: dac@1 { 200 compatible = "st,stm32-dac"; 201 #io-channel-cells = <1>; 202 reg = <1>; 203 status = "disabled"; 204 }; 205 206 dac2: dac@2 { 207 compatible = "st,stm32-dac"; 208 #io-channel-cells = <1>; 209 reg = <2>; 210 status = "disabled"; 211 }; 212 }; 213 214 uart8: serial@40007c00 { 215 compatible = "st,stm32h7-uart"; 216 reg = <0x40007c00 0x400>; 217 interrupts = <83>; 218 status = "disabled"; 219 clocks = <&rcc UART8_CK>; 220 }; 221 222 usart1: serial@40011000 { 223 compatible = "st,stm32h7-uart"; 224 reg = <0x40011000 0x400>; 225 interrupts = <37>; 226 status = "disabled"; 227 clocks = <&rcc USART1_CK>; 228 }; 229 230 spi1: spi@40013000 { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 compatible = "st,stm32h7-spi"; 234 reg = <0x40013000 0x400>; 235 interrupts = <35>; 236 resets = <&rcc STM32H7_APB2_RESET(SPI1)>; 237 clocks = <&rcc SPI1_CK>; 238 status = "disabled"; 239 }; 240 241 spi4: spi@40013400 { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 compatible = "st,stm32h7-spi"; 245 reg = <0x40013400 0x400>; 246 interrupts = <84>; 247 resets = <&rcc STM32H7_APB2_RESET(SPI4)>; 248 clocks = <&rcc SPI4_CK>; 249 status = "disabled"; 250 }; 251 252 spi5: spi@40015000 { 253 #address-cells = <1>; 254 #size-cells = <0>; 255 compatible = "st,stm32h7-spi"; 256 reg = <0x40015000 0x400>; 257 interrupts = <85>; 258 resets = <&rcc STM32H7_APB2_RESET(SPI5)>; 259 clocks = <&rcc SPI5_CK>; 260 status = "disabled"; 261 }; 262 263 dma1: dma-controller@40020000 { 264 compatible = "st,stm32-dma"; 265 reg = <0x40020000 0x400>; 266 interrupts = <11>, 267 <12>, 268 <13>, 269 <14>, 270 <15>, 271 <16>, 272 <17>, 273 <47>; 274 clocks = <&rcc DMA1_CK>; 275 #dma-cells = <4>; 276 st,mem2mem; 277 dma-requests = <8>; 278 status = "disabled"; 279 }; 280 281 dma2: dma-controller@40020400 { 282 compatible = "st,stm32-dma"; 283 reg = <0x40020400 0x400>; 284 interrupts = <56>, 285 <57>, 286 <58>, 287 <59>, 288 <60>, 289 <68>, 290 <69>, 291 <70>; 292 clocks = <&rcc DMA2_CK>; 293 #dma-cells = <4>; 294 st,mem2mem; 295 dma-requests = <8>; 296 status = "disabled"; 297 }; 298 299 dmamux1: dma-router@40020800 { 300 compatible = "st,stm32h7-dmamux"; 301 reg = <0x40020800 0x40>; 302 #dma-cells = <3>; 303 dma-channels = <16>; 304 dma-requests = <128>; 305 dma-masters = <&dma1 &dma2>; 306 clocks = <&rcc DMA1_CK>; 307 }; 308 309 adc_12: adc@40022000 { 310 compatible = "st,stm32h7-adc-core"; 311 reg = <0x40022000 0x400>; 312 interrupts = <18>; 313 clocks = <&rcc ADC12_CK>; 314 clock-names = "bus"; 315 interrupt-controller; 316 #interrupt-cells = <1>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 status = "disabled"; 320 321 adc1: adc@0 { 322 compatible = "st,stm32h7-adc"; 323 #io-channel-cells = <1>; 324 reg = <0x0>; 325 interrupt-parent = <&adc_12>; 326 interrupts = <0>; 327 status = "disabled"; 328 }; 329 330 adc2: adc@100 { 331 compatible = "st,stm32h7-adc"; 332 #io-channel-cells = <1>; 333 reg = <0x100>; 334 interrupt-parent = <&adc_12>; 335 interrupts = <1>; 336 status = "disabled"; 337 }; 338 }; 339 340 usbotg_hs: usb@40040000 { 341 compatible = "st,stm32f7-hsotg"; 342 reg = <0x40040000 0x40000>; 343 interrupts = <77>; 344 clocks = <&rcc USB1OTG_CK>; 345 clock-names = "otg"; 346 g-rx-fifo-size = <256>; 347 g-np-tx-fifo-size = <32>; 348 g-tx-fifo-size = <128 128 64 64 64 64 32 32>; 349 status = "disabled"; 350 }; 351 352 usbotg_fs: usb@40080000 { 353 compatible = "st,stm32f4x9-fsotg"; 354 reg = <0x40080000 0x40000>; 355 interrupts = <101>; 356 clocks = <&rcc USB2OTG_CK>; 357 clock-names = "otg"; 358 status = "disabled"; 359 }; 360 361 ltdc: display-controller@50001000 { 362 compatible = "st,stm32-ltdc"; 363 reg = <0x50001000 0x200>; 364 interrupts = <88>, <89>; 365 resets = <&rcc STM32H7_APB3_RESET(LTDC)>; 366 clocks = <&rcc LTDC_CK>; 367 clock-names = "lcd"; 368 status = "disabled"; 369 }; 370 371 mdma1: dma-controller@52000000 { 372 compatible = "st,stm32h7-mdma"; 373 reg = <0x52000000 0x1000>; 374 interrupts = <122>; 375 clocks = <&rcc MDMA_CK>; 376 #dma-cells = <5>; 377 dma-channels = <16>; 378 dma-requests = <32>; 379 }; 380 381 sdmmc1: mmc@52007000 { 382 compatible = "arm,pl18x", "arm,primecell"; 383 arm,primecell-periphid = <0x10153180>; 384 reg = <0x52007000 0x1000>; 385 interrupts = <49>; 386 clocks = <&rcc SDMMC1_CK>; 387 clock-names = "apb_pclk"; 388 resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; 389 cap-sd-highspeed; 390 cap-mmc-highspeed; 391 max-frequency = <120000000>; 392 }; 393 394 sdmmc2: mmc@48022400 { 395 compatible = "arm,pl18x", "arm,primecell"; 396 arm,primecell-periphid = <0x10153180>; 397 reg = <0x48022400 0x400>; 398 interrupts = <124>; 399 clocks = <&rcc SDMMC2_CK>; 400 clock-names = "apb_pclk"; 401 resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; 402 cap-sd-highspeed; 403 cap-mmc-highspeed; 404 max-frequency = <120000000>; 405 status = "disabled"; 406 }; 407 408 exti: interrupt-controller@58000000 { 409 compatible = "st,stm32h7-exti"; 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 reg = <0x58000000 0x400>; 413 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>; 414 }; 415 416 syscfg: syscon@58000400 { 417 compatible = "st,stm32-syscfg", "syscon"; 418 reg = <0x58000400 0x400>; 419 }; 420 421 spi6: spi@58001400 { 422 #address-cells = <1>; 423 #size-cells = <0>; 424 compatible = "st,stm32h7-spi"; 425 reg = <0x58001400 0x400>; 426 interrupts = <86>; 427 resets = <&rcc STM32H7_APB4_RESET(SPI6)>; 428 clocks = <&rcc SPI6_CK>; 429 status = "disabled"; 430 }; 431 432 i2c4: i2c@58001c00 { 433 compatible = "st,stm32f7-i2c"; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 reg = <0x58001C00 0x400>; 437 interrupts = <95>, 438 <96>; 439 resets = <&rcc STM32H7_APB4_RESET(I2C4)>; 440 clocks = <&rcc I2C4_CK>; 441 status = "disabled"; 442 }; 443 444 lptimer2: timer@58002400 { 445 #address-cells = <1>; 446 #size-cells = <0>; 447 compatible = "st,stm32-lptimer"; 448 reg = <0x58002400 0x400>; 449 clocks = <&rcc LPTIM2_CK>; 450 clock-names = "mux"; 451 status = "disabled"; 452 453 pwm { 454 compatible = "st,stm32-pwm-lp"; 455 #pwm-cells = <3>; 456 status = "disabled"; 457 }; 458 459 trigger@1 { 460 compatible = "st,stm32-lptimer-trigger"; 461 reg = <1>; 462 status = "disabled"; 463 }; 464 465 counter { 466 compatible = "st,stm32-lptimer-counter"; 467 status = "disabled"; 468 }; 469 }; 470 471 lptimer3: timer@58002800 { 472 #address-cells = <1>; 473 #size-cells = <0>; 474 compatible = "st,stm32-lptimer"; 475 reg = <0x58002800 0x400>; 476 clocks = <&rcc LPTIM3_CK>; 477 clock-names = "mux"; 478 status = "disabled"; 479 480 pwm { 481 compatible = "st,stm32-pwm-lp"; 482 #pwm-cells = <3>; 483 status = "disabled"; 484 }; 485 486 trigger@2 { 487 compatible = "st,stm32-lptimer-trigger"; 488 reg = <2>; 489 status = "disabled"; 490 }; 491 }; 492 493 lptimer4: timer@58002c00 { 494 compatible = "st,stm32-lptimer"; 495 reg = <0x58002c00 0x400>; 496 clocks = <&rcc LPTIM4_CK>; 497 clock-names = "mux"; 498 status = "disabled"; 499 500 pwm { 501 compatible = "st,stm32-pwm-lp"; 502 #pwm-cells = <3>; 503 status = "disabled"; 504 }; 505 }; 506 507 lptimer5: timer@58003000 { 508 compatible = "st,stm32-lptimer"; 509 reg = <0x58003000 0x400>; 510 clocks = <&rcc LPTIM5_CK>; 511 clock-names = "mux"; 512 status = "disabled"; 513 514 pwm { 515 compatible = "st,stm32-pwm-lp"; 516 #pwm-cells = <3>; 517 status = "disabled"; 518 }; 519 }; 520 521 vrefbuf: regulator@58003c00 { 522 compatible = "st,stm32-vrefbuf"; 523 reg = <0x58003C00 0x8>; 524 clocks = <&rcc VREF_CK>; 525 regulator-min-microvolt = <1500000>; 526 regulator-max-microvolt = <2500000>; 527 status = "disabled"; 528 }; 529 530 rtc: rtc@58004000 { 531 compatible = "st,stm32h7-rtc"; 532 reg = <0x58004000 0x400>; 533 clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; 534 clock-names = "pclk", "rtc_ck"; 535 assigned-clocks = <&rcc RTC_CK>; 536 assigned-clock-parents = <&rcc LSE_CK>; 537 interrupt-parent = <&exti>; 538 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 539 st,syscfg = <&pwrcfg 0x00 0x100>; 540 status = "disabled"; 541 }; 542 543 rcc: reset-clock-controller@58024400 { 544 compatible = "st,stm32h743-rcc", "st,stm32-rcc"; 545 reg = <0x58024400 0x400>; 546 #clock-cells = <1>; 547 #reset-cells = <1>; 548 clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; 549 st,syscfg = <&pwrcfg>; 550 }; 551 552 pwrcfg: power-config@58024800 { 553 compatible = "st,stm32-power-config", "syscon"; 554 reg = <0x58024800 0x400>; 555 }; 556 557 adc_3: adc@58026000 { 558 compatible = "st,stm32h7-adc-core"; 559 reg = <0x58026000 0x400>; 560 interrupts = <127>; 561 clocks = <&rcc ADC3_CK>; 562 clock-names = "bus"; 563 interrupt-controller; 564 #interrupt-cells = <1>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 status = "disabled"; 568 569 adc3: adc@0 { 570 compatible = "st,stm32h7-adc"; 571 #io-channel-cells = <1>; 572 reg = <0x0>; 573 interrupt-parent = <&adc_3>; 574 interrupts = <0>; 575 status = "disabled"; 576 }; 577 }; 578 579 mac: ethernet@40028000 { 580 compatible = "st,stm32-dwmac", "snps,dwmac-4.10a"; 581 reg = <0x40028000 0x8000>; 582 reg-names = "stmmaceth"; 583 interrupts = <61>; 584 interrupt-names = "macirq"; 585 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; 586 clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>; 587 st,syscon = <&syscfg 0x4>; 588 snps,pbl = <8>; 589 status = "disabled"; 590 }; 591 592 pinctrl: pinctrl@58020000 { 593 #address-cells = <1>; 594 #size-cells = <1>; 595 compatible = "st,stm32h743-pinctrl"; 596 ranges = <0 0x58020000 0x3000>; 597 interrupt-parent = <&exti>; 598 st,syscfg = <&syscfg 0x8>; 599 600 gpioa: gpio@58020000 { 601 gpio-controller; 602 #gpio-cells = <2>; 603 reg = <0x0 0x400>; 604 clocks = <&rcc GPIOA_CK>; 605 st,bank-name = "GPIOA"; 606 interrupt-controller; 607 #interrupt-cells = <2>; 608 ngpios = <16>; 609 gpio-ranges = <&pinctrl 0 0 16>; 610 }; 611 612 gpiob: gpio@58020400 { 613 gpio-controller; 614 #gpio-cells = <2>; 615 reg = <0x400 0x400>; 616 clocks = <&rcc GPIOB_CK>; 617 st,bank-name = "GPIOB"; 618 interrupt-controller; 619 #interrupt-cells = <2>; 620 ngpios = <16>; 621 gpio-ranges = <&pinctrl 0 16 16>; 622 }; 623 624 gpioc: gpio@58020800 { 625 gpio-controller; 626 #gpio-cells = <2>; 627 reg = <0x800 0x400>; 628 clocks = <&rcc GPIOC_CK>; 629 st,bank-name = "GPIOC"; 630 interrupt-controller; 631 #interrupt-cells = <2>; 632 ngpios = <16>; 633 gpio-ranges = <&pinctrl 0 32 16>; 634 }; 635 636 gpiod: gpio@58020c00 { 637 gpio-controller; 638 #gpio-cells = <2>; 639 reg = <0xc00 0x400>; 640 clocks = <&rcc GPIOD_CK>; 641 st,bank-name = "GPIOD"; 642 interrupt-controller; 643 #interrupt-cells = <2>; 644 ngpios = <16>; 645 gpio-ranges = <&pinctrl 0 48 16>; 646 }; 647 648 gpioe: gpio@58021000 { 649 gpio-controller; 650 #gpio-cells = <2>; 651 reg = <0x1000 0x400>; 652 clocks = <&rcc GPIOE_CK>; 653 st,bank-name = "GPIOE"; 654 interrupt-controller; 655 #interrupt-cells = <2>; 656 ngpios = <16>; 657 gpio-ranges = <&pinctrl 0 64 16>; 658 }; 659 660 gpiof: gpio@58021400 { 661 gpio-controller; 662 #gpio-cells = <2>; 663 reg = <0x1400 0x400>; 664 clocks = <&rcc GPIOF_CK>; 665 st,bank-name = "GPIOF"; 666 interrupt-controller; 667 #interrupt-cells = <2>; 668 ngpios = <16>; 669 gpio-ranges = <&pinctrl 0 80 16>; 670 }; 671 672 gpiog: gpio@58021800 { 673 gpio-controller; 674 #gpio-cells = <2>; 675 reg = <0x1800 0x400>; 676 clocks = <&rcc GPIOG_CK>; 677 st,bank-name = "GPIOG"; 678 interrupt-controller; 679 #interrupt-cells = <2>; 680 ngpios = <16>; 681 gpio-ranges = <&pinctrl 0 96 16>; 682 }; 683 684 gpioh: gpio@58021c00 { 685 gpio-controller; 686 #gpio-cells = <2>; 687 reg = <0x1c00 0x400>; 688 clocks = <&rcc GPIOH_CK>; 689 st,bank-name = "GPIOH"; 690 interrupt-controller; 691 #interrupt-cells = <2>; 692 ngpios = <16>; 693 gpio-ranges = <&pinctrl 0 112 16>; 694 }; 695 696 gpioi: gpio@58022000 { 697 gpio-controller; 698 #gpio-cells = <2>; 699 reg = <0x2000 0x400>; 700 clocks = <&rcc GPIOI_CK>; 701 st,bank-name = "GPIOI"; 702 interrupt-controller; 703 #interrupt-cells = <2>; 704 ngpios = <16>; 705 gpio-ranges = <&pinctrl 0 128 16>; 706 }; 707 708 gpioj: gpio@58022400 { 709 gpio-controller; 710 #gpio-cells = <2>; 711 reg = <0x2400 0x400>; 712 clocks = <&rcc GPIOJ_CK>; 713 st,bank-name = "GPIOJ"; 714 interrupt-controller; 715 #interrupt-cells = <2>; 716 ngpios = <16>; 717 gpio-ranges = <&pinctrl 0 144 16>; 718 }; 719 720 gpiok: gpio@58022800 { 721 gpio-controller; 722 #gpio-cells = <2>; 723 reg = <0x2800 0x400>; 724 clocks = <&rcc GPIOK_CK>; 725 st,bank-name = "GPIOK"; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 ngpios = <8>; 729 gpio-ranges = <&pinctrl 0 160 8>; 730 }; 731 }; 732 }; 733}; 734 735&systick { 736 clock-frequency = <250000000>; 737 status = "okay"; 738}; 739