1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2020 Mellanox Technologies. All rights reserved */
3
4 #include "reg.h"
5 #include "core.h"
6 #include "spectrum.h"
7 #include "core_env.h"
8
9 static const char mlxsw_sp_driver_version[] = "1.0";
10
mlxsw_sp_port_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * drvinfo)11 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
12 struct ethtool_drvinfo *drvinfo)
13 {
14 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
15 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
16
17 strscpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
18 sizeof(drvinfo->driver));
19 strscpy(drvinfo->version, mlxsw_sp_driver_version,
20 sizeof(drvinfo->version));
21 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
22 "%d.%d.%d",
23 mlxsw_sp->bus_info->fw_rev.major,
24 mlxsw_sp->bus_info->fw_rev.minor,
25 mlxsw_sp->bus_info->fw_rev.subminor);
26 strscpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
27 sizeof(drvinfo->bus_info));
28 }
29
30 struct mlxsw_sp_ethtool_link_ext_state_opcode_mapping {
31 u32 status_opcode;
32 enum ethtool_link_ext_state link_ext_state;
33 u8 link_ext_substate;
34 };
35
36 static const struct mlxsw_sp_ethtool_link_ext_state_opcode_mapping
37 mlxsw_sp_link_ext_state_opcode_map[] = {
38 {2, ETHTOOL_LINK_EXT_STATE_AUTONEG,
39 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED},
40 {3, ETHTOOL_LINK_EXT_STATE_AUTONEG,
41 ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED},
42 {4, ETHTOOL_LINK_EXT_STATE_AUTONEG,
43 ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED},
44 {36, ETHTOOL_LINK_EXT_STATE_AUTONEG,
45 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE},
46 {38, ETHTOOL_LINK_EXT_STATE_AUTONEG,
47 ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE},
48 {39, ETHTOOL_LINK_EXT_STATE_AUTONEG,
49 ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD},
50
51 {5, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
52 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED},
53 {6, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
54 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT},
55 {7, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
56 ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY},
57 {8, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, 0},
58 {14, ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE,
59 ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT},
60
61 {9, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
62 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK},
63 {10, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
64 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK},
65 {11, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
66 ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS},
67 {12, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
68 ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED},
69 {13, ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH,
70 ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED},
71
72 {15, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, 0},
73 {17, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
74 ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS},
75 {42, ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY,
76 ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE},
77
78 {1024, ETHTOOL_LINK_EXT_STATE_NO_CABLE, 0},
79
80 {16, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
81 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
82 {20, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
83 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
84 {29, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
85 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
86 {1025, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
87 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
88 {1029, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE,
89 ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE},
90 {1031, ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, 0},
91
92 {1027, ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, 0},
93
94 {23, ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, 0},
95
96 {1032, ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, 0},
97
98 {1030, ETHTOOL_LINK_EXT_STATE_OVERHEAT, 0},
99
100 {1042, ETHTOOL_LINK_EXT_STATE_MODULE,
101 ETHTOOL_LINK_EXT_SUBSTATE_MODULE_CMIS_NOT_READY},
102 };
103
104 static void
mlxsw_sp_port_set_link_ext_state(struct mlxsw_sp_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping,struct ethtool_link_ext_state_info * link_ext_state_info)105 mlxsw_sp_port_set_link_ext_state(struct mlxsw_sp_ethtool_link_ext_state_opcode_mapping
106 link_ext_state_mapping,
107 struct ethtool_link_ext_state_info *link_ext_state_info)
108 {
109 switch (link_ext_state_mapping.link_ext_state) {
110 case ETHTOOL_LINK_EXT_STATE_AUTONEG:
111 link_ext_state_info->autoneg =
112 link_ext_state_mapping.link_ext_substate;
113 break;
114 case ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE:
115 link_ext_state_info->link_training =
116 link_ext_state_mapping.link_ext_substate;
117 break;
118 case ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH:
119 link_ext_state_info->link_logical_mismatch =
120 link_ext_state_mapping.link_ext_substate;
121 break;
122 case ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY:
123 link_ext_state_info->bad_signal_integrity =
124 link_ext_state_mapping.link_ext_substate;
125 break;
126 case ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE:
127 link_ext_state_info->cable_issue =
128 link_ext_state_mapping.link_ext_substate;
129 break;
130 case ETHTOOL_LINK_EXT_STATE_MODULE:
131 link_ext_state_info->module =
132 link_ext_state_mapping.link_ext_substate;
133 break;
134 default:
135 break;
136 }
137
138 link_ext_state_info->link_ext_state = link_ext_state_mapping.link_ext_state;
139 }
140
141 static int
mlxsw_sp_port_get_link_ext_state(struct net_device * dev,struct ethtool_link_ext_state_info * link_ext_state_info)142 mlxsw_sp_port_get_link_ext_state(struct net_device *dev,
143 struct ethtool_link_ext_state_info *link_ext_state_info)
144 {
145 struct mlxsw_sp_ethtool_link_ext_state_opcode_mapping link_ext_state_mapping;
146 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
147 char pddr_pl[MLXSW_REG_PDDR_LEN];
148 int opcode, err, i;
149 u32 status_opcode;
150
151 if (netif_carrier_ok(dev))
152 return -ENODATA;
153
154 mlxsw_reg_pddr_pack(pddr_pl, mlxsw_sp_port->local_port,
155 MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO);
156
157 opcode = MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR;
158 mlxsw_reg_pddr_trblsh_group_opcode_set(pddr_pl, opcode);
159
160 err = mlxsw_reg_query(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pddr),
161 pddr_pl);
162 if (err)
163 return err;
164
165 status_opcode = mlxsw_reg_pddr_trblsh_status_opcode_get(pddr_pl);
166 if (!status_opcode)
167 return -ENODATA;
168
169 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_link_ext_state_opcode_map); i++) {
170 link_ext_state_mapping = mlxsw_sp_link_ext_state_opcode_map[i];
171 if (link_ext_state_mapping.status_opcode == status_opcode) {
172 mlxsw_sp_port_set_link_ext_state(link_ext_state_mapping,
173 link_ext_state_info);
174 return 0;
175 }
176 }
177
178 return -ENODATA;
179 }
180
mlxsw_sp_port_get_pauseparam(struct net_device * dev,struct ethtool_pauseparam * pause)181 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
182 struct ethtool_pauseparam *pause)
183 {
184 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
185
186 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
187 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
188 }
189
mlxsw_sp_port_pause_set(struct mlxsw_sp_port * mlxsw_sp_port,struct ethtool_pauseparam * pause)190 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
191 struct ethtool_pauseparam *pause)
192 {
193 char pfcc_pl[MLXSW_REG_PFCC_LEN];
194
195 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
196 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
197 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
198
199 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
200 pfcc_pl);
201 }
202
203 /* Maximum delay buffer needed in case of PAUSE frames. Similar to PFC delay, but is
204 * measured in bytes. Assumes 100m cable and does not take into account MTU.
205 */
206 #define MLXSW_SP_PAUSE_DELAY_BYTES 19476
207
mlxsw_sp_port_set_pauseparam(struct net_device * dev,struct ethtool_pauseparam * pause)208 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
209 struct ethtool_pauseparam *pause)
210 {
211 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
212 bool pause_en = pause->tx_pause || pause->rx_pause;
213 struct mlxsw_sp_hdroom orig_hdroom;
214 struct mlxsw_sp_hdroom hdroom;
215 int prio;
216 int err;
217
218 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
219 netdev_err(dev, "PFC already enabled on port\n");
220 return -EINVAL;
221 }
222
223 if (pause->autoneg) {
224 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
225 return -EINVAL;
226 }
227
228 orig_hdroom = *mlxsw_sp_port->hdroom;
229
230 hdroom = orig_hdroom;
231 if (pause_en)
232 hdroom.delay_bytes = MLXSW_SP_PAUSE_DELAY_BYTES;
233 else
234 hdroom.delay_bytes = 0;
235
236 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++)
237 hdroom.prios.prio[prio].lossy = !pause_en;
238
239 mlxsw_sp_hdroom_bufs_reset_lossiness(&hdroom);
240 mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
241
242 err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
243 if (err) {
244 netdev_err(dev, "Failed to configure port's headroom\n");
245 return err;
246 }
247
248 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
249 if (err) {
250 netdev_err(dev, "Failed to set PAUSE parameters\n");
251 goto err_port_pause_configure;
252 }
253
254 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
255 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
256
257 return 0;
258
259 err_port_pause_configure:
260 mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom);
261 return err;
262 }
263
264 struct mlxsw_sp_port_hw_stats {
265 char str[ETH_GSTRING_LEN] __nonstring;
266 u64 (*getter)(const char *payload);
267 bool cells_bytes;
268 };
269
270 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
271 {
272 .str = "a_frames_transmitted_ok",
273 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
274 },
275 {
276 .str = "a_frames_received_ok",
277 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
278 },
279 {
280 .str = "a_frame_check_sequence_errors",
281 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
282 },
283 {
284 .str = "a_alignment_errors",
285 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
286 },
287 {
288 .str = "a_octets_transmitted_ok",
289 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
290 },
291 {
292 .str = "a_octets_received_ok",
293 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
294 },
295 {
296 .str = "a_multicast_frames_xmitted_ok",
297 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
298 },
299 {
300 .str = "a_broadcast_frames_xmitted_ok",
301 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
302 },
303 {
304 .str = "a_multicast_frames_received_ok",
305 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
306 },
307 {
308 .str = "a_broadcast_frames_received_ok",
309 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
310 },
311 {
312 .str = "a_in_range_length_errors",
313 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
314 },
315 {
316 .str = "a_out_of_range_length_field",
317 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
318 },
319 {
320 .str = "a_frame_too_long_errors",
321 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
322 },
323 {
324 .str = "a_symbol_error_during_carrier",
325 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
326 },
327 {
328 .str = "a_mac_control_frames_transmitted",
329 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
330 },
331 {
332 .str = "a_mac_control_frames_received",
333 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
334 },
335 {
336 .str = "a_unsupported_opcodes_received",
337 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
338 },
339 {
340 .str = "a_pause_mac_ctrl_frames_received",
341 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
342 },
343 {
344 .str = "a_pause_mac_ctrl_frames_xmitted",
345 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
346 },
347 };
348
349 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
350
351 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2863_stats[] = {
352 {
353 .str = "if_in_discards",
354 .getter = mlxsw_reg_ppcnt_if_in_discards_get,
355 },
356 {
357 .str = "if_out_discards",
358 .getter = mlxsw_reg_ppcnt_if_out_discards_get,
359 },
360 {
361 .str = "if_out_errors",
362 .getter = mlxsw_reg_ppcnt_if_out_errors_get,
363 },
364 };
365
366 #define MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN \
367 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2863_stats)
368
369 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
370 {
371 .str = "ether_stats_undersize_pkts",
372 .getter = mlxsw_reg_ppcnt_ether_stats_undersize_pkts_get,
373 },
374 {
375 .str = "ether_stats_oversize_pkts",
376 .getter = mlxsw_reg_ppcnt_ether_stats_oversize_pkts_get,
377 },
378 {
379 .str = "ether_stats_fragments",
380 .getter = mlxsw_reg_ppcnt_ether_stats_fragments_get,
381 },
382 {
383 .str = "ether_pkts64octets",
384 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
385 },
386 {
387 .str = "ether_pkts65to127octets",
388 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
389 },
390 {
391 .str = "ether_pkts128to255octets",
392 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
393 },
394 {
395 .str = "ether_pkts256to511octets",
396 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
397 },
398 {
399 .str = "ether_pkts512to1023octets",
400 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
401 },
402 {
403 .str = "ether_pkts1024to1518octets",
404 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
405 },
406 {
407 .str = "ether_pkts1519to2047octets",
408 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
409 },
410 {
411 .str = "ether_pkts2048to4095octets",
412 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
413 },
414 {
415 .str = "ether_pkts4096to8191octets",
416 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
417 },
418 {
419 .str = "ether_pkts8192to10239octets",
420 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
421 },
422 };
423
424 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
425 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
426
427 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_3635_stats[] = {
428 {
429 .str = "dot3stats_fcs_errors",
430 .getter = mlxsw_reg_ppcnt_dot3stats_fcs_errors_get,
431 },
432 {
433 .str = "dot3stats_symbol_errors",
434 .getter = mlxsw_reg_ppcnt_dot3stats_symbol_errors_get,
435 },
436 {
437 .str = "dot3control_in_unknown_opcodes",
438 .getter = mlxsw_reg_ppcnt_dot3control_in_unknown_opcodes_get,
439 },
440 {
441 .str = "dot3in_pause_frames",
442 .getter = mlxsw_reg_ppcnt_dot3in_pause_frames_get,
443 },
444 };
445
446 #define MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN \
447 ARRAY_SIZE(mlxsw_sp_port_hw_rfc_3635_stats)
448
449 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_ext_stats[] = {
450 {
451 .str = "ecn_marked",
452 .getter = mlxsw_reg_ppcnt_ecn_marked_get,
453 },
454 };
455
456 #define MLXSW_SP_PORT_HW_EXT_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_ext_stats)
457
458 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_discard_stats[] = {
459 {
460 .str = "discard_ingress_general",
461 .getter = mlxsw_reg_ppcnt_ingress_general_get,
462 },
463 {
464 .str = "discard_ingress_policy_engine",
465 .getter = mlxsw_reg_ppcnt_ingress_policy_engine_get,
466 },
467 {
468 .str = "discard_ingress_vlan_membership",
469 .getter = mlxsw_reg_ppcnt_ingress_vlan_membership_get,
470 },
471 {
472 .str = "discard_ingress_tag_frame_type",
473 .getter = mlxsw_reg_ppcnt_ingress_tag_frame_type_get,
474 },
475 {
476 .str = "discard_egress_vlan_membership",
477 .getter = mlxsw_reg_ppcnt_egress_vlan_membership_get,
478 },
479 {
480 .str = "discard_loopback_filter",
481 .getter = mlxsw_reg_ppcnt_loopback_filter_get,
482 },
483 {
484 .str = "discard_egress_general",
485 .getter = mlxsw_reg_ppcnt_egress_general_get,
486 },
487 {
488 .str = "discard_egress_hoq",
489 .getter = mlxsw_reg_ppcnt_egress_hoq_get,
490 },
491 {
492 .str = "discard_egress_policy_engine",
493 .getter = mlxsw_reg_ppcnt_egress_policy_engine_get,
494 },
495 {
496 .str = "discard_ingress_tx_link_down",
497 .getter = mlxsw_reg_ppcnt_ingress_tx_link_down_get,
498 },
499 {
500 .str = "discard_egress_stp_filter",
501 .getter = mlxsw_reg_ppcnt_egress_stp_filter_get,
502 },
503 {
504 .str = "discard_egress_sll",
505 .getter = mlxsw_reg_ppcnt_egress_sll_get,
506 },
507 };
508
509 #define MLXSW_SP_PORT_HW_DISCARD_STATS_LEN \
510 ARRAY_SIZE(mlxsw_sp_port_hw_discard_stats)
511
512 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
513 {
514 .str = "rx_octets_prio",
515 .getter = mlxsw_reg_ppcnt_rx_octets_get,
516 },
517 {
518 .str = "rx_frames_prio",
519 .getter = mlxsw_reg_ppcnt_rx_frames_get,
520 },
521 {
522 .str = "tx_octets_prio",
523 .getter = mlxsw_reg_ppcnt_tx_octets_get,
524 },
525 {
526 .str = "tx_frames_prio",
527 .getter = mlxsw_reg_ppcnt_tx_frames_get,
528 },
529 {
530 .str = "rx_pause_prio",
531 .getter = mlxsw_reg_ppcnt_rx_pause_get,
532 },
533 {
534 .str = "rx_pause_duration_prio",
535 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
536 },
537 {
538 .str = "tx_pause_prio",
539 .getter = mlxsw_reg_ppcnt_tx_pause_get,
540 },
541 {
542 .str = "tx_pause_duration_prio",
543 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
544 },
545 {
546 .str = "rx_discards_pg",
547 .getter = mlxsw_reg_ppcnt_rx_discards_get,
548 },
549 };
550
551 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
552
553 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
554 {
555 .str = "tc_transmit_queue_tc",
556 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
557 .cells_bytes = true,
558 },
559 {
560 .str = "tc_no_buffer_discard_uc_tc",
561 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
562 },
563 };
564
565 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
566
567 struct mlxsw_sp_port_stats {
568 char str[ETH_GSTRING_LEN];
569 u64 (*getter)(struct mlxsw_sp_port *mlxsw_sp_port);
570 };
571
572 static u64
mlxsw_sp_port_get_transceiver_overheat_stats(struct mlxsw_sp_port * mlxsw_sp_port)573 mlxsw_sp_port_get_transceiver_overheat_stats(struct mlxsw_sp_port *mlxsw_sp_port)
574 {
575 struct mlxsw_core *mlxsw_core = mlxsw_sp_port->mlxsw_sp->core;
576 u8 slot_index = mlxsw_sp_port->mapping.slot_index;
577 u8 module = mlxsw_sp_port->mapping.module;
578 u64 stats;
579 int err;
580
581 err = mlxsw_env_module_overheat_counter_get(mlxsw_core, slot_index,
582 module, &stats);
583 if (err)
584 return mlxsw_sp_port->module_overheat_initial_val;
585
586 return stats - mlxsw_sp_port->module_overheat_initial_val;
587 }
588
589 static struct mlxsw_sp_port_stats mlxsw_sp_port_transceiver_stats[] = {
590 {
591 .str = "transceiver_overheat",
592 .getter = mlxsw_sp_port_get_transceiver_overheat_stats,
593 },
594 };
595
596 #define MLXSW_SP_PORT_HW_TRANSCEIVER_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_transceiver_stats)
597
598 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
599 MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN + \
600 MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
601 MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN + \
602 MLXSW_SP_PORT_HW_EXT_STATS_LEN + \
603 MLXSW_SP_PORT_HW_DISCARD_STATS_LEN + \
604 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
605 IEEE_8021QAZ_MAX_TCS) + \
606 (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
607 TC_MAX_QUEUE) + \
608 MLXSW_SP_PORT_HW_TRANSCEIVER_STATS_LEN)
609
mlxsw_sp_port_get_prio_strings(u8 ** p,int prio)610 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
611 {
612 int i;
613
614 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
615 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
616 mlxsw_sp_port_hw_prio_stats[i].str, prio);
617 *p += ETH_GSTRING_LEN;
618 }
619 }
620
mlxsw_sp_port_get_tc_strings(u8 ** p,int tc)621 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
622 {
623 int i;
624
625 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
626 snprintf(*p, ETH_GSTRING_LEN, "%.28s_%d",
627 mlxsw_sp_port_hw_tc_stats[i].str, tc);
628 *p += ETH_GSTRING_LEN;
629 }
630 }
631
mlxsw_sp_port_get_strings(struct net_device * dev,u32 stringset,u8 * data)632 static void mlxsw_sp_port_get_strings(struct net_device *dev,
633 u32 stringset, u8 *data)
634 {
635 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
636 u8 *p = data;
637 int i;
638
639 switch (stringset) {
640 case ETH_SS_STATS:
641 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
642 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
643 ETH_GSTRING_LEN);
644 p += ETH_GSTRING_LEN;
645 }
646
647 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; i++) {
648 memcpy(p, mlxsw_sp_port_hw_rfc_2863_stats[i].str,
649 ETH_GSTRING_LEN);
650 p += ETH_GSTRING_LEN;
651 }
652
653 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
654 memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
655 ETH_GSTRING_LEN);
656 p += ETH_GSTRING_LEN;
657 }
658
659 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; i++) {
660 memcpy(p, mlxsw_sp_port_hw_rfc_3635_stats[i].str,
661 ETH_GSTRING_LEN);
662 p += ETH_GSTRING_LEN;
663 }
664
665 for (i = 0; i < MLXSW_SP_PORT_HW_EXT_STATS_LEN; i++) {
666 memcpy(p, mlxsw_sp_port_hw_ext_stats[i].str,
667 ETH_GSTRING_LEN);
668 p += ETH_GSTRING_LEN;
669 }
670
671 for (i = 0; i < MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; i++) {
672 memcpy(p, mlxsw_sp_port_hw_discard_stats[i].str,
673 ETH_GSTRING_LEN);
674 p += ETH_GSTRING_LEN;
675 }
676
677 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
678 mlxsw_sp_port_get_prio_strings(&p, i);
679
680 for (i = 0; i < TC_MAX_QUEUE; i++)
681 mlxsw_sp_port_get_tc_strings(&p, i);
682
683 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_strings(&p);
684
685 for (i = 0; i < MLXSW_SP_PORT_HW_TRANSCEIVER_STATS_LEN; i++) {
686 memcpy(p, mlxsw_sp_port_transceiver_stats[i].str,
687 ETH_GSTRING_LEN);
688 p += ETH_GSTRING_LEN;
689 }
690 break;
691 }
692 }
693
mlxsw_sp_port_set_phys_id(struct net_device * dev,enum ethtool_phys_id_state state)694 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
695 enum ethtool_phys_id_state state)
696 {
697 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
698 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
699 char mlcr_pl[MLXSW_REG_MLCR_LEN];
700 bool active;
701
702 switch (state) {
703 case ETHTOOL_ID_ACTIVE:
704 active = true;
705 break;
706 case ETHTOOL_ID_INACTIVE:
707 active = false;
708 break;
709 default:
710 return -EOPNOTSUPP;
711 }
712
713 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
714 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
715 }
716
717 static int
mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats ** p_hw_stats,int * p_len,enum mlxsw_reg_ppcnt_grp grp)718 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
719 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
720 {
721 switch (grp) {
722 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
723 *p_hw_stats = mlxsw_sp_port_hw_stats;
724 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
725 break;
726 case MLXSW_REG_PPCNT_RFC_2863_CNT:
727 *p_hw_stats = mlxsw_sp_port_hw_rfc_2863_stats;
728 *p_len = MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
729 break;
730 case MLXSW_REG_PPCNT_RFC_2819_CNT:
731 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
732 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
733 break;
734 case MLXSW_REG_PPCNT_RFC_3635_CNT:
735 *p_hw_stats = mlxsw_sp_port_hw_rfc_3635_stats;
736 *p_len = MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
737 break;
738 case MLXSW_REG_PPCNT_EXT_CNT:
739 *p_hw_stats = mlxsw_sp_port_hw_ext_stats;
740 *p_len = MLXSW_SP_PORT_HW_EXT_STATS_LEN;
741 break;
742 case MLXSW_REG_PPCNT_DISCARD_CNT:
743 *p_hw_stats = mlxsw_sp_port_hw_discard_stats;
744 *p_len = MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
745 break;
746 case MLXSW_REG_PPCNT_PRIO_CNT:
747 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
748 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
749 break;
750 case MLXSW_REG_PPCNT_TC_CNT:
751 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
752 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
753 break;
754 default:
755 WARN_ON(1);
756 return -EOPNOTSUPP;
757 }
758 return 0;
759 }
760
__mlxsw_sp_port_get_stats(struct net_device * dev,enum mlxsw_reg_ppcnt_grp grp,int prio,u64 * data,int data_index)761 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
762 enum mlxsw_reg_ppcnt_grp grp, int prio,
763 u64 *data, int data_index)
764 {
765 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
766 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
767 struct mlxsw_sp_port_hw_stats *hw_stats;
768 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
769 int i, len;
770 int err;
771
772 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
773 if (err)
774 return;
775 err = mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
776 if (err)
777 return;
778 for (i = 0; i < len; i++) {
779 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
780 if (!hw_stats[i].cells_bytes)
781 continue;
782 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
783 data[data_index + i]);
784 }
785 }
786
__mlxsw_sp_port_get_env_stats(struct net_device * dev,u64 * data,int data_index,struct mlxsw_sp_port_stats * port_stats,int len)787 static void __mlxsw_sp_port_get_env_stats(struct net_device *dev, u64 *data, int data_index,
788 struct mlxsw_sp_port_stats *port_stats,
789 int len)
790 {
791 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
792 int i;
793
794 for (i = 0; i < len; i++)
795 data[data_index + i] = port_stats[i].getter(mlxsw_sp_port);
796 }
797
mlxsw_sp_port_get_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)798 static void mlxsw_sp_port_get_stats(struct net_device *dev,
799 struct ethtool_stats *stats, u64 *data)
800 {
801 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
802 int i, data_index = 0;
803
804 /* IEEE 802.3 Counters */
805 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
806 data, data_index);
807 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
808
809 /* RFC 2863 Counters */
810 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2863_CNT, 0,
811 data, data_index);
812 data_index += MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
813
814 /* RFC 2819 Counters */
815 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
816 data, data_index);
817 data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
818
819 /* RFC 3635 Counters */
820 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_3635_CNT, 0,
821 data, data_index);
822 data_index += MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
823
824 /* Extended Counters */
825 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
826 data, data_index);
827 data_index += MLXSW_SP_PORT_HW_EXT_STATS_LEN;
828
829 /* Discard Counters */
830 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_DISCARD_CNT, 0,
831 data, data_index);
832 data_index += MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
833
834 /* Per-Priority Counters */
835 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
836 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
837 data, data_index);
838 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
839 }
840
841 /* Per-TC Counters */
842 for (i = 0; i < TC_MAX_QUEUE; i++) {
843 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
844 data, data_index);
845 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
846 }
847
848 /* PTP counters */
849 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats(mlxsw_sp_port,
850 data, data_index);
851 data_index += mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
852
853 /* Transceiver counters */
854 __mlxsw_sp_port_get_env_stats(dev, data, data_index, mlxsw_sp_port_transceiver_stats,
855 MLXSW_SP_PORT_HW_TRANSCEIVER_STATS_LEN);
856 data_index += MLXSW_SP_PORT_HW_TRANSCEIVER_STATS_LEN;
857 }
858
mlxsw_sp_port_get_sset_count(struct net_device * dev,int sset)859 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
860 {
861 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
862
863 switch (sset) {
864 case ETH_SS_STATS:
865 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN +
866 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
867 default:
868 return -EOPNOTSUPP;
869 }
870 }
871
872 static void
mlxsw_sp_port_get_link_supported(struct mlxsw_sp * mlxsw_sp,u32 eth_proto_cap,struct ethtool_link_ksettings * cmd)873 mlxsw_sp_port_get_link_supported(struct mlxsw_sp *mlxsw_sp, u32 eth_proto_cap,
874 struct ethtool_link_ksettings *cmd)
875 {
876 const struct mlxsw_sp_port_type_speed_ops *ops;
877
878 ops = mlxsw_sp->port_type_speed_ops;
879
880 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
881 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
882 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
883
884 ops->from_ptys_supported_port(mlxsw_sp, eth_proto_cap, cmd);
885 ops->from_ptys_link(mlxsw_sp, eth_proto_cap,
886 cmd->link_modes.supported);
887 }
888
889 static void
mlxsw_sp_port_get_link_advertise(struct mlxsw_sp * mlxsw_sp,u32 eth_proto_admin,bool autoneg,struct ethtool_link_ksettings * cmd)890 mlxsw_sp_port_get_link_advertise(struct mlxsw_sp *mlxsw_sp,
891 u32 eth_proto_admin, bool autoneg,
892 struct ethtool_link_ksettings *cmd)
893 {
894 const struct mlxsw_sp_port_type_speed_ops *ops;
895
896 ops = mlxsw_sp->port_type_speed_ops;
897
898 if (!autoneg)
899 return;
900
901 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
902 ops->from_ptys_link(mlxsw_sp, eth_proto_admin,
903 cmd->link_modes.advertising);
904 }
905
906 static u8
mlxsw_sp_port_connector_port(enum mlxsw_reg_ptys_connector_type connector_type)907 mlxsw_sp_port_connector_port(enum mlxsw_reg_ptys_connector_type connector_type)
908 {
909 switch (connector_type) {
910 case MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR:
911 return PORT_OTHER;
912 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE:
913 return PORT_NONE;
914 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP:
915 return PORT_TP;
916 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI:
917 return PORT_AUI;
918 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC:
919 return PORT_BNC;
920 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII:
921 return PORT_MII;
922 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE:
923 return PORT_FIBRE;
924 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA:
925 return PORT_DA;
926 case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER:
927 return PORT_OTHER;
928 default:
929 WARN_ON_ONCE(1);
930 return PORT_OTHER;
931 }
932 }
933
mlxsw_sp_port_ptys_query(struct mlxsw_sp_port * mlxsw_sp_port,u32 * p_eth_proto_cap,u32 * p_eth_proto_admin,u32 * p_eth_proto_oper,u8 * p_connector_type)934 static int mlxsw_sp_port_ptys_query(struct mlxsw_sp_port *mlxsw_sp_port,
935 u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
936 u32 *p_eth_proto_oper, u8 *p_connector_type)
937 {
938 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
939 const struct mlxsw_sp_port_type_speed_ops *ops;
940 char ptys_pl[MLXSW_REG_PTYS_LEN];
941 int err;
942
943 ops = mlxsw_sp->port_type_speed_ops;
944
945 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port, 0, false);
946 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
947 if (err)
948 return err;
949
950 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, p_eth_proto_cap, p_eth_proto_admin,
951 p_eth_proto_oper);
952 if (p_connector_type)
953 *p_connector_type = mlxsw_reg_ptys_connector_type_get(ptys_pl);
954 return 0;
955 }
956
mlxsw_sp_port_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)957 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
958 struct ethtool_link_ksettings *cmd)
959 {
960 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
961 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
962 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
963 const struct mlxsw_sp_port_type_speed_ops *ops;
964 u8 connector_type;
965 bool autoneg;
966 int err;
967
968 err = mlxsw_sp_port_ptys_query(mlxsw_sp_port, ð_proto_cap, ð_proto_admin,
969 ð_proto_oper, &connector_type);
970 if (err)
971 return err;
972
973 ops = mlxsw_sp->port_type_speed_ops;
974 autoneg = mlxsw_sp_port->link.autoneg;
975
976 mlxsw_sp_port_get_link_supported(mlxsw_sp, eth_proto_cap, cmd);
977
978 mlxsw_sp_port_get_link_advertise(mlxsw_sp, eth_proto_admin, autoneg, cmd);
979
980 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
981 cmd->base.port = mlxsw_sp_port_connector_port(connector_type);
982 ops->from_ptys_link_mode(mlxsw_sp, netif_carrier_ok(dev),
983 eth_proto_oper, cmd);
984
985 return 0;
986 }
987
988 static int
mlxsw_sp_port_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)989 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
990 const struct ethtool_link_ksettings *cmd)
991 {
992 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
993 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
994 const struct mlxsw_sp_port_type_speed_ops *ops;
995 char ptys_pl[MLXSW_REG_PTYS_LEN];
996 u32 eth_proto_cap, eth_proto_new;
997 bool autoneg;
998 int err;
999
1000 ops = mlxsw_sp->port_type_speed_ops;
1001
1002 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
1003 0, false);
1004 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1005 if (err)
1006 return err;
1007 ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, ð_proto_cap, NULL, NULL);
1008
1009 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
1010 eth_proto_new = autoneg ?
1011 ops->to_ptys_advert_link(mlxsw_sp, cmd) :
1012 ops->to_ptys_speed_lanes(mlxsw_sp, mlxsw_sp_port->mapping.width,
1013 cmd);
1014
1015 eth_proto_new = eth_proto_new & eth_proto_cap;
1016 if (!eth_proto_new) {
1017 netdev_err(dev, "No supported speed or lanes requested\n");
1018 return -EINVAL;
1019 }
1020
1021 ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
1022 eth_proto_new, autoneg);
1023 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1024 if (err)
1025 return err;
1026
1027 mlxsw_sp_port->link.autoneg = autoneg;
1028
1029 if (!netif_running(dev))
1030 return 0;
1031
1032 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1033 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1034
1035 return 0;
1036 }
1037
mlxsw_sp_get_module_info(struct net_device * netdev,struct ethtool_modinfo * modinfo)1038 static int mlxsw_sp_get_module_info(struct net_device *netdev,
1039 struct ethtool_modinfo *modinfo)
1040 {
1041 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
1042 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1043
1044 return mlxsw_env_get_module_info(netdev, mlxsw_sp->core,
1045 mlxsw_sp_port->mapping.slot_index,
1046 mlxsw_sp_port->mapping.module,
1047 modinfo);
1048 }
1049
mlxsw_sp_get_module_eeprom(struct net_device * netdev,struct ethtool_eeprom * ee,u8 * data)1050 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
1051 struct ethtool_eeprom *ee, u8 *data)
1052 {
1053 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
1054 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1055 u8 slot_index = mlxsw_sp_port->mapping.slot_index;
1056 u8 module = mlxsw_sp_port->mapping.module;
1057
1058 return mlxsw_env_get_module_eeprom(netdev, mlxsw_sp->core, slot_index,
1059 module, ee, data);
1060 }
1061
1062 static int
mlxsw_sp_get_module_eeprom_by_page(struct net_device * dev,const struct ethtool_module_eeprom * page,struct netlink_ext_ack * extack)1063 mlxsw_sp_get_module_eeprom_by_page(struct net_device *dev,
1064 const struct ethtool_module_eeprom *page,
1065 struct netlink_ext_ack *extack)
1066 {
1067 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1068 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1069 u8 slot_index = mlxsw_sp_port->mapping.slot_index;
1070 u8 module = mlxsw_sp_port->mapping.module;
1071
1072 return mlxsw_env_get_module_eeprom_by_page(mlxsw_sp->core, slot_index,
1073 module, page, extack);
1074 }
1075
1076 static int
mlxsw_sp_set_module_eeprom_by_page(struct net_device * dev,const struct ethtool_module_eeprom * page,struct netlink_ext_ack * extack)1077 mlxsw_sp_set_module_eeprom_by_page(struct net_device *dev,
1078 const struct ethtool_module_eeprom *page,
1079 struct netlink_ext_ack *extack)
1080 {
1081 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1082 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1083 u8 slot_index = mlxsw_sp_port->mapping.slot_index;
1084 u8 module = mlxsw_sp_port->mapping.module;
1085
1086 return mlxsw_env_set_module_eeprom_by_page(mlxsw_sp->core, slot_index,
1087 module, page, extack);
1088 }
1089
1090 static int
mlxsw_sp_get_ts_info(struct net_device * netdev,struct kernel_ethtool_ts_info * info)1091 mlxsw_sp_get_ts_info(struct net_device *netdev, struct kernel_ethtool_ts_info *info)
1092 {
1093 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
1094 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1095
1096 return mlxsw_sp->ptp_ops->get_ts_info(mlxsw_sp, info);
1097 }
1098
1099 static void
mlxsw_sp_get_eth_phy_stats(struct net_device * dev,struct ethtool_eth_phy_stats * phy_stats)1100 mlxsw_sp_get_eth_phy_stats(struct net_device *dev,
1101 struct ethtool_eth_phy_stats *phy_stats)
1102 {
1103 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1104
1105 if (mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1106 0, ppcnt_pl))
1107 return;
1108
1109 phy_stats->SymbolErrorDuringCarrier =
1110 mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get(ppcnt_pl);
1111 }
1112
1113 static void
mlxsw_sp_get_eth_mac_stats(struct net_device * dev,struct ethtool_eth_mac_stats * mac_stats)1114 mlxsw_sp_get_eth_mac_stats(struct net_device *dev,
1115 struct ethtool_eth_mac_stats *mac_stats)
1116 {
1117 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1118
1119 if (mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1120 0, ppcnt_pl))
1121 return;
1122
1123 mac_stats->FramesTransmittedOK =
1124 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1125 mac_stats->FramesReceivedOK =
1126 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1127 mac_stats->FrameCheckSequenceErrors =
1128 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1129 mac_stats->AlignmentErrors =
1130 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1131 mac_stats->OctetsTransmittedOK =
1132 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1133 mac_stats->OctetsReceivedOK =
1134 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1135 mac_stats->MulticastFramesXmittedOK =
1136 mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get(ppcnt_pl);
1137 mac_stats->BroadcastFramesXmittedOK =
1138 mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get(ppcnt_pl);
1139 mac_stats->MulticastFramesReceivedOK =
1140 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1141 mac_stats->BroadcastFramesReceivedOK =
1142 mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get(ppcnt_pl);
1143 mac_stats->InRangeLengthErrors =
1144 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl);
1145 mac_stats->OutOfRangeLengthField =
1146 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl);
1147 mac_stats->FrameTooLongErrors =
1148 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl);
1149 }
1150
1151 static void
mlxsw_sp_get_eth_ctrl_stats(struct net_device * dev,struct ethtool_eth_ctrl_stats * ctrl_stats)1152 mlxsw_sp_get_eth_ctrl_stats(struct net_device *dev,
1153 struct ethtool_eth_ctrl_stats *ctrl_stats)
1154 {
1155 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1156
1157 if (mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1158 0, ppcnt_pl))
1159 return;
1160
1161 ctrl_stats->MACControlFramesTransmitted =
1162 mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get(ppcnt_pl);
1163 ctrl_stats->MACControlFramesReceived =
1164 mlxsw_reg_ppcnt_a_mac_control_frames_received_get(ppcnt_pl);
1165 ctrl_stats->UnsupportedOpcodesReceived =
1166 mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get(ppcnt_pl);
1167 }
1168
1169 static const struct ethtool_rmon_hist_range mlxsw_rmon_ranges[] = {
1170 { 0, 64 },
1171 { 65, 127 },
1172 { 128, 255 },
1173 { 256, 511 },
1174 { 512, 1023 },
1175 { 1024, 1518 },
1176 { 1519, 2047 },
1177 { 2048, 4095 },
1178 { 4096, 8191 },
1179 { 8192, 10239 },
1180 {}
1181 };
1182
1183 static void
mlxsw_sp_get_rmon_stats(struct net_device * dev,struct ethtool_rmon_stats * rmon,const struct ethtool_rmon_hist_range ** ranges)1184 mlxsw_sp_get_rmon_stats(struct net_device *dev,
1185 struct ethtool_rmon_stats *rmon,
1186 const struct ethtool_rmon_hist_range **ranges)
1187 {
1188 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1189
1190 if (mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_RFC_2819_CNT,
1191 0, ppcnt_pl))
1192 return;
1193
1194 rmon->undersize_pkts =
1195 mlxsw_reg_ppcnt_ether_stats_undersize_pkts_get(ppcnt_pl);
1196 rmon->oversize_pkts =
1197 mlxsw_reg_ppcnt_ether_stats_oversize_pkts_get(ppcnt_pl);
1198 rmon->fragments =
1199 mlxsw_reg_ppcnt_ether_stats_fragments_get(ppcnt_pl);
1200
1201 rmon->hist[0] = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get(ppcnt_pl);
1202 rmon->hist[1] =
1203 mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get(ppcnt_pl);
1204 rmon->hist[2] =
1205 mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get(ppcnt_pl);
1206 rmon->hist[3] =
1207 mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get(ppcnt_pl);
1208 rmon->hist[4] =
1209 mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get(ppcnt_pl);
1210 rmon->hist[5] =
1211 mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get(ppcnt_pl);
1212 rmon->hist[6] =
1213 mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get(ppcnt_pl);
1214 rmon->hist[7] =
1215 mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get(ppcnt_pl);
1216 rmon->hist[8] =
1217 mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get(ppcnt_pl);
1218 rmon->hist[9] =
1219 mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get(ppcnt_pl);
1220
1221 *ranges = mlxsw_rmon_ranges;
1222 }
1223
mlxsw_sp_reset(struct net_device * dev,u32 * flags)1224 static int mlxsw_sp_reset(struct net_device *dev, u32 *flags)
1225 {
1226 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1227 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1228 u8 slot_index = mlxsw_sp_port->mapping.slot_index;
1229 u8 module = mlxsw_sp_port->mapping.module;
1230
1231 return mlxsw_env_reset_module(dev, mlxsw_sp->core, slot_index,
1232 module, flags);
1233 }
1234
1235 static int
mlxsw_sp_get_module_power_mode(struct net_device * dev,struct ethtool_module_power_mode_params * params,struct netlink_ext_ack * extack)1236 mlxsw_sp_get_module_power_mode(struct net_device *dev,
1237 struct ethtool_module_power_mode_params *params,
1238 struct netlink_ext_ack *extack)
1239 {
1240 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1241 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1242 u8 slot_index = mlxsw_sp_port->mapping.slot_index;
1243 u8 module = mlxsw_sp_port->mapping.module;
1244
1245 return mlxsw_env_get_module_power_mode(mlxsw_sp->core, slot_index,
1246 module, params, extack);
1247 }
1248
1249 static int
mlxsw_sp_set_module_power_mode(struct net_device * dev,const struct ethtool_module_power_mode_params * params,struct netlink_ext_ack * extack)1250 mlxsw_sp_set_module_power_mode(struct net_device *dev,
1251 const struct ethtool_module_power_mode_params *params,
1252 struct netlink_ext_ack *extack)
1253 {
1254 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1255 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1256 u8 slot_index = mlxsw_sp_port->mapping.slot_index;
1257 u8 module = mlxsw_sp_port->mapping.module;
1258
1259 return mlxsw_env_set_module_power_mode(mlxsw_sp->core, slot_index,
1260 module, params->policy, extack);
1261 }
1262
1263 const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1264 .cap_link_lanes_supported = true,
1265 .op_needs_rtnl = ETHTOOL_OP_NEEDS_RTNL_SPAUSEPARAM |
1266 ETHTOOL_OP_NEEDS_RTNL_GLINK,
1267 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1268 .get_link = ethtool_op_get_link,
1269 .get_link_ext_state = mlxsw_sp_port_get_link_ext_state,
1270 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
1271 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
1272 .get_strings = mlxsw_sp_port_get_strings,
1273 .set_phys_id = mlxsw_sp_port_set_phys_id,
1274 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1275 .get_sset_count = mlxsw_sp_port_get_sset_count,
1276 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
1277 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
1278 .get_module_info = mlxsw_sp_get_module_info,
1279 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
1280 .get_module_eeprom_by_page = mlxsw_sp_get_module_eeprom_by_page,
1281 .set_module_eeprom_by_page = mlxsw_sp_set_module_eeprom_by_page,
1282 .get_ts_info = mlxsw_sp_get_ts_info,
1283 .get_eth_phy_stats = mlxsw_sp_get_eth_phy_stats,
1284 .get_eth_mac_stats = mlxsw_sp_get_eth_mac_stats,
1285 .get_eth_ctrl_stats = mlxsw_sp_get_eth_ctrl_stats,
1286 .get_rmon_stats = mlxsw_sp_get_rmon_stats,
1287 .reset = mlxsw_sp_reset,
1288 .get_module_power_mode = mlxsw_sp_get_module_power_mode,
1289 .set_module_power_mode = mlxsw_sp_set_module_power_mode,
1290 };
1291
1292 struct mlxsw_sp1_port_link_mode {
1293 enum ethtool_link_mode_bit_indices mask_ethtool;
1294 u32 mask;
1295 u32 speed;
1296 };
1297
1298 static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = {
1299 {
1300 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1301 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1302 .speed = SPEED_100,
1303 },
1304 {
1305 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1306 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1307 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1308 .speed = SPEED_1000,
1309 },
1310 {
1311 .mask = MLXSW_REG_PTYS_ETH_SPEED_1000BASE_T,
1312 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1313 .speed = SPEED_1000,
1314 },
1315 {
1316 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1317 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1318 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
1319 .speed = SPEED_10000,
1320 },
1321 {
1322 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1323 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1324 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1325 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1326 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1327 .speed = SPEED_10000,
1328 },
1329 {
1330 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1331 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1332 .speed = SPEED_40000,
1333 },
1334 {
1335 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1336 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1337 .speed = SPEED_40000,
1338 },
1339 {
1340 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1341 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1342 .speed = SPEED_40000,
1343 },
1344 {
1345 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1346 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1347 .speed = SPEED_40000,
1348 },
1349 {
1350 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
1351 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1352 .speed = SPEED_25000,
1353 },
1354 {
1355 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
1356 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1357 .speed = SPEED_25000,
1358 },
1359 {
1360 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1361 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1362 .speed = SPEED_25000,
1363 },
1364 {
1365 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
1366 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1367 .speed = SPEED_50000,
1368 },
1369 {
1370 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1371 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1372 .speed = SPEED_50000,
1373 },
1374 {
1375 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
1376 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1377 .speed = SPEED_50000,
1378 },
1379 {
1380 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
1381 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
1382 .speed = SPEED_100000,
1383 },
1384 {
1385 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
1386 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1387 .speed = SPEED_100000,
1388 },
1389 {
1390 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
1391 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
1392 .speed = SPEED_100000,
1393 },
1394 {
1395 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1396 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
1397 .speed = SPEED_100000,
1398 },
1399 };
1400
1401 #define MLXSW_SP1_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp1_port_link_mode)
1402
1403 static void
mlxsw_sp1_from_ptys_supported_port(struct mlxsw_sp * mlxsw_sp,u32 ptys_eth_proto,struct ethtool_link_ksettings * cmd)1404 mlxsw_sp1_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
1405 u32 ptys_eth_proto,
1406 struct ethtool_link_ksettings *cmd)
1407 {
1408 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1409 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1410 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1411 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1412 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1413 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1414 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
1415
1416 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1417 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1418 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1419 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1420 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1421 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
1422 }
1423
1424 static void
mlxsw_sp1_from_ptys_link(struct mlxsw_sp * mlxsw_sp,u32 ptys_eth_proto,unsigned long * mode)1425 mlxsw_sp1_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
1426 unsigned long *mode)
1427 {
1428 int i;
1429
1430 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1431 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
1432 __set_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
1433 mode);
1434 }
1435 }
1436
1437 static u32
mlxsw_sp1_from_ptys_speed(struct mlxsw_sp * mlxsw_sp,u32 ptys_eth_proto)1438 mlxsw_sp1_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
1439 {
1440 int i;
1441
1442 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1443 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
1444 return mlxsw_sp1_port_link_mode[i].speed;
1445 }
1446
1447 return SPEED_UNKNOWN;
1448 }
1449
1450 static void
mlxsw_sp1_from_ptys_link_mode(struct mlxsw_sp * mlxsw_sp,bool carrier_ok,u32 ptys_eth_proto,struct ethtool_link_ksettings * cmd)1451 mlxsw_sp1_from_ptys_link_mode(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
1452 u32 ptys_eth_proto,
1453 struct ethtool_link_ksettings *cmd)
1454 {
1455 struct mlxsw_sp1_port_link_mode link;
1456 int i;
1457
1458 cmd->base.speed = SPEED_UNKNOWN;
1459 cmd->base.duplex = DUPLEX_UNKNOWN;
1460 cmd->lanes = 0;
1461
1462 if (!carrier_ok)
1463 return;
1464
1465 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1466 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask) {
1467 link = mlxsw_sp1_port_link_mode[i];
1468 ethtool_params_from_link_mode(cmd,
1469 link.mask_ethtool);
1470 }
1471 }
1472 }
1473
mlxsw_sp1_ptys_max_speed(struct mlxsw_sp_port * mlxsw_sp_port,u32 * p_max_speed)1474 static int mlxsw_sp1_ptys_max_speed(struct mlxsw_sp_port *mlxsw_sp_port, u32 *p_max_speed)
1475 {
1476 u32 eth_proto_cap;
1477 u32 max_speed = 0;
1478 int err;
1479 int i;
1480
1481 err = mlxsw_sp_port_ptys_query(mlxsw_sp_port, ð_proto_cap, NULL, NULL, NULL);
1482 if (err)
1483 return err;
1484
1485 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1486 if ((eth_proto_cap & mlxsw_sp1_port_link_mode[i].mask) &&
1487 mlxsw_sp1_port_link_mode[i].speed > max_speed)
1488 max_speed = mlxsw_sp1_port_link_mode[i].speed;
1489 }
1490
1491 *p_max_speed = max_speed;
1492 return 0;
1493 }
1494
1495 static u32
mlxsw_sp1_to_ptys_advert_link(struct mlxsw_sp * mlxsw_sp,const struct ethtool_link_ksettings * cmd)1496 mlxsw_sp1_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp,
1497 const struct ethtool_link_ksettings *cmd)
1498 {
1499 u32 ptys_proto = 0;
1500 int i;
1501
1502 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1503 if (test_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
1504 cmd->link_modes.advertising))
1505 ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
1506 }
1507 return ptys_proto;
1508 }
1509
mlxsw_sp1_to_ptys_speed_lanes(struct mlxsw_sp * mlxsw_sp,u8 width,const struct ethtool_link_ksettings * cmd)1510 static u32 mlxsw_sp1_to_ptys_speed_lanes(struct mlxsw_sp *mlxsw_sp, u8 width,
1511 const struct ethtool_link_ksettings *cmd)
1512 {
1513 u32 ptys_proto = 0;
1514 int i;
1515
1516 if (cmd->lanes > width)
1517 return ptys_proto;
1518
1519 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1520 if (cmd->base.speed == mlxsw_sp1_port_link_mode[i].speed)
1521 ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
1522 }
1523 return ptys_proto;
1524 }
1525
1526 static void
mlxsw_sp1_reg_ptys_eth_pack(struct mlxsw_sp * mlxsw_sp,char * payload,u16 local_port,u32 proto_admin,bool autoneg)1527 mlxsw_sp1_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
1528 u16 local_port, u32 proto_admin, bool autoneg)
1529 {
1530 mlxsw_reg_ptys_eth_pack(payload, local_port, proto_admin, autoneg);
1531 }
1532
1533 static void
mlxsw_sp1_reg_ptys_eth_unpack(struct mlxsw_sp * mlxsw_sp,char * payload,u32 * p_eth_proto_cap,u32 * p_eth_proto_admin,u32 * p_eth_proto_oper)1534 mlxsw_sp1_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
1535 u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
1536 u32 *p_eth_proto_oper)
1537 {
1538 mlxsw_reg_ptys_eth_unpack(payload, p_eth_proto_cap, p_eth_proto_admin,
1539 p_eth_proto_oper);
1540 }
1541
mlxsw_sp1_ptys_proto_cap_masked_get(u32 eth_proto_cap)1542 static u32 mlxsw_sp1_ptys_proto_cap_masked_get(u32 eth_proto_cap)
1543 {
1544 u32 ptys_proto_cap_masked = 0;
1545 int i;
1546
1547 for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
1548 if (mlxsw_sp1_port_link_mode[i].mask & eth_proto_cap)
1549 ptys_proto_cap_masked |=
1550 mlxsw_sp1_port_link_mode[i].mask;
1551 }
1552
1553 return ptys_proto_cap_masked;
1554 }
1555
1556 const struct mlxsw_sp_port_type_speed_ops mlxsw_sp1_port_type_speed_ops = {
1557 .from_ptys_supported_port = mlxsw_sp1_from_ptys_supported_port,
1558 .from_ptys_link = mlxsw_sp1_from_ptys_link,
1559 .from_ptys_speed = mlxsw_sp1_from_ptys_speed,
1560 .from_ptys_link_mode = mlxsw_sp1_from_ptys_link_mode,
1561 .ptys_max_speed = mlxsw_sp1_ptys_max_speed,
1562 .to_ptys_advert_link = mlxsw_sp1_to_ptys_advert_link,
1563 .to_ptys_speed_lanes = mlxsw_sp1_to_ptys_speed_lanes,
1564 .reg_ptys_eth_pack = mlxsw_sp1_reg_ptys_eth_pack,
1565 .reg_ptys_eth_unpack = mlxsw_sp1_reg_ptys_eth_unpack,
1566 .ptys_proto_cap_masked_get = mlxsw_sp1_ptys_proto_cap_masked_get,
1567 };
1568
1569 static const enum ethtool_link_mode_bit_indices
1570 mlxsw_sp2_mask_ethtool_sgmii_100m[] = {
1571 ETHTOOL_LINK_MODE_100baseT_Full_BIT,
1572 };
1573
1574 #define MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN \
1575 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_sgmii_100m)
1576
1577 static const enum ethtool_link_mode_bit_indices
1578 mlxsw_sp2_mask_ethtool_1000base_x_sgmii[] = {
1579 ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1580 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
1581 };
1582
1583 #define MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN \
1584 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_1000base_x_sgmii)
1585
1586 static const enum ethtool_link_mode_bit_indices
1587 mlxsw_sp2_mask_ethtool_5gbase_r[] = {
1588 ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
1589 };
1590
1591 #define MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN \
1592 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_5gbase_r)
1593
1594 static const enum ethtool_link_mode_bit_indices
1595 mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g[] = {
1596 ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
1597 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
1598 ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
1599 ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
1600 ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
1601 ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
1602 ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
1603 };
1604
1605 #define MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN \
1606 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g)
1607
1608 static const enum ethtool_link_mode_bit_indices
1609 mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g[] = {
1610 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
1611 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
1612 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
1613 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
1614 };
1615
1616 #define MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN \
1617 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g)
1618
1619 static const enum ethtool_link_mode_bit_indices
1620 mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr[] = {
1621 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
1622 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
1623 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1624 };
1625
1626 #define MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN \
1627 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr)
1628
1629 static const enum ethtool_link_mode_bit_indices
1630 mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2[] = {
1631 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
1632 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
1633 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1634 };
1635
1636 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN \
1637 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2)
1638
1639 static const enum ethtool_link_mode_bit_indices
1640 mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr[] = {
1641 ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
1642 ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
1643 ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
1644 ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
1645 ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
1646 };
1647
1648 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN \
1649 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr)
1650
1651 static const enum ethtool_link_mode_bit_indices
1652 mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4[] = {
1653 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
1654 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1655 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
1656 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
1657 };
1658
1659 #define MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN \
1660 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4)
1661
1662 static const enum ethtool_link_mode_bit_indices
1663 mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2[] = {
1664 ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
1665 ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
1666 ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
1667 ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
1668 ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
1669 };
1670
1671 #define MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN \
1672 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2)
1673
1674 static const enum ethtool_link_mode_bit_indices
1675 mlxsw_sp2_mask_ethtool_100gaui_1_100gbase_cr_kr[] = {
1676 ETHTOOL_LINK_MODE_100000baseKR_Full_BIT,
1677 ETHTOOL_LINK_MODE_100000baseSR_Full_BIT,
1678 ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT,
1679 ETHTOOL_LINK_MODE_100000baseCR_Full_BIT,
1680 ETHTOOL_LINK_MODE_100000baseDR_Full_BIT,
1681 };
1682
1683 #define MLXSW_SP2_MASK_ETHTOOL_100GAUI_1_100GBASE_CR_KR_LEN \
1684 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_100gaui_1_100gbase_cr_kr)
1685
1686 static const enum ethtool_link_mode_bit_indices
1687 mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = {
1688 ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
1689 ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
1690 ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
1691 ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
1692 ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
1693 };
1694
1695 #define MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN \
1696 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4)
1697
1698 static const enum ethtool_link_mode_bit_indices
1699 mlxsw_sp2_mask_ethtool_200gaui_2_200gbase_cr2_kr2[] = {
1700 ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT,
1701 ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT,
1702 ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT,
1703 ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT,
1704 ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT,
1705 };
1706
1707 #define MLXSW_SP2_MASK_ETHTOOL_200GAUI_2_200GBASE_CR2_KR2_LEN \
1708 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_2_200gbase_cr2_kr2)
1709
1710 static const enum ethtool_link_mode_bit_indices
1711 mlxsw_sp2_mask_ethtool_400gaui_8[] = {
1712 ETHTOOL_LINK_MODE_400000baseKR8_Full_BIT,
1713 ETHTOOL_LINK_MODE_400000baseSR8_Full_BIT,
1714 ETHTOOL_LINK_MODE_400000baseLR8_ER8_FR8_Full_BIT,
1715 ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT,
1716 ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT,
1717 };
1718
1719 #define MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN \
1720 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_400gaui_8)
1721
1722 static const enum ethtool_link_mode_bit_indices
1723 mlxsw_sp2_mask_ethtool_400gaui_4_400gbase_cr4_kr4[] = {
1724 ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT,
1725 ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT,
1726 ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT,
1727 ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT,
1728 ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT,
1729 };
1730
1731 #define MLXSW_SP2_MASK_ETHTOOL_400GAUI_4_400GBASE_CR4_KR4_LEN \
1732 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_400gaui_4_400gbase_cr4_kr4)
1733
1734 static const enum ethtool_link_mode_bit_indices
1735 mlxsw_sp2_mask_ethtool_800gaui_8[] = {
1736 ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT,
1737 ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT,
1738 ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT,
1739 ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT,
1740 ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT,
1741 ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT,
1742 };
1743
1744 #define MLXSW_SP2_MASK_ETHTOOL_800GAUI_8_LEN \
1745 ARRAY_SIZE(mlxsw_sp2_mask_ethtool_800gaui_8)
1746
1747 #define MLXSW_SP_PORT_MASK_WIDTH_1X BIT(0)
1748 #define MLXSW_SP_PORT_MASK_WIDTH_2X BIT(1)
1749 #define MLXSW_SP_PORT_MASK_WIDTH_4X BIT(2)
1750 #define MLXSW_SP_PORT_MASK_WIDTH_8X BIT(3)
1751
mlxsw_sp_port_mask_width_get(u8 width)1752 static u8 mlxsw_sp_port_mask_width_get(u8 width)
1753 {
1754 switch (width) {
1755 case 1:
1756 return MLXSW_SP_PORT_MASK_WIDTH_1X;
1757 case 2:
1758 return MLXSW_SP_PORT_MASK_WIDTH_2X;
1759 case 4:
1760 return MLXSW_SP_PORT_MASK_WIDTH_4X;
1761 case 8:
1762 return MLXSW_SP_PORT_MASK_WIDTH_8X;
1763 default:
1764 WARN_ON_ONCE(1);
1765 return 0;
1766 }
1767 }
1768
1769 struct mlxsw_sp2_port_link_mode {
1770 const enum ethtool_link_mode_bit_indices *mask_ethtool;
1771 int m_ethtool_len;
1772 u32 mask;
1773 u32 speed;
1774 u32 width;
1775 u8 mask_sup_width;
1776 };
1777
1778 static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
1779 {
1780 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M,
1781 .mask_ethtool = mlxsw_sp2_mask_ethtool_sgmii_100m,
1782 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN,
1783 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
1784 MLXSW_SP_PORT_MASK_WIDTH_2X |
1785 MLXSW_SP_PORT_MASK_WIDTH_4X |
1786 MLXSW_SP_PORT_MASK_WIDTH_8X,
1787 .speed = SPEED_100,
1788 .width = 1,
1789 },
1790 {
1791 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII,
1792 .mask_ethtool = mlxsw_sp2_mask_ethtool_1000base_x_sgmii,
1793 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN,
1794 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
1795 MLXSW_SP_PORT_MASK_WIDTH_2X |
1796 MLXSW_SP_PORT_MASK_WIDTH_4X |
1797 MLXSW_SP_PORT_MASK_WIDTH_8X,
1798 .speed = SPEED_1000,
1799 .width = 1,
1800 },
1801 {
1802 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R,
1803 .mask_ethtool = mlxsw_sp2_mask_ethtool_5gbase_r,
1804 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN,
1805 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
1806 MLXSW_SP_PORT_MASK_WIDTH_2X |
1807 MLXSW_SP_PORT_MASK_WIDTH_4X |
1808 MLXSW_SP_PORT_MASK_WIDTH_8X,
1809 .speed = SPEED_5000,
1810 .width = 1,
1811 },
1812 {
1813 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G,
1814 .mask_ethtool = mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g,
1815 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN,
1816 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
1817 MLXSW_SP_PORT_MASK_WIDTH_2X |
1818 MLXSW_SP_PORT_MASK_WIDTH_4X |
1819 MLXSW_SP_PORT_MASK_WIDTH_8X,
1820 .speed = SPEED_10000,
1821 .width = 1,
1822 },
1823 {
1824 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G,
1825 .mask_ethtool = mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g,
1826 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN,
1827 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_4X |
1828 MLXSW_SP_PORT_MASK_WIDTH_8X,
1829 .speed = SPEED_40000,
1830 .width = 4,
1831 },
1832 {
1833 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR,
1834 .mask_ethtool = mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr,
1835 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN,
1836 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_1X |
1837 MLXSW_SP_PORT_MASK_WIDTH_2X |
1838 MLXSW_SP_PORT_MASK_WIDTH_4X |
1839 MLXSW_SP_PORT_MASK_WIDTH_8X,
1840 .speed = SPEED_25000,
1841 .width = 1,
1842 },
1843 {
1844 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
1845 .mask_ethtool = mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2,
1846 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN,
1847 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_2X |
1848 MLXSW_SP_PORT_MASK_WIDTH_4X |
1849 MLXSW_SP_PORT_MASK_WIDTH_8X,
1850 .speed = SPEED_50000,
1851 .width = 2,
1852 },
1853 {
1854 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR,
1855 .mask_ethtool = mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr,
1856 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN,
1857 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_1X,
1858 .speed = SPEED_50000,
1859 .width = 1,
1860 },
1861 {
1862 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4,
1863 .mask_ethtool = mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4,
1864 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN,
1865 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_4X |
1866 MLXSW_SP_PORT_MASK_WIDTH_8X,
1867 .speed = SPEED_100000,
1868 .width = 4,
1869 },
1870 {
1871 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2,
1872 .mask_ethtool = mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2,
1873 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN,
1874 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_2X,
1875 .speed = SPEED_100000,
1876 .width = 2,
1877 },
1878 {
1879 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_1_100GBASE_CR_KR,
1880 .mask_ethtool = mlxsw_sp2_mask_ethtool_100gaui_1_100gbase_cr_kr,
1881 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_100GAUI_1_100GBASE_CR_KR_LEN,
1882 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_1X,
1883 .speed = SPEED_100000,
1884 .width = 1,
1885 },
1886 {
1887 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4,
1888 .mask_ethtool = mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4,
1889 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN,
1890 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_4X |
1891 MLXSW_SP_PORT_MASK_WIDTH_8X,
1892 .speed = SPEED_200000,
1893 .width = 4,
1894 },
1895 {
1896 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_2_200GBASE_CR2_KR2,
1897 .mask_ethtool = mlxsw_sp2_mask_ethtool_200gaui_2_200gbase_cr2_kr2,
1898 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_200GAUI_2_200GBASE_CR2_KR2_LEN,
1899 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_2X,
1900 .speed = SPEED_200000,
1901 .width = 2,
1902 },
1903 {
1904 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8,
1905 .mask_ethtool = mlxsw_sp2_mask_ethtool_400gaui_8,
1906 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN,
1907 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_8X,
1908 .speed = SPEED_400000,
1909 .width = 8,
1910 },
1911 {
1912 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_4_400GBASE_CR4_KR4,
1913 .mask_ethtool = mlxsw_sp2_mask_ethtool_400gaui_4_400gbase_cr4_kr4,
1914 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_400GAUI_4_400GBASE_CR4_KR4_LEN,
1915 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_4X,
1916 .speed = SPEED_400000,
1917 .width = 4,
1918 },
1919 {
1920 .mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8,
1921 .mask_ethtool = mlxsw_sp2_mask_ethtool_800gaui_8,
1922 .m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_800GAUI_8_LEN,
1923 .mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_8X,
1924 .speed = SPEED_800000,
1925 .width = 8,
1926 },
1927 };
1928
1929 #define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)
1930
1931 static void
mlxsw_sp2_from_ptys_supported_port(struct mlxsw_sp * mlxsw_sp,u32 ptys_eth_proto,struct ethtool_link_ksettings * cmd)1932 mlxsw_sp2_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
1933 u32 ptys_eth_proto,
1934 struct ethtool_link_ksettings *cmd)
1935 {
1936 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
1937 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
1938 }
1939
1940 static void
mlxsw_sp2_set_bit_ethtool(const struct mlxsw_sp2_port_link_mode * link_mode,unsigned long * mode)1941 mlxsw_sp2_set_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
1942 unsigned long *mode)
1943 {
1944 int i;
1945
1946 for (i = 0; i < link_mode->m_ethtool_len; i++)
1947 __set_bit(link_mode->mask_ethtool[i], mode);
1948 }
1949
1950 static void
mlxsw_sp2_from_ptys_link(struct mlxsw_sp * mlxsw_sp,u32 ptys_eth_proto,unsigned long * mode)1951 mlxsw_sp2_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
1952 unsigned long *mode)
1953 {
1954 int i;
1955
1956 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
1957 if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask)
1958 mlxsw_sp2_set_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
1959 mode);
1960 }
1961 }
1962
1963 static u32
mlxsw_sp2_from_ptys_speed(struct mlxsw_sp * mlxsw_sp,u32 ptys_eth_proto)1964 mlxsw_sp2_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
1965 {
1966 int i;
1967
1968 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
1969 if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask)
1970 return mlxsw_sp2_port_link_mode[i].speed;
1971 }
1972
1973 return SPEED_UNKNOWN;
1974 }
1975
1976 static void
mlxsw_sp2_from_ptys_link_mode(struct mlxsw_sp * mlxsw_sp,bool carrier_ok,u32 ptys_eth_proto,struct ethtool_link_ksettings * cmd)1977 mlxsw_sp2_from_ptys_link_mode(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
1978 u32 ptys_eth_proto,
1979 struct ethtool_link_ksettings *cmd)
1980 {
1981 struct mlxsw_sp2_port_link_mode link;
1982 int i;
1983
1984 cmd->base.speed = SPEED_UNKNOWN;
1985 cmd->base.duplex = DUPLEX_UNKNOWN;
1986 cmd->lanes = 0;
1987
1988 if (!carrier_ok)
1989 return;
1990
1991 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
1992 if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) {
1993 link = mlxsw_sp2_port_link_mode[i];
1994 ethtool_params_from_link_mode(cmd,
1995 link.mask_ethtool[1]);
1996 }
1997 }
1998 }
1999
mlxsw_sp2_ptys_max_speed(struct mlxsw_sp_port * mlxsw_sp_port,u32 * p_max_speed)2000 static int mlxsw_sp2_ptys_max_speed(struct mlxsw_sp_port *mlxsw_sp_port, u32 *p_max_speed)
2001 {
2002 u32 eth_proto_cap;
2003 u32 max_speed = 0;
2004 int err;
2005 int i;
2006
2007 err = mlxsw_sp_port_ptys_query(mlxsw_sp_port, ð_proto_cap, NULL, NULL, NULL);
2008 if (err)
2009 return err;
2010
2011 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
2012 if ((eth_proto_cap & mlxsw_sp2_port_link_mode[i].mask) &&
2013 mlxsw_sp2_port_link_mode[i].speed > max_speed)
2014 max_speed = mlxsw_sp2_port_link_mode[i].speed;
2015 }
2016
2017 *p_max_speed = max_speed;
2018 return 0;
2019 }
2020
2021 static bool
mlxsw_sp2_test_bit_ethtool(const struct mlxsw_sp2_port_link_mode * link_mode,const unsigned long * mode)2022 mlxsw_sp2_test_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
2023 const unsigned long *mode)
2024 {
2025 int cnt = 0;
2026 int i;
2027
2028 for (i = 0; i < link_mode->m_ethtool_len; i++) {
2029 if (test_bit(link_mode->mask_ethtool[i], mode))
2030 cnt++;
2031 }
2032
2033 return cnt == link_mode->m_ethtool_len;
2034 }
2035
2036 static u32
mlxsw_sp2_to_ptys_advert_link(struct mlxsw_sp * mlxsw_sp,const struct ethtool_link_ksettings * cmd)2037 mlxsw_sp2_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp,
2038 const struct ethtool_link_ksettings *cmd)
2039 {
2040 u32 ptys_proto = 0;
2041 int i;
2042
2043 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
2044 if (mlxsw_sp2_test_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
2045 cmd->link_modes.advertising))
2046 ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
2047 }
2048 return ptys_proto;
2049 }
2050
mlxsw_sp2_to_ptys_speed_lanes(struct mlxsw_sp * mlxsw_sp,u8 width,const struct ethtool_link_ksettings * cmd)2051 static u32 mlxsw_sp2_to_ptys_speed_lanes(struct mlxsw_sp *mlxsw_sp, u8 width,
2052 const struct ethtool_link_ksettings *cmd)
2053 {
2054 u8 mask_width = mlxsw_sp_port_mask_width_get(width);
2055 struct mlxsw_sp2_port_link_mode link_mode;
2056 u32 ptys_proto = 0;
2057 int i;
2058
2059 if (cmd->lanes > width)
2060 return ptys_proto;
2061
2062 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
2063 if (cmd->base.speed == mlxsw_sp2_port_link_mode[i].speed) {
2064 link_mode = mlxsw_sp2_port_link_mode[i];
2065
2066 if (!cmd->lanes) {
2067 /* If number of lanes was not set by user space,
2068 * choose the link mode that supports the width
2069 * of the port.
2070 */
2071 if (mask_width & link_mode.mask_sup_width)
2072 ptys_proto |= link_mode.mask;
2073 } else if (cmd->lanes == link_mode.width) {
2074 /* Else if the number of lanes was set, choose
2075 * the link mode that its actual width equals to
2076 * it.
2077 */
2078 ptys_proto |= link_mode.mask;
2079 }
2080 }
2081 }
2082 return ptys_proto;
2083 }
2084
2085 static void
mlxsw_sp2_reg_ptys_eth_pack(struct mlxsw_sp * mlxsw_sp,char * payload,u16 local_port,u32 proto_admin,bool autoneg)2086 mlxsw_sp2_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
2087 u16 local_port, u32 proto_admin,
2088 bool autoneg)
2089 {
2090 mlxsw_reg_ptys_ext_eth_pack(payload, local_port, proto_admin, autoneg);
2091 }
2092
2093 static void
mlxsw_sp2_reg_ptys_eth_unpack(struct mlxsw_sp * mlxsw_sp,char * payload,u32 * p_eth_proto_cap,u32 * p_eth_proto_admin,u32 * p_eth_proto_oper)2094 mlxsw_sp2_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
2095 u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
2096 u32 *p_eth_proto_oper)
2097 {
2098 mlxsw_reg_ptys_ext_eth_unpack(payload, p_eth_proto_cap,
2099 p_eth_proto_admin, p_eth_proto_oper);
2100 }
2101
mlxsw_sp2_ptys_proto_cap_masked_get(u32 eth_proto_cap)2102 static u32 mlxsw_sp2_ptys_proto_cap_masked_get(u32 eth_proto_cap)
2103 {
2104 u32 ptys_proto_cap_masked = 0;
2105 int i;
2106
2107 for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
2108 if (mlxsw_sp2_port_link_mode[i].mask & eth_proto_cap)
2109 ptys_proto_cap_masked |=
2110 mlxsw_sp2_port_link_mode[i].mask;
2111 }
2112
2113 return ptys_proto_cap_masked;
2114 }
2115
2116 const struct mlxsw_sp_port_type_speed_ops mlxsw_sp2_port_type_speed_ops = {
2117 .from_ptys_supported_port = mlxsw_sp2_from_ptys_supported_port,
2118 .from_ptys_link = mlxsw_sp2_from_ptys_link,
2119 .from_ptys_speed = mlxsw_sp2_from_ptys_speed,
2120 .from_ptys_link_mode = mlxsw_sp2_from_ptys_link_mode,
2121 .ptys_max_speed = mlxsw_sp2_ptys_max_speed,
2122 .to_ptys_advert_link = mlxsw_sp2_to_ptys_advert_link,
2123 .to_ptys_speed_lanes = mlxsw_sp2_to_ptys_speed_lanes,
2124 .reg_ptys_eth_pack = mlxsw_sp2_reg_ptys_eth_pack,
2125 .reg_ptys_eth_unpack = mlxsw_sp2_reg_ptys_eth_unpack,
2126 .ptys_proto_cap_masked_get = mlxsw_sp2_ptys_proto_cap_masked_get,
2127 };
2128