1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2023, Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/clock/intel,agilex5-clkmgr.h> 12 13/ { 14 compatible = "intel,socfpga-agilex5"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 reserved-memory { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 ranges; 22 23 service_reserved: svcbuffer@0 { 24 compatible = "shared-dma-pool"; 25 reg = <0x0 0x80000000 0x0 0x2000000>; 26 alignment = <0x1000>; 27 no-map; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu0: cpu@0 { 36 compatible = "arm,cortex-a55"; 37 reg = <0x0>; 38 device_type = "cpu"; 39 enable-method = "psci"; 40 next-level-cache = <&L2>; 41 }; 42 43 cpu1: cpu@1 { 44 compatible = "arm,cortex-a55"; 45 reg = <0x100>; 46 device_type = "cpu"; 47 enable-method = "psci"; 48 next-level-cache = <&L2>; 49 }; 50 51 cpu2: cpu@2 { 52 compatible = "arm,cortex-a76"; 53 reg = <0x200>; 54 device_type = "cpu"; 55 enable-method = "psci"; 56 next-level-cache = <&L2>; 57 }; 58 59 cpu3: cpu@3 { 60 compatible = "arm,cortex-a76"; 61 reg = <0x300>; 62 device_type = "cpu"; 63 enable-method = "psci"; 64 next-level-cache = <&L2>; 65 }; 66 67 L2: l2-cache { 68 compatible = "cache"; 69 cache-level = <2>; 70 next-level-cache = <&L3>; 71 cache-unified; 72 }; 73 74 L3: l3-cache { 75 compatible = "cache"; 76 cache-level = <3>; 77 cache-unified; 78 }; 79 80 }; 81 82 firmware { 83 svc { 84 compatible = "intel,agilex5-svc"; 85 method = "smc"; 86 memory-region = <&service_reserved>; 87 iommus = <&smmu 10>; 88 }; 89 }; 90 91 psci { 92 compatible = "arm,psci-0.2"; 93 method = "smc"; 94 }; 95 96 intc: interrupt-controller@1d000000 { 97 compatible = "arm,gic-v3"; 98 reg = <0x0 0x1d000000 0 0x10000>, 99 <0x0 0x1d060000 0 0x100000>; 100 ranges; 101 #interrupt-cells = <3>; 102 #address-cells = <2>; 103 #size-cells = <2>; 104 interrupt-controller; 105 interrupt-parent = <&intc>; 106 #redistributor-regions = <1>; 107 redistributor-stride = <0x0 0x20000>; 108 /* VGIC maintenance interrupt */ 109 interrupts = <GIC_PPI 25 IRQ_TYPE_LEVEL_HIGH>; 110 111 its: msi-controller@1d040000 { 112 compatible = "arm,gic-v3-its"; 113 reg = <0x0 0x1d040000 0x0 0x20000>; 114 msi-controller; 115 #msi-cells = <1>; 116 }; 117 }; 118 119 /* Clock tree 5 main sources*/ 120 clocks { 121 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 122 #clock-cells = <0>; 123 compatible = "fixed-clock"; 124 clock-frequency = <0>; 125 }; 126 127 cb_intosc_ls_clk: cb-intosc-ls-clk { 128 #clock-cells = <0>; 129 compatible = "fixed-clock"; 130 clock-frequency = <0>; 131 }; 132 133 f2s_free_clk: f2s-free-clk { 134 #clock-cells = <0>; 135 compatible = "fixed-clock"; 136 clock-frequency = <0>; 137 }; 138 139 osc1: osc1 { 140 #clock-cells = <0>; 141 compatible = "fixed-clock"; 142 clock-frequency = <0>; 143 }; 144 145 qspi_clk: qspi-clk { 146 #clock-cells = <0>; 147 compatible = "fixed-clock"; 148 clock-frequency = <200000000>; 149 }; 150 }; 151 152 timer { 153 compatible = "arm,armv8-timer"; 154 interrupt-parent = <&intc>; 155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 156 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 157 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 158 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 159 }; 160 161 usbphy0: usbphy { 162 #phy-cells = <0>; 163 compatible = "usb-nop-xceiv"; 164 }; 165 166 pmu0: pmu { 167 compatible = "arm,armv8-pmuv3"; 168 interrupt-parent = <&intc>; 169 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 170 }; 171 172 soc: soc@0 { 173 compatible = "simple-bus"; 174 ranges = <0 0 0 0xffffffff>; 175 #address-cells = <1>; 176 #size-cells = <1>; 177 device_type = "soc"; 178 interrupt-parent = <&intc>; 179 180 clkmgr: clock-controller@10d10000 { 181 compatible = "intel,agilex5-clkmgr"; 182 reg = <0x10d10000 0x1000>; 183 #clock-cells = <1>; 184 }; 185 186 i2c0: i2c@10c02800 { 187 compatible = "snps,designware-i2c"; 188 reg = <0x10c02800 0x100>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 192 resets = <&rst I2C0_RESET>; 193 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 194 status = "disabled"; 195 }; 196 197 i2c1: i2c@10c02900 { 198 compatible = "snps,designware-i2c"; 199 reg = <0x10c02900 0x100>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 203 resets = <&rst I2C1_RESET>; 204 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 205 status = "disabled"; 206 }; 207 208 i2c2: i2c@10c02a00 { 209 compatible = "snps,designware-i2c"; 210 reg = <0x10c02a00 0x100>; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 214 resets = <&rst I2C2_RESET>; 215 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 216 status = "disabled"; 217 }; 218 219 i2c3: i2c@10c02b00 { 220 compatible = "snps,designware-i2c"; 221 reg = <0x10c02b00 0x100>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 225 resets = <&rst I2C3_RESET>; 226 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 227 status = "disabled"; 228 }; 229 230 i2c4: i2c@10c02c00 { 231 compatible = "snps,designware-i2c"; 232 reg = <0x10c02c00 0x100>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 236 resets = <&rst I2C4_RESET>; 237 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 238 status = "disabled"; 239 }; 240 241 i3c0: i3c@10da0000 { 242 compatible = "altr,agilex5-dw-i3c-master", 243 "snps,dw-i3c-master-1.00a"; 244 reg = <0x10da0000 0x1000>; 245 #address-cells = <3>; 246 #size-cells = <0>; 247 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&clkmgr AGILEX5_L4_MP_CLK>; 249 status = "disabled"; 250 }; 251 252 i3c1: i3c@10da1000 { 253 compatible = "altr,agilex5-dw-i3c-master", 254 "snps,dw-i3c-master-1.00a"; 255 reg = <0x10da1000 0x1000>; 256 #address-cells = <3>; 257 #size-cells = <0>; 258 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&clkmgr AGILEX5_L4_MP_CLK>; 260 status = "disabled"; 261 }; 262 263 gpio0: gpio@10c03200 { 264 compatible = "snps,dw-apb-gpio"; 265 reg = <0x10c03200 0x100>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 resets = <&rst GPIO0_RESET>; 269 status = "disabled"; 270 271 porta: gpio-controller@0 { 272 compatible = "snps,dw-apb-gpio-port"; 273 reg = <0>; 274 gpio-controller; 275 #gpio-cells = <2>; 276 snps,nr-gpios = <24>; 277 interrupt-controller; 278 #interrupt-cells = <2>; 279 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 280 }; 281 }; 282 283 gpio1: gpio@10c03300 { 284 compatible = "snps,dw-apb-gpio"; 285 reg = <0x10c03300 0x100>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 resets = <&rst GPIO1_RESET>; 289 status = "disabled"; 290 291 portb: gpio-controller@0 { 292 compatible = "snps,dw-apb-gpio-port"; 293 reg = <0>; 294 gpio-controller; 295 #gpio-cells = <2>; 296 snps,nr-gpios = <24>; 297 interrupt-controller; 298 #interrupt-cells = <2>; 299 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 300 }; 301 }; 302 303 nand: nand-controller@10b80000 { 304 compatible = "cdns,hp-nfc"; 305 reg = <0x10b80000 0x10000>, 306 <0x10840000 0x10000>; 307 reg-names = "reg", "sdma"; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&clkmgr AGILEX5_NAND_NF_CLK>; 312 clock-names = "nf_clk"; 313 cdns,board-delay-ps = <4830>; 314 iommus = <&smmu 4>; 315 status = "disabled"; 316 }; 317 318 ocram: sram@0 { 319 compatible = "mmio-sram"; 320 reg = <0x00000000 0x80000>; 321 ranges = <0 0 0x80000>; 322 #address-cells = <1>; 323 #size-cells = <1>; 324 }; 325 326 dmac0: dma-controller@10db0000 { 327 compatible = "snps,axi-dma-1.01a"; 328 reg = <0x10db0000 0x500>; 329 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, 330 <&clkmgr AGILEX5_L4_MP_CLK>; 331 clock-names = "core-clk", "cfgr-clk"; 332 interrupt-parent = <&intc>; 333 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 334 #dma-cells = <1>; 335 dma-channels = <4>; 336 snps,dma-masters = <1>; 337 snps,data-width = <2>; 338 snps,block-size = <32767 32767 32767 32767>; 339 snps,priority = <0 1 2 3>; 340 snps,axi-max-burst-len = <8>; 341 iommus = <&smmu 8>; 342 }; 343 344 dmac1: dma-controller@10dc0000 { 345 compatible = "snps,axi-dma-1.01a"; 346 reg = <0x10dc0000 0x500>; 347 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, 348 <&clkmgr AGILEX5_L4_MP_CLK>; 349 clock-names = "core-clk", "cfgr-clk"; 350 interrupt-parent = <&intc>; 351 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 352 #dma-cells = <1>; 353 dma-channels = <4>; 354 snps,dma-masters = <1>; 355 snps,data-width = <2>; 356 snps,block-size = <32767 32767 32767 32767>; 357 snps,priority = <0 1 2 3>; 358 snps,axi-max-burst-len = <8>; 359 iommus = <&smmu 9>; 360 }; 361 362 rst: rstmgr@10d11000 { 363 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; 364 reg = <0x10d11000 0x1000>; 365 #reset-cells = <1>; 366 }; 367 368 smmu: iommu@16000000 { 369 compatible = "arm,smmu-v3"; 370 reg = <0x16000000 0x30000>; 371 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 372 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 373 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>; 374 interrupt-names = "eventq", "gerror", "priq"; 375 dma-coherent; 376 #iommu-cells = <1>; 377 status = "disabled"; 378 }; 379 380 spi0: spi@10da4000 { 381 compatible = "snps,dw-apb-ssi"; 382 reg = <0x10da4000 0x1000>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 386 resets = <&rst SPIM0_RESET>; 387 reset-names = "spi"; 388 reg-io-width = <4>; 389 num-cs = <4>; 390 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; 391 dmas = <&dmac0 16>, <&dmac0 17>; 392 dma-names = "tx", "rx"; 393 status = "disabled"; 394 395 }; 396 397 spi1: spi@10da5000 { 398 compatible = "snps,dw-apb-ssi"; 399 reg = <0x10da5000 0x1000>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 403 resets = <&rst SPIM1_RESET>; 404 reset-names = "spi"; 405 reg-io-width = <4>; 406 num-cs = <4>; 407 clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; 408 dmas = <&dmac0 20>, <&dmac0 21>; 409 dma-names = "tx", "rx"; 410 status = "disabled"; 411 }; 412 413 sysmgr: sysmgr@10d12000 { 414 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 415 reg = <0x10d12000 0x500>; 416 }; 417 418 timer0: timer0@10c03000 { 419 compatible = "snps,dw-apb-timer"; 420 reg = <0x10c03000 0x100>; 421 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 423 clock-names = "timer"; 424 }; 425 426 timer1: timer1@10c03100 { 427 compatible = "snps,dw-apb-timer"; 428 reg = <0x10c03100 0x100>; 429 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 431 clock-names = "timer"; 432 }; 433 434 timer2: timer2@10d00000 { 435 compatible = "snps,dw-apb-timer"; 436 reg = <0x10d00000 0x100>; 437 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 439 clock-names = "timer"; 440 }; 441 442 timer3: timer3@10d00100 { 443 compatible = "snps,dw-apb-timer"; 444 reg = <0x10d00100 0x100>; 445 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 447 clock-names = "timer"; 448 }; 449 450 uart0: serial@10c02000 { 451 compatible = "snps,dw-apb-uart"; 452 reg = <0x10c02000 0x100>; 453 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 454 reg-shift = <2>; 455 reg-io-width = <4>; 456 resets = <&rst UART0_RESET>; 457 status = "disabled"; 458 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 459 }; 460 461 uart1: serial@10c02100 { 462 compatible = "snps,dw-apb-uart"; 463 reg = <0x10c02100 0x100>; 464 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 465 reg-shift = <2>; 466 reg-io-width = <4>; 467 resets = <&rst UART1_RESET>; 468 status = "disabled"; 469 clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 470 }; 471 472 usb0: usb@10b00000 { 473 compatible = "snps,dwc2"; 474 reg = <0x10b00000 0x40000>; 475 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 476 phys = <&usbphy0>; 477 phy-names = "usb2-phy"; 478 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 479 reset-names = "dwc2", "dwc2-ecc"; 480 iommus = <&smmu 6>; 481 clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>; 482 clock-names = "otg"; 483 status = "disabled"; 484 }; 485 486 watchdog0: watchdog@10d00200 { 487 compatible = "snps,dw-wdt"; 488 reg = <0x10d00200 0x100>; 489 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 490 resets = <&rst WATCHDOG0_RESET>; 491 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 492 status = "disabled"; 493 }; 494 495 watchdog1: watchdog@10d00300 { 496 compatible = "snps,dw-wdt"; 497 reg = <0x10d00300 0x100>; 498 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 499 resets = <&rst WATCHDOG1_RESET>; 500 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 501 status = "disabled"; 502 }; 503 504 watchdog2: watchdog@10d00400 { 505 compatible = "snps,dw-wdt"; 506 reg = <0x10d00400 0x100>; 507 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 508 resets = <&rst WATCHDOG2_RESET>; 509 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 510 status = "disabled"; 511 }; 512 513 watchdog3: watchdog@10d00500 { 514 compatible = "snps,dw-wdt"; 515 reg = <0x10d00500 0x100>; 516 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 517 resets = <&rst WATCHDOG3_RESET>; 518 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 519 status = "disabled"; 520 }; 521 522 watchdog4: watchdog@10d00600 { 523 compatible = "snps,dw-wdt"; 524 reg = <0x10d00600 0x100>; 525 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 526 resets = <&rst WATCHDOG4_RESET>; 527 clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 528 status = "disabled"; 529 }; 530 531 qspi: spi@108d2000 { 532 compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 533 reg = <0x108d2000 0x100>, 534 <0x10900000 0x100000>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 538 cdns,fifo-depth = <128>; 539 cdns,fifo-width = <4>; 540 cdns,trigger-address = <0x00000000>; 541 clocks = <&qspi_clk>; 542 status = "disabled"; 543 }; 544 545 gmac0: ethernet@10810000 { 546 compatible = "altr,socfpga-stmmac-agilex5", 547 "snps,dwxgmac-2.10"; 548 reg = <0x10810000 0x3500>; 549 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 550 interrupt-names = "macirq"; 551 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 552 reset-names = "stmmaceth", "ahb"; 553 clocks = <&clkmgr AGILEX5_EMAC0_CLK>, 554 <&clkmgr AGILEX5_EMAC_PTP_CLK>; 555 clock-names = "stmmaceth", "ptp_ref"; 556 mac-address = [00 00 00 00 00 00]; 557 tx-fifo-depth = <32768>; 558 rx-fifo-depth = <16384>; 559 snps,multicast-filter-bins = <64>; 560 snps,perfect-filter-entries = <64>; 561 snps,axi-config = <&stmmac_axi_emac0_setup>; 562 snps,mtl-rx-config = <&mtl_rx_emac0_setup>; 563 snps,mtl-tx-config = <&mtl_tx_emac0_setup>; 564 snps,pbl = <32>; 565 snps,tso; 566 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 567 snps,clk-csr = <0>; 568 status = "disabled"; 569 570 stmmac_axi_emac0_setup: stmmac-axi-config { 571 snps,wr_osr_lmt = <31>; 572 snps,rd_osr_lmt = <31>; 573 snps,blen = <0 0 0 32 16 8 4>; 574 }; 575 576 mtl_rx_emac0_setup: rx-queues-config { 577 snps,rx-queues-to-use = <8>; 578 snps,rx-sched-sp; 579 queue0 { 580 snps,dcb-algorithm; 581 snps,map-to-dma-channel = <0x0>; 582 }; 583 queue1 { 584 snps,dcb-algorithm; 585 snps,map-to-dma-channel = <0x1>; 586 }; 587 queue2 { 588 snps,dcb-algorithm; 589 snps,map-to-dma-channel = <0x2>; 590 }; 591 queue3 { 592 snps,dcb-algorithm; 593 snps,map-to-dma-channel = <0x3>; 594 }; 595 queue4 { 596 snps,dcb-algorithm; 597 snps,map-to-dma-channel = <0x4>; 598 }; 599 queue5 { 600 snps,dcb-algorithm; 601 snps,map-to-dma-channel = <0x5>; 602 }; 603 queue6 { 604 snps,dcb-algorithm; 605 snps,map-to-dma-channel = <0x6>; 606 }; 607 queue7 { 608 snps,dcb-algorithm; 609 snps,map-to-dma-channel = <0x7>; 610 }; 611 }; 612 613 mtl_tx_emac0_setup: tx-queues-config { 614 snps,tx-queues-to-use = <8>; 615 snps,tx-sched-wrr; 616 queue0 { 617 snps,weight = <0x09>; 618 snps,dcb-algorithm; 619 }; 620 queue1 { 621 snps,weight = <0x0A>; 622 snps,dcb-algorithm; 623 }; 624 queue2 { 625 snps,weight = <0x0B>; 626 snps,coe-unsupported; 627 snps,dcb-algorithm; 628 }; 629 queue3 { 630 snps,weight = <0x0C>; 631 snps,coe-unsupported; 632 snps,dcb-algorithm; 633 }; 634 queue4 { 635 snps,weight = <0x0D>; 636 snps,coe-unsupported; 637 snps,dcb-algorithm; 638 }; 639 queue5 { 640 snps,weight = <0x0E>; 641 snps,coe-unsupported; 642 snps,dcb-algorithm; 643 }; 644 queue6 { 645 snps,weight = <0x0F>; 646 snps,coe-unsupported; 647 snps,dcb-algorithm; 648 }; 649 queue7 { 650 snps,weight = <0x10>; 651 snps,coe-unsupported; 652 snps,dcb-algorithm; 653 }; 654 }; 655 }; 656 657 gmac1: ethernet@10820000 { 658 compatible = "altr,socfpga-stmmac-agilex5", 659 "snps,dwxgmac-2.10"; 660 reg = <0x10820000 0x3500>; 661 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 662 interrupt-names = "macirq"; 663 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 664 reset-names = "stmmaceth", "ahb"; 665 clocks = <&clkmgr AGILEX5_EMAC1_CLK>, 666 <&clkmgr AGILEX5_EMAC_PTP_CLK>; 667 clock-names = "stmmaceth", "ptp_ref"; 668 mac-address = [00 00 00 00 00 00]; 669 tx-fifo-depth = <32768>; 670 rx-fifo-depth = <16384>; 671 snps,multicast-filter-bins = <64>; 672 snps,perfect-filter-entries = <64>; 673 snps,axi-config = <&stmmac_axi_emac1_setup>; 674 snps,mtl-rx-config = <&mtl_rx_emac1_setup>; 675 snps,mtl-tx-config = <&mtl_tx_emac1_setup>; 676 snps,pbl = <32>; 677 snps,tso; 678 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 679 snps,clk-csr = <0>; 680 status = "disabled"; 681 682 stmmac_axi_emac1_setup: stmmac-axi-config { 683 snps,wr_osr_lmt = <31>; 684 snps,rd_osr_lmt = <31>; 685 snps,blen = <0 0 0 32 16 8 4>; 686 }; 687 688 mtl_rx_emac1_setup: rx-queues-config { 689 snps,rx-queues-to-use = <8>; 690 snps,rx-sched-sp; 691 queue0 { 692 snps,dcb-algorithm; 693 snps,map-to-dma-channel = <0x0>; 694 }; 695 queue1 { 696 snps,dcb-algorithm; 697 snps,map-to-dma-channel = <0x1>; 698 }; 699 queue2 { 700 snps,dcb-algorithm; 701 snps,map-to-dma-channel = <0x2>; 702 }; 703 queue3 { 704 snps,dcb-algorithm; 705 snps,map-to-dma-channel = <0x3>; 706 }; 707 queue4 { 708 snps,dcb-algorithm; 709 snps,map-to-dma-channel = <0x4>; 710 }; 711 queue5 { 712 snps,dcb-algorithm; 713 snps,map-to-dma-channel = <0x5>; 714 }; 715 queue6 { 716 snps,dcb-algorithm; 717 snps,map-to-dma-channel = <0x6>; 718 }; 719 queue7 { 720 snps,dcb-algorithm; 721 snps,map-to-dma-channel = <0x7>; 722 }; 723 }; 724 725 mtl_tx_emac1_setup: tx-queues-config { 726 snps,tx-queues-to-use = <8>; 727 snps,tx-sched-wrr; 728 queue0 { 729 snps,weight = <0x09>; 730 snps,dcb-algorithm; 731 }; 732 queue1 { 733 snps,weight = <0x0A>; 734 snps,dcb-algorithm; 735 }; 736 queue2 { 737 snps,weight = <0x0B>; 738 snps,coe-unsupported; 739 snps,dcb-algorithm; 740 }; 741 queue3 { 742 snps,weight = <0x0C>; 743 snps,coe-unsupported; 744 snps,dcb-algorithm; 745 }; 746 queue4 { 747 snps,weight = <0x0D>; 748 snps,coe-unsupported; 749 snps,dcb-algorithm; 750 }; 751 queue5 { 752 snps,weight = <0x0E>; 753 snps,coe-unsupported; 754 snps,dcb-algorithm; 755 }; 756 queue6 { 757 snps,weight = <0x0F>; 758 snps,coe-unsupported; 759 snps,dcb-algorithm; 760 }; 761 queue7 { 762 snps,weight = <0x10>; 763 snps,coe-unsupported; 764 snps,dcb-algorithm; 765 }; 766 }; 767 }; 768 769 gmac2: ethernet@10830000 { 770 compatible = "altr,socfpga-stmmac-agilex5", 771 "snps,dwxgmac-2.10"; 772 reg = <0x10830000 0x3500>; 773 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 774 interrupt-names = "macirq"; 775 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 776 reset-names = "stmmaceth", "ahb"; 777 clocks = <&clkmgr AGILEX5_EMAC2_CLK>, 778 <&clkmgr AGILEX5_EMAC_PTP_CLK>; 779 clock-names = "stmmaceth", "ptp_ref"; 780 mac-address = [00 00 00 00 00 00]; 781 tx-fifo-depth = <32768>; 782 rx-fifo-depth = <16384>; 783 snps,multicast-filter-bins = <64>; 784 snps,perfect-filter-entries = <64>; 785 snps,axi-config = <&stmmac_axi_emac2_setup>; 786 snps,mtl-rx-config = <&mtl_rx_emac2_setup>; 787 snps,mtl-tx-config = <&mtl_tx_emac2_setup>; 788 snps,pbl = <32>; 789 snps,tso; 790 altr,sysmgr-syscon = <&sysmgr 0x4c 0>; 791 snps,clk-csr = <0>; 792 status = "disabled"; 793 794 stmmac_axi_emac2_setup: stmmac-axi-config { 795 snps,wr_osr_lmt = <31>; 796 snps,rd_osr_lmt = <31>; 797 snps,blen = <0 0 0 32 16 8 4>; 798 }; 799 800 mtl_rx_emac2_setup: rx-queues-config { 801 snps,rx-queues-to-use = <8>; 802 snps,rx-sched-sp; 803 queue0 { 804 snps,dcb-algorithm; 805 snps,map-to-dma-channel = <0x0>; 806 }; 807 queue1 { 808 snps,dcb-algorithm; 809 snps,map-to-dma-channel = <0x1>; 810 }; 811 queue2 { 812 snps,dcb-algorithm; 813 snps,map-to-dma-channel = <0x2>; 814 }; 815 queue3 { 816 snps,dcb-algorithm; 817 snps,map-to-dma-channel = <0x3>; 818 }; 819 queue4 { 820 snps,dcb-algorithm; 821 snps,map-to-dma-channel = <0x4>; 822 }; 823 queue5 { 824 snps,dcb-algorithm; 825 snps,map-to-dma-channel = <0x5>; 826 }; 827 queue6 { 828 snps,dcb-algorithm; 829 snps,map-to-dma-channel = <0x6>; 830 }; 831 queue7 { 832 snps,dcb-algorithm; 833 snps,map-to-dma-channel = <0x7>; 834 }; 835 }; 836 837 mtl_tx_emac2_setup: tx-queues-config { 838 snps,tx-queues-to-use = <8>; 839 snps,tx-sched-wrr; 840 queue0 { 841 snps,weight = <0x09>; 842 snps,dcb-algorithm; 843 }; 844 queue1 { 845 snps,weight = <0x0A>; 846 snps,dcb-algorithm; 847 }; 848 queue2 { 849 snps,weight = <0x0B>; 850 snps,coe-unsupported; 851 snps,dcb-algorithm; 852 }; 853 queue3 { 854 snps,weight = <0x0C>; 855 snps,coe-unsupported; 856 snps,dcb-algorithm; 857 }; 858 queue4 { 859 snps,weight = <0x0D>; 860 snps,coe-unsupported; 861 snps,dcb-algorithm; 862 }; 863 queue5 { 864 snps,weight = <0x0E>; 865 snps,coe-unsupported; 866 snps,dcb-algorithm; 867 }; 868 queue6 { 869 snps,weight = <0x0F>; 870 snps,coe-unsupported; 871 snps,dcb-algorithm; 872 }; 873 queue7 { 874 snps,weight = <0x10>; 875 snps,coe-unsupported; 876 snps,dcb-algorithm; 877 }; 878 }; 879 }; 880 881 pmu0_tcu: pmu@16002000 { 882 compatible = "arm,smmu-v3-pmcg"; 883 reg = <0x16002000 0x1000>, 884 <0x16022000 0x1000>; 885 interrupt-parent = <&intc>; 886 interrupts = <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>; 887 }; 888 889 pmu0_tbu0: pmu@16042000 { 890 compatible = "arm,smmu-v3-pmcg"; 891 reg = <0x16042000 0x1000>, 892 <0x16052000 0x1000>; 893 interrupt-parent = <&intc>; 894 interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>; 895 }; 896 897 pmu0_tbu1: pmu@16062000 { 898 compatible = "arm,smmu-v3-pmcg"; 899 reg = <0x16062000 0x1000>, 900 <0x16072000 0x1000>; 901 interrupt-parent = <&intc>; 902 interrupts = <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 903 }; 904 905 pmu0_tbu2: pmu@16082000 { 906 compatible = "arm,smmu-v3-pmcg"; 907 reg = <0x16082000 0x1000>, 908 <0x16092000 0x1000>; 909 interrupt-parent = <&intc>; 910 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 911 }; 912 913 pmu0_tbu3: pmu@160a2000 { 914 compatible = "arm,smmu-v3-pmcg"; 915 reg = <0x160A2000 0x1000>, 916 <0x160B2000 0x1000>; 917 interrupt-parent = <&intc>; 918 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 919 }; 920 921 pmu0_tbu4: pmu@160c2000 { 922 compatible = "arm,smmu-v3-pmcg"; 923 reg = <0x160C2000 0x1000>, 924 <0x160D2000 0x1000>; 925 interrupt-parent = <&intc>; 926 interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; 927 }; 928 929 pmu0_tbu5: pmu@160e2000 { 930 compatible = "arm,smmu-v3-pmcg"; 931 reg = <0x160E2000 0x1000>, 932 <0x160F2000 0x1000>; 933 interrupt-parent = <&intc>; 934 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 935 }; 936 }; 937}; 938