1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019, Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/agilex-clock.h> 11 12/ { 13 compatible = "intel,socfpga-agilex"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 reserved-memory { 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 service_reserved: svcbuffer@0 { 23 compatible = "shared-dma-pool"; 24 reg = <0x0 0x0 0x0 0x2000000>; 25 alignment = <0x1000>; 26 no-map; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 compatible = "arm,cortex-a53"; 36 device_type = "cpu"; 37 enable-method = "psci"; 38 reg = <0x0>; 39 }; 40 41 cpu1: cpu@1 { 42 compatible = "arm,cortex-a53"; 43 device_type = "cpu"; 44 enable-method = "psci"; 45 reg = <0x1>; 46 }; 47 48 cpu2: cpu@2 { 49 compatible = "arm,cortex-a53"; 50 device_type = "cpu"; 51 enable-method = "psci"; 52 reg = <0x2>; 53 }; 54 55 cpu3: cpu@3 { 56 compatible = "arm,cortex-a53"; 57 device_type = "cpu"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 }; 61 }; 62 63 firmware { 64 svc { 65 compatible = "intel,agilex-svc"; 66 method = "smc"; 67 memory-region = <&service_reserved>; 68 69 fpga_mgr: fpga-mgr { 70 compatible = "intel,agilex-soc-fpga-mgr"; 71 }; 72 }; 73 }; 74 75 fpga-region { 76 compatible = "fpga-region"; 77 #address-cells = <0x2>; 78 #size-cells = <0x2>; 79 fpga-mgr = <&fpga_mgr>; 80 }; 81 82 pmu { 83 compatible = "arm,cortex-a53-pmu"; 84 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 88 interrupt-affinity = <&cpu0>, 89 <&cpu1>, 90 <&cpu2>, 91 <&cpu3>; 92 interrupt-parent = <&intc>; 93 }; 94 95 psci { 96 compatible = "arm,psci-0.2"; 97 method = "smc"; 98 }; 99 100 intc: interrupt-controller@fffc1000 { 101 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 102 #interrupt-cells = <3>; 103 interrupt-controller; 104 interrupt-parent = <&intc>; 105 reg = <0x0 0xfffc1000 0x0 0x1000>, 106 <0x0 0xfffc2000 0x0 0x2000>, 107 <0x0 0xfffc4000 0x0 0x2000>, 108 <0x0 0xfffc6000 0x0 0x2000>; 109 /* VGIC maintenance interrupt */ 110 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 111 }; 112 113 clocks { 114 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 115 #clock-cells = <0>; 116 compatible = "fixed-clock"; 117 clock-frequency = <200000000>; 118 }; 119 120 cb_intosc_ls_clk: cb-intosc-ls-clk { 121 #clock-cells = <0>; 122 compatible = "fixed-clock"; 123 clock-frequency = <400000000>; 124 }; 125 126 f2s_free_clk: f2s-free-clk { 127 #clock-cells = <0>; 128 compatible = "fixed-clock"; 129 clock-frequency = <100000000>; 130 }; 131 132 osc1: osc1 { 133 #clock-cells = <0>; 134 compatible = "fixed-clock"; 135 }; 136 137 qspi_clk: qspi-clk { 138 #clock-cells = <0>; 139 compatible = "fixed-clock"; 140 clock-frequency = <200000000>; 141 }; 142 }; 143 144 timer { 145 compatible = "arm,armv8-timer"; 146 interrupt-parent = <&intc>; 147 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 148 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 149 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 151 }; 152 153 usbphy0: usbphy { 154 #phy-cells = <0>; 155 compatible = "usb-nop-xceiv"; 156 }; 157 158 soc@0 { 159 #address-cells = <1>; 160 #size-cells = <1>; 161 compatible = "simple-bus"; 162 device_type = "soc"; 163 interrupt-parent = <&intc>; 164 ranges = <0 0 0 0xffffffff>; 165 166 clkmgr: clock-controller@ffd10000 { 167 compatible = "intel,agilex-clkmgr"; 168 reg = <0xffd10000 0x1000>; 169 #clock-cells = <1>; 170 }; 171 172 gmac0: ethernet@ff800000 { 173 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 174 reg = <0xff800000 0x2000>; 175 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 176 interrupt-names = "macirq"; 177 mac-address = [00 00 00 00 00 00]; 178 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 179 reset-names = "stmmaceth", "ahb"; 180 tx-fifo-depth = <16384>; 181 rx-fifo-depth = <16384>; 182 snps,multicast-filter-bins = <256>; 183 iommus = <&smmu 1>; 184 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 185 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 186 clock-names = "stmmaceth", "ptp_ref"; 187 status = "disabled"; 188 }; 189 190 gmac1: ethernet@ff802000 { 191 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 192 reg = <0xff802000 0x2000>; 193 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 194 interrupt-names = "macirq"; 195 mac-address = [00 00 00 00 00 00]; 196 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 197 reset-names = "stmmaceth", "ahb"; 198 tx-fifo-depth = <16384>; 199 rx-fifo-depth = <16384>; 200 snps,multicast-filter-bins = <256>; 201 iommus = <&smmu 2>; 202 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 203 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 204 clock-names = "stmmaceth", "ptp_ref"; 205 status = "disabled"; 206 }; 207 208 gmac2: ethernet@ff804000 { 209 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 210 reg = <0xff804000 0x2000>; 211 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-names = "macirq"; 213 mac-address = [00 00 00 00 00 00]; 214 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 215 reset-names = "stmmaceth", "ahb"; 216 tx-fifo-depth = <16384>; 217 rx-fifo-depth = <16384>; 218 snps,multicast-filter-bins = <256>; 219 iommus = <&smmu 3>; 220 altr,sysmgr-syscon = <&sysmgr 0x4c 0>; 221 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 222 clock-names = "stmmaceth", "ptp_ref"; 223 status = "disabled"; 224 }; 225 226 gpio0: gpio@ffc03200 { 227 #address-cells = <1>; 228 #size-cells = <0>; 229 compatible = "snps,dw-apb-gpio"; 230 reg = <0xffc03200 0x100>; 231 resets = <&rst GPIO0_RESET>; 232 status = "disabled"; 233 234 porta: gpio-controller@0 { 235 compatible = "snps,dw-apb-gpio-port"; 236 gpio-controller; 237 #gpio-cells = <2>; 238 snps,nr-gpios = <24>; 239 reg = <0>; 240 interrupt-controller; 241 #interrupt-cells = <2>; 242 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 243 }; 244 }; 245 246 gpio1: gpio@ffc03300 { 247 #address-cells = <1>; 248 #size-cells = <0>; 249 compatible = "snps,dw-apb-gpio"; 250 reg = <0xffc03300 0x100>; 251 resets = <&rst GPIO1_RESET>; 252 status = "disabled"; 253 254 portb: gpio-controller@0 { 255 compatible = "snps,dw-apb-gpio-port"; 256 gpio-controller; 257 #gpio-cells = <2>; 258 snps,nr-gpios = <24>; 259 reg = <0>; 260 interrupt-controller; 261 #interrupt-cells = <2>; 262 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 263 }; 264 }; 265 266 i2c0: i2c@ffc02800 { 267 #address-cells = <1>; 268 #size-cells = <0>; 269 compatible = "snps,designware-i2c"; 270 reg = <0xffc02800 0x100>; 271 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 272 resets = <&rst I2C0_RESET>; 273 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 274 status = "disabled"; 275 }; 276 277 i2c1: i2c@ffc02900 { 278 #address-cells = <1>; 279 #size-cells = <0>; 280 compatible = "snps,designware-i2c"; 281 reg = <0xffc02900 0x100>; 282 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 283 resets = <&rst I2C1_RESET>; 284 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 285 status = "disabled"; 286 }; 287 288 i2c2: i2c@ffc02a00 { 289 #address-cells = <1>; 290 #size-cells = <0>; 291 compatible = "snps,designware-i2c"; 292 reg = <0xffc02a00 0x100>; 293 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 294 resets = <&rst I2C2_RESET>; 295 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 296 status = "disabled"; 297 }; 298 299 i2c3: i2c@ffc02b00 { 300 #address-cells = <1>; 301 #size-cells = <0>; 302 compatible = "snps,designware-i2c"; 303 reg = <0xffc02b00 0x100>; 304 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 305 resets = <&rst I2C3_RESET>; 306 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 307 status = "disabled"; 308 }; 309 310 i2c4: i2c@ffc02c00 { 311 #address-cells = <1>; 312 #size-cells = <0>; 313 compatible = "snps,designware-i2c"; 314 reg = <0xffc02c00 0x100>; 315 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 316 resets = <&rst I2C4_RESET>; 317 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 318 status = "disabled"; 319 }; 320 321 mmc: mmc@ff808000 { 322 #address-cells = <1>; 323 #size-cells = <0>; 324 compatible = "altr,socfpga-dw-mshc"; 325 reg = <0xff808000 0x1000>; 326 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 327 fifo-depth = <0x400>; 328 resets = <&rst SDMMC_RESET>; 329 reset-names = "reset"; 330 clocks = <&clkmgr AGILEX_L4_MP_CLK>, 331 <&clkmgr AGILEX_SDMMC_CLK>; 332 clock-names = "biu", "ciu"; 333 iommus = <&smmu 5>; 334 altr,sysmgr-syscon = <&sysmgr 0x28 4>; 335 status = "disabled"; 336 }; 337 338 nand: nand-controller@ffb90000 { 339 #address-cells = <1>; 340 #size-cells = <0>; 341 compatible = "altr,socfpga-denali-nand"; 342 reg = <0xffb90000 0x10000>, 343 <0xffb80000 0x1000>; 344 reg-names = "nand_data", "denali_reg"; 345 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&clkmgr AGILEX_NAND_CLK>, 347 <&clkmgr AGILEX_NAND_X_CLK>, 348 <&clkmgr AGILEX_NAND_ECC_CLK>; 349 clock-names = "nand", "nand_x", "ecc"; 350 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 351 status = "disabled"; 352 }; 353 354 ocram: sram@ffe00000 { 355 compatible = "mmio-sram"; 356 reg = <0xffe00000 0x40000>; 357 #address-cells = <1>; 358 #size-cells = <1>; 359 ranges = <0 0xffe00000 0x40000>; 360 }; 361 362 pdma: dma-controller@ffda0000 { 363 compatible = "arm,pl330", "arm,primecell"; 364 reg = <0xffda0000 0x1000>; 365 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 374 #dma-cells = <1>; 375 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 376 reset-names = "dma", "dma-ocp"; 377 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 378 clock-names = "apb_pclk"; 379 }; 380 381 pinctrl0: pinctrl@ffd13000 { 382 compatible = "pinctrl-single"; 383 #pinctrl-cells = <1>; 384 reg = <0xffd13000 0xa0>; 385 pinctrl-single,register-width = <32>; 386 pinctrl-single,function-mask = <0x0000000f>; 387 }; 388 389 pinctrl1: pinctrl@ffd13100 { 390 compatible = "pinctrl-single"; 391 #pinctrl-cells = <1>; 392 reg = <0xffd13100 0x20>; 393 pinctrl-single,register-width = <32>; 394 }; 395 396 rst: rstmgr@ffd11000 { 397 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; 398 reg = <0xffd11000 0x100>; 399 #reset-cells = <1>; 400 }; 401 402 smmu: iommu@fa000000 { 403 compatible = "arm,mmu-500", "arm,smmu-v2"; 404 reg = <0xfa000000 0x40000>; 405 #global-interrupts = <2>; 406 #iommu-cells = <1>; 407 interrupt-parent = <&intc>; 408 /* Global Secure Fault */ 409 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 410 /* Global Non-secure Fault */ 411 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 412 /* Non-secure Context Interrupts (32) */ 413 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 445 stream-match-mask = <0x7ff0>; 446 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>, 447 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>, 448 <&clkmgr AGILEX_L4_MAIN_CLK>; 449 status = "disabled"; 450 }; 451 452 spi0: spi@ffda4000 { 453 compatible = "snps,dw-apb-ssi"; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 reg = <0xffda4000 0x1000>; 457 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 458 resets = <&rst SPIM0_RESET>; 459 reset-names = "spi"; 460 reg-io-width = <4>; 461 num-cs = <4>; 462 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 463 dmas = <&pdma 16>, <&pdma 17>; 464 dma-names = "tx", "rx"; 465 status = "disabled"; 466 }; 467 468 spi1: spi@ffda5000 { 469 compatible = "snps,dw-apb-ssi"; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 reg = <0xffda5000 0x1000>; 473 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 474 resets = <&rst SPIM1_RESET>; 475 reset-names = "spi"; 476 reg-io-width = <4>; 477 num-cs = <4>; 478 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 479 dmas = <&pdma 20>, <&pdma 21>; 480 dma-names = "tx", "rx"; 481 status = "disabled"; 482 }; 483 484 sysmgr: sysmgr@ffd12000 { 485 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 486 reg = <0xffd12000 0x500>; 487 }; 488 489 timer0: timer0@ffc03000 { 490 compatible = "snps,dw-apb-timer"; 491 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 492 reg = <0xffc03000 0x100>; 493 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 494 clock-names = "timer"; 495 }; 496 497 timer1: timer1@ffc03100 { 498 compatible = "snps,dw-apb-timer"; 499 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 500 reg = <0xffc03100 0x100>; 501 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 502 clock-names = "timer"; 503 }; 504 505 timer2: timer2@ffd00000 { 506 compatible = "snps,dw-apb-timer"; 507 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 508 reg = <0xffd00000 0x100>; 509 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 510 clock-names = "timer"; 511 }; 512 513 timer3: timer3@ffd00100 { 514 compatible = "snps,dw-apb-timer"; 515 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 516 reg = <0xffd00100 0x100>; 517 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 518 clock-names = "timer"; 519 }; 520 521 uart0: serial@ffc02000 { 522 compatible = "snps,dw-apb-uart"; 523 reg = <0xffc02000 0x100>; 524 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 525 reg-shift = <2>; 526 reg-io-width = <4>; 527 resets = <&rst UART0_RESET>; 528 status = "disabled"; 529 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 530 }; 531 532 uart1: serial@ffc02100 { 533 compatible = "snps,dw-apb-uart"; 534 reg = <0xffc02100 0x100>; 535 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 536 reg-shift = <2>; 537 reg-io-width = <4>; 538 resets = <&rst UART1_RESET>; 539 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 540 status = "disabled"; 541 }; 542 543 usb0: usb@ffb00000 { 544 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; 545 reg = <0xffb00000 0x40000>; 546 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 547 phys = <&usbphy0>; 548 phy-names = "usb2-phy"; 549 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 550 reset-names = "dwc2", "dwc2-ecc"; 551 clocks = <&clkmgr AGILEX_USB_CLK>; 552 clock-names = "otg"; 553 iommus = <&smmu 6>; 554 status = "disabled"; 555 }; 556 557 usb1: usb@ffb40000 { 558 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; 559 reg = <0xffb40000 0x40000>; 560 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 561 phys = <&usbphy0>; 562 phy-names = "usb2-phy"; 563 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 564 reset-names = "dwc2", "dwc2-ecc"; 565 iommus = <&smmu 7>; 566 clocks = <&clkmgr AGILEX_USB_CLK>; 567 status = "disabled"; 568 }; 569 570 watchdog0: watchdog@ffd00200 { 571 compatible = "snps,dw-wdt"; 572 reg = <0xffd00200 0x100>; 573 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 574 resets = <&rst WATCHDOG0_RESET>; 575 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 576 status = "disabled"; 577 }; 578 579 watchdog1: watchdog@ffd00300 { 580 compatible = "snps,dw-wdt"; 581 reg = <0xffd00300 0x100>; 582 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 583 resets = <&rst WATCHDOG1_RESET>; 584 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 585 status = "disabled"; 586 }; 587 588 watchdog2: watchdog@ffd00400 { 589 compatible = "snps,dw-wdt"; 590 reg = <0xffd00400 0x100>; 591 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 592 resets = <&rst WATCHDOG2_RESET>; 593 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 594 status = "disabled"; 595 }; 596 597 watchdog3: watchdog@ffd00500 { 598 compatible = "snps,dw-wdt"; 599 reg = <0xffd00500 0x100>; 600 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 601 resets = <&rst WATCHDOG3_RESET>; 602 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 603 status = "disabled"; 604 }; 605 606 sdr: sdr@f8011100 { 607 compatible = "altr,sdr-ctl", "syscon"; 608 reg = <0xf8011100 0xc0>; 609 }; 610 611 eccmgr { 612 compatible = "altr,socfpga-s10-ecc-manager", 613 "altr,socfpga-a10-ecc-manager"; 614 altr,sysmgr-syscon = <&sysmgr>; 615 #address-cells = <1>; 616 #size-cells = <1>; 617 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 618 interrupt-controller; 619 #interrupt-cells = <2>; 620 ranges; 621 622 sdramedac { 623 compatible = "altr,sdram-edac-s10"; 624 altr,sdr-syscon = <&sdr>; 625 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 626 }; 627 628 ocram-ecc@ff8cc000 { 629 compatible = "altr,socfpga-s10-ocram-ecc", 630 "altr,socfpga-a10-ocram-ecc"; 631 reg = <0xff8cc000 0x100>; 632 altr,ecc-parent = <&ocram>; 633 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 634 }; 635 636 usb0-ecc@ff8c4000 { 637 compatible = "altr,socfpga-s10-usb-ecc", 638 "altr,socfpga-usb-ecc"; 639 reg = <0xff8c4000 0x100>; 640 altr,ecc-parent = <&usb0>; 641 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 642 }; 643 644 emac0-rx-ecc@ff8c0000 { 645 compatible = "altr,socfpga-s10-eth-mac-ecc", 646 "altr,socfpga-eth-mac-ecc"; 647 reg = <0xff8c0000 0x100>; 648 altr,ecc-parent = <&gmac0>; 649 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 650 }; 651 652 emac0-tx-ecc@ff8c0400 { 653 compatible = "altr,socfpga-s10-eth-mac-ecc", 654 "altr,socfpga-eth-mac-ecc"; 655 reg = <0xff8c0400 0x100>; 656 altr,ecc-parent = <&gmac0>; 657 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 658 }; 659 660 sdmmca-ecc@ff8c8c00 { 661 compatible = "altr,socfpga-s10-sdmmc-ecc", 662 "altr,socfpga-sdmmc-ecc"; 663 reg = <0xff8c8c00 0x100>; 664 altr,ecc-parent = <&mmc>; 665 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 666 <15 IRQ_TYPE_LEVEL_HIGH>; 667 }; 668 }; 669 670 qspi: spi@ff8d2000 { 671 compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 reg = <0xff8d2000 0x100>, 675 <0xff900000 0x100000>; 676 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 677 cdns,fifo-depth = <128>; 678 cdns,fifo-width = <4>; 679 cdns,trigger-address = <0x00000000>; 680 clocks = <&qspi_clk>; 681 682 status = "disabled"; 683 }; 684 }; 685}; 686