1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2019, Intel Corporation 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/agilex-clock.h> 11 12/ { 13 compatible = "intel,socfpga-agilex"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 reserved-memory { 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 22 service_reserved: svcbuffer@0 { 23 compatible = "shared-dma-pool"; 24 reg = <0x0 0x0 0x0 0x2000000>; 25 alignment = <0x1000>; 26 no-map; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 compatible = "arm,cortex-a53"; 36 device_type = "cpu"; 37 enable-method = "psci"; 38 reg = <0x0>; 39 }; 40 41 cpu1: cpu@1 { 42 compatible = "arm,cortex-a53"; 43 device_type = "cpu"; 44 enable-method = "psci"; 45 reg = <0x1>; 46 }; 47 48 cpu2: cpu@2 { 49 compatible = "arm,cortex-a53"; 50 device_type = "cpu"; 51 enable-method = "psci"; 52 reg = <0x2>; 53 }; 54 55 cpu3: cpu@3 { 56 compatible = "arm,cortex-a53"; 57 device_type = "cpu"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 }; 61 }; 62 63 firmware { 64 svc { 65 compatible = "intel,agilex-svc"; 66 method = "smc"; 67 memory-region = <&service_reserved>; 68 69 fpga_mgr: fpga-mgr { 70 compatible = "intel,agilex-soc-fpga-mgr"; 71 }; 72 }; 73 }; 74 75 fpga-region { 76 compatible = "fpga-region"; 77 #address-cells = <0x2>; 78 #size-cells = <0x2>; 79 fpga-mgr = <&fpga_mgr>; 80 }; 81 82 pmu { 83 compatible = "arm,cortex-a53-pmu"; 84 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 88 interrupt-affinity = <&cpu0>, 89 <&cpu1>, 90 <&cpu2>, 91 <&cpu3>; 92 interrupt-parent = <&intc>; 93 }; 94 95 psci { 96 compatible = "arm,psci-0.2"; 97 method = "smc"; 98 }; 99 100 intc: interrupt-controller@fffc1000 { 101 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 102 #interrupt-cells = <3>; 103 interrupt-controller; 104 interrupt-parent = <&intc>; 105 reg = <0x0 0xfffc1000 0x0 0x1000>, 106 <0x0 0xfffc2000 0x0 0x2000>, 107 <0x0 0xfffc4000 0x0 0x2000>, 108 <0x0 0xfffc6000 0x0 0x2000>; 109 /* VGIC maintenance interrupt */ 110 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 111 }; 112 113 clocks { 114 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 115 #clock-cells = <0>; 116 compatible = "fixed-clock"; 117 clock-frequency = <200000000>; 118 }; 119 120 cb_intosc_ls_clk: cb-intosc-ls-clk { 121 #clock-cells = <0>; 122 compatible = "fixed-clock"; 123 clock-frequency = <400000000>; 124 }; 125 126 f2s_free_clk: f2s-free-clk { 127 #clock-cells = <0>; 128 compatible = "fixed-clock"; 129 }; 130 131 osc1: osc1 { 132 #clock-cells = <0>; 133 compatible = "fixed-clock"; 134 }; 135 136 qspi_clk: qspi-clk { 137 #clock-cells = <0>; 138 compatible = "fixed-clock"; 139 clock-frequency = <200000000>; 140 }; 141 }; 142 143 timer { 144 compatible = "arm,armv8-timer"; 145 interrupt-parent = <&intc>; 146 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 147 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 148 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 149 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 150 }; 151 152 usbphy0: usbphy { 153 #phy-cells = <0>; 154 compatible = "usb-nop-xceiv"; 155 }; 156 157 soc@0 { 158 #address-cells = <1>; 159 #size-cells = <1>; 160 compatible = "simple-bus"; 161 device_type = "soc"; 162 interrupt-parent = <&intc>; 163 ranges = <0 0 0 0xffffffff>; 164 165 clkmgr: clock-controller@ffd10000 { 166 compatible = "intel,agilex-clkmgr"; 167 reg = <0xffd10000 0x1000>; 168 #clock-cells = <1>; 169 }; 170 171 gmac0: ethernet@ff800000 { 172 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 173 reg = <0xff800000 0x2000>; 174 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 175 interrupt-names = "macirq"; 176 mac-address = [00 00 00 00 00 00]; 177 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 178 reset-names = "stmmaceth", "ahb"; 179 tx-fifo-depth = <16384>; 180 rx-fifo-depth = <16384>; 181 snps,multicast-filter-bins = <256>; 182 iommus = <&smmu 1>; 183 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 184 clocks = <&clkmgr AGILEX_EMAC0_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 185 clock-names = "stmmaceth", "ptp_ref"; 186 status = "disabled"; 187 }; 188 189 gmac1: ethernet@ff802000 { 190 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 191 reg = <0xff802000 0x2000>; 192 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 193 interrupt-names = "macirq"; 194 mac-address = [00 00 00 00 00 00]; 195 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 196 reset-names = "stmmaceth", "ahb"; 197 tx-fifo-depth = <16384>; 198 rx-fifo-depth = <16384>; 199 snps,multicast-filter-bins = <256>; 200 iommus = <&smmu 2>; 201 altr,sysmgr-syscon = <&sysmgr 0x48 0>; 202 clocks = <&clkmgr AGILEX_EMAC1_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 203 clock-names = "stmmaceth", "ptp_ref"; 204 status = "disabled"; 205 }; 206 207 gmac2: ethernet@ff804000 { 208 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 209 reg = <0xff804000 0x2000>; 210 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 211 interrupt-names = "macirq"; 212 mac-address = [00 00 00 00 00 00]; 213 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 214 reset-names = "stmmaceth", "ahb"; 215 tx-fifo-depth = <16384>; 216 rx-fifo-depth = <16384>; 217 snps,multicast-filter-bins = <256>; 218 iommus = <&smmu 3>; 219 altr,sysmgr-syscon = <&sysmgr 0x4c 0>; 220 clocks = <&clkmgr AGILEX_EMAC2_CLK>, <&clkmgr AGILEX_EMAC_PTP_CLK>; 221 clock-names = "stmmaceth", "ptp_ref"; 222 status = "disabled"; 223 }; 224 225 gpio0: gpio@ffc03200 { 226 #address-cells = <1>; 227 #size-cells = <0>; 228 compatible = "snps,dw-apb-gpio"; 229 reg = <0xffc03200 0x100>; 230 resets = <&rst GPIO0_RESET>; 231 status = "disabled"; 232 233 porta: gpio-controller@0 { 234 compatible = "snps,dw-apb-gpio-port"; 235 gpio-controller; 236 #gpio-cells = <2>; 237 snps,nr-gpios = <24>; 238 reg = <0>; 239 interrupt-controller; 240 #interrupt-cells = <2>; 241 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 242 }; 243 }; 244 245 gpio1: gpio@ffc03300 { 246 #address-cells = <1>; 247 #size-cells = <0>; 248 compatible = "snps,dw-apb-gpio"; 249 reg = <0xffc03300 0x100>; 250 resets = <&rst GPIO1_RESET>; 251 status = "disabled"; 252 253 portb: gpio-controller@0 { 254 compatible = "snps,dw-apb-gpio-port"; 255 gpio-controller; 256 #gpio-cells = <2>; 257 snps,nr-gpios = <24>; 258 reg = <0>; 259 interrupt-controller; 260 #interrupt-cells = <2>; 261 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 262 }; 263 }; 264 265 i2c0: i2c@ffc02800 { 266 #address-cells = <1>; 267 #size-cells = <0>; 268 compatible = "snps,designware-i2c"; 269 reg = <0xffc02800 0x100>; 270 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 271 resets = <&rst I2C0_RESET>; 272 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 273 status = "disabled"; 274 }; 275 276 i2c1: i2c@ffc02900 { 277 #address-cells = <1>; 278 #size-cells = <0>; 279 compatible = "snps,designware-i2c"; 280 reg = <0xffc02900 0x100>; 281 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 282 resets = <&rst I2C1_RESET>; 283 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 284 status = "disabled"; 285 }; 286 287 i2c2: i2c@ffc02a00 { 288 #address-cells = <1>; 289 #size-cells = <0>; 290 compatible = "snps,designware-i2c"; 291 reg = <0xffc02a00 0x100>; 292 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 293 resets = <&rst I2C2_RESET>; 294 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 295 status = "disabled"; 296 }; 297 298 i2c3: i2c@ffc02b00 { 299 #address-cells = <1>; 300 #size-cells = <0>; 301 compatible = "snps,designware-i2c"; 302 reg = <0xffc02b00 0x100>; 303 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 304 resets = <&rst I2C3_RESET>; 305 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 306 status = "disabled"; 307 }; 308 309 i2c4: i2c@ffc02c00 { 310 #address-cells = <1>; 311 #size-cells = <0>; 312 compatible = "snps,designware-i2c"; 313 reg = <0xffc02c00 0x100>; 314 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 315 resets = <&rst I2C4_RESET>; 316 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 317 status = "disabled"; 318 }; 319 320 mmc: mmc@ff808000 { 321 #address-cells = <1>; 322 #size-cells = <0>; 323 compatible = "altr,socfpga-dw-mshc"; 324 reg = <0xff808000 0x1000>; 325 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 326 fifo-depth = <0x400>; 327 resets = <&rst SDMMC_RESET>; 328 reset-names = "reset"; 329 clocks = <&clkmgr AGILEX_L4_MP_CLK>, 330 <&clkmgr AGILEX_SDMMC_CLK>; 331 clock-names = "biu", "ciu"; 332 iommus = <&smmu 5>; 333 altr,sysmgr-syscon = <&sysmgr 0x28 4>; 334 status = "disabled"; 335 }; 336 337 nand: nand-controller@ffb90000 { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 compatible = "altr,socfpga-denali-nand"; 341 reg = <0xffb90000 0x10000>, 342 <0xffb80000 0x1000>; 343 reg-names = "nand_data", "denali_reg"; 344 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&clkmgr AGILEX_NAND_CLK>, 346 <&clkmgr AGILEX_NAND_X_CLK>, 347 <&clkmgr AGILEX_NAND_ECC_CLK>; 348 clock-names = "nand", "nand_x", "ecc"; 349 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 350 status = "disabled"; 351 }; 352 353 ocram: sram@ffe00000 { 354 compatible = "mmio-sram"; 355 reg = <0xffe00000 0x40000>; 356 #address-cells = <1>; 357 #size-cells = <1>; 358 ranges = <0 0xffe00000 0x40000>; 359 }; 360 361 pdma: dma-controller@ffda0000 { 362 compatible = "arm,pl330", "arm,primecell"; 363 reg = <0xffda0000 0x1000>; 364 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 373 #dma-cells = <1>; 374 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 375 reset-names = "dma", "dma-ocp"; 376 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 377 clock-names = "apb_pclk"; 378 }; 379 380 pinctrl0: pinctrl@ffd13000 { 381 compatible = "pinctrl-single"; 382 #pinctrl-cells = <1>; 383 reg = <0xffd13000 0xa0>; 384 pinctrl-single,register-width = <32>; 385 pinctrl-single,function-mask = <0x0000000f>; 386 }; 387 388 pinctrl1: pinctrl@ffd13100 { 389 compatible = "pinctrl-single"; 390 #pinctrl-cells = <1>; 391 reg = <0xffd13100 0x20>; 392 pinctrl-single,register-width = <32>; 393 }; 394 395 rst: rstmgr@ffd11000 { 396 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; 397 reg = <0xffd11000 0x100>; 398 #reset-cells = <1>; 399 }; 400 401 smmu: iommu@fa000000 { 402 compatible = "arm,mmu-500", "arm,smmu-v2"; 403 reg = <0xfa000000 0x40000>; 404 #global-interrupts = <2>; 405 #iommu-cells = <1>; 406 interrupt-parent = <&intc>; 407 /* Global Secure Fault */ 408 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 409 /* Global Non-secure Fault */ 410 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 411 /* Non-secure Context Interrupts (32) */ 412 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 444 stream-match-mask = <0x7ff0>; 445 clocks = <&clkmgr AGILEX_MPU_CCU_CLK>, 446 <&clkmgr AGILEX_L3_MAIN_FREE_CLK>, 447 <&clkmgr AGILEX_L4_MAIN_CLK>; 448 status = "disabled"; 449 }; 450 451 spi0: spi@ffda4000 { 452 compatible = "snps,dw-apb-ssi"; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 reg = <0xffda4000 0x1000>; 456 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 457 resets = <&rst SPIM0_RESET>; 458 reset-names = "spi"; 459 reg-io-width = <4>; 460 num-cs = <4>; 461 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 462 dmas = <&pdma 16>, <&pdma 17>; 463 dma-names = "tx", "rx"; 464 status = "disabled"; 465 }; 466 467 spi1: spi@ffda5000 { 468 compatible = "snps,dw-apb-ssi"; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 reg = <0xffda5000 0x1000>; 472 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 473 resets = <&rst SPIM1_RESET>; 474 reset-names = "spi"; 475 reg-io-width = <4>; 476 num-cs = <4>; 477 clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; 478 dmas = <&pdma 20>, <&pdma 21>; 479 dma-names = "tx", "rx"; 480 status = "disabled"; 481 }; 482 483 sysmgr: sysmgr@ffd12000 { 484 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 485 reg = <0xffd12000 0x500>; 486 }; 487 488 timer0: timer0@ffc03000 { 489 compatible = "snps,dw-apb-timer"; 490 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 491 reg = <0xffc03000 0x100>; 492 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 493 clock-names = "timer"; 494 }; 495 496 timer1: timer1@ffc03100 { 497 compatible = "snps,dw-apb-timer"; 498 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 499 reg = <0xffc03100 0x100>; 500 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 501 clock-names = "timer"; 502 }; 503 504 timer2: timer2@ffd00000 { 505 compatible = "snps,dw-apb-timer"; 506 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 507 reg = <0xffd00000 0x100>; 508 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 509 clock-names = "timer"; 510 }; 511 512 timer3: timer3@ffd00100 { 513 compatible = "snps,dw-apb-timer"; 514 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 515 reg = <0xffd00100 0x100>; 516 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 517 clock-names = "timer"; 518 }; 519 520 uart0: serial@ffc02000 { 521 compatible = "snps,dw-apb-uart"; 522 reg = <0xffc02000 0x100>; 523 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 524 reg-shift = <2>; 525 reg-io-width = <4>; 526 resets = <&rst UART0_RESET>; 527 status = "disabled"; 528 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 529 }; 530 531 uart1: serial@ffc02100 { 532 compatible = "snps,dw-apb-uart"; 533 reg = <0xffc02100 0x100>; 534 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 535 reg-shift = <2>; 536 reg-io-width = <4>; 537 resets = <&rst UART1_RESET>; 538 clocks = <&clkmgr AGILEX_L4_SP_CLK>; 539 status = "disabled"; 540 }; 541 542 usb0: usb@ffb00000 { 543 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; 544 reg = <0xffb00000 0x40000>; 545 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 546 phys = <&usbphy0>; 547 phy-names = "usb2-phy"; 548 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 549 reset-names = "dwc2", "dwc2-ecc"; 550 clocks = <&clkmgr AGILEX_USB_CLK>; 551 clock-names = "otg"; 552 iommus = <&smmu 6>; 553 status = "disabled"; 554 }; 555 556 usb1: usb@ffb40000 { 557 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; 558 reg = <0xffb40000 0x40000>; 559 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 560 phys = <&usbphy0>; 561 phy-names = "usb2-phy"; 562 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 563 reset-names = "dwc2", "dwc2-ecc"; 564 iommus = <&smmu 7>; 565 clocks = <&clkmgr AGILEX_USB_CLK>; 566 status = "disabled"; 567 }; 568 569 watchdog0: watchdog@ffd00200 { 570 compatible = "snps,dw-wdt"; 571 reg = <0xffd00200 0x100>; 572 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 573 resets = <&rst WATCHDOG0_RESET>; 574 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 575 status = "disabled"; 576 }; 577 578 watchdog1: watchdog@ffd00300 { 579 compatible = "snps,dw-wdt"; 580 reg = <0xffd00300 0x100>; 581 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 582 resets = <&rst WATCHDOG1_RESET>; 583 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 584 status = "disabled"; 585 }; 586 587 watchdog2: watchdog@ffd00400 { 588 compatible = "snps,dw-wdt"; 589 reg = <0xffd00400 0x100>; 590 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 591 resets = <&rst WATCHDOG2_RESET>; 592 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 593 status = "disabled"; 594 }; 595 596 watchdog3: watchdog@ffd00500 { 597 compatible = "snps,dw-wdt"; 598 reg = <0xffd00500 0x100>; 599 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 600 resets = <&rst WATCHDOG3_RESET>; 601 clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>; 602 status = "disabled"; 603 }; 604 605 sdr: sdr@f8011100 { 606 compatible = "altr,sdr-ctl", "syscon"; 607 reg = <0xf8011100 0xc0>; 608 }; 609 610 eccmgr { 611 compatible = "altr,socfpga-s10-ecc-manager", 612 "altr,socfpga-a10-ecc-manager"; 613 altr,sysmgr-syscon = <&sysmgr>; 614 #address-cells = <1>; 615 #size-cells = <1>; 616 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 617 interrupt-controller; 618 #interrupt-cells = <2>; 619 ranges; 620 621 sdramedac { 622 compatible = "altr,sdram-edac-s10"; 623 altr,sdr-syscon = <&sdr>; 624 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 625 }; 626 627 ocram-ecc@ff8cc000 { 628 compatible = "altr,socfpga-s10-ocram-ecc", 629 "altr,socfpga-a10-ocram-ecc"; 630 reg = <0xff8cc000 0x100>; 631 altr,ecc-parent = <&ocram>; 632 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 633 }; 634 635 usb0-ecc@ff8c4000 { 636 compatible = "altr,socfpga-s10-usb-ecc", 637 "altr,socfpga-usb-ecc"; 638 reg = <0xff8c4000 0x100>; 639 altr,ecc-parent = <&usb0>; 640 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 641 }; 642 643 emac0-rx-ecc@ff8c0000 { 644 compatible = "altr,socfpga-s10-eth-mac-ecc", 645 "altr,socfpga-eth-mac-ecc"; 646 reg = <0xff8c0000 0x100>; 647 altr,ecc-parent = <&gmac0>; 648 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 649 }; 650 651 emac0-tx-ecc@ff8c0400 { 652 compatible = "altr,socfpga-s10-eth-mac-ecc", 653 "altr,socfpga-eth-mac-ecc"; 654 reg = <0xff8c0400 0x100>; 655 altr,ecc-parent = <&gmac0>; 656 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 657 }; 658 659 sdmmca-ecc@ff8c8c00 { 660 compatible = "altr,socfpga-s10-sdmmc-ecc", 661 "altr,socfpga-sdmmc-ecc"; 662 reg = <0xff8c8c00 0x100>; 663 altr,ecc-parent = <&mmc>; 664 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 665 <15 IRQ_TYPE_LEVEL_HIGH>; 666 }; 667 }; 668 669 qspi: spi@ff8d2000 { 670 compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 reg = <0xff8d2000 0x100>, 674 <0xff900000 0x100000>; 675 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 676 cdns,fifo-depth = <128>; 677 cdns,fifo-width = <4>; 678 cdns,trigger-address = <0x00000000>; 679 clocks = <&qspi_clk>; 680 681 status = "disabled"; 682 }; 683 }; 684}; 685