1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __SMU_V14_0_H__ 24 #define __SMU_V14_0_H__ 25 26 #include "amdgpu_smu.h" 27 28 #define SMU14_DRIVER_IF_VERSION_INV 0xFFFFFFFF 29 #define SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 0x7 30 #define SMU14_DRIVER_IF_VERSION_SMU_V14_0_1 0x6 31 #define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x26 32 33 #define FEATURE_MASK(feature) (1ULL << feature) 34 35 /* MP Apertures */ 36 #define MP0_Public 0x03800000 37 #define MP0_SRAM 0x03900000 38 #define MP1_Public 0x03b00000 39 #define MP1_SRAM 0x03c00004 40 41 /* address block */ 42 #define smnMP1_FIRMWARE_FLAGS_14_0_0 0x3010028 43 #define smnMP1_FIRMWARE_FLAGS 0x3010024 44 #define smnMP1_PUB_CTRL 0x3010d10 45 46 #define MAX_DPM_LEVELS 16 47 #define MAX_PCIE_CONF 3 48 49 #define SMU14_TOOL_SIZE 0x19000 50 51 #define CTF_OFFSET_EDGE 5 52 #define CTF_OFFSET_HOTSPOT 5 53 #define CTF_OFFSET_MEM 5 54 55 extern const int decoded_link_speed[5]; 56 extern const int decoded_link_width[7]; 57 58 #define DECODE_GEN_SPEED(gen_speed_idx) (decoded_link_speed[gen_speed_idx]) 59 #define DECODE_LANE_WIDTH(lane_width_idx) (decoded_link_width[lane_width_idx]) 60 61 struct smu_14_0_max_sustainable_clocks { 62 uint32_t display_clock; 63 uint32_t phy_clock; 64 uint32_t pixel_clock; 65 uint32_t uclock; 66 uint32_t dcef_clock; 67 uint32_t soc_clock; 68 }; 69 70 struct smu_14_0_dpm_clk_level { 71 bool enabled; 72 uint32_t value; 73 }; 74 75 struct smu_14_0_dpm_table { 76 uint32_t min; /* MHz */ 77 uint32_t max; /* MHz */ 78 uint32_t count; 79 bool is_fine_grained; 80 struct smu_14_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS]; 81 }; 82 83 struct smu_14_0_pcie_table { 84 uint8_t pcie_gen[MAX_PCIE_CONF]; 85 uint8_t pcie_lane[MAX_PCIE_CONF]; 86 uint16_t clk_freq[MAX_PCIE_CONF]; 87 uint32_t num_of_link_levels; 88 }; 89 90 struct smu_14_0_dpm_tables { 91 struct smu_14_0_dpm_table soc_table; 92 struct smu_14_0_dpm_table gfx_table; 93 struct smu_14_0_dpm_table uclk_table; 94 struct smu_14_0_dpm_table eclk_table; 95 struct smu_14_0_dpm_table vclk_table; 96 struct smu_14_0_dpm_table dclk_table; 97 struct smu_14_0_dpm_table dcef_table; 98 struct smu_14_0_dpm_table pixel_table; 99 struct smu_14_0_dpm_table display_table; 100 struct smu_14_0_dpm_table phy_table; 101 struct smu_14_0_dpm_table fclk_table; 102 struct smu_14_0_pcie_table pcie_table; 103 }; 104 105 struct smu_14_0_dpm_context { 106 struct smu_14_0_dpm_tables dpm_tables; 107 uint32_t workload_policy_mask; 108 uint32_t dcef_min_ds_clk; 109 }; 110 111 enum smu_14_0_power_state { 112 SMU_14_0_POWER_STATE__D0 = 0, 113 SMU_14_0_POWER_STATE__D1, 114 SMU_14_0_POWER_STATE__D3, /* Sleep*/ 115 SMU_14_0_POWER_STATE__D4, /* Hibernate*/ 116 SMU_14_0_POWER_STATE__D5, /* Power off*/ 117 }; 118 119 struct smu_14_0_power_context { 120 uint32_t power_source; 121 uint8_t in_power_limit_boost_mode; 122 enum smu_14_0_power_state power_state; 123 }; 124 125 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) 126 127 int smu_v14_0_init_microcode(struct smu_context *smu); 128 129 void smu_v14_0_fini_microcode(struct smu_context *smu); 130 131 int smu_v14_0_load_microcode(struct smu_context *smu); 132 133 int smu_v14_0_init_smc_tables(struct smu_context *smu); 134 135 int smu_v14_0_fini_smc_tables(struct smu_context *smu); 136 137 int smu_v14_0_init_power(struct smu_context *smu); 138 139 int smu_v14_0_fini_power(struct smu_context *smu); 140 141 int smu_v14_0_check_fw_status(struct smu_context *smu); 142 143 int smu_v14_0_setup_pptable(struct smu_context *smu); 144 145 int smu_v14_0_get_vbios_bootup_values(struct smu_context *smu); 146 147 int smu_v14_0_check_fw_version(struct smu_context *smu); 148 149 int smu_v14_0_set_driver_table_location(struct smu_context *smu); 150 151 int smu_v14_0_set_tool_table_location(struct smu_context *smu); 152 153 int smu_v14_0_notify_memory_pool_location(struct smu_context *smu); 154 155 int smu_v14_0_system_features_control(struct smu_context *smu, 156 bool en); 157 158 int smu_v14_0_set_allowed_mask(struct smu_context *smu); 159 160 int smu_v14_0_notify_display_change(struct smu_context *smu); 161 162 int smu_v14_0_get_current_power_limit(struct smu_context *smu, 163 uint32_t *power_limit); 164 165 int smu_v14_0_set_power_limit(struct smu_context *smu, 166 enum smu_ppt_limit_type limit_type, 167 uint32_t limit); 168 169 int smu_v14_0_gfx_off_control(struct smu_context *smu, bool enable); 170 171 int smu_v14_0_register_irq_handler(struct smu_context *smu); 172 173 int smu_v14_0_baco_set_armd3_sequence(struct smu_context *smu, 174 enum smu_baco_seq baco_seq); 175 176 int smu_v14_0_get_bamaco_support(struct smu_context *smu); 177 178 enum smu_baco_state smu_v14_0_baco_get_state(struct smu_context *smu); 179 180 int smu_v14_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state); 181 182 int smu_v14_0_baco_enter(struct smu_context *smu); 183 int smu_v14_0_baco_exit(struct smu_context *smu); 184 185 int smu_v14_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 186 uint32_t *min, uint32_t *max); 187 188 int smu_v14_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 189 uint32_t min, uint32_t max); 190 191 int smu_v14_0_set_hard_freq_limited_range(struct smu_context *smu, 192 enum smu_clk_type clk_type, 193 uint32_t min, 194 uint32_t max); 195 196 int smu_v14_0_set_performance_level(struct smu_context *smu, 197 enum amd_dpm_forced_level level); 198 199 int smu_v14_0_set_power_source(struct smu_context *smu, 200 enum smu_power_src_type power_src); 201 202 int smu_v14_0_set_single_dpm_table(struct smu_context *smu, 203 enum smu_clk_type clk_type, 204 struct smu_14_0_dpm_table *single_dpm_table); 205 206 int smu_v14_0_gfx_ulv_control(struct smu_context *smu, 207 bool enablement); 208 209 int smu_v14_0_wait_for_event(struct smu_context *smu, enum smu_event_type event, 210 uint64_t event_arg); 211 212 int smu_v14_0_set_vcn_enable(struct smu_context *smu, 213 bool enable); 214 215 int smu_v14_0_set_jpeg_enable(struct smu_context *smu, 216 bool enable); 217 218 int smu_v14_0_init_pptable_microcode(struct smu_context *smu); 219 220 int smu_v14_0_run_btc(struct smu_context *smu); 221 222 int smu_v14_0_gpo_control(struct smu_context *smu, 223 bool enablement); 224 225 int smu_v14_0_deep_sleep_control(struct smu_context *smu, 226 bool enablement); 227 228 int smu_v14_0_set_gfx_power_up_by_imu(struct smu_context *smu); 229 230 int smu_v14_0_set_default_dpm_tables(struct smu_context *smu); 231 232 int smu_v14_0_get_pptable_from_firmware(struct smu_context *smu, 233 void **table, 234 uint32_t *size, 235 uint32_t pptable_id); 236 237 int smu_v14_0_od_edit_dpm_table(struct smu_context *smu, 238 enum PP_OD_DPM_TABLE_COMMAND type, 239 long input[], uint32_t size); 240 241 void smu_v14_0_set_smu_mailbox_registers(struct smu_context *smu); 242 243 int smu_v14_0_enable_thermal_alert(struct smu_context *smu); 244 245 int smu_v14_0_disable_thermal_alert(struct smu_context *smu); 246 247 #endif 248 #endif 249