1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __SMU_CMN_H__ 24 #define __SMU_CMN_H__ 25 26 #include "amdgpu_smu.h" 27 28 extern const struct smu_msg_ops smu_msg_v1_ops; 29 30 int smu_msg_wait_response(struct smu_msg_ctl *ctl, u32 timeout_us); 31 int smu_msg_send_async_locked(struct smu_msg_ctl *ctl, 32 enum smu_message_type msg, u32 param); 33 34 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4) 35 36 #define FDO_PWM_MODE_STATIC 1 37 #define FDO_PWM_MODE_STATIC_RPM 5 38 39 #define SMU_IH_INTERRUPT_ID_TO_DRIVER 0xFE 40 #define SMU_IH_INTERRUPT_CONTEXT_ID_BACO 0x2 41 #define SMU_IH_INTERRUPT_CONTEXT_ID_AC 0x3 42 #define SMU_IH_INTERRUPT_CONTEXT_ID_DC 0x4 43 #define SMU_IH_INTERRUPT_CONTEXT_ID_AUDIO_D0 0x5 44 #define SMU_IH_INTERRUPT_CONTEXT_ID_AUDIO_D3 0x6 45 #define SMU_IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 46 #define SMU_IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 47 #define SMU_IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 48 49 #define SMU_IGNORE_IF_VERSION 0xFFFFFFFF 50 51 #define smu_cmn_init_soft_gpu_metrics(ptr, frev, crev) \ 52 do { \ 53 typecheck(struct gpu_metrics_v##frev##_##crev *, (ptr)); \ 54 struct gpu_metrics_v##frev##_##crev *tmp = (ptr); \ 55 struct metrics_table_header *header = \ 56 (struct metrics_table_header *)tmp; \ 57 memset(header, 0xFF, sizeof(*tmp)); \ 58 header->format_revision = frev; \ 59 header->content_revision = crev; \ 60 header->structure_size = sizeof(*tmp); \ 61 } while (0) 62 63 #define smu_cmn_init_partition_metrics(ptr, fr, cr) \ 64 do { \ 65 typecheck(struct amdgpu_partition_metrics_v##fr##_##cr *, \ 66 (ptr)); \ 67 struct amdgpu_partition_metrics_v##fr##_##cr *tmp = (ptr); \ 68 struct metrics_table_header *header = \ 69 (struct metrics_table_header *)tmp; \ 70 memset(header, 0xFF, sizeof(*tmp)); \ 71 header->format_revision = fr; \ 72 header->content_revision = cr; \ 73 header->structure_size = sizeof(*tmp); \ 74 } while (0) 75 76 #define smu_cmn_init_baseboard_temp_metrics(ptr, fr, cr) \ 77 do { \ 78 typecheck(struct amdgpu_baseboard_temp_metrics_v##fr##_##cr *, \ 79 (ptr)); \ 80 struct amdgpu_baseboard_temp_metrics_v##fr##_##cr *tmp = (ptr); \ 81 struct metrics_table_header *header = \ 82 (struct metrics_table_header *)tmp; \ 83 memset(header, 0xFF, sizeof(*tmp)); \ 84 header->format_revision = fr; \ 85 header->content_revision = cr; \ 86 header->structure_size = sizeof(*tmp); \ 87 } while (0) 88 89 #define smu_cmn_init_gpuboard_temp_metrics(ptr, fr, cr) \ 90 do { \ 91 typecheck(struct amdgpu_gpuboard_temp_metrics_v##fr##_##cr *, \ 92 (ptr)); \ 93 struct amdgpu_gpuboard_temp_metrics_v##fr##_##cr *tmp = (ptr); \ 94 struct metrics_table_header *header = \ 95 (struct metrics_table_header *)tmp; \ 96 memset(header, 0xFF, sizeof(*tmp)); \ 97 header->format_revision = fr; \ 98 header->content_revision = cr; \ 99 header->structure_size = sizeof(*tmp); \ 100 } while (0) 101 102 #define SMU_DPM_PCIE_GEN_IDX(gen) smu_cmn_dpm_pcie_gen_idx((gen)) 103 #define SMU_DPM_PCIE_WIDTH_IDX(width) smu_cmn_dpm_pcie_width_idx((width)) 104 105 #define smu_cmn_update_table(smu, table_index, argument, table_data, drv2smu) \ 106 smu_cmn_update_table_read_arg((smu), (table_index), (argument), (table_data), NULL, (drv2smu)) 107 108 extern const int link_speed[]; 109 110 /* Helper to Convert from PCIE Gen 1/2/3/4/5/6 to 0.1 GT/s speed units */ 111 static inline int pcie_gen_to_speed(uint32_t gen) 112 { 113 return ((gen == 0) ? link_speed[0] : link_speed[gen - 1]); 114 } 115 116 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu, 117 enum smu_message_type msg, 118 uint32_t param, 119 uint32_t *read_arg); 120 121 int smu_cmn_send_smc_msg_with_params_ext(struct smu_context *smu, 122 enum smu_message_type msg, 123 const uint32_t *params, 124 size_t num_params, 125 uint32_t *read_args, 126 size_t num_read_args, 127 uint32_t flags, 128 uint32_t timeout); 129 130 static inline int smu_cmn_send_smc_msg_with_params(struct smu_context *smu, 131 enum smu_message_type msg, 132 const uint32_t *params, 133 size_t num_params, 134 uint32_t *read_args, 135 size_t num_read_args) 136 { 137 return smu_cmn_send_smc_msg_with_params_ext(smu, msg, 138 params, num_params, 139 read_args, num_read_args, 140 0, 0); 141 } 142 143 int smu_cmn_send_smc_msg(struct smu_context *smu, 144 enum smu_message_type msg, 145 uint32_t *read_arg); 146 147 int smu_cmn_send_debug_smc_msg(struct smu_context *smu, 148 uint32_t msg); 149 150 int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu, 151 uint32_t msg, uint32_t param); 152 153 int smu_cmn_wait_for_response(struct smu_context *smu); 154 155 int smu_cmn_to_asic_specific_index(struct smu_context *smu, 156 enum smu_cmn2asic_mapping_type type, 157 uint32_t index); 158 159 int smu_cmn_feature_is_supported(struct smu_context *smu, 160 enum smu_feature_mask mask); 161 162 int smu_cmn_feature_is_enabled(struct smu_context *smu, 163 enum smu_feature_mask mask); 164 165 bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu, 166 enum smu_clk_type clk_type); 167 168 int smu_cmn_get_enabled_mask(struct smu_context *smu, 169 struct smu_feature_bits *feature_mask); 170 171 uint64_t smu_cmn_get_indep_throttler_status( 172 const unsigned long dep_status, 173 const uint8_t *throttler_map); 174 175 int smu_cmn_feature_update_enable_state(struct smu_context *smu, 176 uint64_t feature_mask, 177 bool enabled); 178 179 int smu_cmn_feature_set_enabled(struct smu_context *smu, 180 enum smu_feature_mask mask, 181 bool enable); 182 183 size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, 184 char *buf); 185 186 int smu_cmn_set_pp_feature_mask(struct smu_context *smu, 187 uint64_t new_mask); 188 189 int smu_cmn_disable_all_features_with_exception(struct smu_context *smu, 190 enum smu_feature_mask mask); 191 192 int smu_cmn_get_smc_version(struct smu_context *smu, 193 uint32_t *if_version, 194 uint32_t *smu_version); 195 196 int smu_cmn_update_table_read_arg(struct smu_context *smu, 197 enum smu_table_id table_index, 198 int argument, 199 void *table_data, 200 uint32_t *read_arg, 201 bool drv2smu); 202 203 int smu_cmn_vram_cpy(struct smu_context *smu, void *dst, 204 const void *src, size_t len); 205 206 int smu_cmn_write_watermarks_table(struct smu_context *smu); 207 208 int smu_cmn_write_pptable(struct smu_context *smu); 209 210 int smu_cmn_get_metrics_table(struct smu_context *smu, 211 void *metrics_table, 212 bool bypass_cache); 213 214 int smu_cmn_get_combo_pptable(struct smu_context *smu); 215 216 int smu_cmn_set_mp1_state(struct smu_context *smu, 217 enum pp_mp1_state mp1_state); 218 219 bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev); 220 void smu_cmn_generic_soc_policy_desc(struct smu_dpm_policy *policy); 221 void smu_cmn_generic_plpd_policy_desc(struct smu_dpm_policy *policy); 222 223 void smu_cmn_get_backend_workload_mask(struct smu_context *smu, 224 u32 workload_mask, 225 u32 *backend_workload_mask); 226 227 int smu_cmn_print_dpm_clk_levels(struct smu_context *smu, 228 struct smu_dpm_table *dpm_table, 229 uint32_t cur_clk, 230 char *buf, int *offset); 231 232 int smu_cmn_print_pcie_levels(struct smu_context *smu, 233 struct smu_pcie_table *pcie_table, 234 uint32_t cur_gen, uint32_t cur_lane, 235 char *buf, int *offset); 236 void smu_cmn_reset_custom_level(struct smu_context *smu); 237 238 int smu_cmn_dpm_pcie_gen_idx(int gen); 239 int smu_cmn_dpm_pcie_width_idx(int width); 240 int smu_cmn_check_fw_version(struct smu_context *smu); 241 242 /*SMU gpu metrics */ 243 244 /* Attribute ID mapping */ 245 #define SMU_MATTR(X) AMDGPU_METRICS_ATTR_ID_##X 246 /* Type ID mapping */ 247 #define SMU_MTYPE(X) AMDGPU_METRICS_TYPE_##X 248 /* Unit ID mapping */ 249 #define SMU_MUNIT(X) AMDGPU_METRICS_UNIT_##X 250 251 /* Map TYPEID to C type */ 252 #define SMU_CTYPE(TYPEID) SMU_CTYPE_##TYPEID 253 254 #define SMU_CTYPE_AMDGPU_METRICS_TYPE_U8 u8 255 #define SMU_CTYPE_AMDGPU_METRICS_TYPE_S8 s8 256 #define SMU_CTYPE_AMDGPU_METRICS_TYPE_U16 u16 257 #define SMU_CTYPE_AMDGPU_METRICS_TYPE_S16 s16 258 #define SMU_CTYPE_AMDGPU_METRICS_TYPE_U32 u32 259 #define SMU_CTYPE_AMDGPU_METRICS_TYPE_S32 s32 260 #define SMU_CTYPE_AMDGPU_METRICS_TYPE_U64 u64 261 #define SMU_CTYPE_AMDGPU_METRICS_TYPE_S64 s64 262 263 /* struct members */ 264 #define SMU_METRICS_SCALAR(ID, UNIT, TYPEID, NAME) \ 265 u64 NAME##_ftype; \ 266 SMU_CTYPE(TYPEID) NAME 267 268 #define SMU_METRICS_ARRAY(ID, UNIT, TYPEID, NAME, SIZE) \ 269 u64 NAME##_ftype; \ 270 SMU_CTYPE(TYPEID) NAME[SIZE] 271 272 /* Init functions for scalar/array fields - init to 0xFFs */ 273 #define SMU_METRICS_INIT_SCALAR(ID, UNIT, TYPEID, NAME) \ 274 do { \ 275 obj->NAME##_ftype = \ 276 AMDGPU_METRICS_ENC_ATTR(UNIT, TYPEID, ID, 1); \ 277 obj->NAME = (SMU_CTYPE(TYPEID)) ~0; \ 278 count++; \ 279 } while (0) 280 281 #define SMU_METRICS_INIT_ARRAY(ID, UNIT, TYPEID, NAME, SIZE) \ 282 do { \ 283 obj->NAME##_ftype = \ 284 AMDGPU_METRICS_ENC_ATTR(UNIT, TYPEID, ID, SIZE); \ 285 memset(obj->NAME, 0xFF, sizeof(obj->NAME)); \ 286 count++; \ 287 } while (0) 288 289 /* Declare Metrics Class and Template object */ 290 #define DECLARE_SMU_METRICS_CLASS(CLASSNAME, SMU_METRICS_FIELD_LIST) \ 291 struct __packed CLASSNAME { \ 292 struct metrics_table_header header; \ 293 int attr_count; \ 294 SMU_METRICS_FIELD_LIST(SMU_METRICS_SCALAR, SMU_METRICS_ARRAY); \ 295 }; \ 296 static inline void CLASSNAME##_init(struct CLASSNAME *obj, \ 297 uint8_t frev, uint8_t crev) \ 298 { \ 299 int count = 0; \ 300 memset(obj, 0xFF, sizeof(*obj)); \ 301 obj->header.format_revision = frev; \ 302 obj->header.content_revision = crev; \ 303 obj->header.structure_size = sizeof(*obj); \ 304 SMU_METRICS_FIELD_LIST(SMU_METRICS_INIT_SCALAR, \ 305 SMU_METRICS_INIT_ARRAY) \ 306 obj->attr_count = count; \ 307 } 308 309 #endif 310 #endif 311