1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sm8250.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sm8250.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/soc/qcom,apr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6afe.h> 23#include <dt-bindings/thermal/thermal.h> 24#include <dt-bindings/clock/qcom,camcc-sm8250.h> 25#include <dt-bindings/clock/qcom,videocc-sm8250.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 aliases { 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 i2c12 = &i2c12; 47 i2c13 = &i2c13; 48 i2c14 = &i2c14; 49 i2c15 = &i2c15; 50 i2c16 = &i2c16; 51 i2c17 = &i2c17; 52 i2c18 = &i2c18; 53 i2c19 = &i2c19; 54 spi0 = &spi0; 55 spi1 = &spi1; 56 spi2 = &spi2; 57 spi3 = &spi3; 58 spi4 = &spi4; 59 spi5 = &spi5; 60 spi6 = &spi6; 61 spi7 = &spi7; 62 spi8 = &spi8; 63 spi9 = &spi9; 64 spi10 = &spi10; 65 spi11 = &spi11; 66 spi12 = &spi12; 67 spi13 = &spi13; 68 spi14 = &spi14; 69 spi15 = &spi15; 70 spi16 = &spi16; 71 spi17 = &spi17; 72 spi18 = &spi18; 73 spi19 = &spi19; 74 }; 75 76 chosen { }; 77 78 clocks { 79 xo_board: xo-board { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 clock-frequency = <38400000>; 83 clock-output-names = "xo_board"; 84 }; 85 86 sleep_clk: sleep-clk { 87 compatible = "fixed-clock"; 88 clock-frequency = <32764>; 89 #clock-cells = <0>; 90 }; 91 }; 92 93 cpus { 94 #address-cells = <2>; 95 #size-cells = <0>; 96 97 cpu0: cpu@0 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo485"; 100 reg = <0x0 0x0>; 101 clocks = <&cpufreq_hw 0>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <448>; 104 dynamic-power-coefficient = <105>; 105 next-level-cache = <&l2_0>; 106 power-domains = <&cpu_pd0>; 107 power-domain-names = "psci"; 108 qcom,freq-domain = <&cpufreq_hw 0>; 109 operating-points-v2 = <&cpu0_opp_table>; 110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 111 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 112 #cooling-cells = <2>; 113 l2_0: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-size = <0x20000>; 117 cache-unified; 118 next-level-cache = <&l3_0>; 119 l3_0: l3-cache { 120 compatible = "cache"; 121 cache-level = <3>; 122 cache-size = <0x400000>; 123 cache-unified; 124 }; 125 }; 126 }; 127 128 cpu1: cpu@100 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo485"; 131 reg = <0x0 0x100>; 132 clocks = <&cpufreq_hw 0>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <448>; 135 dynamic-power-coefficient = <105>; 136 next-level-cache = <&l2_100>; 137 power-domains = <&cpu_pd1>; 138 power-domain-names = "psci"; 139 qcom,freq-domain = <&cpufreq_hw 0>; 140 operating-points-v2 = <&cpu0_opp_table>; 141 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 142 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 143 #cooling-cells = <2>; 144 l2_100: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-size = <0x20000>; 148 cache-unified; 149 next-level-cache = <&l3_0>; 150 }; 151 }; 152 153 cpu2: cpu@200 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo485"; 156 reg = <0x0 0x200>; 157 clocks = <&cpufreq_hw 0>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <448>; 160 dynamic-power-coefficient = <105>; 161 next-level-cache = <&l2_200>; 162 power-domains = <&cpu_pd2>; 163 power-domain-names = "psci"; 164 qcom,freq-domain = <&cpufreq_hw 0>; 165 operating-points-v2 = <&cpu0_opp_table>; 166 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 167 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 168 #cooling-cells = <2>; 169 l2_200: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-size = <0x20000>; 173 cache-unified; 174 next-level-cache = <&l3_0>; 175 }; 176 }; 177 178 cpu3: cpu@300 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo485"; 181 reg = <0x0 0x300>; 182 clocks = <&cpufreq_hw 0>; 183 enable-method = "psci"; 184 capacity-dmips-mhz = <448>; 185 dynamic-power-coefficient = <105>; 186 next-level-cache = <&l2_300>; 187 power-domains = <&cpu_pd3>; 188 power-domain-names = "psci"; 189 qcom,freq-domain = <&cpufreq_hw 0>; 190 operating-points-v2 = <&cpu0_opp_table>; 191 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 192 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 193 #cooling-cells = <2>; 194 l2_300: l2-cache { 195 compatible = "cache"; 196 cache-level = <2>; 197 cache-size = <0x20000>; 198 cache-unified; 199 next-level-cache = <&l3_0>; 200 }; 201 }; 202 203 cpu4: cpu@400 { 204 device_type = "cpu"; 205 compatible = "qcom,kryo485"; 206 reg = <0x0 0x400>; 207 clocks = <&cpufreq_hw 1>; 208 enable-method = "psci"; 209 capacity-dmips-mhz = <1024>; 210 dynamic-power-coefficient = <379>; 211 next-level-cache = <&l2_400>; 212 power-domains = <&cpu_pd4>; 213 power-domain-names = "psci"; 214 qcom,freq-domain = <&cpufreq_hw 1>; 215 operating-points-v2 = <&cpu4_opp_table>; 216 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 217 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 218 #cooling-cells = <2>; 219 l2_400: l2-cache { 220 compatible = "cache"; 221 cache-level = <2>; 222 cache-size = <0x40000>; 223 cache-unified; 224 next-level-cache = <&l3_0>; 225 }; 226 }; 227 228 cpu5: cpu@500 { 229 device_type = "cpu"; 230 compatible = "qcom,kryo485"; 231 reg = <0x0 0x500>; 232 clocks = <&cpufreq_hw 1>; 233 enable-method = "psci"; 234 capacity-dmips-mhz = <1024>; 235 dynamic-power-coefficient = <379>; 236 next-level-cache = <&l2_500>; 237 power-domains = <&cpu_pd5>; 238 power-domain-names = "psci"; 239 qcom,freq-domain = <&cpufreq_hw 1>; 240 operating-points-v2 = <&cpu4_opp_table>; 241 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 242 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 243 #cooling-cells = <2>; 244 l2_500: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-size = <0x40000>; 248 cache-unified; 249 next-level-cache = <&l3_0>; 250 }; 251 }; 252 253 cpu6: cpu@600 { 254 device_type = "cpu"; 255 compatible = "qcom,kryo485"; 256 reg = <0x0 0x600>; 257 clocks = <&cpufreq_hw 1>; 258 enable-method = "psci"; 259 capacity-dmips-mhz = <1024>; 260 dynamic-power-coefficient = <379>; 261 next-level-cache = <&l2_600>; 262 power-domains = <&cpu_pd6>; 263 power-domain-names = "psci"; 264 qcom,freq-domain = <&cpufreq_hw 1>; 265 operating-points-v2 = <&cpu4_opp_table>; 266 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 267 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 268 #cooling-cells = <2>; 269 l2_600: l2-cache { 270 compatible = "cache"; 271 cache-level = <2>; 272 cache-size = <0x40000>; 273 cache-unified; 274 next-level-cache = <&l3_0>; 275 }; 276 }; 277 278 cpu7: cpu@700 { 279 device_type = "cpu"; 280 compatible = "qcom,kryo485"; 281 reg = <0x0 0x700>; 282 clocks = <&cpufreq_hw 2>; 283 enable-method = "psci"; 284 capacity-dmips-mhz = <1024>; 285 dynamic-power-coefficient = <444>; 286 next-level-cache = <&l2_700>; 287 power-domains = <&cpu_pd7>; 288 power-domain-names = "psci"; 289 qcom,freq-domain = <&cpufreq_hw 2>; 290 operating-points-v2 = <&cpu7_opp_table>; 291 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 292 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 293 #cooling-cells = <2>; 294 l2_700: l2-cache { 295 compatible = "cache"; 296 cache-level = <2>; 297 cache-size = <0x80000>; 298 cache-unified; 299 next-level-cache = <&l3_0>; 300 }; 301 }; 302 303 cpu-map { 304 cluster0 { 305 core0 { 306 cpu = <&cpu0>; 307 }; 308 309 core1 { 310 cpu = <&cpu1>; 311 }; 312 313 core2 { 314 cpu = <&cpu2>; 315 }; 316 317 core3 { 318 cpu = <&cpu3>; 319 }; 320 321 core4 { 322 cpu = <&cpu4>; 323 }; 324 325 core5 { 326 cpu = <&cpu5>; 327 }; 328 329 core6 { 330 cpu = <&cpu6>; 331 }; 332 333 core7 { 334 cpu = <&cpu7>; 335 }; 336 }; 337 }; 338 339 idle-states { 340 entry-method = "psci"; 341 342 little_cpu_sleep_0: cpu-sleep-0-0 { 343 compatible = "arm,idle-state"; 344 idle-state-name = "silver-rail-power-collapse"; 345 arm,psci-suspend-param = <0x40000004>; 346 entry-latency-us = <360>; 347 exit-latency-us = <531>; 348 min-residency-us = <3934>; 349 local-timer-stop; 350 }; 351 352 big_cpu_sleep_0: cpu-sleep-1-0 { 353 compatible = "arm,idle-state"; 354 idle-state-name = "gold-rail-power-collapse"; 355 arm,psci-suspend-param = <0x40000004>; 356 entry-latency-us = <702>; 357 exit-latency-us = <1061>; 358 min-residency-us = <4488>; 359 local-timer-stop; 360 }; 361 }; 362 363 domain-idle-states { 364 cluster_sleep_0: cluster-sleep-0 { 365 compatible = "domain-idle-state"; 366 arm,psci-suspend-param = <0x4100c244>; 367 entry-latency-us = <3264>; 368 exit-latency-us = <6562>; 369 min-residency-us = <9987>; 370 }; 371 }; 372 }; 373 374 qup_virt: interconnect-qup-virt { 375 compatible = "qcom,sm8250-qup-virt"; 376 #interconnect-cells = <2>; 377 qcom,bcm-voters = <&apps_bcm_voter>; 378 }; 379 380 cpu0_opp_table: opp-table-cpu0 { 381 compatible = "operating-points-v2"; 382 opp-shared; 383 384 cpu0_opp1: opp-300000000 { 385 opp-hz = /bits/ 64 <300000000>; 386 opp-peak-kBps = <800000 9600000>; 387 }; 388 389 cpu0_opp2: opp-403200000 { 390 opp-hz = /bits/ 64 <403200000>; 391 opp-peak-kBps = <800000 9600000>; 392 }; 393 394 cpu0_opp3: opp-518400000 { 395 opp-hz = /bits/ 64 <518400000>; 396 opp-peak-kBps = <800000 16588800>; 397 }; 398 399 cpu0_opp4: opp-614400000 { 400 opp-hz = /bits/ 64 <614400000>; 401 opp-peak-kBps = <800000 16588800>; 402 }; 403 404 cpu0_opp5: opp-691200000 { 405 opp-hz = /bits/ 64 <691200000>; 406 opp-peak-kBps = <800000 19660800>; 407 }; 408 409 cpu0_opp6: opp-787200000 { 410 opp-hz = /bits/ 64 <787200000>; 411 opp-peak-kBps = <1804000 19660800>; 412 }; 413 414 cpu0_opp7: opp-883200000 { 415 opp-hz = /bits/ 64 <883200000>; 416 opp-peak-kBps = <1804000 23347200>; 417 }; 418 419 cpu0_opp8: opp-979200000 { 420 opp-hz = /bits/ 64 <979200000>; 421 opp-peak-kBps = <1804000 26419200>; 422 }; 423 424 cpu0_opp9: opp-1075200000 { 425 opp-hz = /bits/ 64 <1075200000>; 426 opp-peak-kBps = <1804000 29491200>; 427 }; 428 429 cpu0_opp10: opp-1171200000 { 430 opp-hz = /bits/ 64 <1171200000>; 431 opp-peak-kBps = <1804000 32563200>; 432 }; 433 434 cpu0_opp11: opp-1248000000 { 435 opp-hz = /bits/ 64 <1248000000>; 436 opp-peak-kBps = <1804000 36249600>; 437 }; 438 439 cpu0_opp12: opp-1344000000 { 440 opp-hz = /bits/ 64 <1344000000>; 441 opp-peak-kBps = <2188000 36249600>; 442 }; 443 444 cpu0_opp13: opp-1420800000 { 445 opp-hz = /bits/ 64 <1420800000>; 446 opp-peak-kBps = <2188000 39321600>; 447 }; 448 449 cpu0_opp14: opp-1516800000 { 450 opp-hz = /bits/ 64 <1516800000>; 451 opp-peak-kBps = <3072000 42393600>; 452 }; 453 454 cpu0_opp15: opp-1612800000 { 455 opp-hz = /bits/ 64 <1612800000>; 456 opp-peak-kBps = <3072000 42393600>; 457 }; 458 459 cpu0_opp16: opp-1708800000 { 460 opp-hz = /bits/ 64 <1708800000>; 461 opp-peak-kBps = <4068000 42393600>; 462 }; 463 464 cpu0_opp17: opp-1804800000 { 465 opp-hz = /bits/ 64 <1804800000>; 466 opp-peak-kBps = <4068000 42393600>; 467 }; 468 }; 469 470 cpu4_opp_table: opp-table-cpu4 { 471 compatible = "operating-points-v2"; 472 opp-shared; 473 474 cpu4_opp1: opp-710400000 { 475 opp-hz = /bits/ 64 <710400000>; 476 opp-peak-kBps = <1804000 19660800>; 477 }; 478 479 cpu4_opp2: opp-825600000 { 480 opp-hz = /bits/ 64 <825600000>; 481 opp-peak-kBps = <2188000 23347200>; 482 }; 483 484 cpu4_opp3: opp-940800000 { 485 opp-hz = /bits/ 64 <940800000>; 486 opp-peak-kBps = <2188000 26419200>; 487 }; 488 489 cpu4_opp4: opp-1056000000 { 490 opp-hz = /bits/ 64 <1056000000>; 491 opp-peak-kBps = <3072000 26419200>; 492 }; 493 494 cpu4_opp5: opp-1171200000 { 495 opp-hz = /bits/ 64 <1171200000>; 496 opp-peak-kBps = <3072000 29491200>; 497 }; 498 499 cpu4_opp6: opp-1286400000 { 500 opp-hz = /bits/ 64 <1286400000>; 501 opp-peak-kBps = <4068000 29491200>; 502 }; 503 504 cpu4_opp7: opp-1382400000 { 505 opp-hz = /bits/ 64 <1382400000>; 506 opp-peak-kBps = <4068000 32563200>; 507 }; 508 509 cpu4_opp8: opp-1478400000 { 510 opp-hz = /bits/ 64 <1478400000>; 511 opp-peak-kBps = <4068000 32563200>; 512 }; 513 514 cpu4_opp9: opp-1574400000 { 515 opp-hz = /bits/ 64 <1574400000>; 516 opp-peak-kBps = <5412000 39321600>; 517 }; 518 519 cpu4_opp10: opp-1670400000 { 520 opp-hz = /bits/ 64 <1670400000>; 521 opp-peak-kBps = <5412000 42393600>; 522 }; 523 524 cpu4_opp11: opp-1766400000 { 525 opp-hz = /bits/ 64 <1766400000>; 526 opp-peak-kBps = <5412000 45465600>; 527 }; 528 529 cpu4_opp12: opp-1862400000 { 530 opp-hz = /bits/ 64 <1862400000>; 531 opp-peak-kBps = <6220000 45465600>; 532 }; 533 534 cpu4_opp13: opp-1958400000 { 535 opp-hz = /bits/ 64 <1958400000>; 536 opp-peak-kBps = <6220000 48537600>; 537 }; 538 539 cpu4_opp14: opp-2054400000 { 540 opp-hz = /bits/ 64 <2054400000>; 541 opp-peak-kBps = <7216000 48537600>; 542 }; 543 544 cpu4_opp15: opp-2150400000 { 545 opp-hz = /bits/ 64 <2150400000>; 546 opp-peak-kBps = <7216000 51609600>; 547 }; 548 549 cpu4_opp16: opp-2246400000 { 550 opp-hz = /bits/ 64 <2246400000>; 551 opp-peak-kBps = <7216000 51609600>; 552 }; 553 554 cpu4_opp17: opp-2342400000 { 555 opp-hz = /bits/ 64 <2342400000>; 556 opp-peak-kBps = <8368000 51609600>; 557 }; 558 559 cpu4_opp18: opp-2419200000 { 560 opp-hz = /bits/ 64 <2419200000>; 561 opp-peak-kBps = <8368000 51609600>; 562 }; 563 }; 564 565 cpu7_opp_table: opp-table-cpu7 { 566 compatible = "operating-points-v2"; 567 opp-shared; 568 569 cpu7_opp1: opp-844800000 { 570 opp-hz = /bits/ 64 <844800000>; 571 opp-peak-kBps = <2188000 19660800>; 572 }; 573 574 cpu7_opp2: opp-960000000 { 575 opp-hz = /bits/ 64 <960000000>; 576 opp-peak-kBps = <2188000 26419200>; 577 }; 578 579 cpu7_opp3: opp-1075200000 { 580 opp-hz = /bits/ 64 <1075200000>; 581 opp-peak-kBps = <3072000 26419200>; 582 }; 583 584 cpu7_opp4: opp-1190400000 { 585 opp-hz = /bits/ 64 <1190400000>; 586 opp-peak-kBps = <3072000 29491200>; 587 }; 588 589 cpu7_opp5: opp-1305600000 { 590 opp-hz = /bits/ 64 <1305600000>; 591 opp-peak-kBps = <4068000 32563200>; 592 }; 593 594 cpu7_opp6: opp-1401600000 { 595 opp-hz = /bits/ 64 <1401600000>; 596 opp-peak-kBps = <4068000 32563200>; 597 }; 598 599 cpu7_opp7: opp-1516800000 { 600 opp-hz = /bits/ 64 <1516800000>; 601 opp-peak-kBps = <4068000 36249600>; 602 }; 603 604 cpu7_opp8: opp-1632000000 { 605 opp-hz = /bits/ 64 <1632000000>; 606 opp-peak-kBps = <5412000 39321600>; 607 }; 608 609 cpu7_opp9: opp-1747200000 { 610 opp-hz = /bits/ 64 <1747200000>; 611 opp-peak-kBps = <5412000 42393600>; 612 }; 613 614 cpu7_opp10: opp-1862400000 { 615 opp-hz = /bits/ 64 <1862400000>; 616 opp-peak-kBps = <6220000 45465600>; 617 }; 618 619 cpu7_opp11: opp-1977600000 { 620 opp-hz = /bits/ 64 <1977600000>; 621 opp-peak-kBps = <6220000 48537600>; 622 }; 623 624 cpu7_opp12: opp-2073600000 { 625 opp-hz = /bits/ 64 <2073600000>; 626 opp-peak-kBps = <7216000 48537600>; 627 }; 628 629 cpu7_opp13: opp-2169600000 { 630 opp-hz = /bits/ 64 <2169600000>; 631 opp-peak-kBps = <7216000 51609600>; 632 }; 633 634 cpu7_opp14: opp-2265600000 { 635 opp-hz = /bits/ 64 <2265600000>; 636 opp-peak-kBps = <7216000 51609600>; 637 }; 638 639 cpu7_opp15: opp-2361600000 { 640 opp-hz = /bits/ 64 <2361600000>; 641 opp-peak-kBps = <8368000 51609600>; 642 }; 643 644 cpu7_opp16: opp-2457600000 { 645 opp-hz = /bits/ 64 <2457600000>; 646 opp-peak-kBps = <8368000 51609600>; 647 }; 648 649 cpu7_opp17: opp-2553600000 { 650 opp-hz = /bits/ 64 <2553600000>; 651 opp-peak-kBps = <8368000 51609600>; 652 }; 653 654 cpu7_opp18: opp-2649600000 { 655 opp-hz = /bits/ 64 <2649600000>; 656 opp-peak-kBps = <8368000 51609600>; 657 }; 658 659 cpu7_opp19: opp-2745600000 { 660 opp-hz = /bits/ 64 <2745600000>; 661 opp-peak-kBps = <8368000 51609600>; 662 }; 663 664 cpu7_opp20: opp-2841600000 { 665 opp-hz = /bits/ 64 <2841600000>; 666 opp-peak-kBps = <8368000 51609600>; 667 }; 668 }; 669 670 firmware { 671 scm: scm { 672 compatible = "qcom,scm-sm8250", "qcom,scm"; 673 qcom,dload-mode = <&tcsr 0x13000>; 674 #reset-cells = <1>; 675 }; 676 }; 677 678 memory@80000000 { 679 device_type = "memory"; 680 /* We expect the bootloader to fill in the size */ 681 reg = <0x0 0x80000000 0x0 0x0>; 682 }; 683 684 pmu { 685 compatible = "arm,armv8-pmuv3"; 686 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 687 }; 688 689 psci { 690 compatible = "arm,psci-1.0"; 691 method = "smc"; 692 693 cpu_pd0: power-domain-cpu0 { 694 #power-domain-cells = <0>; 695 power-domains = <&cluster_pd>; 696 domain-idle-states = <&little_cpu_sleep_0>; 697 }; 698 699 cpu_pd1: power-domain-cpu1 { 700 #power-domain-cells = <0>; 701 power-domains = <&cluster_pd>; 702 domain-idle-states = <&little_cpu_sleep_0>; 703 }; 704 705 cpu_pd2: power-domain-cpu2 { 706 #power-domain-cells = <0>; 707 power-domains = <&cluster_pd>; 708 domain-idle-states = <&little_cpu_sleep_0>; 709 }; 710 711 cpu_pd3: power-domain-cpu3 { 712 #power-domain-cells = <0>; 713 power-domains = <&cluster_pd>; 714 domain-idle-states = <&little_cpu_sleep_0>; 715 }; 716 717 cpu_pd4: power-domain-cpu4 { 718 #power-domain-cells = <0>; 719 power-domains = <&cluster_pd>; 720 domain-idle-states = <&big_cpu_sleep_0>; 721 }; 722 723 cpu_pd5: power-domain-cpu5 { 724 #power-domain-cells = <0>; 725 power-domains = <&cluster_pd>; 726 domain-idle-states = <&big_cpu_sleep_0>; 727 }; 728 729 cpu_pd6: power-domain-cpu6 { 730 #power-domain-cells = <0>; 731 power-domains = <&cluster_pd>; 732 domain-idle-states = <&big_cpu_sleep_0>; 733 }; 734 735 cpu_pd7: power-domain-cpu7 { 736 #power-domain-cells = <0>; 737 power-domains = <&cluster_pd>; 738 domain-idle-states = <&big_cpu_sleep_0>; 739 }; 740 741 cluster_pd: power-domain-cpu-cluster0 { 742 #power-domain-cells = <0>; 743 domain-idle-states = <&cluster_sleep_0>; 744 }; 745 }; 746 747 qup_opp_table: opp-table-qup { 748 compatible = "operating-points-v2"; 749 750 opp-50000000 { 751 opp-hz = /bits/ 64 <50000000>; 752 required-opps = <&rpmhpd_opp_min_svs>; 753 }; 754 755 opp-75000000 { 756 opp-hz = /bits/ 64 <75000000>; 757 required-opps = <&rpmhpd_opp_low_svs>; 758 }; 759 760 opp-120000000 { 761 opp-hz = /bits/ 64 <120000000>; 762 required-opps = <&rpmhpd_opp_svs>; 763 }; 764 }; 765 766 reserved-memory { 767 #address-cells = <2>; 768 #size-cells = <2>; 769 ranges; 770 771 hyp_mem: memory@80000000 { 772 reg = <0x0 0x80000000 0x0 0x600000>; 773 no-map; 774 }; 775 776 xbl_aop_mem: memory@80700000 { 777 reg = <0x0 0x80700000 0x0 0x160000>; 778 no-map; 779 }; 780 781 cmd_db: memory@80860000 { 782 compatible = "qcom,cmd-db"; 783 reg = <0x0 0x80860000 0x0 0x20000>; 784 no-map; 785 }; 786 787 smem_mem: memory@80900000 { 788 reg = <0x0 0x80900000 0x0 0x200000>; 789 no-map; 790 }; 791 792 removed_mem: memory@80b00000 { 793 reg = <0x0 0x80b00000 0x0 0x5300000>; 794 no-map; 795 }; 796 797 camera_mem: memory@86200000 { 798 reg = <0x0 0x86200000 0x0 0x500000>; 799 no-map; 800 }; 801 802 wlan_mem: memory@86700000 { 803 reg = <0x0 0x86700000 0x0 0x100000>; 804 no-map; 805 }; 806 807 ipa_fw_mem: memory@86800000 { 808 reg = <0x0 0x86800000 0x0 0x10000>; 809 no-map; 810 }; 811 812 ipa_gsi_mem: memory@86810000 { 813 reg = <0x0 0x86810000 0x0 0xa000>; 814 no-map; 815 }; 816 817 gpu_mem: memory@8681a000 { 818 reg = <0x0 0x8681a000 0x0 0x2000>; 819 no-map; 820 }; 821 822 npu_mem: memory@86900000 { 823 reg = <0x0 0x86900000 0x0 0x500000>; 824 no-map; 825 }; 826 827 video_mem: memory@86e00000 { 828 reg = <0x0 0x86e00000 0x0 0x500000>; 829 no-map; 830 }; 831 832 cvp_mem: memory@87300000 { 833 reg = <0x0 0x87300000 0x0 0x500000>; 834 no-map; 835 }; 836 837 cdsp_mem: memory@87800000 { 838 reg = <0x0 0x87800000 0x0 0x1400000>; 839 no-map; 840 }; 841 842 slpi_mem: memory@88c00000 { 843 reg = <0x0 0x88c00000 0x0 0x1500000>; 844 no-map; 845 }; 846 847 adsp_mem: memory@8a100000 { 848 reg = <0x0 0x8a100000 0x0 0x1d00000>; 849 no-map; 850 }; 851 852 spss_mem: memory@8be00000 { 853 reg = <0x0 0x8be00000 0x0 0x100000>; 854 no-map; 855 }; 856 857 cdsp_secure_heap: memory@8bf00000 { 858 reg = <0x0 0x8bf00000 0x0 0x4600000>; 859 no-map; 860 }; 861 }; 862 863 smem { 864 compatible = "qcom,smem"; 865 memory-region = <&smem_mem>; 866 hwlocks = <&tcsr_mutex 3>; 867 }; 868 869 smp2p-adsp { 870 compatible = "qcom,smp2p"; 871 qcom,smem = <443>, <429>; 872 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 873 IPCC_MPROC_SIGNAL_SMP2P 874 IRQ_TYPE_EDGE_RISING>; 875 mboxes = <&ipcc IPCC_CLIENT_LPASS 876 IPCC_MPROC_SIGNAL_SMP2P>; 877 878 qcom,local-pid = <0>; 879 qcom,remote-pid = <2>; 880 881 smp2p_adsp_out: master-kernel { 882 qcom,entry-name = "master-kernel"; 883 #qcom,smem-state-cells = <1>; 884 }; 885 886 smp2p_adsp_in: slave-kernel { 887 qcom,entry-name = "slave-kernel"; 888 interrupt-controller; 889 #interrupt-cells = <2>; 890 }; 891 }; 892 893 smp2p-cdsp { 894 compatible = "qcom,smp2p"; 895 qcom,smem = <94>, <432>; 896 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 897 IPCC_MPROC_SIGNAL_SMP2P 898 IRQ_TYPE_EDGE_RISING>; 899 mboxes = <&ipcc IPCC_CLIENT_CDSP 900 IPCC_MPROC_SIGNAL_SMP2P>; 901 902 qcom,local-pid = <0>; 903 qcom,remote-pid = <5>; 904 905 smp2p_cdsp_out: master-kernel { 906 qcom,entry-name = "master-kernel"; 907 #qcom,smem-state-cells = <1>; 908 }; 909 910 smp2p_cdsp_in: slave-kernel { 911 qcom,entry-name = "slave-kernel"; 912 interrupt-controller; 913 #interrupt-cells = <2>; 914 }; 915 }; 916 917 smp2p-slpi { 918 compatible = "qcom,smp2p"; 919 qcom,smem = <481>, <430>; 920 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 921 IPCC_MPROC_SIGNAL_SMP2P 922 IRQ_TYPE_EDGE_RISING>; 923 mboxes = <&ipcc IPCC_CLIENT_SLPI 924 IPCC_MPROC_SIGNAL_SMP2P>; 925 926 qcom,local-pid = <0>; 927 qcom,remote-pid = <3>; 928 929 smp2p_slpi_out: master-kernel { 930 qcom,entry-name = "master-kernel"; 931 #qcom,smem-state-cells = <1>; 932 }; 933 934 smp2p_slpi_in: slave-kernel { 935 qcom,entry-name = "slave-kernel"; 936 interrupt-controller; 937 #interrupt-cells = <2>; 938 }; 939 }; 940 941 soc: soc@0 { 942 #address-cells = <2>; 943 #size-cells = <2>; 944 ranges = <0 0 0 0 0x10 0>; 945 dma-ranges = <0 0 0 0 0x10 0>; 946 compatible = "simple-bus"; 947 948 gcc: clock-controller@100000 { 949 compatible = "qcom,gcc-sm8250"; 950 reg = <0x0 0x00100000 0x0 0x1f0000>; 951 #clock-cells = <1>; 952 #reset-cells = <1>; 953 #power-domain-cells = <1>; 954 clock-names = "bi_tcxo", 955 "bi_tcxo_ao", 956 "sleep_clk"; 957 clocks = <&rpmhcc RPMH_CXO_CLK>, 958 <&rpmhcc RPMH_CXO_CLK_A>, 959 <&sleep_clk>; 960 }; 961 962 ipcc: mailbox@408000 { 963 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 964 reg = <0 0x00408000 0 0x1000>; 965 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 966 interrupt-controller; 967 #interrupt-cells = <3>; 968 #mbox-cells = <2>; 969 }; 970 971 qfprom: efuse@784000 { 972 compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; 973 reg = <0 0x00784000 0 0x8ff>; 974 #address-cells = <1>; 975 #size-cells = <1>; 976 977 gpu_speed_bin: gpu-speed-bin@19b { 978 reg = <0x19b 0x1>; 979 bits = <5 3>; 980 }; 981 }; 982 983 rng: rng@793000 { 984 compatible = "qcom,prng-ee"; 985 reg = <0 0x00793000 0 0x1000>; 986 clocks = <&gcc GCC_PRNG_AHB_CLK>; 987 clock-names = "core"; 988 }; 989 990 gpi_dma2: dma-controller@800000 { 991 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 992 reg = <0 0x00800000 0 0x70000>; 993 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 1003 dma-channels = <10>; 1004 dma-channel-mask = <0x3f>; 1005 iommus = <&apps_smmu 0x76 0x0>; 1006 #dma-cells = <3>; 1007 status = "disabled"; 1008 }; 1009 1010 qupv3_id_2: geniqup@8c0000 { 1011 compatible = "qcom,geni-se-qup"; 1012 reg = <0x0 0x008c0000 0x0 0x6000>; 1013 clock-names = "m-ahb", "s-ahb"; 1014 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1015 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1016 #address-cells = <2>; 1017 #size-cells = <2>; 1018 iommus = <&apps_smmu 0x63 0x0>; 1019 ranges; 1020 status = "disabled"; 1021 1022 i2c14: i2c@880000 { 1023 compatible = "qcom,geni-i2c"; 1024 reg = <0 0x00880000 0 0x4000>; 1025 clock-names = "se"; 1026 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1027 pinctrl-names = "default"; 1028 pinctrl-0 = <&qup_i2c14_default>; 1029 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1030 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1031 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1032 dma-names = "tx", "rx"; 1033 power-domains = <&rpmhpd SM8250_CX>; 1034 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1035 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1036 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1037 interconnect-names = "qup-core", 1038 "qup-config", 1039 "qup-memory"; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 status = "disabled"; 1043 }; 1044 1045 spi14: spi@880000 { 1046 compatible = "qcom,geni-spi"; 1047 reg = <0 0x00880000 0 0x4000>; 1048 clock-names = "se"; 1049 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1050 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1051 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1052 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1053 dma-names = "tx", "rx"; 1054 power-domains = <&rpmhpd RPMHPD_CX>; 1055 operating-points-v2 = <&qup_opp_table>; 1056 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1057 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1058 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1059 interconnect-names = "qup-core", 1060 "qup-config", 1061 "qup-memory"; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 i2c15: i2c@884000 { 1068 compatible = "qcom,geni-i2c"; 1069 reg = <0 0x00884000 0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&qup_i2c15_default>; 1074 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1075 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1076 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1077 dma-names = "tx", "rx"; 1078 power-domains = <&rpmhpd SM8250_CX>; 1079 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1080 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1081 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1082 interconnect-names = "qup-core", 1083 "qup-config", 1084 "qup-memory"; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 spi15: spi@884000 { 1091 compatible = "qcom,geni-spi"; 1092 reg = <0 0x00884000 0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1095 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1096 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1097 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1098 dma-names = "tx", "rx"; 1099 power-domains = <&rpmhpd RPMHPD_CX>; 1100 operating-points-v2 = <&qup_opp_table>; 1101 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1102 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1103 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1104 interconnect-names = "qup-core", 1105 "qup-config", 1106 "qup-memory"; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 status = "disabled"; 1110 }; 1111 1112 i2c16: i2c@888000 { 1113 compatible = "qcom,geni-i2c"; 1114 reg = <0 0x00888000 0 0x4000>; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_i2c16_default>; 1119 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1120 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1121 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1122 dma-names = "tx", "rx"; 1123 power-domains = <&rpmhpd SM8250_CX>; 1124 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1125 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1126 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1127 interconnect-names = "qup-core", 1128 "qup-config", 1129 "qup-memory"; 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 status = "disabled"; 1133 }; 1134 1135 spi16: spi@888000 { 1136 compatible = "qcom,geni-spi"; 1137 reg = <0 0x00888000 0 0x4000>; 1138 clock-names = "se"; 1139 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1140 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1141 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1142 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1143 dma-names = "tx", "rx"; 1144 power-domains = <&rpmhpd RPMHPD_CX>; 1145 operating-points-v2 = <&qup_opp_table>; 1146 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1147 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1148 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1149 interconnect-names = "qup-core", 1150 "qup-config", 1151 "qup-memory"; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 status = "disabled"; 1155 }; 1156 1157 i2c17: i2c@88c000 { 1158 compatible = "qcom,geni-i2c"; 1159 reg = <0 0x0088c000 0 0x4000>; 1160 clock-names = "se"; 1161 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_i2c17_default>; 1164 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1165 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1166 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1167 dma-names = "tx", "rx"; 1168 power-domains = <&rpmhpd SM8250_CX>; 1169 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1170 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1171 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1172 interconnect-names = "qup-core", 1173 "qup-config", 1174 "qup-memory"; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 status = "disabled"; 1178 }; 1179 1180 spi17: spi@88c000 { 1181 compatible = "qcom,geni-spi"; 1182 reg = <0 0x0088c000 0 0x4000>; 1183 clock-names = "se"; 1184 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1185 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1186 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1187 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1188 dma-names = "tx", "rx"; 1189 power-domains = <&rpmhpd RPMHPD_CX>; 1190 operating-points-v2 = <&qup_opp_table>; 1191 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1192 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1193 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1194 interconnect-names = "qup-core", 1195 "qup-config", 1196 "qup-memory"; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 status = "disabled"; 1200 }; 1201 1202 uart17: serial@88c000 { 1203 compatible = "qcom,geni-uart"; 1204 reg = <0 0x0088c000 0 0x4000>; 1205 clock-names = "se"; 1206 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1207 pinctrl-names = "default"; 1208 pinctrl-0 = <&qup_uart17_default>; 1209 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1210 power-domains = <&rpmhpd RPMHPD_CX>; 1211 operating-points-v2 = <&qup_opp_table>; 1212 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1213 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1214 interconnect-names = "qup-core", 1215 "qup-config"; 1216 status = "disabled"; 1217 }; 1218 1219 i2c18: i2c@890000 { 1220 compatible = "qcom,geni-i2c"; 1221 reg = <0 0x00890000 0 0x4000>; 1222 clock-names = "se"; 1223 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1224 pinctrl-names = "default"; 1225 pinctrl-0 = <&qup_i2c18_default>; 1226 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1227 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1228 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1229 dma-names = "tx", "rx"; 1230 power-domains = <&rpmhpd SM8250_CX>; 1231 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1232 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1233 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1234 interconnect-names = "qup-core", 1235 "qup-config", 1236 "qup-memory"; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 status = "disabled"; 1240 }; 1241 1242 spi18: spi@890000 { 1243 compatible = "qcom,geni-spi"; 1244 reg = <0 0x00890000 0 0x4000>; 1245 clock-names = "se"; 1246 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1247 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1248 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1249 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1250 dma-names = "tx", "rx"; 1251 power-domains = <&rpmhpd RPMHPD_CX>; 1252 operating-points-v2 = <&qup_opp_table>; 1253 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1254 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1255 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1256 interconnect-names = "qup-core", 1257 "qup-config", 1258 "qup-memory"; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 status = "disabled"; 1262 }; 1263 1264 uart18: serial@890000 { 1265 compatible = "qcom,geni-uart"; 1266 reg = <0 0x00890000 0 0x4000>; 1267 clock-names = "se"; 1268 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&qup_uart18_default>; 1271 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1272 power-domains = <&rpmhpd RPMHPD_CX>; 1273 operating-points-v2 = <&qup_opp_table>; 1274 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1275 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1276 interconnect-names = "qup-core", 1277 "qup-config"; 1278 status = "disabled"; 1279 }; 1280 1281 i2c19: i2c@894000 { 1282 compatible = "qcom,geni-i2c"; 1283 reg = <0 0x00894000 0 0x4000>; 1284 clock-names = "se"; 1285 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1286 pinctrl-names = "default"; 1287 pinctrl-0 = <&qup_i2c19_default>; 1288 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1289 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1290 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1291 dma-names = "tx", "rx"; 1292 power-domains = <&rpmhpd SM8250_CX>; 1293 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1294 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1295 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1296 interconnect-names = "qup-core", 1297 "qup-config", 1298 "qup-memory"; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 status = "disabled"; 1302 }; 1303 1304 spi19: spi@894000 { 1305 compatible = "qcom,geni-spi"; 1306 reg = <0 0x00894000 0 0x4000>; 1307 clock-names = "se"; 1308 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1309 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1310 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1311 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1312 dma-names = "tx", "rx"; 1313 power-domains = <&rpmhpd RPMHPD_CX>; 1314 operating-points-v2 = <&qup_opp_table>; 1315 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1316 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1317 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1318 interconnect-names = "qup-core", 1319 "qup-config", 1320 "qup-memory"; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 status = "disabled"; 1324 }; 1325 }; 1326 1327 gpi_dma0: dma-controller@900000 { 1328 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1329 reg = <0 0x00900000 0 0x70000>; 1330 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1343 dma-channels = <15>; 1344 dma-channel-mask = <0x7ff>; 1345 iommus = <&apps_smmu 0x5b6 0x0>; 1346 #dma-cells = <3>; 1347 status = "disabled"; 1348 }; 1349 1350 qupv3_id_0: geniqup@9c0000 { 1351 compatible = "qcom,geni-se-qup"; 1352 reg = <0x0 0x009c0000 0x0 0x6000>; 1353 clock-names = "m-ahb", "s-ahb"; 1354 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1355 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1356 #address-cells = <2>; 1357 #size-cells = <2>; 1358 iommus = <&apps_smmu 0x5a3 0x0>; 1359 ranges; 1360 status = "disabled"; 1361 1362 i2c0: i2c@980000 { 1363 compatible = "qcom,geni-i2c"; 1364 reg = <0 0x00980000 0 0x4000>; 1365 clock-names = "se"; 1366 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1367 pinctrl-names = "default"; 1368 pinctrl-0 = <&qup_i2c0_default>; 1369 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1370 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1371 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1372 dma-names = "tx", "rx"; 1373 power-domains = <&rpmhpd SM8250_CX>; 1374 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1375 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1376 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1377 interconnect-names = "qup-core", 1378 "qup-config", 1379 "qup-memory"; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 status = "disabled"; 1383 }; 1384 1385 spi0: spi@980000 { 1386 compatible = "qcom,geni-spi"; 1387 reg = <0 0x00980000 0 0x4000>; 1388 clock-names = "se"; 1389 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1390 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1391 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1392 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1393 dma-names = "tx", "rx"; 1394 power-domains = <&rpmhpd RPMHPD_CX>; 1395 operating-points-v2 = <&qup_opp_table>; 1396 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1397 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1398 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1399 interconnect-names = "qup-core", 1400 "qup-config", 1401 "qup-memory"; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 status = "disabled"; 1405 }; 1406 1407 i2c1: i2c@984000 { 1408 compatible = "qcom,geni-i2c"; 1409 reg = <0 0x00984000 0 0x4000>; 1410 clock-names = "se"; 1411 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&qup_i2c1_default>; 1414 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1415 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1416 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1417 dma-names = "tx", "rx"; 1418 power-domains = <&rpmhpd SM8250_CX>; 1419 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1420 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1421 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1422 interconnect-names = "qup-core", 1423 "qup-config", 1424 "qup-memory"; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 status = "disabled"; 1428 }; 1429 1430 spi1: spi@984000 { 1431 compatible = "qcom,geni-spi"; 1432 reg = <0 0x00984000 0 0x4000>; 1433 clock-names = "se"; 1434 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1435 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1436 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1437 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1438 dma-names = "tx", "rx"; 1439 power-domains = <&rpmhpd RPMHPD_CX>; 1440 operating-points-v2 = <&qup_opp_table>; 1441 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1442 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1443 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1444 interconnect-names = "qup-core", 1445 "qup-config", 1446 "qup-memory"; 1447 #address-cells = <1>; 1448 #size-cells = <0>; 1449 status = "disabled"; 1450 }; 1451 1452 i2c2: i2c@988000 { 1453 compatible = "qcom,geni-i2c"; 1454 reg = <0 0x00988000 0 0x4000>; 1455 clock-names = "se"; 1456 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1457 pinctrl-names = "default"; 1458 pinctrl-0 = <&qup_i2c2_default>; 1459 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1460 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1461 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1462 dma-names = "tx", "rx"; 1463 power-domains = <&rpmhpd SM8250_CX>; 1464 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1465 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1466 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1467 interconnect-names = "qup-core", 1468 "qup-config", 1469 "qup-memory"; 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 status = "disabled"; 1473 }; 1474 1475 spi2: spi@988000 { 1476 compatible = "qcom,geni-spi"; 1477 reg = <0 0x00988000 0 0x4000>; 1478 clock-names = "se"; 1479 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1480 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1481 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1482 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1483 dma-names = "tx", "rx"; 1484 power-domains = <&rpmhpd RPMHPD_CX>; 1485 operating-points-v2 = <&qup_opp_table>; 1486 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1487 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1488 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1489 interconnect-names = "qup-core", 1490 "qup-config", 1491 "qup-memory"; 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 status = "disabled"; 1495 }; 1496 1497 uart2: serial@988000 { 1498 compatible = "qcom,geni-debug-uart"; 1499 reg = <0 0x00988000 0 0x4000>; 1500 clock-names = "se"; 1501 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1502 pinctrl-names = "default"; 1503 pinctrl-0 = <&qup_uart2_default>; 1504 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1505 power-domains = <&rpmhpd RPMHPD_CX>; 1506 operating-points-v2 = <&qup_opp_table>; 1507 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1508 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1509 interconnect-names = "qup-core", 1510 "qup-config"; 1511 status = "disabled"; 1512 }; 1513 1514 i2c3: i2c@98c000 { 1515 compatible = "qcom,geni-i2c"; 1516 reg = <0 0x0098c000 0 0x4000>; 1517 clock-names = "se"; 1518 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1519 pinctrl-names = "default"; 1520 pinctrl-0 = <&qup_i2c3_default>; 1521 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1522 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1523 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1524 dma-names = "tx", "rx"; 1525 power-domains = <&rpmhpd SM8250_CX>; 1526 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1527 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1528 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1529 interconnect-names = "qup-core", 1530 "qup-config", 1531 "qup-memory"; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 status = "disabled"; 1535 }; 1536 1537 spi3: spi@98c000 { 1538 compatible = "qcom,geni-spi"; 1539 reg = <0 0x0098c000 0 0x4000>; 1540 clock-names = "se"; 1541 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1542 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1543 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1544 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1545 dma-names = "tx", "rx"; 1546 power-domains = <&rpmhpd RPMHPD_CX>; 1547 operating-points-v2 = <&qup_opp_table>; 1548 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1549 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1550 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1551 interconnect-names = "qup-core", 1552 "qup-config", 1553 "qup-memory"; 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 status = "disabled"; 1557 }; 1558 1559 i2c4: i2c@990000 { 1560 compatible = "qcom,geni-i2c"; 1561 reg = <0 0x00990000 0 0x4000>; 1562 clock-names = "se"; 1563 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1564 pinctrl-names = "default"; 1565 pinctrl-0 = <&qup_i2c4_default>; 1566 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1567 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1568 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1569 dma-names = "tx", "rx"; 1570 power-domains = <&rpmhpd SM8250_CX>; 1571 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1572 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1573 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1574 interconnect-names = "qup-core", 1575 "qup-config", 1576 "qup-memory"; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 status = "disabled"; 1580 }; 1581 1582 spi4: spi@990000 { 1583 compatible = "qcom,geni-spi"; 1584 reg = <0 0x00990000 0 0x4000>; 1585 clock-names = "se"; 1586 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1587 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1588 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1589 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1590 dma-names = "tx", "rx"; 1591 power-domains = <&rpmhpd RPMHPD_CX>; 1592 operating-points-v2 = <&qup_opp_table>; 1593 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1594 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1595 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1596 interconnect-names = "qup-core", 1597 "qup-config", 1598 "qup-memory"; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 status = "disabled"; 1602 }; 1603 1604 i2c5: i2c@994000 { 1605 compatible = "qcom,geni-i2c"; 1606 reg = <0 0x00994000 0 0x4000>; 1607 clock-names = "se"; 1608 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1609 pinctrl-names = "default"; 1610 pinctrl-0 = <&qup_i2c5_default>; 1611 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1612 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1613 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1614 dma-names = "tx", "rx"; 1615 power-domains = <&rpmhpd SM8250_CX>; 1616 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1617 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1618 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1619 interconnect-names = "qup-core", 1620 "qup-config", 1621 "qup-memory"; 1622 #address-cells = <1>; 1623 #size-cells = <0>; 1624 status = "disabled"; 1625 }; 1626 1627 spi5: spi@994000 { 1628 compatible = "qcom,geni-spi"; 1629 reg = <0 0x00994000 0 0x4000>; 1630 clock-names = "se"; 1631 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1632 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1633 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1634 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1635 dma-names = "tx", "rx"; 1636 power-domains = <&rpmhpd RPMHPD_CX>; 1637 operating-points-v2 = <&qup_opp_table>; 1638 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1639 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1640 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1641 interconnect-names = "qup-core", 1642 "qup-config", 1643 "qup-memory"; 1644 #address-cells = <1>; 1645 #size-cells = <0>; 1646 status = "disabled"; 1647 }; 1648 1649 i2c6: i2c@998000 { 1650 compatible = "qcom,geni-i2c"; 1651 reg = <0 0x00998000 0 0x4000>; 1652 clock-names = "se"; 1653 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1654 pinctrl-names = "default"; 1655 pinctrl-0 = <&qup_i2c6_default>; 1656 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1657 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1658 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1659 dma-names = "tx", "rx"; 1660 power-domains = <&rpmhpd SM8250_CX>; 1661 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1662 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1663 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1664 interconnect-names = "qup-core", 1665 "qup-config", 1666 "qup-memory"; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 status = "disabled"; 1670 }; 1671 1672 spi6: spi@998000 { 1673 compatible = "qcom,geni-spi"; 1674 reg = <0 0x00998000 0 0x4000>; 1675 clock-names = "se"; 1676 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1677 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1678 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1679 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1680 dma-names = "tx", "rx"; 1681 power-domains = <&rpmhpd RPMHPD_CX>; 1682 operating-points-v2 = <&qup_opp_table>; 1683 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1684 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1685 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1686 interconnect-names = "qup-core", 1687 "qup-config", 1688 "qup-memory"; 1689 #address-cells = <1>; 1690 #size-cells = <0>; 1691 status = "disabled"; 1692 }; 1693 1694 uart6: serial@998000 { 1695 compatible = "qcom,geni-uart"; 1696 reg = <0 0x00998000 0 0x4000>; 1697 clock-names = "se"; 1698 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1699 pinctrl-names = "default"; 1700 pinctrl-0 = <&qup_uart6_default>; 1701 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1702 power-domains = <&rpmhpd RPMHPD_CX>; 1703 operating-points-v2 = <&qup_opp_table>; 1704 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1705 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1706 interconnect-names = "qup-core", 1707 "qup-config"; 1708 status = "disabled"; 1709 }; 1710 1711 i2c7: i2c@99c000 { 1712 compatible = "qcom,geni-i2c"; 1713 reg = <0 0x0099c000 0 0x4000>; 1714 clock-names = "se"; 1715 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1716 pinctrl-names = "default"; 1717 pinctrl-0 = <&qup_i2c7_default>; 1718 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1719 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1720 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1721 dma-names = "tx", "rx"; 1722 power-domains = <&rpmhpd SM8250_CX>; 1723 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1724 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1725 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1726 interconnect-names = "qup-core", 1727 "qup-config", 1728 "qup-memory"; 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 status = "disabled"; 1732 }; 1733 1734 spi7: spi@99c000 { 1735 compatible = "qcom,geni-spi"; 1736 reg = <0 0x0099c000 0 0x4000>; 1737 clock-names = "se"; 1738 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1739 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1740 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1741 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1742 dma-names = "tx", "rx"; 1743 power-domains = <&rpmhpd RPMHPD_CX>; 1744 operating-points-v2 = <&qup_opp_table>; 1745 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1746 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1747 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1748 interconnect-names = "qup-core", 1749 "qup-config", 1750 "qup-memory"; 1751 #address-cells = <1>; 1752 #size-cells = <0>; 1753 status = "disabled"; 1754 }; 1755 }; 1756 1757 gpi_dma1: dma-controller@a00000 { 1758 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1759 reg = <0 0x00a00000 0 0x70000>; 1760 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1770 dma-channels = <10>; 1771 dma-channel-mask = <0x3f>; 1772 iommus = <&apps_smmu 0x56 0x0>; 1773 #dma-cells = <3>; 1774 status = "disabled"; 1775 }; 1776 1777 qupv3_id_1: geniqup@ac0000 { 1778 compatible = "qcom,geni-se-qup"; 1779 reg = <0x0 0x00ac0000 0x0 0x6000>; 1780 clock-names = "m-ahb", "s-ahb"; 1781 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1782 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1783 #address-cells = <2>; 1784 #size-cells = <2>; 1785 iommus = <&apps_smmu 0x43 0x0>; 1786 ranges; 1787 status = "disabled"; 1788 1789 i2c8: i2c@a80000 { 1790 compatible = "qcom,geni-i2c"; 1791 reg = <0 0x00a80000 0 0x4000>; 1792 clock-names = "se"; 1793 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1794 pinctrl-names = "default"; 1795 pinctrl-0 = <&qup_i2c8_default>; 1796 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1797 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1798 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1799 dma-names = "tx", "rx"; 1800 power-domains = <&rpmhpd SM8250_CX>; 1801 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1802 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1803 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1804 interconnect-names = "qup-core", 1805 "qup-config", 1806 "qup-memory"; 1807 #address-cells = <1>; 1808 #size-cells = <0>; 1809 status = "disabled"; 1810 }; 1811 1812 spi8: spi@a80000 { 1813 compatible = "qcom,geni-spi"; 1814 reg = <0 0x00a80000 0 0x4000>; 1815 clock-names = "se"; 1816 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1817 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1818 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1819 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1820 dma-names = "tx", "rx"; 1821 power-domains = <&rpmhpd RPMHPD_CX>; 1822 operating-points-v2 = <&qup_opp_table>; 1823 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1824 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1825 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1826 interconnect-names = "qup-core", 1827 "qup-config", 1828 "qup-memory"; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 status = "disabled"; 1832 }; 1833 1834 i2c9: i2c@a84000 { 1835 compatible = "qcom,geni-i2c"; 1836 reg = <0 0x00a84000 0 0x4000>; 1837 clock-names = "se"; 1838 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1839 pinctrl-names = "default"; 1840 pinctrl-0 = <&qup_i2c9_default>; 1841 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1842 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1843 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1844 dma-names = "tx", "rx"; 1845 power-domains = <&rpmhpd SM8250_CX>; 1846 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1847 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1848 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1849 interconnect-names = "qup-core", 1850 "qup-config", 1851 "qup-memory"; 1852 #address-cells = <1>; 1853 #size-cells = <0>; 1854 status = "disabled"; 1855 }; 1856 1857 spi9: spi@a84000 { 1858 compatible = "qcom,geni-spi"; 1859 reg = <0 0x00a84000 0 0x4000>; 1860 clock-names = "se"; 1861 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1862 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1863 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1864 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1865 dma-names = "tx", "rx"; 1866 power-domains = <&rpmhpd RPMHPD_CX>; 1867 operating-points-v2 = <&qup_opp_table>; 1868 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1869 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1870 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1871 interconnect-names = "qup-core", 1872 "qup-config", 1873 "qup-memory"; 1874 #address-cells = <1>; 1875 #size-cells = <0>; 1876 status = "disabled"; 1877 }; 1878 1879 i2c10: i2c@a88000 { 1880 compatible = "qcom,geni-i2c"; 1881 reg = <0 0x00a88000 0 0x4000>; 1882 clock-names = "se"; 1883 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1884 pinctrl-names = "default"; 1885 pinctrl-0 = <&qup_i2c10_default>; 1886 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1887 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1888 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1889 dma-names = "tx", "rx"; 1890 power-domains = <&rpmhpd SM8250_CX>; 1891 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1892 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1893 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1894 interconnect-names = "qup-core", 1895 "qup-config", 1896 "qup-memory"; 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 status = "disabled"; 1900 }; 1901 1902 spi10: spi@a88000 { 1903 compatible = "qcom,geni-spi"; 1904 reg = <0 0x00a88000 0 0x4000>; 1905 clock-names = "se"; 1906 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1907 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1908 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1909 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1910 dma-names = "tx", "rx"; 1911 power-domains = <&rpmhpd RPMHPD_CX>; 1912 operating-points-v2 = <&qup_opp_table>; 1913 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1914 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1915 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1916 interconnect-names = "qup-core", 1917 "qup-config", 1918 "qup-memory"; 1919 #address-cells = <1>; 1920 #size-cells = <0>; 1921 status = "disabled"; 1922 }; 1923 1924 i2c11: i2c@a8c000 { 1925 compatible = "qcom,geni-i2c"; 1926 reg = <0 0x00a8c000 0 0x4000>; 1927 clock-names = "se"; 1928 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1929 pinctrl-names = "default"; 1930 pinctrl-0 = <&qup_i2c11_default>; 1931 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1932 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1933 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1934 dma-names = "tx", "rx"; 1935 power-domains = <&rpmhpd SM8250_CX>; 1936 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1937 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1938 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1939 interconnect-names = "qup-core", 1940 "qup-config", 1941 "qup-memory"; 1942 #address-cells = <1>; 1943 #size-cells = <0>; 1944 status = "disabled"; 1945 }; 1946 1947 spi11: spi@a8c000 { 1948 compatible = "qcom,geni-spi"; 1949 reg = <0 0x00a8c000 0 0x4000>; 1950 clock-names = "se"; 1951 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1952 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1953 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1954 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1955 dma-names = "tx", "rx"; 1956 power-domains = <&rpmhpd RPMHPD_CX>; 1957 operating-points-v2 = <&qup_opp_table>; 1958 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1959 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1960 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1961 interconnect-names = "qup-core", 1962 "qup-config", 1963 "qup-memory"; 1964 #address-cells = <1>; 1965 #size-cells = <0>; 1966 status = "disabled"; 1967 }; 1968 1969 i2c12: i2c@a90000 { 1970 compatible = "qcom,geni-i2c"; 1971 reg = <0 0x00a90000 0 0x4000>; 1972 clock-names = "se"; 1973 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1974 pinctrl-names = "default"; 1975 pinctrl-0 = <&qup_i2c12_default>; 1976 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1977 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1978 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1979 dma-names = "tx", "rx"; 1980 power-domains = <&rpmhpd SM8250_CX>; 1981 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1982 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1983 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1984 interconnect-names = "qup-core", 1985 "qup-config", 1986 "qup-memory"; 1987 #address-cells = <1>; 1988 #size-cells = <0>; 1989 status = "disabled"; 1990 }; 1991 1992 spi12: spi@a90000 { 1993 compatible = "qcom,geni-spi"; 1994 reg = <0 0x00a90000 0 0x4000>; 1995 clock-names = "se"; 1996 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1997 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1998 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1999 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2000 dma-names = "tx", "rx"; 2001 power-domains = <&rpmhpd RPMHPD_CX>; 2002 operating-points-v2 = <&qup_opp_table>; 2003 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2004 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2005 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2006 interconnect-names = "qup-core", 2007 "qup-config", 2008 "qup-memory"; 2009 #address-cells = <1>; 2010 #size-cells = <0>; 2011 status = "disabled"; 2012 }; 2013 2014 uart12: serial@a90000 { 2015 compatible = "qcom,geni-debug-uart"; 2016 reg = <0x0 0x00a90000 0x0 0x4000>; 2017 clock-names = "se"; 2018 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2019 pinctrl-names = "default"; 2020 pinctrl-0 = <&qup_uart12_default>; 2021 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2022 power-domains = <&rpmhpd RPMHPD_CX>; 2023 operating-points-v2 = <&qup_opp_table>; 2024 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2025 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 2026 interconnect-names = "qup-core", 2027 "qup-config"; 2028 status = "disabled"; 2029 }; 2030 2031 i2c13: i2c@a94000 { 2032 compatible = "qcom,geni-i2c"; 2033 reg = <0 0x00a94000 0 0x4000>; 2034 clock-names = "se"; 2035 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2036 pinctrl-names = "default"; 2037 pinctrl-0 = <&qup_i2c13_default>; 2038 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2039 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2040 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2041 dma-names = "tx", "rx"; 2042 power-domains = <&rpmhpd SM8250_CX>; 2043 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2044 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2045 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2046 interconnect-names = "qup-core", 2047 "qup-config", 2048 "qup-memory"; 2049 #address-cells = <1>; 2050 #size-cells = <0>; 2051 status = "disabled"; 2052 }; 2053 2054 spi13: spi@a94000 { 2055 compatible = "qcom,geni-spi"; 2056 reg = <0 0x00a94000 0 0x4000>; 2057 clock-names = "se"; 2058 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2059 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2060 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2061 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2062 dma-names = "tx", "rx"; 2063 power-domains = <&rpmhpd RPMHPD_CX>; 2064 operating-points-v2 = <&qup_opp_table>; 2065 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2066 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2067 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2068 interconnect-names = "qup-core", 2069 "qup-config", 2070 "qup-memory"; 2071 #address-cells = <1>; 2072 #size-cells = <0>; 2073 status = "disabled"; 2074 }; 2075 }; 2076 2077 config_noc: interconnect@1500000 { 2078 compatible = "qcom,sm8250-config-noc"; 2079 reg = <0 0x01500000 0 0xa580>; 2080 #interconnect-cells = <2>; 2081 qcom,bcm-voters = <&apps_bcm_voter>; 2082 }; 2083 2084 system_noc: interconnect@1620000 { 2085 compatible = "qcom,sm8250-system-noc"; 2086 reg = <0 0x01620000 0 0x1c200>; 2087 #interconnect-cells = <2>; 2088 qcom,bcm-voters = <&apps_bcm_voter>; 2089 }; 2090 2091 mc_virt: interconnect@163d000 { 2092 compatible = "qcom,sm8250-mc-virt"; 2093 reg = <0 0x0163d000 0 0x1000>; 2094 #interconnect-cells = <2>; 2095 qcom,bcm-voters = <&apps_bcm_voter>; 2096 }; 2097 2098 aggre1_noc: interconnect@16e0000 { 2099 compatible = "qcom,sm8250-aggre1-noc"; 2100 reg = <0 0x016e0000 0 0x1f180>; 2101 #interconnect-cells = <2>; 2102 qcom,bcm-voters = <&apps_bcm_voter>; 2103 }; 2104 2105 aggre2_noc: interconnect@1700000 { 2106 compatible = "qcom,sm8250-aggre2-noc"; 2107 reg = <0 0x01700000 0 0x33000>; 2108 #interconnect-cells = <2>; 2109 qcom,bcm-voters = <&apps_bcm_voter>; 2110 }; 2111 2112 compute_noc: interconnect@1733000 { 2113 compatible = "qcom,sm8250-compute-noc"; 2114 reg = <0 0x01733000 0 0xa180>; 2115 #interconnect-cells = <2>; 2116 qcom,bcm-voters = <&apps_bcm_voter>; 2117 }; 2118 2119 mmss_noc: interconnect@1740000 { 2120 compatible = "qcom,sm8250-mmss-noc"; 2121 reg = <0 0x01740000 0 0x1f080>; 2122 #interconnect-cells = <2>; 2123 qcom,bcm-voters = <&apps_bcm_voter>; 2124 }; 2125 2126 pcie0: pcie@1c00000 { 2127 compatible = "qcom,pcie-sm8250"; 2128 reg = <0 0x01c00000 0 0x3000>, 2129 <0 0x60000000 0 0xf1d>, 2130 <0 0x60000f20 0 0xa8>, 2131 <0 0x60001000 0 0x1000>, 2132 <0 0x60100000 0 0x100000>, 2133 <0 0x01c03000 0 0x1000>; 2134 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2135 device_type = "pci"; 2136 linux,pci-domain = <0>; 2137 bus-range = <0x00 0xff>; 2138 num-lanes = <1>; 2139 2140 #address-cells = <3>; 2141 #size-cells = <2>; 2142 2143 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2144 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 2145 2146 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2154 interrupt-names = "msi0", 2155 "msi1", 2156 "msi2", 2157 "msi3", 2158 "msi4", 2159 "msi5", 2160 "msi6", 2161 "msi7"; 2162 #interrupt-cells = <1>; 2163 interrupt-map-mask = <0 0 0 0x7>; 2164 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2165 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2166 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2167 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2168 2169 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2170 <&gcc GCC_PCIE_0_AUX_CLK>, 2171 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2172 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2173 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2174 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2175 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2176 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2177 clock-names = "pipe", 2178 "aux", 2179 "cfg", 2180 "bus_master", 2181 "bus_slave", 2182 "slave_q2a", 2183 "tbu", 2184 "ddrss_sf_tbu"; 2185 2186 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2187 <0x100 &apps_smmu 0x1c01 0x1>; 2188 2189 resets = <&gcc GCC_PCIE_0_BCR>; 2190 reset-names = "pci"; 2191 2192 power-domains = <&gcc PCIE_0_GDSC>; 2193 2194 phys = <&pcie0_phy>; 2195 phy-names = "pciephy"; 2196 2197 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 2198 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 2199 2200 pinctrl-names = "default"; 2201 pinctrl-0 = <&pcie0_default_state>; 2202 dma-coherent; 2203 2204 status = "disabled"; 2205 2206 pcieport0: pcie@0 { 2207 device_type = "pci"; 2208 reg = <0x0 0x0 0x0 0x0 0x0>; 2209 bus-range = <0x01 0xff>; 2210 2211 #address-cells = <3>; 2212 #size-cells = <2>; 2213 ranges; 2214 }; 2215 }; 2216 2217 pcie0_phy: phy@1c06000 { 2218 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 2219 reg = <0 0x01c06000 0 0x1000>; 2220 2221 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2222 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2223 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 2224 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 2225 <&gcc GCC_PCIE_0_PIPE_CLK>; 2226 clock-names = "aux", 2227 "cfg_ahb", 2228 "ref", 2229 "refgen", 2230 "pipe"; 2231 2232 clock-output-names = "pcie_0_pipe_clk"; 2233 #clock-cells = <0>; 2234 2235 #phy-cells = <0>; 2236 2237 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2238 reset-names = "phy"; 2239 2240 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 2241 assigned-clock-rates = <100000000>; 2242 2243 status = "disabled"; 2244 }; 2245 2246 pcie1: pcie@1c08000 { 2247 compatible = "qcom,pcie-sm8250"; 2248 reg = <0 0x01c08000 0 0x3000>, 2249 <0 0x40000000 0 0xf1d>, 2250 <0 0x40000f20 0 0xa8>, 2251 <0 0x40001000 0 0x1000>, 2252 <0 0x40100000 0 0x100000>, 2253 <0 0x01c0b000 0 0x1000>; 2254 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2255 device_type = "pci"; 2256 linux,pci-domain = <1>; 2257 bus-range = <0x00 0xff>; 2258 num-lanes = <2>; 2259 2260 #address-cells = <3>; 2261 #size-cells = <2>; 2262 2263 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2264 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2265 2266 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2267 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2268 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2269 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2270 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2271 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2272 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2273 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2274 interrupt-names = "msi0", 2275 "msi1", 2276 "msi2", 2277 "msi3", 2278 "msi4", 2279 "msi5", 2280 "msi6", 2281 "msi7"; 2282 #interrupt-cells = <1>; 2283 interrupt-map-mask = <0 0 0 0x7>; 2284 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2285 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2286 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2287 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2288 2289 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2290 <&gcc GCC_PCIE_1_AUX_CLK>, 2291 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2292 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2293 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2294 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2295 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2296 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2297 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2298 clock-names = "pipe", 2299 "aux", 2300 "cfg", 2301 "bus_master", 2302 "bus_slave", 2303 "slave_q2a", 2304 "ref", 2305 "tbu", 2306 "ddrss_sf_tbu"; 2307 2308 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2309 assigned-clock-rates = <19200000>; 2310 2311 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2312 <0x100 &apps_smmu 0x1c81 0x1>; 2313 2314 resets = <&gcc GCC_PCIE_1_BCR>; 2315 reset-names = "pci"; 2316 2317 power-domains = <&gcc PCIE_1_GDSC>; 2318 2319 phys = <&pcie1_phy>; 2320 phy-names = "pciephy"; 2321 2322 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 2323 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 2324 2325 pinctrl-names = "default"; 2326 pinctrl-0 = <&pcie1_default_state>; 2327 dma-coherent; 2328 2329 status = "disabled"; 2330 2331 pcie@0 { 2332 device_type = "pci"; 2333 reg = <0x0 0x0 0x0 0x0 0x0>; 2334 bus-range = <0x01 0xff>; 2335 2336 #address-cells = <3>; 2337 #size-cells = <2>; 2338 ranges; 2339 }; 2340 }; 2341 2342 pcie1_phy: phy@1c0e000 { 2343 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2344 reg = <0 0x01c0e000 0 0x1000>; 2345 2346 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2347 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2348 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2349 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2350 <&gcc GCC_PCIE_1_PIPE_CLK>; 2351 clock-names = "aux", 2352 "cfg_ahb", 2353 "ref", 2354 "refgen", 2355 "pipe"; 2356 2357 clock-output-names = "pcie_1_pipe_clk"; 2358 #clock-cells = <0>; 2359 2360 #phy-cells = <0>; 2361 2362 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2363 reset-names = "phy"; 2364 2365 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2366 assigned-clock-rates = <100000000>; 2367 2368 status = "disabled"; 2369 }; 2370 2371 pcie2: pcie@1c10000 { 2372 compatible = "qcom,pcie-sm8250"; 2373 reg = <0 0x01c10000 0 0x3000>, 2374 <0 0x64000000 0 0xf1d>, 2375 <0 0x64000f20 0 0xa8>, 2376 <0 0x64001000 0 0x1000>, 2377 <0 0x64100000 0 0x100000>, 2378 <0 0x01c13000 0 0x1000>; 2379 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2380 device_type = "pci"; 2381 linux,pci-domain = <2>; 2382 bus-range = <0x00 0xff>; 2383 num-lanes = <2>; 2384 2385 #address-cells = <3>; 2386 #size-cells = <2>; 2387 2388 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, 2389 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2390 2391 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 2392 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2393 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2394 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2395 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2396 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 2399 interrupt-names = "msi0", 2400 "msi1", 2401 "msi2", 2402 "msi3", 2403 "msi4", 2404 "msi5", 2405 "msi6", 2406 "msi7"; 2407 #interrupt-cells = <1>; 2408 interrupt-map-mask = <0 0 0 0x7>; 2409 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2410 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2411 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2412 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2413 2414 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2415 <&gcc GCC_PCIE_2_AUX_CLK>, 2416 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2417 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2418 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2419 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2420 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2421 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2422 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2423 clock-names = "pipe", 2424 "aux", 2425 "cfg", 2426 "bus_master", 2427 "bus_slave", 2428 "slave_q2a", 2429 "ref", 2430 "tbu", 2431 "ddrss_sf_tbu"; 2432 2433 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2434 assigned-clock-rates = <19200000>; 2435 2436 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2437 <0x100 &apps_smmu 0x1d01 0x1>; 2438 2439 resets = <&gcc GCC_PCIE_2_BCR>; 2440 reset-names = "pci"; 2441 2442 power-domains = <&gcc PCIE_2_GDSC>; 2443 2444 phys = <&pcie2_phy>; 2445 phy-names = "pciephy"; 2446 2447 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2448 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2449 2450 pinctrl-names = "default"; 2451 pinctrl-0 = <&pcie2_default_state>; 2452 dma-coherent; 2453 2454 status = "disabled"; 2455 2456 pcie@0 { 2457 device_type = "pci"; 2458 reg = <0x0 0x0 0x0 0x0 0x0>; 2459 bus-range = <0x01 0xff>; 2460 2461 #address-cells = <3>; 2462 #size-cells = <2>; 2463 ranges; 2464 }; 2465 }; 2466 2467 pcie2_phy: phy@1c16000 { 2468 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2469 reg = <0 0x01c16000 0 0x1000>; 2470 2471 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2472 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2473 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2474 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2475 <&gcc GCC_PCIE_2_PIPE_CLK>; 2476 clock-names = "aux", 2477 "cfg_ahb", 2478 "ref", 2479 "refgen", 2480 "pipe"; 2481 2482 clock-output-names = "pcie_2_pipe_clk"; 2483 #clock-cells = <0>; 2484 2485 #phy-cells = <0>; 2486 2487 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2488 reset-names = "phy"; 2489 2490 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2491 assigned-clock-rates = <100000000>; 2492 2493 status = "disabled"; 2494 }; 2495 2496 ufs_mem_hc: ufshc@1d84000 { 2497 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2498 "jedec,ufs-2.0"; 2499 reg = <0 0x01d84000 0 0x3000>; 2500 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2501 phys = <&ufs_mem_phy>; 2502 phy-names = "ufsphy"; 2503 lanes-per-direction = <2>; 2504 #reset-cells = <1>; 2505 resets = <&gcc GCC_UFS_PHY_BCR>; 2506 reset-names = "rst"; 2507 2508 power-domains = <&gcc UFS_PHY_GDSC>; 2509 2510 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2511 2512 clock-names = 2513 "core_clk", 2514 "bus_aggr_clk", 2515 "iface_clk", 2516 "core_clk_unipro", 2517 "ref_clk", 2518 "tx_lane0_sync_clk", 2519 "rx_lane0_sync_clk", 2520 "rx_lane1_sync_clk"; 2521 clocks = 2522 <&gcc GCC_UFS_PHY_AXI_CLK>, 2523 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2524 <&gcc GCC_UFS_PHY_AHB_CLK>, 2525 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2526 <&rpmhcc RPMH_CXO_CLK>, 2527 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2528 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2529 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2530 2531 operating-points-v2 = <&ufs_opp_table>; 2532 2533 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>, 2534 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2535 interconnect-names = "ufs-ddr", "cpu-ufs"; 2536 2537 status = "disabled"; 2538 2539 ufs_opp_table: opp-table { 2540 compatible = "operating-points-v2"; 2541 2542 opp-37500000 { 2543 opp-hz = /bits/ 64 <37500000>, 2544 /bits/ 64 <0>, 2545 /bits/ 64 <0>, 2546 /bits/ 64 <37500000>, 2547 /bits/ 64 <0>, 2548 /bits/ 64 <0>, 2549 /bits/ 64 <0>, 2550 /bits/ 64 <0>; 2551 required-opps = <&rpmhpd_opp_low_svs>; 2552 }; 2553 2554 opp-300000000 { 2555 opp-hz = /bits/ 64 <300000000>, 2556 /bits/ 64 <0>, 2557 /bits/ 64 <0>, 2558 /bits/ 64 <300000000>, 2559 /bits/ 64 <0>, 2560 /bits/ 64 <0>, 2561 /bits/ 64 <0>, 2562 /bits/ 64 <0>; 2563 required-opps = <&rpmhpd_opp_nom>; 2564 }; 2565 }; 2566 }; 2567 2568 ufs_mem_phy: phy@1d87000 { 2569 compatible = "qcom,sm8250-qmp-ufs-phy"; 2570 reg = <0 0x01d87000 0 0x1000>; 2571 2572 clocks = <&rpmhcc RPMH_CXO_CLK>, 2573 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2574 <&gcc GCC_UFS_1X_CLKREF_EN>; 2575 clock-names = "ref", 2576 "ref_aux", 2577 "qref"; 2578 2579 resets = <&ufs_mem_hc 0>; 2580 reset-names = "ufsphy"; 2581 2582 power-domains = <&gcc UFS_PHY_GDSC>; 2583 2584 #phy-cells = <0>; 2585 2586 status = "disabled"; 2587 }; 2588 2589 cryptobam: dma-controller@1dc4000 { 2590 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2591 reg = <0 0x01dc4000 0 0x24000>; 2592 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2593 #dma-cells = <1>; 2594 qcom,ee = <0>; 2595 qcom,controlled-remotely; 2596 num-channels = <8>; 2597 qcom,num-ees = <2>; 2598 iommus = <&apps_smmu 0x592 0x0000>, 2599 <&apps_smmu 0x598 0x0000>, 2600 <&apps_smmu 0x599 0x0000>, 2601 <&apps_smmu 0x59f 0x0000>, 2602 <&apps_smmu 0x586 0x0011>, 2603 <&apps_smmu 0x596 0x0011>; 2604 }; 2605 2606 crypto: crypto@1dfa000 { 2607 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce"; 2608 reg = <0 0x01dfa000 0 0x6000>; 2609 dmas = <&cryptobam 4>, <&cryptobam 5>; 2610 dma-names = "rx", "tx"; 2611 iommus = <&apps_smmu 0x592 0x0000>, 2612 <&apps_smmu 0x598 0x0000>, 2613 <&apps_smmu 0x599 0x0000>, 2614 <&apps_smmu 0x59f 0x0000>, 2615 <&apps_smmu 0x586 0x0011>, 2616 <&apps_smmu 0x596 0x0011>; 2617 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2618 interconnect-names = "memory"; 2619 }; 2620 2621 tcsr_mutex: hwlock@1f40000 { 2622 compatible = "qcom,tcsr-mutex"; 2623 reg = <0x0 0x01f40000 0x0 0x40000>; 2624 #hwlock-cells = <1>; 2625 }; 2626 2627 tcsr: syscon@1fc0000 { 2628 compatible = "qcom,sm8250-tcsr", "syscon"; 2629 reg = <0x0 0x1fc0000 0x0 0x30000>; 2630 }; 2631 2632 wsamacro: codec@3240000 { 2633 compatible = "qcom,sm8250-lpass-wsa-macro"; 2634 reg = <0 0x03240000 0 0x1000>; 2635 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2636 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2637 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2638 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2639 <&vamacro>; 2640 2641 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2642 2643 #clock-cells = <0>; 2644 clock-output-names = "mclk"; 2645 #sound-dai-cells = <1>; 2646 2647 pinctrl-names = "default"; 2648 pinctrl-0 = <&wsa_swr_active>; 2649 2650 status = "disabled"; 2651 }; 2652 2653 swr0: soundwire@3250000 { 2654 reg = <0 0x03250000 0 0x2000>; 2655 compatible = "qcom,soundwire-v1.5.1"; 2656 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2657 clocks = <&wsamacro>; 2658 clock-names = "iface"; 2659 2660 qcom,din-ports = <2>; 2661 qcom,dout-ports = <6>; 2662 2663 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2664 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2665 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2666 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2667 2668 #sound-dai-cells = <1>; 2669 #address-cells = <2>; 2670 #size-cells = <0>; 2671 2672 status = "disabled"; 2673 }; 2674 2675 vamacro: codec@3370000 { 2676 compatible = "qcom,sm8250-lpass-va-macro"; 2677 reg = <0 0x03370000 0 0x1000>; 2678 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2679 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2680 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2681 2682 clock-names = "mclk", "macro", "dcodec"; 2683 2684 #clock-cells = <0>; 2685 clock-output-names = "fsgen"; 2686 #sound-dai-cells = <1>; 2687 }; 2688 2689 rxmacro: rxmacro@3200000 { 2690 pinctrl-names = "default"; 2691 pinctrl-0 = <&rx_swr_active>; 2692 compatible = "qcom,sm8250-lpass-rx-macro"; 2693 reg = <0 0x03200000 0 0x1000>; 2694 status = "disabled"; 2695 2696 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2697 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2698 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2699 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2700 <&vamacro>; 2701 2702 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2703 2704 #clock-cells = <0>; 2705 clock-output-names = "mclk"; 2706 #sound-dai-cells = <1>; 2707 }; 2708 2709 swr1: soundwire@3210000 { 2710 reg = <0 0x03210000 0 0x2000>; 2711 compatible = "qcom,soundwire-v1.5.1"; 2712 status = "disabled"; 2713 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2714 clocks = <&rxmacro>; 2715 clock-names = "iface"; 2716 label = "RX"; 2717 qcom,din-ports = <0>; 2718 qcom,dout-ports = <5>; 2719 2720 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2721 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2722 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2723 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2724 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2725 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2726 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2727 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2728 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2729 2730 #sound-dai-cells = <1>; 2731 #address-cells = <2>; 2732 #size-cells = <0>; 2733 }; 2734 2735 txmacro: txmacro@3220000 { 2736 pinctrl-names = "default"; 2737 pinctrl-0 = <&tx_swr_active>; 2738 compatible = "qcom,sm8250-lpass-tx-macro"; 2739 reg = <0 0x03220000 0 0x1000>; 2740 status = "disabled"; 2741 2742 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2743 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2744 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2745 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2746 <&vamacro>; 2747 2748 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2749 2750 #clock-cells = <0>; 2751 clock-output-names = "mclk"; 2752 #sound-dai-cells = <1>; 2753 }; 2754 2755 /* tx macro */ 2756 swr2: soundwire@3230000 { 2757 reg = <0 0x03230000 0 0x2000>; 2758 compatible = "qcom,soundwire-v1.5.1"; 2759 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2760 interrupt-names = "core"; 2761 status = "disabled"; 2762 2763 clocks = <&txmacro>; 2764 clock-names = "iface"; 2765 label = "TX"; 2766 2767 qcom,din-ports = <5>; 2768 qcom,dout-ports = <0>; 2769 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; 2770 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; 2771 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; 2772 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2773 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2774 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2775 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2776 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2777 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; 2778 #sound-dai-cells = <1>; 2779 #address-cells = <2>; 2780 #size-cells = <0>; 2781 }; 2782 2783 lpass_tlmm: pinctrl@33c0000 { 2784 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2785 reg = <0 0x033c0000 0x0 0x20000>, 2786 <0 0x03550000 0x0 0x10000>; 2787 gpio-controller; 2788 #gpio-cells = <2>; 2789 gpio-ranges = <&lpass_tlmm 0 0 14>; 2790 2791 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2792 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2793 clock-names = "core", "audio"; 2794 2795 wsa_swr_active: wsa-swr-active-state { 2796 clk-pins { 2797 pins = "gpio10"; 2798 function = "wsa_swr_clk"; 2799 drive-strength = <2>; 2800 slew-rate = <1>; 2801 bias-disable; 2802 }; 2803 2804 data-pins { 2805 pins = "gpio11"; 2806 function = "wsa_swr_data"; 2807 drive-strength = <2>; 2808 slew-rate = <1>; 2809 bias-bus-hold; 2810 }; 2811 }; 2812 2813 wsa_swr_sleep: wsa-swr-sleep-state { 2814 clk-pins { 2815 pins = "gpio10"; 2816 function = "wsa_swr_clk"; 2817 drive-strength = <2>; 2818 bias-pull-down; 2819 }; 2820 2821 data-pins { 2822 pins = "gpio11"; 2823 function = "wsa_swr_data"; 2824 drive-strength = <2>; 2825 bias-pull-down; 2826 }; 2827 }; 2828 2829 dmic01_active: dmic01-active-state { 2830 clk-pins { 2831 pins = "gpio6"; 2832 function = "dmic1_clk"; 2833 drive-strength = <8>; 2834 output-high; 2835 }; 2836 data-pins { 2837 pins = "gpio7"; 2838 function = "dmic1_data"; 2839 drive-strength = <8>; 2840 }; 2841 }; 2842 2843 dmic01_sleep: dmic01-sleep-state { 2844 clk-pins { 2845 pins = "gpio6"; 2846 function = "dmic1_clk"; 2847 drive-strength = <2>; 2848 bias-disable; 2849 output-low; 2850 }; 2851 2852 data-pins { 2853 pins = "gpio7"; 2854 function = "dmic1_data"; 2855 drive-strength = <2>; 2856 bias-pull-down; 2857 }; 2858 }; 2859 2860 rx_swr_active: rx-swr-active-state { 2861 clk-pins { 2862 pins = "gpio3"; 2863 function = "swr_rx_clk"; 2864 drive-strength = <2>; 2865 slew-rate = <1>; 2866 bias-disable; 2867 }; 2868 2869 data-pins { 2870 pins = "gpio4", "gpio5"; 2871 function = "swr_rx_data"; 2872 drive-strength = <2>; 2873 slew-rate = <1>; 2874 bias-bus-hold; 2875 }; 2876 }; 2877 2878 tx_swr_active: tx-swr-active-state { 2879 clk-pins { 2880 pins = "gpio0"; 2881 function = "swr_tx_clk"; 2882 drive-strength = <2>; 2883 slew-rate = <1>; 2884 bias-disable; 2885 }; 2886 2887 data-pins { 2888 pins = "gpio1", "gpio2"; 2889 function = "swr_tx_data"; 2890 drive-strength = <2>; 2891 slew-rate = <1>; 2892 bias-bus-hold; 2893 }; 2894 }; 2895 2896 tx_swr_sleep: tx-swr-sleep-state { 2897 clk-pins { 2898 pins = "gpio0"; 2899 function = "swr_tx_clk"; 2900 drive-strength = <2>; 2901 bias-pull-down; 2902 }; 2903 2904 data1-pins { 2905 pins = "gpio1"; 2906 function = "swr_tx_data"; 2907 drive-strength = <2>; 2908 bias-bus-hold; 2909 }; 2910 2911 data2-pins { 2912 pins = "gpio2"; 2913 function = "swr_tx_data"; 2914 drive-strength = <2>; 2915 bias-pull-down; 2916 }; 2917 }; 2918 }; 2919 2920 gpu: gpu@3d00000 { 2921 compatible = "qcom,adreno-650.2", 2922 "qcom,adreno"; 2923 2924 reg = <0 0x03d00000 0 0x40000>; 2925 reg-names = "kgsl_3d0_reg_memory"; 2926 2927 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2928 2929 iommus = <&adreno_smmu 0 0x401>; 2930 2931 operating-points-v2 = <&gpu_opp_table>; 2932 2933 qcom,gmu = <&gmu>; 2934 2935 nvmem-cells = <&gpu_speed_bin>; 2936 nvmem-cell-names = "speed_bin"; 2937 #cooling-cells = <2>; 2938 2939 status = "disabled"; 2940 2941 zap-shader { 2942 memory-region = <&gpu_mem>; 2943 }; 2944 2945 gpu_opp_table: opp-table { 2946 compatible = "operating-points-v2"; 2947 2948 opp-670000000 { 2949 opp-hz = /bits/ 64 <670000000>; 2950 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2951 opp-supported-hw = <0xa>; 2952 }; 2953 2954 opp-587000000 { 2955 opp-hz = /bits/ 64 <587000000>; 2956 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2957 opp-supported-hw = <0xb>; 2958 }; 2959 2960 opp-525000000 { 2961 opp-hz = /bits/ 64 <525000000>; 2962 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2963 opp-supported-hw = <0xf>; 2964 }; 2965 2966 opp-490000000 { 2967 opp-hz = /bits/ 64 <490000000>; 2968 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2969 opp-supported-hw = <0xf>; 2970 }; 2971 2972 opp-441600000 { 2973 opp-hz = /bits/ 64 <441600000>; 2974 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2975 opp-supported-hw = <0xf>; 2976 }; 2977 2978 opp-400000000 { 2979 opp-hz = /bits/ 64 <400000000>; 2980 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2981 opp-supported-hw = <0xf>; 2982 }; 2983 2984 opp-305000000 { 2985 opp-hz = /bits/ 64 <305000000>; 2986 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2987 opp-supported-hw = <0xf>; 2988 }; 2989 }; 2990 }; 2991 2992 gmu: gmu@3d6a000 { 2993 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2994 2995 reg = <0 0x03d6a000 0 0x30000>, 2996 <0 0x3de0000 0 0x10000>, 2997 <0 0xb290000 0 0x10000>, 2998 <0 0xb490000 0 0x10000>; 2999 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 3000 3001 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3002 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3003 interrupt-names = "hfi", "gmu"; 3004 3005 clocks = <&gpucc GPU_CC_AHB_CLK>, 3006 <&gpucc GPU_CC_CX_GMU_CLK>, 3007 <&gpucc GPU_CC_CXO_CLK>, 3008 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3009 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 3010 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 3011 3012 power-domains = <&gpucc GPU_CX_GDSC>, 3013 <&gpucc GPU_GX_GDSC>; 3014 power-domain-names = "cx", "gx"; 3015 3016 iommus = <&adreno_smmu 5 0x400>; 3017 3018 operating-points-v2 = <&gmu_opp_table>; 3019 3020 status = "disabled"; 3021 3022 gmu_opp_table: opp-table { 3023 compatible = "operating-points-v2"; 3024 3025 opp-200000000 { 3026 opp-hz = /bits/ 64 <200000000>; 3027 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3028 }; 3029 }; 3030 }; 3031 3032 gpucc: clock-controller@3d90000 { 3033 compatible = "qcom,sm8250-gpucc"; 3034 reg = <0 0x03d90000 0 0x9000>; 3035 clocks = <&rpmhcc RPMH_CXO_CLK>, 3036 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3037 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3038 clock-names = "bi_tcxo", 3039 "gcc_gpu_gpll0_clk_src", 3040 "gcc_gpu_gpll0_div_clk_src"; 3041 #clock-cells = <1>; 3042 #reset-cells = <1>; 3043 #power-domain-cells = <1>; 3044 }; 3045 3046 adreno_smmu: iommu@3da0000 { 3047 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", 3048 "qcom,smmu-500", "arm,mmu-500"; 3049 reg = <0 0x03da0000 0 0x10000>; 3050 #iommu-cells = <2>; 3051 #global-interrupts = <2>; 3052 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 3053 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3054 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3055 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3056 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3057 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3058 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3059 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3060 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3061 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 3062 clocks = <&gpucc GPU_CC_AHB_CLK>, 3063 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3064 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 3065 clock-names = "ahb", "bus", "iface"; 3066 3067 power-domains = <&gpucc GPU_CX_GDSC>; 3068 dma-coherent; 3069 }; 3070 3071 slpi: remoteproc@5c00000 { 3072 compatible = "qcom,sm8250-slpi-pas"; 3073 reg = <0 0x05c00000 0 0x4000>; 3074 3075 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 3076 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 3077 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 3078 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 3079 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 3080 interrupt-names = "wdog", "fatal", "ready", 3081 "handover", "stop-ack"; 3082 3083 clocks = <&rpmhcc RPMH_CXO_CLK>; 3084 clock-names = "xo"; 3085 3086 power-domains = <&rpmhpd RPMHPD_LCX>, 3087 <&rpmhpd RPMHPD_LMX>; 3088 power-domain-names = "lcx", "lmx"; 3089 3090 memory-region = <&slpi_mem>; 3091 3092 qcom,qmp = <&aoss_qmp>; 3093 3094 qcom,smem-states = <&smp2p_slpi_out 0>; 3095 qcom,smem-state-names = "stop"; 3096 3097 status = "disabled"; 3098 3099 glink-edge { 3100 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 3101 IPCC_MPROC_SIGNAL_GLINK_QMP 3102 IRQ_TYPE_EDGE_RISING>; 3103 mboxes = <&ipcc IPCC_CLIENT_SLPI 3104 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3105 3106 label = "slpi"; 3107 qcom,remote-pid = <3>; 3108 3109 fastrpc { 3110 compatible = "qcom,fastrpc"; 3111 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3112 label = "sdsp"; 3113 qcom,non-secure-domain; 3114 #address-cells = <1>; 3115 #size-cells = <0>; 3116 3117 compute-cb@1 { 3118 compatible = "qcom,fastrpc-compute-cb"; 3119 reg = <1>; 3120 iommus = <&apps_smmu 0x0541 0x0>; 3121 }; 3122 3123 compute-cb@2 { 3124 compatible = "qcom,fastrpc-compute-cb"; 3125 reg = <2>; 3126 iommus = <&apps_smmu 0x0542 0x0>; 3127 }; 3128 3129 compute-cb@3 { 3130 compatible = "qcom,fastrpc-compute-cb"; 3131 reg = <3>; 3132 iommus = <&apps_smmu 0x0543 0x0>; 3133 /* note: shared-cb = <4> in downstream */ 3134 }; 3135 }; 3136 }; 3137 }; 3138 3139 stm@6002000 { 3140 compatible = "arm,coresight-stm", "arm,primecell"; 3141 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; 3142 reg-names = "stm-base", "stm-stimulus-base"; 3143 3144 clocks = <&aoss_qmp>; 3145 clock-names = "apb_pclk"; 3146 3147 out-ports { 3148 port { 3149 stm_out: endpoint { 3150 remote-endpoint = <&funnel0_in7>; 3151 }; 3152 }; 3153 }; 3154 }; 3155 3156 tpda@6004000 { 3157 compatible = "qcom,coresight-tpda", "arm,primecell"; 3158 reg = <0 0x06004000 0 0x1000>; 3159 3160 clocks = <&aoss_qmp>; 3161 clock-names = "apb_pclk"; 3162 3163 out-ports { 3164 3165 port { 3166 tpda_out_funnel_qatb: endpoint { 3167 remote-endpoint = <&funnel_qatb_in_tpda>; 3168 }; 3169 }; 3170 }; 3171 3172 in-ports { 3173 #address-cells = <1>; 3174 #size-cells = <0>; 3175 3176 port@9 { 3177 reg = <9>; 3178 tpda_9_in_tpdm_mm: endpoint { 3179 remote-endpoint = <&tpdm_mm_out_tpda9>; 3180 }; 3181 }; 3182 3183 port@17 { 3184 reg = <23>; 3185 tpda_23_in_tpdm_prng: endpoint { 3186 remote-endpoint = <&tpdm_prng_out_tpda_23>; 3187 }; 3188 }; 3189 }; 3190 }; 3191 3192 funnel@6005000 { 3193 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3194 reg = <0 0x06005000 0 0x1000>; 3195 3196 clocks = <&aoss_qmp>; 3197 clock-names = "apb_pclk"; 3198 3199 out-ports { 3200 port { 3201 funnel_qatb_out_funnel_in0: endpoint { 3202 remote-endpoint = <&funnel_in0_in_funnel_qatb>; 3203 }; 3204 }; 3205 }; 3206 3207 in-ports { 3208 port { 3209 funnel_qatb_in_tpda: endpoint { 3210 remote-endpoint = <&tpda_out_funnel_qatb>; 3211 }; 3212 }; 3213 }; 3214 }; 3215 3216 funnel@6041000 { 3217 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3218 reg = <0 0x06041000 0 0x1000>; 3219 3220 clocks = <&aoss_qmp>; 3221 clock-names = "apb_pclk"; 3222 3223 out-ports { 3224 port { 3225 funnel_in0_out_funnel_merg: endpoint { 3226 remote-endpoint = <&funnel_merg_in_funnel_in0>; 3227 }; 3228 }; 3229 }; 3230 3231 in-ports { 3232 #address-cells = <1>; 3233 #size-cells = <0>; 3234 3235 port@6 { 3236 reg = <6>; 3237 funnel_in0_in_funnel_qatb: endpoint { 3238 remote-endpoint = <&funnel_qatb_out_funnel_in0>; 3239 }; 3240 }; 3241 3242 port@7 { 3243 reg = <7>; 3244 funnel0_in7: endpoint { 3245 remote-endpoint = <&stm_out>; 3246 }; 3247 }; 3248 }; 3249 }; 3250 3251 funnel@6042000 { 3252 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3253 reg = <0 0x06042000 0 0x1000>; 3254 3255 clocks = <&aoss_qmp>; 3256 clock-names = "apb_pclk"; 3257 3258 out-ports { 3259 port { 3260 funnel_in1_out_funnel_merg: endpoint { 3261 remote-endpoint = <&funnel_merg_in_funnel_in1>; 3262 }; 3263 }; 3264 }; 3265 3266 in-ports { 3267 #address-cells = <1>; 3268 #size-cells = <0>; 3269 3270 port@4 { 3271 reg = <4>; 3272 funnel_in1_in_funnel_apss_merg: endpoint { 3273 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; 3274 }; 3275 }; 3276 }; 3277 }; 3278 3279 funnel@6045000 { 3280 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3281 reg = <0 0x06045000 0 0x1000>; 3282 3283 clocks = <&aoss_qmp>; 3284 clock-names = "apb_pclk"; 3285 3286 out-ports { 3287 port { 3288 funnel_merg_out_funnel_swao: endpoint { 3289 remote-endpoint = <&funnel_swao_in_funnel_merg>; 3290 }; 3291 }; 3292 }; 3293 3294 in-ports { 3295 #address-cells = <1>; 3296 #size-cells = <0>; 3297 3298 port@0 { 3299 reg = <0>; 3300 funnel_merg_in_funnel_in0: endpoint { 3301 remote-endpoint = <&funnel_in0_out_funnel_merg>; 3302 }; 3303 }; 3304 3305 port@1 { 3306 reg = <1>; 3307 funnel_merg_in_funnel_in1: endpoint { 3308 remote-endpoint = <&funnel_in1_out_funnel_merg>; 3309 }; 3310 }; 3311 }; 3312 }; 3313 3314 replicator@6046000 { 3315 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3316 reg = <0 0x06046000 0 0x1000>; 3317 3318 clocks = <&aoss_qmp>; 3319 clock-names = "apb_pclk"; 3320 3321 out-ports { 3322 port { 3323 replicator_out: endpoint { 3324 remote-endpoint = <&etr_in>; 3325 }; 3326 }; 3327 }; 3328 3329 in-ports { 3330 port { 3331 replicator_cx_in_swao_out: endpoint { 3332 remote-endpoint = <&replicator_swao_out_cx_in>; 3333 }; 3334 }; 3335 }; 3336 }; 3337 3338 etr@6048000 { 3339 compatible = "arm,coresight-tmc", "arm,primecell"; 3340 reg = <0 0x06048000 0 0x1000>; 3341 3342 clocks = <&aoss_qmp>; 3343 clock-names = "apb_pclk"; 3344 arm,scatter-gather; 3345 3346 in-ports { 3347 port { 3348 etr_in: endpoint { 3349 remote-endpoint = <&replicator_out>; 3350 }; 3351 }; 3352 }; 3353 }; 3354 3355 tpdm@684c000 { 3356 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3357 reg = <0 0x0684c000 0 0x1000>; 3358 3359 clocks = <&aoss_qmp>; 3360 clock-names = "apb_pclk"; 3361 3362 out-ports { 3363 port { 3364 tpdm_prng_out_tpda_23: endpoint { 3365 remote-endpoint = <&tpda_23_in_tpdm_prng>; 3366 }; 3367 }; 3368 }; 3369 }; 3370 3371 funnel@6b04000 { 3372 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3373 arm,primecell-periphid = <0x000bb908>; 3374 3375 reg = <0 0x06b04000 0 0x1000>; 3376 3377 clocks = <&aoss_qmp>; 3378 clock-names = "apb_pclk"; 3379 3380 out-ports { 3381 port { 3382 funnel_swao_out_etf: endpoint { 3383 remote-endpoint = <&etf_in_funnel_swao_out>; 3384 }; 3385 }; 3386 }; 3387 3388 in-ports { 3389 #address-cells = <1>; 3390 #size-cells = <0>; 3391 3392 port@7 { 3393 reg = <7>; 3394 funnel_swao_in_funnel_merg: endpoint { 3395 remote-endpoint = <&funnel_merg_out_funnel_swao>; 3396 }; 3397 }; 3398 }; 3399 }; 3400 3401 etf@6b05000 { 3402 compatible = "arm,coresight-tmc", "arm,primecell"; 3403 reg = <0 0x06b05000 0 0x1000>; 3404 3405 clocks = <&aoss_qmp>; 3406 clock-names = "apb_pclk"; 3407 3408 out-ports { 3409 port { 3410 etf_out: endpoint { 3411 remote-endpoint = <&replicator_in>; 3412 }; 3413 }; 3414 }; 3415 3416 in-ports { 3417 3418 port { 3419 etf_in_funnel_swao_out: endpoint { 3420 remote-endpoint = <&funnel_swao_out_etf>; 3421 }; 3422 }; 3423 }; 3424 }; 3425 3426 replicator@6b06000 { 3427 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3428 reg = <0 0x06b06000 0 0x1000>; 3429 3430 clocks = <&aoss_qmp>; 3431 clock-names = "apb_pclk"; 3432 3433 out-ports { 3434 port { 3435 replicator_swao_out_cx_in: endpoint { 3436 remote-endpoint = <&replicator_cx_in_swao_out>; 3437 }; 3438 }; 3439 }; 3440 3441 in-ports { 3442 port { 3443 replicator_in: endpoint { 3444 remote-endpoint = <&etf_out>; 3445 }; 3446 }; 3447 }; 3448 }; 3449 3450 tpdm@6c08000 { 3451 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3452 reg = <0 0x06c08000 0 0x1000>; 3453 3454 clocks = <&aoss_qmp>; 3455 clock-names = "apb_pclk"; 3456 3457 out-ports { 3458 port { 3459 tpdm_mm_out_funnel_dl_mm: endpoint { 3460 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; 3461 }; 3462 }; 3463 }; 3464 }; 3465 3466 funnel@6c0b000 { 3467 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3468 reg = <0 0x06c0b000 0 0x1000>; 3469 3470 clocks = <&aoss_qmp>; 3471 clock-names = "apb_pclk"; 3472 3473 out-ports { 3474 port { 3475 funnel_dl_mm_out_funnel_dl_center: endpoint { 3476 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>; 3477 }; 3478 }; 3479 }; 3480 3481 in-ports { 3482 #address-cells = <1>; 3483 #size-cells = <0>; 3484 3485 port@3 { 3486 reg = <3>; 3487 funnel_dl_mm_in_tpdm_mm: endpoint { 3488 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>; 3489 }; 3490 }; 3491 }; 3492 }; 3493 3494 funnel@6c2d000 { 3495 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3496 reg = <0 0x06c2d000 0 0x1000>; 3497 3498 clocks = <&aoss_qmp>; 3499 clock-names = "apb_pclk"; 3500 3501 out-ports { 3502 port { 3503 tpdm_mm_out_tpda9: endpoint { 3504 remote-endpoint = <&tpda_9_in_tpdm_mm>; 3505 }; 3506 }; 3507 }; 3508 3509 in-ports { 3510 #address-cells = <1>; 3511 #size-cells = <0>; 3512 3513 port@2 { 3514 reg = <2>; 3515 funnel_dl_center_in_funnel_dl_mm: endpoint { 3516 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>; 3517 }; 3518 }; 3519 }; 3520 }; 3521 3522 etm@7040000 { 3523 compatible = "arm,coresight-etm4x", "arm,primecell"; 3524 reg = <0 0x07040000 0 0x1000>; 3525 3526 cpu = <&cpu0>; 3527 3528 clocks = <&aoss_qmp>; 3529 clock-names = "apb_pclk"; 3530 arm,coresight-loses-context-with-cpu; 3531 3532 out-ports { 3533 port { 3534 etm0_out: endpoint { 3535 remote-endpoint = <&apss_funnel_in0>; 3536 }; 3537 }; 3538 }; 3539 }; 3540 3541 etm@7140000 { 3542 compatible = "arm,coresight-etm4x", "arm,primecell"; 3543 reg = <0 0x07140000 0 0x1000>; 3544 3545 cpu = <&cpu1>; 3546 3547 clocks = <&aoss_qmp>; 3548 clock-names = "apb_pclk"; 3549 arm,coresight-loses-context-with-cpu; 3550 3551 out-ports { 3552 port { 3553 etm1_out: endpoint { 3554 remote-endpoint = <&apss_funnel_in1>; 3555 }; 3556 }; 3557 }; 3558 }; 3559 3560 etm@7240000 { 3561 compatible = "arm,coresight-etm4x", "arm,primecell"; 3562 reg = <0 0x07240000 0 0x1000>; 3563 3564 cpu = <&cpu2>; 3565 3566 clocks = <&aoss_qmp>; 3567 clock-names = "apb_pclk"; 3568 arm,coresight-loses-context-with-cpu; 3569 3570 out-ports { 3571 port { 3572 etm2_out: endpoint { 3573 remote-endpoint = <&apss_funnel_in2>; 3574 }; 3575 }; 3576 }; 3577 }; 3578 3579 etm@7340000 { 3580 compatible = "arm,coresight-etm4x", "arm,primecell"; 3581 reg = <0 0x07340000 0 0x1000>; 3582 3583 cpu = <&cpu3>; 3584 3585 clocks = <&aoss_qmp>; 3586 clock-names = "apb_pclk"; 3587 arm,coresight-loses-context-with-cpu; 3588 3589 out-ports { 3590 port { 3591 etm3_out: endpoint { 3592 remote-endpoint = <&apss_funnel_in3>; 3593 }; 3594 }; 3595 }; 3596 }; 3597 3598 etm@7440000 { 3599 compatible = "arm,coresight-etm4x", "arm,primecell"; 3600 reg = <0 0x07440000 0 0x1000>; 3601 3602 cpu = <&cpu4>; 3603 3604 clocks = <&aoss_qmp>; 3605 clock-names = "apb_pclk"; 3606 arm,coresight-loses-context-with-cpu; 3607 3608 out-ports { 3609 port { 3610 etm4_out: endpoint { 3611 remote-endpoint = <&apss_funnel_in4>; 3612 }; 3613 }; 3614 }; 3615 }; 3616 3617 etm@7540000 { 3618 compatible = "arm,coresight-etm4x", "arm,primecell"; 3619 reg = <0 0x07540000 0 0x1000>; 3620 3621 cpu = <&cpu5>; 3622 3623 clocks = <&aoss_qmp>; 3624 clock-names = "apb_pclk"; 3625 arm,coresight-loses-context-with-cpu; 3626 3627 out-ports { 3628 port { 3629 etm5_out: endpoint { 3630 remote-endpoint = <&apss_funnel_in5>; 3631 }; 3632 }; 3633 }; 3634 }; 3635 3636 etm@7640000 { 3637 compatible = "arm,coresight-etm4x", "arm,primecell"; 3638 reg = <0 0x07640000 0 0x1000>; 3639 3640 cpu = <&cpu6>; 3641 3642 clocks = <&aoss_qmp>; 3643 clock-names = "apb_pclk"; 3644 arm,coresight-loses-context-with-cpu; 3645 3646 out-ports { 3647 port { 3648 etm6_out: endpoint { 3649 remote-endpoint = <&apss_funnel_in6>; 3650 }; 3651 }; 3652 }; 3653 }; 3654 3655 etm@7740000 { 3656 compatible = "arm,coresight-etm4x", "arm,primecell"; 3657 reg = <0 0x07740000 0 0x1000>; 3658 3659 cpu = <&cpu7>; 3660 3661 clocks = <&aoss_qmp>; 3662 clock-names = "apb_pclk"; 3663 arm,coresight-loses-context-with-cpu; 3664 3665 out-ports { 3666 port { 3667 etm7_out: endpoint { 3668 remote-endpoint = <&apss_funnel_in7>; 3669 }; 3670 }; 3671 }; 3672 }; 3673 3674 funnel@7800000 { 3675 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3676 reg = <0 0x07800000 0 0x1000>; 3677 3678 clocks = <&aoss_qmp>; 3679 clock-names = "apb_pclk"; 3680 3681 out-ports { 3682 port { 3683 funnel_apss_out_funnel_apss_merg: endpoint { 3684 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; 3685 }; 3686 }; 3687 }; 3688 3689 in-ports { 3690 #address-cells = <1>; 3691 #size-cells = <0>; 3692 3693 port@0 { 3694 reg = <0>; 3695 apss_funnel_in0: endpoint { 3696 remote-endpoint = <&etm0_out>; 3697 }; 3698 }; 3699 3700 port@1 { 3701 reg = <1>; 3702 apss_funnel_in1: endpoint { 3703 remote-endpoint = <&etm1_out>; 3704 }; 3705 }; 3706 3707 port@2 { 3708 reg = <2>; 3709 apss_funnel_in2: endpoint { 3710 remote-endpoint = <&etm2_out>; 3711 }; 3712 }; 3713 3714 port@3 { 3715 reg = <3>; 3716 apss_funnel_in3: endpoint { 3717 remote-endpoint = <&etm3_out>; 3718 }; 3719 }; 3720 3721 port@4 { 3722 reg = <4>; 3723 apss_funnel_in4: endpoint { 3724 remote-endpoint = <&etm4_out>; 3725 }; 3726 }; 3727 3728 port@5 { 3729 reg = <5>; 3730 apss_funnel_in5: endpoint { 3731 remote-endpoint = <&etm5_out>; 3732 }; 3733 }; 3734 3735 port@6 { 3736 reg = <6>; 3737 apss_funnel_in6: endpoint { 3738 remote-endpoint = <&etm6_out>; 3739 }; 3740 }; 3741 3742 port@7 { 3743 reg = <7>; 3744 apss_funnel_in7: endpoint { 3745 remote-endpoint = <&etm7_out>; 3746 }; 3747 }; 3748 }; 3749 }; 3750 3751 funnel@7810000 { 3752 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3753 reg = <0 0x07810000 0 0x1000>; 3754 3755 clocks = <&aoss_qmp>; 3756 clock-names = "apb_pclk"; 3757 3758 out-ports { 3759 port { 3760 funnel_apss_merg_out_funnel_in1: endpoint { 3761 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; 3762 }; 3763 }; 3764 }; 3765 3766 in-ports { 3767 port { 3768 funnel_apss_merg_in_funnel_apss: endpoint { 3769 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; 3770 }; 3771 }; 3772 }; 3773 }; 3774 3775 cdsp: remoteproc@8300000 { 3776 compatible = "qcom,sm8250-cdsp-pas"; 3777 reg = <0 0x08300000 0 0x10000>; 3778 3779 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3780 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3781 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3782 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3783 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3784 interrupt-names = "wdog", "fatal", "ready", 3785 "handover", "stop-ack"; 3786 3787 clocks = <&rpmhcc RPMH_CXO_CLK>; 3788 clock-names = "xo"; 3789 3790 power-domains = <&rpmhpd RPMHPD_CX>; 3791 3792 memory-region = <&cdsp_mem>; 3793 3794 qcom,qmp = <&aoss_qmp>; 3795 3796 qcom,smem-states = <&smp2p_cdsp_out 0>; 3797 qcom,smem-state-names = "stop"; 3798 3799 status = "disabled"; 3800 3801 glink-edge { 3802 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3803 IPCC_MPROC_SIGNAL_GLINK_QMP 3804 IRQ_TYPE_EDGE_RISING>; 3805 mboxes = <&ipcc IPCC_CLIENT_CDSP 3806 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3807 3808 label = "cdsp"; 3809 qcom,remote-pid = <5>; 3810 3811 fastrpc { 3812 compatible = "qcom,fastrpc"; 3813 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3814 label = "cdsp"; 3815 qcom,non-secure-domain; 3816 #address-cells = <1>; 3817 #size-cells = <0>; 3818 3819 compute-cb@1 { 3820 compatible = "qcom,fastrpc-compute-cb"; 3821 reg = <1>; 3822 iommus = <&apps_smmu 0x1001 0x0460>; 3823 }; 3824 3825 compute-cb@2 { 3826 compatible = "qcom,fastrpc-compute-cb"; 3827 reg = <2>; 3828 iommus = <&apps_smmu 0x1002 0x0460>; 3829 }; 3830 3831 compute-cb@3 { 3832 compatible = "qcom,fastrpc-compute-cb"; 3833 reg = <3>; 3834 iommus = <&apps_smmu 0x1003 0x0460>; 3835 }; 3836 3837 compute-cb@4 { 3838 compatible = "qcom,fastrpc-compute-cb"; 3839 reg = <4>; 3840 iommus = <&apps_smmu 0x1004 0x0460>; 3841 }; 3842 3843 compute-cb@5 { 3844 compatible = "qcom,fastrpc-compute-cb"; 3845 reg = <5>; 3846 iommus = <&apps_smmu 0x1005 0x0460>; 3847 }; 3848 3849 compute-cb@6 { 3850 compatible = "qcom,fastrpc-compute-cb"; 3851 reg = <6>; 3852 iommus = <&apps_smmu 0x1006 0x0460>; 3853 }; 3854 3855 compute-cb@7 { 3856 compatible = "qcom,fastrpc-compute-cb"; 3857 reg = <7>; 3858 iommus = <&apps_smmu 0x1007 0x0460>; 3859 }; 3860 3861 compute-cb@8 { 3862 compatible = "qcom,fastrpc-compute-cb"; 3863 reg = <8>; 3864 iommus = <&apps_smmu 0x1008 0x0460>; 3865 }; 3866 3867 /* note: secure cb9 in downstream */ 3868 }; 3869 }; 3870 }; 3871 3872 usb_1_hsphy: phy@88e3000 { 3873 compatible = "qcom,sm8250-usb-hs-phy", 3874 "qcom,usb-snps-hs-7nm-phy"; 3875 reg = <0 0x088e3000 0 0x400>; 3876 status = "disabled"; 3877 #phy-cells = <0>; 3878 3879 clocks = <&rpmhcc RPMH_CXO_CLK>; 3880 clock-names = "ref"; 3881 3882 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3883 }; 3884 3885 usb_2_hsphy: phy@88e4000 { 3886 compatible = "qcom,sm8250-usb-hs-phy", 3887 "qcom,usb-snps-hs-7nm-phy"; 3888 reg = <0 0x088e4000 0 0x400>; 3889 status = "disabled"; 3890 #phy-cells = <0>; 3891 3892 clocks = <&rpmhcc RPMH_CXO_CLK>; 3893 clock-names = "ref"; 3894 3895 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3896 }; 3897 3898 usb_1_qmpphy: phy@88e8000 { 3899 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 3900 reg = <0 0x088e8000 0 0x3000>; 3901 status = "disabled"; 3902 3903 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3904 <&rpmhcc RPMH_CXO_CLK>, 3905 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3906 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3907 clock-names = "aux", 3908 "ref", 3909 "com_aux", 3910 "usb3_pipe"; 3911 3912 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3913 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3914 reset-names = "phy", "common"; 3915 3916 #clock-cells = <1>; 3917 #phy-cells = <1>; 3918 3919 orientation-switch; 3920 3921 ports { 3922 #address-cells = <1>; 3923 #size-cells = <0>; 3924 3925 port@0 { 3926 reg = <0>; 3927 usb_1_qmpphy_out: endpoint {}; 3928 }; 3929 3930 port@1 { 3931 reg = <1>; 3932 3933 usb_1_qmpphy_usb_ss_in: endpoint { 3934 remote-endpoint = <&usb_1_dwc3_ss_out>; 3935 }; 3936 }; 3937 3938 port@2 { 3939 reg = <2>; 3940 3941 usb_1_qmpphy_dp_in: endpoint {}; 3942 }; 3943 }; 3944 }; 3945 3946 usb_2_qmpphy: phy@88eb000 { 3947 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 3948 reg = <0 0x088eb000 0 0x1000>; 3949 3950 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3951 <&gcc GCC_USB3_SEC_CLKREF_EN>, 3952 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3953 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3954 clock-names = "aux", 3955 "ref", 3956 "com_aux", 3957 "pipe"; 3958 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3959 #clock-cells = <0>; 3960 #phy-cells = <0>; 3961 3962 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3963 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3964 reset-names = "phy", 3965 "phy_phy"; 3966 3967 status = "disabled"; 3968 }; 3969 3970 sdhc_2: mmc@8804000 { 3971 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 3972 reg = <0 0x08804000 0 0x1000>; 3973 3974 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3975 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3976 interrupt-names = "hc_irq", "pwr_irq"; 3977 3978 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3979 <&gcc GCC_SDCC2_APPS_CLK>, 3980 <&rpmhcc RPMH_CXO_CLK>; 3981 clock-names = "iface", "core", "xo"; 3982 iommus = <&apps_smmu 0x4a0 0x0>; 3983 qcom,dll-config = <0x0007642c>; 3984 qcom,ddr-config = <0x80040868>; 3985 power-domains = <&rpmhpd RPMHPD_CX>; 3986 operating-points-v2 = <&sdhc2_opp_table>; 3987 3988 status = "disabled"; 3989 3990 sdhc2_opp_table: opp-table { 3991 compatible = "operating-points-v2"; 3992 3993 opp-19200000 { 3994 opp-hz = /bits/ 64 <19200000>; 3995 required-opps = <&rpmhpd_opp_min_svs>; 3996 }; 3997 3998 opp-50000000 { 3999 opp-hz = /bits/ 64 <50000000>; 4000 required-opps = <&rpmhpd_opp_low_svs>; 4001 }; 4002 4003 opp-100000000 { 4004 opp-hz = /bits/ 64 <100000000>; 4005 required-opps = <&rpmhpd_opp_svs>; 4006 }; 4007 4008 opp-202000000 { 4009 opp-hz = /bits/ 64 <202000000>; 4010 required-opps = <&rpmhpd_opp_svs_l1>; 4011 }; 4012 }; 4013 }; 4014 4015 pmu@9091000 { 4016 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4017 reg = <0 0x09091000 0 0x1000>; 4018 4019 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4020 4021 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>; 4022 4023 operating-points-v2 = <&llcc_bwmon_opp_table>; 4024 4025 llcc_bwmon_opp_table: opp-table { 4026 compatible = "operating-points-v2"; 4027 4028 opp-800000 { 4029 opp-peak-kBps = <(200 * 4 * 1000)>; 4030 }; 4031 4032 opp-1200000 { 4033 opp-peak-kBps = <(300 * 4 * 1000)>; 4034 }; 4035 4036 opp-1804000 { 4037 opp-peak-kBps = <(451 * 4 * 1000)>; 4038 }; 4039 4040 opp-2188000 { 4041 opp-peak-kBps = <(547 * 4 * 1000)>; 4042 }; 4043 4044 opp-2724000 { 4045 opp-peak-kBps = <(681 * 4 * 1000)>; 4046 }; 4047 4048 opp-3072000 { 4049 opp-peak-kBps = <(768 * 4 * 1000)>; 4050 }; 4051 4052 opp-4068000 { 4053 opp-peak-kBps = <(1017 * 4 * 1000)>; 4054 }; 4055 4056 /* 1353 MHz, LPDDR4X */ 4057 4058 opp-6220000 { 4059 opp-peak-kBps = <(1555 * 4 * 1000)>; 4060 }; 4061 4062 opp-7216000 { 4063 opp-peak-kBps = <(1804 * 4 * 1000)>; 4064 }; 4065 4066 opp-8368000 { 4067 opp-peak-kBps = <(2092 * 4 * 1000)>; 4068 }; 4069 4070 /* LPDDR5 */ 4071 opp-10944000 { 4072 opp-peak-kBps = <(2736 * 4 * 1000)>; 4073 }; 4074 }; 4075 }; 4076 4077 pmu@90b6400 { 4078 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon"; 4079 reg = <0 0x090b6400 0 0x600>; 4080 4081 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4082 4083 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>; 4084 operating-points-v2 = <&cpu_bwmon_opp_table>; 4085 4086 cpu_bwmon_opp_table: opp-table { 4087 compatible = "operating-points-v2"; 4088 4089 opp-800000 { 4090 opp-peak-kBps = <(200 * 4 * 1000)>; 4091 }; 4092 4093 opp-1804000 { 4094 opp-peak-kBps = <(451 * 4 * 1000)>; 4095 }; 4096 4097 opp-2188000 { 4098 opp-peak-kBps = <(547 * 4 * 1000)>; 4099 }; 4100 4101 opp-2724000 { 4102 opp-peak-kBps = <(681 * 4 * 1000)>; 4103 }; 4104 4105 opp-3072000 { 4106 opp-peak-kBps = <(768 * 4 * 1000)>; 4107 }; 4108 4109 /* 1017MHz, 1353 MHz, LPDDR4X */ 4110 4111 opp-6220000 { 4112 opp-peak-kBps = <(1555 * 4 * 1000)>; 4113 }; 4114 4115 opp-6832000 { 4116 opp-peak-kBps = <(1708 * 4 * 1000)>; 4117 }; 4118 4119 opp-8368000 { 4120 opp-peak-kBps = <(2092 * 4 * 1000)>; 4121 }; 4122 4123 /* 2133MHz, LPDDR4X */ 4124 4125 /* LPDDR5 */ 4126 opp-10944000 { 4127 opp-peak-kBps = <(2736 * 4 * 1000)>; 4128 }; 4129 4130 /* LPDDR5 */ 4131 opp-12784000 { 4132 opp-peak-kBps = <(3196 * 4 * 1000)>; 4133 }; 4134 }; 4135 }; 4136 4137 dc_noc: interconnect@90c0000 { 4138 compatible = "qcom,sm8250-dc-noc"; 4139 reg = <0 0x090c0000 0 0x4200>; 4140 #interconnect-cells = <2>; 4141 qcom,bcm-voters = <&apps_bcm_voter>; 4142 }; 4143 4144 gem_noc: interconnect@9100000 { 4145 compatible = "qcom,sm8250-gem-noc"; 4146 reg = <0 0x09100000 0 0xb4000>; 4147 #interconnect-cells = <2>; 4148 qcom,bcm-voters = <&apps_bcm_voter>; 4149 }; 4150 4151 npu_noc: interconnect@9990000 { 4152 compatible = "qcom,sm8250-npu-noc"; 4153 reg = <0 0x09990000 0 0x1600>; 4154 #interconnect-cells = <2>; 4155 qcom,bcm-voters = <&apps_bcm_voter>; 4156 }; 4157 4158 usb_1: usb@a6f8800 { 4159 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 4160 reg = <0 0x0a6f8800 0 0x400>; 4161 status = "disabled"; 4162 #address-cells = <2>; 4163 #size-cells = <2>; 4164 ranges; 4165 dma-ranges; 4166 4167 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4168 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4169 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4170 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4171 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4172 <&gcc GCC_USB3_SEC_CLKREF_EN>; 4173 clock-names = "cfg_noc", 4174 "core", 4175 "iface", 4176 "sleep", 4177 "mock_utmi", 4178 "xo"; 4179 4180 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4181 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4182 assigned-clock-rates = <19200000>, <200000000>; 4183 4184 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4185 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4186 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4187 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4188 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4189 interrupt-names = "pwr_event", 4190 "hs_phy_irq", 4191 "dp_hs_phy_irq", 4192 "dm_hs_phy_irq", 4193 "ss_phy_irq"; 4194 4195 power-domains = <&gcc USB30_PRIM_GDSC>; 4196 wakeup-source; 4197 4198 resets = <&gcc GCC_USB30_PRIM_BCR>; 4199 4200 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 4201 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 4202 interconnect-names = "usb-ddr", "apps-usb"; 4203 4204 usb_1_dwc3: usb@a600000 { 4205 compatible = "snps,dwc3"; 4206 reg = <0 0x0a600000 0 0xcd00>; 4207 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4208 iommus = <&apps_smmu 0x0 0x0>; 4209 snps,dis_u2_susphy_quirk; 4210 snps,dis_enblslpm_quirk; 4211 snps,dis-u1-entry-quirk; 4212 snps,dis-u2-entry-quirk; 4213 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4214 phy-names = "usb2-phy", "usb3-phy"; 4215 4216 ports { 4217 #address-cells = <1>; 4218 #size-cells = <0>; 4219 4220 port@0 { 4221 reg = <0>; 4222 4223 usb_1_dwc3_hs_out: endpoint { 4224 }; 4225 }; 4226 4227 port@1 { 4228 reg = <1>; 4229 4230 usb_1_dwc3_ss_out: endpoint { 4231 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4232 }; 4233 }; 4234 }; 4235 }; 4236 }; 4237 4238 system-cache-controller@9200000 { 4239 compatible = "qcom,sm8250-llcc"; 4240 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 4241 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 4242 <0 0x09600000 0 0x50000>; 4243 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4244 "llcc3_base", "llcc_broadcast_base"; 4245 }; 4246 4247 usb_2: usb@a8f8800 { 4248 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 4249 reg = <0 0x0a8f8800 0 0x400>; 4250 status = "disabled"; 4251 #address-cells = <2>; 4252 #size-cells = <2>; 4253 ranges; 4254 dma-ranges; 4255 4256 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4257 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4258 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4259 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4260 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4261 <&gcc GCC_USB3_SEC_CLKREF_EN>; 4262 clock-names = "cfg_noc", 4263 "core", 4264 "iface", 4265 "sleep", 4266 "mock_utmi", 4267 "xo"; 4268 4269 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4270 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4271 assigned-clock-rates = <19200000>, <200000000>; 4272 4273 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4274 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4275 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 4276 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 4277 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 4278 interrupt-names = "pwr_event", 4279 "hs_phy_irq", 4280 "dp_hs_phy_irq", 4281 "dm_hs_phy_irq", 4282 "ss_phy_irq"; 4283 4284 power-domains = <&gcc USB30_SEC_GDSC>; 4285 wakeup-source; 4286 4287 resets = <&gcc GCC_USB30_SEC_BCR>; 4288 4289 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 4290 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 4291 interconnect-names = "usb-ddr", "apps-usb"; 4292 4293 usb_2_dwc3: usb@a800000 { 4294 compatible = "snps,dwc3"; 4295 reg = <0 0x0a800000 0 0xcd00>; 4296 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4297 iommus = <&apps_smmu 0x20 0>; 4298 snps,dis_u2_susphy_quirk; 4299 snps,dis_enblslpm_quirk; 4300 snps,dis-u1-entry-quirk; 4301 snps,dis-u2-entry-quirk; 4302 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 4303 phy-names = "usb2-phy", "usb3-phy"; 4304 }; 4305 }; 4306 4307 venus: video-codec@aa00000 { 4308 compatible = "qcom,sm8250-venus"; 4309 reg = <0 0x0aa00000 0 0x100000>; 4310 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4311 power-domains = <&videocc MVS0C_GDSC>, 4312 <&videocc MVS0_GDSC>, 4313 <&rpmhpd RPMHPD_MX>; 4314 power-domain-names = "venus", "vcodec0", "mx"; 4315 operating-points-v2 = <&venus_opp_table>; 4316 4317 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4318 <&videocc VIDEO_CC_MVS0C_CLK>, 4319 <&videocc VIDEO_CC_MVS0_CLK>; 4320 clock-names = "iface", "core", "vcodec0_core"; 4321 4322 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>, 4323 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>; 4324 interconnect-names = "cpu-cfg", "video-mem"; 4325 4326 iommus = <&apps_smmu 0x2100 0x0400>; 4327 memory-region = <&video_mem>; 4328 4329 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 4330 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 4331 reset-names = "bus", "core"; 4332 4333 status = "disabled"; 4334 4335 video-decoder { 4336 compatible = "venus-decoder"; 4337 }; 4338 4339 video-encoder { 4340 compatible = "venus-encoder"; 4341 }; 4342 4343 venus_opp_table: opp-table { 4344 compatible = "operating-points-v2"; 4345 4346 opp-720000000 { 4347 opp-hz = /bits/ 64 <720000000>; 4348 required-opps = <&rpmhpd_opp_low_svs>; 4349 }; 4350 4351 opp-1014000000 { 4352 opp-hz = /bits/ 64 <1014000000>; 4353 required-opps = <&rpmhpd_opp_svs>; 4354 }; 4355 4356 opp-1098000000 { 4357 opp-hz = /bits/ 64 <1098000000>; 4358 required-opps = <&rpmhpd_opp_svs_l1>; 4359 }; 4360 4361 opp-1332000000 { 4362 opp-hz = /bits/ 64 <1332000000>; 4363 required-opps = <&rpmhpd_opp_nom>; 4364 }; 4365 }; 4366 }; 4367 4368 videocc: clock-controller@abf0000 { 4369 compatible = "qcom,sm8250-videocc"; 4370 reg = <0 0x0abf0000 0 0x10000>; 4371 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4372 <&rpmhcc RPMH_CXO_CLK>, 4373 <&rpmhcc RPMH_CXO_CLK_A>; 4374 power-domains = <&rpmhpd RPMHPD_MMCX>; 4375 required-opps = <&rpmhpd_opp_low_svs>; 4376 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 4377 #clock-cells = <1>; 4378 #reset-cells = <1>; 4379 #power-domain-cells = <1>; 4380 }; 4381 4382 cci0: cci@ac4f000 { 4383 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4384 #address-cells = <1>; 4385 #size-cells = <0>; 4386 4387 reg = <0 0x0ac4f000 0 0x1000>; 4388 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4389 power-domains = <&camcc TITAN_TOP_GDSC>; 4390 4391 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4392 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4393 <&camcc CAM_CC_CPAS_AHB_CLK>, 4394 <&camcc CAM_CC_CCI_0_CLK>, 4395 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4396 clock-names = "camnoc_axi", 4397 "slow_ahb_src", 4398 "cpas_ahb", 4399 "cci", 4400 "cci_src"; 4401 4402 pinctrl-0 = <&cci0_default>; 4403 pinctrl-1 = <&cci0_sleep>; 4404 pinctrl-names = "default", "sleep"; 4405 4406 status = "disabled"; 4407 4408 cci0_i2c0: i2c-bus@0 { 4409 reg = <0>; 4410 clock-frequency = <1000000>; 4411 #address-cells = <1>; 4412 #size-cells = <0>; 4413 }; 4414 4415 cci0_i2c1: i2c-bus@1 { 4416 reg = <1>; 4417 clock-frequency = <1000000>; 4418 #address-cells = <1>; 4419 #size-cells = <0>; 4420 }; 4421 }; 4422 4423 cci1: cci@ac50000 { 4424 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4425 #address-cells = <1>; 4426 #size-cells = <0>; 4427 4428 reg = <0 0x0ac50000 0 0x1000>; 4429 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4430 power-domains = <&camcc TITAN_TOP_GDSC>; 4431 4432 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4433 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4434 <&camcc CAM_CC_CPAS_AHB_CLK>, 4435 <&camcc CAM_CC_CCI_1_CLK>, 4436 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4437 clock-names = "camnoc_axi", 4438 "slow_ahb_src", 4439 "cpas_ahb", 4440 "cci", 4441 "cci_src"; 4442 4443 pinctrl-0 = <&cci1_default>; 4444 pinctrl-1 = <&cci1_sleep>; 4445 pinctrl-names = "default", "sleep"; 4446 4447 status = "disabled"; 4448 4449 cci1_i2c0: i2c-bus@0 { 4450 reg = <0>; 4451 clock-frequency = <1000000>; 4452 #address-cells = <1>; 4453 #size-cells = <0>; 4454 }; 4455 4456 cci1_i2c1: i2c-bus@1 { 4457 reg = <1>; 4458 clock-frequency = <1000000>; 4459 #address-cells = <1>; 4460 #size-cells = <0>; 4461 }; 4462 }; 4463 4464 camss: camss@ac6a000 { 4465 compatible = "qcom,sm8250-camss"; 4466 status = "disabled"; 4467 4468 reg = <0 0x0ac6a000 0 0x2000>, 4469 <0 0x0ac6c000 0 0x2000>, 4470 <0 0x0ac6e000 0 0x1000>, 4471 <0 0x0ac70000 0 0x1000>, 4472 <0 0x0ac72000 0 0x1000>, 4473 <0 0x0ac74000 0 0x1000>, 4474 <0 0x0acb4000 0 0xd000>, 4475 <0 0x0acc3000 0 0xd000>, 4476 <0 0x0acd9000 0 0x2200>, 4477 <0 0x0acdb200 0 0x2200>; 4478 reg-names = "csiphy0", 4479 "csiphy1", 4480 "csiphy2", 4481 "csiphy3", 4482 "csiphy4", 4483 "csiphy5", 4484 "vfe0", 4485 "vfe1", 4486 "vfe_lite0", 4487 "vfe_lite1"; 4488 4489 interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4490 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4491 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4492 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4493 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 4494 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 4495 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4496 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4497 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4498 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4499 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4500 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4501 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4502 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; 4503 interrupt-names = "csiphy0", 4504 "csiphy1", 4505 "csiphy2", 4506 "csiphy3", 4507 "csiphy4", 4508 "csiphy5", 4509 "csid0", 4510 "csid1", 4511 "csid2", 4512 "csid3", 4513 "vfe0", 4514 "vfe1", 4515 "vfe_lite0", 4516 "vfe_lite1"; 4517 4518 power-domains = <&camcc IFE_0_GDSC>, 4519 <&camcc IFE_1_GDSC>, 4520 <&camcc TITAN_TOP_GDSC>; 4521 4522 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4523 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4524 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4525 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4526 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 4527 <&camcc CAM_CC_CORE_AHB_CLK>, 4528 <&camcc CAM_CC_CPAS_AHB_CLK>, 4529 <&camcc CAM_CC_CSIPHY0_CLK>, 4530 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4531 <&camcc CAM_CC_CSIPHY1_CLK>, 4532 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4533 <&camcc CAM_CC_CSIPHY2_CLK>, 4534 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4535 <&camcc CAM_CC_CSIPHY3_CLK>, 4536 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4537 <&camcc CAM_CC_CSIPHY4_CLK>, 4538 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 4539 <&camcc CAM_CC_CSIPHY5_CLK>, 4540 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 4541 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4542 <&camcc CAM_CC_IFE_0_AHB_CLK>, 4543 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4544 <&camcc CAM_CC_IFE_0_CLK>, 4545 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4546 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4547 <&camcc CAM_CC_IFE_0_AREG_CLK>, 4548 <&camcc CAM_CC_IFE_1_AHB_CLK>, 4549 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4550 <&camcc CAM_CC_IFE_1_CLK>, 4551 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4552 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4553 <&camcc CAM_CC_IFE_1_AREG_CLK>, 4554 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4555 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 4556 <&camcc CAM_CC_IFE_LITE_CLK>, 4557 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4558 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4559 4560 clock-names = "cam_ahb_clk", 4561 "cam_hf_axi", 4562 "cam_sf_axi", 4563 "camnoc_axi", 4564 "camnoc_axi_src", 4565 "core_ahb", 4566 "cpas_ahb", 4567 "csiphy0", 4568 "csiphy0_timer", 4569 "csiphy1", 4570 "csiphy1_timer", 4571 "csiphy2", 4572 "csiphy2_timer", 4573 "csiphy3", 4574 "csiphy3_timer", 4575 "csiphy4", 4576 "csiphy4_timer", 4577 "csiphy5", 4578 "csiphy5_timer", 4579 "slow_ahb_src", 4580 "vfe0_ahb", 4581 "vfe0_axi", 4582 "vfe0", 4583 "vfe0_cphy_rx", 4584 "vfe0_csid", 4585 "vfe0_areg", 4586 "vfe1_ahb", 4587 "vfe1_axi", 4588 "vfe1", 4589 "vfe1_cphy_rx", 4590 "vfe1_csid", 4591 "vfe1_areg", 4592 "vfe_lite_ahb", 4593 "vfe_lite_axi", 4594 "vfe_lite", 4595 "vfe_lite_cphy_rx", 4596 "vfe_lite_csid"; 4597 4598 iommus = <&apps_smmu 0x800 0x400>, 4599 <&apps_smmu 0x801 0x400>, 4600 <&apps_smmu 0x840 0x400>, 4601 <&apps_smmu 0x841 0x400>, 4602 <&apps_smmu 0xc00 0x400>, 4603 <&apps_smmu 0xc01 0x400>, 4604 <&apps_smmu 0xc40 0x400>, 4605 <&apps_smmu 0xc41 0x400>; 4606 4607 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>, 4608 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>, 4609 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>, 4610 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>; 4611 interconnect-names = "cam_ahb", 4612 "cam_hf_0_mnoc", 4613 "cam_sf_0_mnoc", 4614 "cam_sf_icp_mnoc"; 4615 4616 ports { 4617 #address-cells = <1>; 4618 #size-cells = <0>; 4619 4620 port@0 { 4621 reg = <0>; 4622 }; 4623 4624 port@1 { 4625 reg = <1>; 4626 }; 4627 4628 port@2 { 4629 reg = <2>; 4630 }; 4631 4632 port@3 { 4633 reg = <3>; 4634 }; 4635 4636 port@4 { 4637 reg = <4>; 4638 }; 4639 4640 port@5 { 4641 reg = <5>; 4642 }; 4643 }; 4644 }; 4645 4646 camcc: clock-controller@ad00000 { 4647 compatible = "qcom,sm8250-camcc"; 4648 reg = <0 0x0ad00000 0 0x10000>; 4649 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4650 <&rpmhcc RPMH_CXO_CLK>, 4651 <&rpmhcc RPMH_CXO_CLK_A>, 4652 <&sleep_clk>; 4653 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4654 power-domains = <&rpmhpd RPMHPD_MMCX>; 4655 required-opps = <&rpmhpd_opp_low_svs>; 4656 status = "disabled"; 4657 #clock-cells = <1>; 4658 #reset-cells = <1>; 4659 #power-domain-cells = <1>; 4660 }; 4661 4662 mdss: display-subsystem@ae00000 { 4663 compatible = "qcom,sm8250-mdss"; 4664 reg = <0 0x0ae00000 0 0x1000>; 4665 reg-names = "mdss"; 4666 4667 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 4668 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 4669 interconnect-names = "mdp0-mem", "mdp1-mem"; 4670 4671 power-domains = <&dispcc MDSS_GDSC>; 4672 4673 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4674 <&gcc GCC_DISP_HF_AXI_CLK>, 4675 <&gcc GCC_DISP_SF_AXI_CLK>, 4676 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4677 clock-names = "iface", "bus", "nrt_bus", "core"; 4678 4679 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4680 interrupt-controller; 4681 #interrupt-cells = <1>; 4682 4683 iommus = <&apps_smmu 0x820 0x402>; 4684 4685 status = "disabled"; 4686 4687 #address-cells = <2>; 4688 #size-cells = <2>; 4689 ranges; 4690 4691 mdss_mdp: display-controller@ae01000 { 4692 compatible = "qcom,sm8250-dpu"; 4693 reg = <0 0x0ae01000 0 0x8f000>, 4694 <0 0x0aeb0000 0 0x3000>; 4695 reg-names = "mdp", "vbif"; 4696 4697 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4698 <&gcc GCC_DISP_HF_AXI_CLK>, 4699 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4700 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4701 clock-names = "iface", "bus", "core", "vsync"; 4702 4703 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4704 assigned-clock-rates = <19200000>; 4705 4706 operating-points-v2 = <&mdp_opp_table>; 4707 power-domains = <&rpmhpd RPMHPD_MMCX>; 4708 4709 interrupt-parent = <&mdss>; 4710 interrupts = <0>; 4711 4712 ports { 4713 #address-cells = <1>; 4714 #size-cells = <0>; 4715 4716 port@0 { 4717 reg = <0>; 4718 dpu_intf1_out: endpoint { 4719 remote-endpoint = <&mdss_dsi0_in>; 4720 }; 4721 }; 4722 4723 port@1 { 4724 reg = <1>; 4725 dpu_intf2_out: endpoint { 4726 remote-endpoint = <&mdss_dsi1_in>; 4727 }; 4728 }; 4729 4730 port@2 { 4731 reg = <2>; 4732 4733 dpu_intf0_out: endpoint { 4734 remote-endpoint = <&mdss_dp_in>; 4735 }; 4736 }; 4737 }; 4738 4739 mdp_opp_table: opp-table { 4740 compatible = "operating-points-v2"; 4741 4742 opp-200000000 { 4743 opp-hz = /bits/ 64 <200000000>; 4744 required-opps = <&rpmhpd_opp_low_svs>; 4745 }; 4746 4747 opp-300000000 { 4748 opp-hz = /bits/ 64 <300000000>; 4749 required-opps = <&rpmhpd_opp_svs>; 4750 }; 4751 4752 opp-345000000 { 4753 opp-hz = /bits/ 64 <345000000>; 4754 required-opps = <&rpmhpd_opp_svs_l1>; 4755 }; 4756 4757 opp-460000000 { 4758 opp-hz = /bits/ 64 <460000000>; 4759 required-opps = <&rpmhpd_opp_nom>; 4760 }; 4761 }; 4762 }; 4763 4764 mdss_dp: displayport-controller@ae90000 { 4765 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp"; 4766 reg = <0 0xae90000 0 0x200>, 4767 <0 0xae90200 0 0x200>, 4768 <0 0xae90400 0 0x600>, 4769 <0 0xae91000 0 0x400>, 4770 <0 0xae91400 0 0x400>; 4771 interrupt-parent = <&mdss>; 4772 interrupts = <12>; 4773 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4774 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4775 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4776 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4777 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4778 clock-names = "core_iface", 4779 "core_aux", 4780 "ctrl_link", 4781 "ctrl_link_iface", 4782 "stream_pixel"; 4783 4784 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4785 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4786 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4787 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4788 4789 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4790 phy-names = "dp"; 4791 4792 #sound-dai-cells = <0>; 4793 4794 operating-points-v2 = <&dp_opp_table>; 4795 power-domains = <&rpmhpd SM8250_MMCX>; 4796 4797 status = "disabled"; 4798 4799 ports { 4800 #address-cells = <1>; 4801 #size-cells = <0>; 4802 4803 port@0 { 4804 reg = <0>; 4805 mdss_dp_in: endpoint { 4806 remote-endpoint = <&dpu_intf0_out>; 4807 }; 4808 }; 4809 4810 port@1 { 4811 reg = <1>; 4812 4813 mdss_dp_out: endpoint { 4814 }; 4815 }; 4816 }; 4817 4818 dp_opp_table: opp-table { 4819 compatible = "operating-points-v2"; 4820 4821 opp-160000000 { 4822 opp-hz = /bits/ 64 <160000000>; 4823 required-opps = <&rpmhpd_opp_low_svs>; 4824 }; 4825 4826 opp-270000000 { 4827 opp-hz = /bits/ 64 <270000000>; 4828 required-opps = <&rpmhpd_opp_svs>; 4829 }; 4830 4831 opp-540000000 { 4832 opp-hz = /bits/ 64 <540000000>; 4833 required-opps = <&rpmhpd_opp_svs_l1>; 4834 }; 4835 4836 opp-810000000 { 4837 opp-hz = /bits/ 64 <810000000>; 4838 required-opps = <&rpmhpd_opp_nom>; 4839 }; 4840 }; 4841 }; 4842 4843 mdss_dsi0: dsi@ae94000 { 4844 compatible = "qcom,sm8250-dsi-ctrl", 4845 "qcom,mdss-dsi-ctrl"; 4846 reg = <0 0x0ae94000 0 0x400>; 4847 reg-names = "dsi_ctrl"; 4848 4849 interrupt-parent = <&mdss>; 4850 interrupts = <4>; 4851 4852 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4853 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4854 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4855 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4856 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4857 <&gcc GCC_DISP_HF_AXI_CLK>; 4858 clock-names = "byte", 4859 "byte_intf", 4860 "pixel", 4861 "core", 4862 "iface", 4863 "bus"; 4864 4865 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 4866 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4867 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4868 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 4869 4870 operating-points-v2 = <&dsi_opp_table>; 4871 power-domains = <&rpmhpd RPMHPD_MMCX>; 4872 4873 phys = <&mdss_dsi0_phy>; 4874 4875 status = "disabled"; 4876 4877 #address-cells = <1>; 4878 #size-cells = <0>; 4879 4880 ports { 4881 #address-cells = <1>; 4882 #size-cells = <0>; 4883 4884 port@0 { 4885 reg = <0>; 4886 mdss_dsi0_in: endpoint { 4887 remote-endpoint = <&dpu_intf1_out>; 4888 }; 4889 }; 4890 4891 port@1 { 4892 reg = <1>; 4893 mdss_dsi0_out: endpoint { 4894 }; 4895 }; 4896 }; 4897 4898 dsi_opp_table: opp-table { 4899 compatible = "operating-points-v2"; 4900 4901 opp-187500000 { 4902 opp-hz = /bits/ 64 <187500000>; 4903 required-opps = <&rpmhpd_opp_low_svs>; 4904 }; 4905 4906 opp-300000000 { 4907 opp-hz = /bits/ 64 <300000000>; 4908 required-opps = <&rpmhpd_opp_svs>; 4909 }; 4910 4911 opp-358000000 { 4912 opp-hz = /bits/ 64 <358000000>; 4913 required-opps = <&rpmhpd_opp_svs_l1>; 4914 }; 4915 }; 4916 }; 4917 4918 mdss_dsi0_phy: phy@ae94400 { 4919 compatible = "qcom,dsi-phy-7nm"; 4920 reg = <0 0x0ae94400 0 0x200>, 4921 <0 0x0ae94600 0 0x280>, 4922 <0 0x0ae94900 0 0x260>; 4923 reg-names = "dsi_phy", 4924 "dsi_phy_lane", 4925 "dsi_pll"; 4926 4927 #clock-cells = <1>; 4928 #phy-cells = <0>; 4929 4930 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4931 <&rpmhcc RPMH_CXO_CLK>; 4932 clock-names = "iface", "ref"; 4933 4934 status = "disabled"; 4935 }; 4936 4937 mdss_dsi1: dsi@ae96000 { 4938 compatible = "qcom,sm8250-dsi-ctrl", 4939 "qcom,mdss-dsi-ctrl"; 4940 reg = <0 0x0ae96000 0 0x400>; 4941 reg-names = "dsi_ctrl"; 4942 4943 interrupt-parent = <&mdss>; 4944 interrupts = <5>; 4945 4946 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4947 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4948 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4949 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4950 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4951 <&gcc GCC_DISP_HF_AXI_CLK>; 4952 clock-names = "byte", 4953 "byte_intf", 4954 "pixel", 4955 "core", 4956 "iface", 4957 "bus"; 4958 4959 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 4960 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4961 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4962 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 4963 4964 operating-points-v2 = <&dsi_opp_table>; 4965 power-domains = <&rpmhpd RPMHPD_MMCX>; 4966 4967 phys = <&mdss_dsi1_phy>; 4968 4969 status = "disabled"; 4970 4971 #address-cells = <1>; 4972 #size-cells = <0>; 4973 4974 ports { 4975 #address-cells = <1>; 4976 #size-cells = <0>; 4977 4978 port@0 { 4979 reg = <0>; 4980 mdss_dsi1_in: endpoint { 4981 remote-endpoint = <&dpu_intf2_out>; 4982 }; 4983 }; 4984 4985 port@1 { 4986 reg = <1>; 4987 mdss_dsi1_out: endpoint { 4988 }; 4989 }; 4990 }; 4991 }; 4992 4993 mdss_dsi1_phy: phy@ae96400 { 4994 compatible = "qcom,dsi-phy-7nm"; 4995 reg = <0 0x0ae96400 0 0x200>, 4996 <0 0x0ae96600 0 0x280>, 4997 <0 0x0ae96900 0 0x260>; 4998 reg-names = "dsi_phy", 4999 "dsi_phy_lane", 5000 "dsi_pll"; 5001 5002 #clock-cells = <1>; 5003 #phy-cells = <0>; 5004 5005 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5006 <&rpmhcc RPMH_CXO_CLK>; 5007 clock-names = "iface", "ref"; 5008 5009 status = "disabled"; 5010 }; 5011 }; 5012 5013 dispcc: clock-controller@af00000 { 5014 compatible = "qcom,sm8250-dispcc"; 5015 reg = <0 0x0af00000 0 0x10000>; 5016 power-domains = <&rpmhpd RPMHPD_MMCX>; 5017 required-opps = <&rpmhpd_opp_low_svs>; 5018 clocks = <&rpmhcc RPMH_CXO_CLK>, 5019 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5020 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 5021 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 5022 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 5023 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5024 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5025 clock-names = "bi_tcxo", 5026 "dsi0_phy_pll_out_byteclk", 5027 "dsi0_phy_pll_out_dsiclk", 5028 "dsi1_phy_pll_out_byteclk", 5029 "dsi1_phy_pll_out_dsiclk", 5030 "dp_phy_pll_link_clk", 5031 "dp_phy_pll_vco_div_clk"; 5032 #clock-cells = <1>; 5033 #reset-cells = <1>; 5034 #power-domain-cells = <1>; 5035 }; 5036 5037 pdc: interrupt-controller@b220000 { 5038 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 5039 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 5040 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 5041 <125 63 1>, <126 716 12>; 5042 #interrupt-cells = <2>; 5043 interrupt-parent = <&intc>; 5044 interrupt-controller; 5045 }; 5046 5047 tsens0: thermal-sensor@c263000 { 5048 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 5049 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5050 <0 0x0c222000 0 0x1ff>; /* SROT */ 5051 #qcom,sensors = <16>; 5052 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5054 interrupt-names = "uplow", "critical"; 5055 #thermal-sensor-cells = <1>; 5056 }; 5057 5058 tsens1: thermal-sensor@c265000 { 5059 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 5060 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5061 <0 0x0c223000 0 0x1ff>; /* SROT */ 5062 #qcom,sensors = <9>; 5063 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5065 interrupt-names = "uplow", "critical"; 5066 #thermal-sensor-cells = <1>; 5067 }; 5068 5069 aoss_qmp: power-management@c300000 { 5070 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 5071 reg = <0 0x0c300000 0 0x400>; 5072 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5073 IPCC_MPROC_SIGNAL_GLINK_QMP 5074 IRQ_TYPE_EDGE_RISING>; 5075 mboxes = <&ipcc IPCC_CLIENT_AOP 5076 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5077 5078 #clock-cells = <0>; 5079 }; 5080 5081 sram@c3f0000 { 5082 compatible = "qcom,rpmh-stats"; 5083 reg = <0 0x0c3f0000 0 0x400>; 5084 }; 5085 5086 spmi_bus: spmi@c440000 { 5087 compatible = "qcom,spmi-pmic-arb"; 5088 reg = <0x0 0x0c440000 0x0 0x0001100>, 5089 <0x0 0x0c600000 0x0 0x2000000>, 5090 <0x0 0x0e600000 0x0 0x0100000>, 5091 <0x0 0x0e700000 0x0 0x00a0000>, 5092 <0x0 0x0c40a000 0x0 0x0026000>; 5093 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5094 interrupt-names = "periph_irq"; 5095 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5096 qcom,ee = <0>; 5097 qcom,channel = <0>; 5098 #address-cells = <2>; 5099 #size-cells = <0>; 5100 interrupt-controller; 5101 #interrupt-cells = <4>; 5102 }; 5103 5104 tlmm: pinctrl@f100000 { 5105 compatible = "qcom,sm8250-pinctrl"; 5106 reg = <0 0x0f100000 0 0x300000>, 5107 <0 0x0f500000 0 0x300000>, 5108 <0 0x0f900000 0 0x300000>; 5109 reg-names = "west", "south", "north"; 5110 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5111 gpio-controller; 5112 #gpio-cells = <2>; 5113 interrupt-controller; 5114 #interrupt-cells = <2>; 5115 gpio-ranges = <&tlmm 0 0 181>; 5116 wakeup-parent = <&pdc>; 5117 5118 cam2_default: cam2-default-state { 5119 rst-pins { 5120 pins = "gpio78"; 5121 function = "gpio"; 5122 drive-strength = <2>; 5123 bias-disable; 5124 }; 5125 5126 mclk-pins { 5127 pins = "gpio96"; 5128 function = "cam_mclk"; 5129 drive-strength = <16>; 5130 bias-disable; 5131 }; 5132 }; 5133 5134 cam2_suspend: cam2-suspend-state { 5135 rst-pins { 5136 pins = "gpio78"; 5137 function = "gpio"; 5138 drive-strength = <2>; 5139 bias-pull-down; 5140 output-low; 5141 }; 5142 5143 mclk-pins { 5144 pins = "gpio96"; 5145 function = "cam_mclk"; 5146 drive-strength = <2>; 5147 bias-disable; 5148 }; 5149 }; 5150 5151 cci0_default: cci0-default-state { 5152 cci0_i2c0_default: cci0-i2c0-default-pins { 5153 /* SDA, SCL */ 5154 pins = "gpio101", "gpio102"; 5155 function = "cci_i2c"; 5156 5157 bias-pull-up; 5158 drive-strength = <2>; /* 2 mA */ 5159 }; 5160 5161 cci0_i2c1_default: cci0-i2c1-default-pins { 5162 /* SDA, SCL */ 5163 pins = "gpio103", "gpio104"; 5164 function = "cci_i2c"; 5165 5166 bias-pull-up; 5167 drive-strength = <2>; /* 2 mA */ 5168 }; 5169 }; 5170 5171 cci0_sleep: cci0-sleep-state { 5172 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 5173 /* SDA, SCL */ 5174 pins = "gpio101", "gpio102"; 5175 function = "cci_i2c"; 5176 5177 drive-strength = <2>; /* 2 mA */ 5178 bias-pull-down; 5179 }; 5180 5181 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 5182 /* SDA, SCL */ 5183 pins = "gpio103", "gpio104"; 5184 function = "cci_i2c"; 5185 5186 drive-strength = <2>; /* 2 mA */ 5187 bias-pull-down; 5188 }; 5189 }; 5190 5191 cci1_default: cci1-default-state { 5192 cci1_i2c0_default: cci1-i2c0-default-pins { 5193 /* SDA, SCL */ 5194 pins = "gpio105","gpio106"; 5195 function = "cci_i2c"; 5196 5197 bias-pull-up; 5198 drive-strength = <2>; /* 2 mA */ 5199 }; 5200 5201 cci1_i2c1_default: cci1-i2c1-default-pins { 5202 /* SDA, SCL */ 5203 pins = "gpio107","gpio108"; 5204 function = "cci_i2c"; 5205 5206 bias-pull-up; 5207 drive-strength = <2>; /* 2 mA */ 5208 }; 5209 }; 5210 5211 cci1_sleep: cci1-sleep-state { 5212 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 5213 /* SDA, SCL */ 5214 pins = "gpio105","gpio106"; 5215 function = "cci_i2c"; 5216 5217 bias-pull-down; 5218 drive-strength = <2>; /* 2 mA */ 5219 }; 5220 5221 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 5222 /* SDA, SCL */ 5223 pins = "gpio107","gpio108"; 5224 function = "cci_i2c"; 5225 5226 bias-pull-down; 5227 drive-strength = <2>; /* 2 mA */ 5228 }; 5229 }; 5230 5231 pri_mi2s_active: pri-mi2s-active-state { 5232 sclk-pins { 5233 pins = "gpio138"; 5234 function = "mi2s0_sck"; 5235 drive-strength = <8>; 5236 bias-disable; 5237 }; 5238 5239 ws-pins { 5240 pins = "gpio141"; 5241 function = "mi2s0_ws"; 5242 drive-strength = <8>; 5243 output-high; 5244 }; 5245 5246 data0-pins { 5247 pins = "gpio139"; 5248 function = "mi2s0_data0"; 5249 drive-strength = <8>; 5250 bias-disable; 5251 output-high; 5252 }; 5253 5254 data1-pins { 5255 pins = "gpio140"; 5256 function = "mi2s0_data1"; 5257 drive-strength = <8>; 5258 output-high; 5259 }; 5260 }; 5261 5262 qup_i2c0_default: qup-i2c0-default-state { 5263 pins = "gpio28", "gpio29"; 5264 function = "qup0"; 5265 drive-strength = <2>; 5266 bias-disable; 5267 }; 5268 5269 qup_i2c1_default: qup-i2c1-default-state { 5270 pins = "gpio4", "gpio5"; 5271 function = "qup1"; 5272 drive-strength = <2>; 5273 bias-disable; 5274 }; 5275 5276 qup_i2c2_default: qup-i2c2-default-state { 5277 pins = "gpio115", "gpio116"; 5278 function = "qup2"; 5279 drive-strength = <2>; 5280 bias-disable; 5281 }; 5282 5283 qup_i2c3_default: qup-i2c3-default-state { 5284 pins = "gpio119", "gpio120"; 5285 function = "qup3"; 5286 drive-strength = <2>; 5287 bias-disable; 5288 }; 5289 5290 qup_i2c4_default: qup-i2c4-default-state { 5291 pins = "gpio8", "gpio9"; 5292 function = "qup4"; 5293 drive-strength = <2>; 5294 bias-disable; 5295 }; 5296 5297 qup_i2c5_default: qup-i2c5-default-state { 5298 pins = "gpio12", "gpio13"; 5299 function = "qup5"; 5300 drive-strength = <2>; 5301 bias-disable; 5302 }; 5303 5304 qup_i2c6_default: qup-i2c6-default-state { 5305 pins = "gpio16", "gpio17"; 5306 function = "qup6"; 5307 drive-strength = <2>; 5308 bias-disable; 5309 }; 5310 5311 qup_i2c7_default: qup-i2c7-default-state { 5312 pins = "gpio20", "gpio21"; 5313 function = "qup7"; 5314 drive-strength = <2>; 5315 bias-disable; 5316 }; 5317 5318 qup_i2c8_default: qup-i2c8-default-state { 5319 pins = "gpio24", "gpio25"; 5320 function = "qup8"; 5321 drive-strength = <2>; 5322 bias-disable; 5323 }; 5324 5325 qup_i2c9_default: qup-i2c9-default-state { 5326 pins = "gpio125", "gpio126"; 5327 function = "qup9"; 5328 drive-strength = <2>; 5329 bias-disable; 5330 }; 5331 5332 qup_i2c10_default: qup-i2c10-default-state { 5333 pins = "gpio129", "gpio130"; 5334 function = "qup10"; 5335 drive-strength = <2>; 5336 bias-disable; 5337 }; 5338 5339 qup_i2c11_default: qup-i2c11-default-state { 5340 pins = "gpio60", "gpio61"; 5341 function = "qup11"; 5342 drive-strength = <2>; 5343 bias-disable; 5344 }; 5345 5346 qup_i2c12_default: qup-i2c12-default-state { 5347 pins = "gpio32", "gpio33"; 5348 function = "qup12"; 5349 drive-strength = <2>; 5350 bias-disable; 5351 }; 5352 5353 qup_i2c13_default: qup-i2c13-default-state { 5354 pins = "gpio36", "gpio37"; 5355 function = "qup13"; 5356 drive-strength = <2>; 5357 bias-disable; 5358 }; 5359 5360 qup_i2c14_default: qup-i2c14-default-state { 5361 pins = "gpio40", "gpio41"; 5362 function = "qup14"; 5363 drive-strength = <2>; 5364 bias-disable; 5365 }; 5366 5367 qup_i2c15_default: qup-i2c15-default-state { 5368 pins = "gpio44", "gpio45"; 5369 function = "qup15"; 5370 drive-strength = <2>; 5371 bias-disable; 5372 }; 5373 5374 qup_i2c16_default: qup-i2c16-default-state { 5375 pins = "gpio48", "gpio49"; 5376 function = "qup16"; 5377 drive-strength = <2>; 5378 bias-disable; 5379 }; 5380 5381 qup_i2c17_default: qup-i2c17-default-state { 5382 pins = "gpio52", "gpio53"; 5383 function = "qup17"; 5384 drive-strength = <2>; 5385 bias-disable; 5386 }; 5387 5388 qup_i2c18_default: qup-i2c18-default-state { 5389 pins = "gpio56", "gpio57"; 5390 function = "qup18"; 5391 drive-strength = <2>; 5392 bias-disable; 5393 }; 5394 5395 qup_i2c19_default: qup-i2c19-default-state { 5396 pins = "gpio0", "gpio1"; 5397 function = "qup19"; 5398 drive-strength = <2>; 5399 bias-disable; 5400 }; 5401 5402 qup_spi0_cs: qup-spi0-cs-state { 5403 pins = "gpio31"; 5404 function = "qup0"; 5405 }; 5406 5407 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5408 pins = "gpio31"; 5409 function = "gpio"; 5410 }; 5411 5412 qup_spi0_data_clk: qup-spi0-data-clk-state { 5413 pins = "gpio28", "gpio29", 5414 "gpio30"; 5415 function = "qup0"; 5416 }; 5417 5418 qup_spi1_cs: qup-spi1-cs-state { 5419 pins = "gpio7"; 5420 function = "qup1"; 5421 }; 5422 5423 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5424 pins = "gpio7"; 5425 function = "gpio"; 5426 }; 5427 5428 qup_spi1_data_clk: qup-spi1-data-clk-state { 5429 pins = "gpio4", "gpio5", 5430 "gpio6"; 5431 function = "qup1"; 5432 }; 5433 5434 qup_spi2_cs: qup-spi2-cs-state { 5435 pins = "gpio118"; 5436 function = "qup2"; 5437 }; 5438 5439 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5440 pins = "gpio118"; 5441 function = "gpio"; 5442 }; 5443 5444 qup_spi2_data_clk: qup-spi2-data-clk-state { 5445 pins = "gpio115", "gpio116", 5446 "gpio117"; 5447 function = "qup2"; 5448 }; 5449 5450 qup_spi3_cs: qup-spi3-cs-state { 5451 pins = "gpio122"; 5452 function = "qup3"; 5453 }; 5454 5455 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5456 pins = "gpio122"; 5457 function = "gpio"; 5458 }; 5459 5460 qup_spi3_data_clk: qup-spi3-data-clk-state { 5461 pins = "gpio119", "gpio120", 5462 "gpio121"; 5463 function = "qup3"; 5464 }; 5465 5466 qup_spi4_cs: qup-spi4-cs-state { 5467 pins = "gpio11"; 5468 function = "qup4"; 5469 }; 5470 5471 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5472 pins = "gpio11"; 5473 function = "gpio"; 5474 }; 5475 5476 qup_spi4_data_clk: qup-spi4-data-clk-state { 5477 pins = "gpio8", "gpio9", 5478 "gpio10"; 5479 function = "qup4"; 5480 }; 5481 5482 qup_spi5_cs: qup-spi5-cs-state { 5483 pins = "gpio15"; 5484 function = "qup5"; 5485 }; 5486 5487 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5488 pins = "gpio15"; 5489 function = "gpio"; 5490 }; 5491 5492 qup_spi5_data_clk: qup-spi5-data-clk-state { 5493 pins = "gpio12", "gpio13", 5494 "gpio14"; 5495 function = "qup5"; 5496 }; 5497 5498 qup_spi6_cs: qup-spi6-cs-state { 5499 pins = "gpio19"; 5500 function = "qup6"; 5501 }; 5502 5503 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5504 pins = "gpio19"; 5505 function = "gpio"; 5506 }; 5507 5508 qup_spi6_data_clk: qup-spi6-data-clk-state { 5509 pins = "gpio16", "gpio17", 5510 "gpio18"; 5511 function = "qup6"; 5512 }; 5513 5514 qup_spi7_cs: qup-spi7-cs-state { 5515 pins = "gpio23"; 5516 function = "qup7"; 5517 }; 5518 5519 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5520 pins = "gpio23"; 5521 function = "gpio"; 5522 }; 5523 5524 qup_spi7_data_clk: qup-spi7-data-clk-state { 5525 pins = "gpio20", "gpio21", 5526 "gpio22"; 5527 function = "qup7"; 5528 }; 5529 5530 qup_spi8_cs: qup-spi8-cs-state { 5531 pins = "gpio27"; 5532 function = "qup8"; 5533 }; 5534 5535 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5536 pins = "gpio27"; 5537 function = "gpio"; 5538 }; 5539 5540 qup_spi8_data_clk: qup-spi8-data-clk-state { 5541 pins = "gpio24", "gpio25", 5542 "gpio26"; 5543 function = "qup8"; 5544 }; 5545 5546 qup_spi9_cs: qup-spi9-cs-state { 5547 pins = "gpio128"; 5548 function = "qup9"; 5549 }; 5550 5551 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5552 pins = "gpio128"; 5553 function = "gpio"; 5554 }; 5555 5556 qup_spi9_data_clk: qup-spi9-data-clk-state { 5557 pins = "gpio125", "gpio126", 5558 "gpio127"; 5559 function = "qup9"; 5560 }; 5561 5562 qup_spi10_cs: qup-spi10-cs-state { 5563 pins = "gpio132"; 5564 function = "qup10"; 5565 }; 5566 5567 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5568 pins = "gpio132"; 5569 function = "gpio"; 5570 }; 5571 5572 qup_spi10_data_clk: qup-spi10-data-clk-state { 5573 pins = "gpio129", "gpio130", 5574 "gpio131"; 5575 function = "qup10"; 5576 }; 5577 5578 qup_spi11_cs: qup-spi11-cs-state { 5579 pins = "gpio63"; 5580 function = "qup11"; 5581 }; 5582 5583 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5584 pins = "gpio63"; 5585 function = "gpio"; 5586 }; 5587 5588 qup_spi11_data_clk: qup-spi11-data-clk-state { 5589 pins = "gpio60", "gpio61", 5590 "gpio62"; 5591 function = "qup11"; 5592 }; 5593 5594 qup_spi12_cs: qup-spi12-cs-state { 5595 pins = "gpio35"; 5596 function = "qup12"; 5597 }; 5598 5599 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5600 pins = "gpio35"; 5601 function = "gpio"; 5602 }; 5603 5604 qup_spi12_data_clk: qup-spi12-data-clk-state { 5605 pins = "gpio32", "gpio33", 5606 "gpio34"; 5607 function = "qup12"; 5608 }; 5609 5610 qup_spi13_cs: qup-spi13-cs-state { 5611 pins = "gpio39"; 5612 function = "qup13"; 5613 }; 5614 5615 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5616 pins = "gpio39"; 5617 function = "gpio"; 5618 }; 5619 5620 qup_spi13_data_clk: qup-spi13-data-clk-state { 5621 pins = "gpio36", "gpio37", 5622 "gpio38"; 5623 function = "qup13"; 5624 }; 5625 5626 qup_spi14_cs: qup-spi14-cs-state { 5627 pins = "gpio43"; 5628 function = "qup14"; 5629 }; 5630 5631 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5632 pins = "gpio43"; 5633 function = "gpio"; 5634 }; 5635 5636 qup_spi14_data_clk: qup-spi14-data-clk-state { 5637 pins = "gpio40", "gpio41", 5638 "gpio42"; 5639 function = "qup14"; 5640 }; 5641 5642 qup_spi15_cs: qup-spi15-cs-state { 5643 pins = "gpio47"; 5644 function = "qup15"; 5645 }; 5646 5647 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5648 pins = "gpio47"; 5649 function = "gpio"; 5650 }; 5651 5652 qup_spi15_data_clk: qup-spi15-data-clk-state { 5653 pins = "gpio44", "gpio45", 5654 "gpio46"; 5655 function = "qup15"; 5656 }; 5657 5658 qup_spi16_cs: qup-spi16-cs-state { 5659 pins = "gpio51"; 5660 function = "qup16"; 5661 }; 5662 5663 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 5664 pins = "gpio51"; 5665 function = "gpio"; 5666 }; 5667 5668 qup_spi16_data_clk: qup-spi16-data-clk-state { 5669 pins = "gpio48", "gpio49", 5670 "gpio50"; 5671 function = "qup16"; 5672 }; 5673 5674 qup_spi17_cs: qup-spi17-cs-state { 5675 pins = "gpio55"; 5676 function = "qup17"; 5677 }; 5678 5679 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { 5680 pins = "gpio55"; 5681 function = "gpio"; 5682 }; 5683 5684 qup_spi17_data_clk: qup-spi17-data-clk-state { 5685 pins = "gpio52", "gpio53", 5686 "gpio54"; 5687 function = "qup17"; 5688 }; 5689 5690 qup_spi18_cs: qup-spi18-cs-state { 5691 pins = "gpio59"; 5692 function = "qup18"; 5693 }; 5694 5695 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { 5696 pins = "gpio59"; 5697 function = "gpio"; 5698 }; 5699 5700 qup_spi18_data_clk: qup-spi18-data-clk-state { 5701 pins = "gpio56", "gpio57", 5702 "gpio58"; 5703 function = "qup18"; 5704 }; 5705 5706 qup_spi19_cs: qup-spi19-cs-state { 5707 pins = "gpio3"; 5708 function = "qup19"; 5709 }; 5710 5711 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { 5712 pins = "gpio3"; 5713 function = "gpio"; 5714 }; 5715 5716 qup_spi19_data_clk: qup-spi19-data-clk-state { 5717 pins = "gpio0", "gpio1", 5718 "gpio2"; 5719 function = "qup19"; 5720 }; 5721 5722 qup_uart2_default: qup-uart2-default-state { 5723 pins = "gpio117", "gpio118"; 5724 function = "qup2"; 5725 }; 5726 5727 qup_uart6_default: qup-uart6-default-state { 5728 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 5729 function = "qup6"; 5730 }; 5731 5732 qup_uart12_default: qup-uart12-default-state { 5733 pins = "gpio34", "gpio35"; 5734 function = "qup12"; 5735 }; 5736 5737 qup_uart17_default: qup-uart17-default-state { 5738 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5739 function = "qup17"; 5740 }; 5741 5742 qup_uart18_default: qup-uart18-default-state { 5743 pins = "gpio58", "gpio59"; 5744 function = "qup18"; 5745 }; 5746 5747 tert_mi2s_active: tert-mi2s-active-state { 5748 sck-pins { 5749 pins = "gpio133"; 5750 function = "mi2s2_sck"; 5751 drive-strength = <8>; 5752 bias-disable; 5753 }; 5754 5755 data0-pins { 5756 pins = "gpio134"; 5757 function = "mi2s2_data0"; 5758 drive-strength = <8>; 5759 bias-disable; 5760 output-high; 5761 }; 5762 5763 ws-pins { 5764 pins = "gpio135"; 5765 function = "mi2s2_ws"; 5766 drive-strength = <8>; 5767 output-high; 5768 }; 5769 }; 5770 5771 sdc2_sleep_state: sdc2-sleep-state { 5772 clk-pins { 5773 pins = "sdc2_clk"; 5774 drive-strength = <2>; 5775 bias-disable; 5776 }; 5777 5778 cmd-pins { 5779 pins = "sdc2_cmd"; 5780 drive-strength = <2>; 5781 bias-pull-up; 5782 }; 5783 5784 data-pins { 5785 pins = "sdc2_data"; 5786 drive-strength = <2>; 5787 bias-pull-up; 5788 }; 5789 }; 5790 5791 pcie0_default_state: pcie0-default-state { 5792 perst-pins { 5793 pins = "gpio79"; 5794 function = "gpio"; 5795 drive-strength = <2>; 5796 bias-pull-down; 5797 }; 5798 5799 clkreq-pins { 5800 pins = "gpio80"; 5801 function = "pci_e0"; 5802 drive-strength = <2>; 5803 bias-pull-up; 5804 }; 5805 5806 wake-pins { 5807 pins = "gpio81"; 5808 function = "gpio"; 5809 drive-strength = <2>; 5810 bias-pull-up; 5811 }; 5812 }; 5813 5814 pcie1_default_state: pcie1-default-state { 5815 perst-pins { 5816 pins = "gpio82"; 5817 function = "gpio"; 5818 drive-strength = <2>; 5819 bias-pull-down; 5820 }; 5821 5822 clkreq-pins { 5823 pins = "gpio83"; 5824 function = "pci_e1"; 5825 drive-strength = <2>; 5826 bias-pull-up; 5827 }; 5828 5829 wake-pins { 5830 pins = "gpio84"; 5831 function = "gpio"; 5832 drive-strength = <2>; 5833 bias-pull-up; 5834 }; 5835 }; 5836 5837 pcie2_default_state: pcie2-default-state { 5838 perst-pins { 5839 pins = "gpio85"; 5840 function = "gpio"; 5841 drive-strength = <2>; 5842 bias-pull-down; 5843 }; 5844 5845 clkreq-pins { 5846 pins = "gpio86"; 5847 function = "pci_e2"; 5848 drive-strength = <2>; 5849 bias-pull-up; 5850 }; 5851 5852 wake-pins { 5853 pins = "gpio87"; 5854 function = "gpio"; 5855 drive-strength = <2>; 5856 bias-pull-up; 5857 }; 5858 }; 5859 }; 5860 5861 apps_smmu: iommu@15000000 { 5862 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5863 reg = <0 0x15000000 0 0x100000>; 5864 #iommu-cells = <2>; 5865 #global-interrupts = <2>; 5866 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5867 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5868 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5869 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5870 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5871 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5872 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5873 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5874 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5875 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5876 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5877 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5878 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5879 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5880 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5881 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5882 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5883 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5884 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5885 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5886 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5887 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5888 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5889 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5890 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5891 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5892 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5893 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5894 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5895 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5896 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5897 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5898 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5899 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5900 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5901 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5902 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5903 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5904 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5905 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5906 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5907 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5908 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5909 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5910 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5911 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5912 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5913 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5914 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5915 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5916 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5917 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5918 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5919 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5920 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5921 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5922 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5923 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5924 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5925 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5926 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5927 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5928 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5929 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5930 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5931 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5932 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5933 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5934 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5935 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5936 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5937 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5938 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5939 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5940 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5941 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5942 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5943 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5944 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5945 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5946 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5947 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5948 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5949 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5950 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5951 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5952 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5953 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5954 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5955 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5956 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5957 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5958 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5959 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5960 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5961 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5962 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5963 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 5964 dma-coherent; 5965 }; 5966 5967 adsp: remoteproc@17300000 { 5968 compatible = "qcom,sm8250-adsp-pas"; 5969 reg = <0 0x17300000 0 0x100>; 5970 5971 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 5972 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5973 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5974 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5975 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5976 interrupt-names = "wdog", "fatal", "ready", 5977 "handover", "stop-ack"; 5978 5979 clocks = <&rpmhcc RPMH_CXO_CLK>; 5980 clock-names = "xo"; 5981 5982 power-domains = <&rpmhpd RPMHPD_LCX>, 5983 <&rpmhpd RPMHPD_LMX>; 5984 power-domain-names = "lcx", "lmx"; 5985 5986 memory-region = <&adsp_mem>; 5987 5988 qcom,qmp = <&aoss_qmp>; 5989 5990 qcom,smem-states = <&smp2p_adsp_out 0>; 5991 qcom,smem-state-names = "stop"; 5992 5993 status = "disabled"; 5994 5995 glink-edge { 5996 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5997 IPCC_MPROC_SIGNAL_GLINK_QMP 5998 IRQ_TYPE_EDGE_RISING>; 5999 mboxes = <&ipcc IPCC_CLIENT_LPASS 6000 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6001 6002 label = "lpass"; 6003 qcom,remote-pid = <2>; 6004 6005 apr { 6006 compatible = "qcom,apr-v2"; 6007 qcom,glink-channels = "apr_audio_svc"; 6008 qcom,domain = <APR_DOMAIN_ADSP>; 6009 #address-cells = <1>; 6010 #size-cells = <0>; 6011 6012 service@3 { 6013 reg = <APR_SVC_ADSP_CORE>; 6014 compatible = "qcom,q6core"; 6015 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6016 }; 6017 6018 q6afe: service@4 { 6019 compatible = "qcom,q6afe"; 6020 reg = <APR_SVC_AFE>; 6021 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6022 q6afedai: dais { 6023 compatible = "qcom,q6afe-dais"; 6024 #address-cells = <1>; 6025 #size-cells = <0>; 6026 #sound-dai-cells = <1>; 6027 }; 6028 6029 q6afecc: clock-controller { 6030 compatible = "qcom,q6afe-clocks"; 6031 #clock-cells = <2>; 6032 }; 6033 }; 6034 6035 q6asm: service@7 { 6036 compatible = "qcom,q6asm"; 6037 reg = <APR_SVC_ASM>; 6038 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6039 q6asmdai: dais { 6040 compatible = "qcom,q6asm-dais"; 6041 #address-cells = <1>; 6042 #size-cells = <0>; 6043 #sound-dai-cells = <1>; 6044 iommus = <&apps_smmu 0x1801 0x0>; 6045 }; 6046 }; 6047 6048 q6adm: service@8 { 6049 compatible = "qcom,q6adm"; 6050 reg = <APR_SVC_ADM>; 6051 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6052 q6routing: routing { 6053 compatible = "qcom,q6adm-routing"; 6054 #sound-dai-cells = <0>; 6055 }; 6056 }; 6057 }; 6058 6059 fastrpc { 6060 compatible = "qcom,fastrpc"; 6061 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6062 label = "adsp"; 6063 qcom,non-secure-domain; 6064 #address-cells = <1>; 6065 #size-cells = <0>; 6066 6067 compute-cb@3 { 6068 compatible = "qcom,fastrpc-compute-cb"; 6069 reg = <3>; 6070 iommus = <&apps_smmu 0x1803 0x0>; 6071 }; 6072 6073 compute-cb@4 { 6074 compatible = "qcom,fastrpc-compute-cb"; 6075 reg = <4>; 6076 iommus = <&apps_smmu 0x1804 0x0>; 6077 }; 6078 6079 compute-cb@5 { 6080 compatible = "qcom,fastrpc-compute-cb"; 6081 reg = <5>; 6082 iommus = <&apps_smmu 0x1805 0x0>; 6083 }; 6084 }; 6085 }; 6086 }; 6087 6088 intc: interrupt-controller@17a00000 { 6089 compatible = "arm,gic-v3"; 6090 #interrupt-cells = <3>; 6091 interrupt-controller; 6092 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 6093 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 6094 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 6095 }; 6096 6097 watchdog@17c10000 { 6098 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 6099 reg = <0 0x17c10000 0 0x1000>; 6100 clocks = <&sleep_clk>; 6101 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6102 }; 6103 6104 timer@17c20000 { 6105 #address-cells = <1>; 6106 #size-cells = <1>; 6107 ranges = <0 0 0 0x20000000>; 6108 compatible = "arm,armv7-timer-mem"; 6109 reg = <0x0 0x17c20000 0x0 0x1000>; 6110 clock-frequency = <19200000>; 6111 6112 frame@17c21000 { 6113 frame-number = <0>; 6114 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6115 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6116 reg = <0x17c21000 0x1000>, 6117 <0x17c22000 0x1000>; 6118 }; 6119 6120 frame@17c23000 { 6121 frame-number = <1>; 6122 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6123 reg = <0x17c23000 0x1000>; 6124 status = "disabled"; 6125 }; 6126 6127 frame@17c25000 { 6128 frame-number = <2>; 6129 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6130 reg = <0x17c25000 0x1000>; 6131 status = "disabled"; 6132 }; 6133 6134 frame@17c27000 { 6135 frame-number = <3>; 6136 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6137 reg = <0x17c27000 0x1000>; 6138 status = "disabled"; 6139 }; 6140 6141 frame@17c29000 { 6142 frame-number = <4>; 6143 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6144 reg = <0x17c29000 0x1000>; 6145 status = "disabled"; 6146 }; 6147 6148 frame@17c2b000 { 6149 frame-number = <5>; 6150 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6151 reg = <0x17c2b000 0x1000>; 6152 status = "disabled"; 6153 }; 6154 6155 frame@17c2d000 { 6156 frame-number = <6>; 6157 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6158 reg = <0x17c2d000 0x1000>; 6159 status = "disabled"; 6160 }; 6161 }; 6162 6163 apps_rsc: rsc@18200000 { 6164 label = "apps_rsc"; 6165 compatible = "qcom,rpmh-rsc"; 6166 reg = <0x0 0x18200000 0x0 0x10000>, 6167 <0x0 0x18210000 0x0 0x10000>, 6168 <0x0 0x18220000 0x0 0x10000>; 6169 reg-names = "drv-0", "drv-1", "drv-2"; 6170 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6171 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6172 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6173 qcom,tcs-offset = <0xd00>; 6174 qcom,drv-id = <2>; 6175 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 6176 <WAKE_TCS 3>, <CONTROL_TCS 1>; 6177 power-domains = <&cluster_pd>; 6178 6179 rpmhcc: clock-controller { 6180 compatible = "qcom,sm8250-rpmh-clk"; 6181 #clock-cells = <1>; 6182 clock-names = "xo"; 6183 clocks = <&xo_board>; 6184 }; 6185 6186 rpmhpd: power-controller { 6187 compatible = "qcom,sm8250-rpmhpd"; 6188 #power-domain-cells = <1>; 6189 operating-points-v2 = <&rpmhpd_opp_table>; 6190 6191 rpmhpd_opp_table: opp-table { 6192 compatible = "operating-points-v2"; 6193 6194 rpmhpd_opp_ret: opp1 { 6195 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6196 }; 6197 6198 rpmhpd_opp_min_svs: opp2 { 6199 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6200 }; 6201 6202 rpmhpd_opp_low_svs: opp3 { 6203 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6204 }; 6205 6206 rpmhpd_opp_svs: opp4 { 6207 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6208 }; 6209 6210 rpmhpd_opp_svs_l1: opp5 { 6211 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6212 }; 6213 6214 rpmhpd_opp_nom: opp6 { 6215 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6216 }; 6217 6218 rpmhpd_opp_nom_l1: opp7 { 6219 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6220 }; 6221 6222 rpmhpd_opp_nom_l2: opp8 { 6223 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6224 }; 6225 6226 rpmhpd_opp_turbo: opp9 { 6227 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6228 }; 6229 6230 rpmhpd_opp_turbo_l1: opp10 { 6231 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6232 }; 6233 }; 6234 }; 6235 6236 apps_bcm_voter: bcm-voter { 6237 compatible = "qcom,bcm-voter"; 6238 }; 6239 }; 6240 6241 epss_l3: interconnect@18590000 { 6242 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; 6243 reg = <0 0x18590000 0 0x1000>; 6244 6245 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 6246 clock-names = "xo", "alternate"; 6247 6248 #interconnect-cells = <1>; 6249 }; 6250 6251 cpufreq_hw: cpufreq@18591000 { 6252 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 6253 reg = <0 0x18591000 0 0x1000>, 6254 <0 0x18592000 0 0x1000>, 6255 <0 0x18593000 0 0x1000>; 6256 reg-names = "freq-domain0", "freq-domain1", 6257 "freq-domain2"; 6258 6259 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 6260 clock-names = "xo", "alternate"; 6261 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 6262 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6263 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 6264 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 6265 #freq-domain-cells = <1>; 6266 #clock-cells = <1>; 6267 }; 6268 }; 6269 6270 sound: sound { 6271 }; 6272 6273 timer { 6274 compatible = "arm,armv8-timer"; 6275 interrupts = <GIC_PPI 13 6276 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6277 <GIC_PPI 14 6278 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6279 <GIC_PPI 11 6280 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6281 <GIC_PPI 10 6282 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6283 }; 6284 6285 thermal-zones { 6286 cpu0-thermal { 6287 polling-delay-passive = <250>; 6288 6289 thermal-sensors = <&tsens0 1>; 6290 6291 trips { 6292 cpu0_alert0: trip-point0 { 6293 temperature = <90000>; 6294 hysteresis = <2000>; 6295 type = "passive"; 6296 }; 6297 6298 cpu0_alert1: trip-point1 { 6299 temperature = <95000>; 6300 hysteresis = <2000>; 6301 type = "passive"; 6302 }; 6303 6304 cpu0_crit: cpu-crit { 6305 temperature = <110000>; 6306 hysteresis = <1000>; 6307 type = "critical"; 6308 }; 6309 }; 6310 6311 cooling-maps { 6312 map0 { 6313 trip = <&cpu0_alert0>; 6314 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6315 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6316 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6317 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6318 }; 6319 map1 { 6320 trip = <&cpu0_alert1>; 6321 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6322 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6323 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6324 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6325 }; 6326 }; 6327 }; 6328 6329 cpu1-thermal { 6330 polling-delay-passive = <250>; 6331 6332 thermal-sensors = <&tsens0 2>; 6333 6334 trips { 6335 cpu1_alert0: trip-point0 { 6336 temperature = <90000>; 6337 hysteresis = <2000>; 6338 type = "passive"; 6339 }; 6340 6341 cpu1_alert1: trip-point1 { 6342 temperature = <95000>; 6343 hysteresis = <2000>; 6344 type = "passive"; 6345 }; 6346 6347 cpu1_crit: cpu-crit { 6348 temperature = <110000>; 6349 hysteresis = <1000>; 6350 type = "critical"; 6351 }; 6352 }; 6353 6354 cooling-maps { 6355 map0 { 6356 trip = <&cpu1_alert0>; 6357 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6358 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6359 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6360 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6361 }; 6362 map1 { 6363 trip = <&cpu1_alert1>; 6364 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6365 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6366 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6367 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6368 }; 6369 }; 6370 }; 6371 6372 cpu2-thermal { 6373 polling-delay-passive = <250>; 6374 6375 thermal-sensors = <&tsens0 3>; 6376 6377 trips { 6378 cpu2_alert0: trip-point0 { 6379 temperature = <90000>; 6380 hysteresis = <2000>; 6381 type = "passive"; 6382 }; 6383 6384 cpu2_alert1: trip-point1 { 6385 temperature = <95000>; 6386 hysteresis = <2000>; 6387 type = "passive"; 6388 }; 6389 6390 cpu2_crit: cpu-crit { 6391 temperature = <110000>; 6392 hysteresis = <1000>; 6393 type = "critical"; 6394 }; 6395 }; 6396 6397 cooling-maps { 6398 map0 { 6399 trip = <&cpu2_alert0>; 6400 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6401 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6402 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6403 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6404 }; 6405 map1 { 6406 trip = <&cpu2_alert1>; 6407 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6408 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6409 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6410 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6411 }; 6412 }; 6413 }; 6414 6415 cpu3-thermal { 6416 polling-delay-passive = <250>; 6417 6418 thermal-sensors = <&tsens0 4>; 6419 6420 trips { 6421 cpu3_alert0: trip-point0 { 6422 temperature = <90000>; 6423 hysteresis = <2000>; 6424 type = "passive"; 6425 }; 6426 6427 cpu3_alert1: trip-point1 { 6428 temperature = <95000>; 6429 hysteresis = <2000>; 6430 type = "passive"; 6431 }; 6432 6433 cpu3_crit: cpu-crit { 6434 temperature = <110000>; 6435 hysteresis = <1000>; 6436 type = "critical"; 6437 }; 6438 }; 6439 6440 cooling-maps { 6441 map0 { 6442 trip = <&cpu3_alert0>; 6443 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6444 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6445 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6446 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6447 }; 6448 map1 { 6449 trip = <&cpu3_alert1>; 6450 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6451 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6452 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6453 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6454 }; 6455 }; 6456 }; 6457 6458 cpu4-top-thermal { 6459 polling-delay-passive = <250>; 6460 6461 thermal-sensors = <&tsens0 7>; 6462 6463 trips { 6464 cpu4_top_alert0: trip-point0 { 6465 temperature = <90000>; 6466 hysteresis = <2000>; 6467 type = "passive"; 6468 }; 6469 6470 cpu4_top_alert1: trip-point1 { 6471 temperature = <95000>; 6472 hysteresis = <2000>; 6473 type = "passive"; 6474 }; 6475 6476 cpu4_top_crit: cpu-crit { 6477 temperature = <110000>; 6478 hysteresis = <1000>; 6479 type = "critical"; 6480 }; 6481 }; 6482 6483 cooling-maps { 6484 map0 { 6485 trip = <&cpu4_top_alert0>; 6486 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6487 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6488 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6489 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6490 }; 6491 map1 { 6492 trip = <&cpu4_top_alert1>; 6493 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6494 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6495 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6496 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6497 }; 6498 }; 6499 }; 6500 6501 cpu5-top-thermal { 6502 polling-delay-passive = <250>; 6503 6504 thermal-sensors = <&tsens0 8>; 6505 6506 trips { 6507 cpu5_top_alert0: trip-point0 { 6508 temperature = <90000>; 6509 hysteresis = <2000>; 6510 type = "passive"; 6511 }; 6512 6513 cpu5_top_alert1: trip-point1 { 6514 temperature = <95000>; 6515 hysteresis = <2000>; 6516 type = "passive"; 6517 }; 6518 6519 cpu5_top_crit: cpu-crit { 6520 temperature = <110000>; 6521 hysteresis = <1000>; 6522 type = "critical"; 6523 }; 6524 }; 6525 6526 cooling-maps { 6527 map0 { 6528 trip = <&cpu5_top_alert0>; 6529 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6530 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6531 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6532 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6533 }; 6534 map1 { 6535 trip = <&cpu5_top_alert1>; 6536 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6537 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6538 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6539 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6540 }; 6541 }; 6542 }; 6543 6544 cpu6-top-thermal { 6545 polling-delay-passive = <250>; 6546 6547 thermal-sensors = <&tsens0 9>; 6548 6549 trips { 6550 cpu6_top_alert0: trip-point0 { 6551 temperature = <90000>; 6552 hysteresis = <2000>; 6553 type = "passive"; 6554 }; 6555 6556 cpu6_top_alert1: trip-point1 { 6557 temperature = <95000>; 6558 hysteresis = <2000>; 6559 type = "passive"; 6560 }; 6561 6562 cpu6_top_crit: cpu-crit { 6563 temperature = <110000>; 6564 hysteresis = <1000>; 6565 type = "critical"; 6566 }; 6567 }; 6568 6569 cooling-maps { 6570 map0 { 6571 trip = <&cpu6_top_alert0>; 6572 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6573 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6574 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6575 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6576 }; 6577 map1 { 6578 trip = <&cpu6_top_alert1>; 6579 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6580 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6581 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6582 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6583 }; 6584 }; 6585 }; 6586 6587 cpu7-top-thermal { 6588 polling-delay-passive = <250>; 6589 6590 thermal-sensors = <&tsens0 10>; 6591 6592 trips { 6593 cpu7_top_alert0: trip-point0 { 6594 temperature = <90000>; 6595 hysteresis = <2000>; 6596 type = "passive"; 6597 }; 6598 6599 cpu7_top_alert1: trip-point1 { 6600 temperature = <95000>; 6601 hysteresis = <2000>; 6602 type = "passive"; 6603 }; 6604 6605 cpu7_top_crit: cpu-crit { 6606 temperature = <110000>; 6607 hysteresis = <1000>; 6608 type = "critical"; 6609 }; 6610 }; 6611 6612 cooling-maps { 6613 map0 { 6614 trip = <&cpu7_top_alert0>; 6615 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6616 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6617 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6618 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6619 }; 6620 map1 { 6621 trip = <&cpu7_top_alert1>; 6622 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6623 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6624 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6625 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6626 }; 6627 }; 6628 }; 6629 6630 cpu4-bottom-thermal { 6631 polling-delay-passive = <250>; 6632 6633 thermal-sensors = <&tsens0 11>; 6634 6635 trips { 6636 cpu4_bottom_alert0: trip-point0 { 6637 temperature = <90000>; 6638 hysteresis = <2000>; 6639 type = "passive"; 6640 }; 6641 6642 cpu4_bottom_alert1: trip-point1 { 6643 temperature = <95000>; 6644 hysteresis = <2000>; 6645 type = "passive"; 6646 }; 6647 6648 cpu4_bottom_crit: cpu-crit { 6649 temperature = <110000>; 6650 hysteresis = <1000>; 6651 type = "critical"; 6652 }; 6653 }; 6654 6655 cooling-maps { 6656 map0 { 6657 trip = <&cpu4_bottom_alert0>; 6658 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6659 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6660 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6661 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6662 }; 6663 map1 { 6664 trip = <&cpu4_bottom_alert1>; 6665 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6666 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6667 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6668 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6669 }; 6670 }; 6671 }; 6672 6673 cpu5-bottom-thermal { 6674 polling-delay-passive = <250>; 6675 6676 thermal-sensors = <&tsens0 12>; 6677 6678 trips { 6679 cpu5_bottom_alert0: trip-point0 { 6680 temperature = <90000>; 6681 hysteresis = <2000>; 6682 type = "passive"; 6683 }; 6684 6685 cpu5_bottom_alert1: trip-point1 { 6686 temperature = <95000>; 6687 hysteresis = <2000>; 6688 type = "passive"; 6689 }; 6690 6691 cpu5_bottom_crit: cpu-crit { 6692 temperature = <110000>; 6693 hysteresis = <1000>; 6694 type = "critical"; 6695 }; 6696 }; 6697 6698 cooling-maps { 6699 map0 { 6700 trip = <&cpu5_bottom_alert0>; 6701 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6702 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6703 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6704 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6705 }; 6706 map1 { 6707 trip = <&cpu5_bottom_alert1>; 6708 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6709 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6710 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6711 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6712 }; 6713 }; 6714 }; 6715 6716 cpu6-bottom-thermal { 6717 polling-delay-passive = <250>; 6718 6719 thermal-sensors = <&tsens0 13>; 6720 6721 trips { 6722 cpu6_bottom_alert0: trip-point0 { 6723 temperature = <90000>; 6724 hysteresis = <2000>; 6725 type = "passive"; 6726 }; 6727 6728 cpu6_bottom_alert1: trip-point1 { 6729 temperature = <95000>; 6730 hysteresis = <2000>; 6731 type = "passive"; 6732 }; 6733 6734 cpu6_bottom_crit: cpu-crit { 6735 temperature = <110000>; 6736 hysteresis = <1000>; 6737 type = "critical"; 6738 }; 6739 }; 6740 6741 cooling-maps { 6742 map0 { 6743 trip = <&cpu6_bottom_alert0>; 6744 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6745 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6746 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6747 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6748 }; 6749 map1 { 6750 trip = <&cpu6_bottom_alert1>; 6751 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6752 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6753 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6754 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6755 }; 6756 }; 6757 }; 6758 6759 cpu7-bottom-thermal { 6760 polling-delay-passive = <250>; 6761 6762 thermal-sensors = <&tsens0 14>; 6763 6764 trips { 6765 cpu7_bottom_alert0: trip-point0 { 6766 temperature = <90000>; 6767 hysteresis = <2000>; 6768 type = "passive"; 6769 }; 6770 6771 cpu7_bottom_alert1: trip-point1 { 6772 temperature = <95000>; 6773 hysteresis = <2000>; 6774 type = "passive"; 6775 }; 6776 6777 cpu7_bottom_crit: cpu-crit { 6778 temperature = <110000>; 6779 hysteresis = <1000>; 6780 type = "critical"; 6781 }; 6782 }; 6783 6784 cooling-maps { 6785 map0 { 6786 trip = <&cpu7_bottom_alert0>; 6787 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6788 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6789 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6790 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6791 }; 6792 map1 { 6793 trip = <&cpu7_bottom_alert1>; 6794 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6795 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6796 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6797 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6798 }; 6799 }; 6800 }; 6801 6802 aoss0-thermal { 6803 polling-delay-passive = <250>; 6804 6805 thermal-sensors = <&tsens0 0>; 6806 6807 trips { 6808 aoss0_alert0: trip-point0 { 6809 temperature = <90000>; 6810 hysteresis = <2000>; 6811 type = "hot"; 6812 }; 6813 }; 6814 }; 6815 6816 cluster0-thermal { 6817 polling-delay-passive = <250>; 6818 6819 thermal-sensors = <&tsens0 5>; 6820 6821 trips { 6822 cluster0_alert0: trip-point0 { 6823 temperature = <90000>; 6824 hysteresis = <2000>; 6825 type = "hot"; 6826 }; 6827 cluster0_crit: cluster0-crit { 6828 temperature = <110000>; 6829 hysteresis = <2000>; 6830 type = "critical"; 6831 }; 6832 }; 6833 }; 6834 6835 cluster1-thermal { 6836 polling-delay-passive = <250>; 6837 6838 thermal-sensors = <&tsens0 6>; 6839 6840 trips { 6841 cluster1_alert0: trip-point0 { 6842 temperature = <90000>; 6843 hysteresis = <2000>; 6844 type = "hot"; 6845 }; 6846 cluster1_crit: cluster1-crit { 6847 temperature = <110000>; 6848 hysteresis = <2000>; 6849 type = "critical"; 6850 }; 6851 }; 6852 }; 6853 6854 gpu-top-thermal { 6855 polling-delay-passive = <250>; 6856 6857 thermal-sensors = <&tsens0 15>; 6858 6859 cooling-maps { 6860 map0 { 6861 trip = <&gpu_top_alert0>; 6862 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6863 }; 6864 }; 6865 6866 trips { 6867 gpu_top_alert0: trip-point0 { 6868 temperature = <85000>; 6869 hysteresis = <1000>; 6870 type = "passive"; 6871 }; 6872 6873 trip-point1 { 6874 temperature = <90000>; 6875 hysteresis = <1000>; 6876 type = "hot"; 6877 }; 6878 6879 trip-point2 { 6880 temperature = <110000>; 6881 hysteresis = <1000>; 6882 type = "critical"; 6883 }; 6884 }; 6885 }; 6886 6887 aoss1-thermal { 6888 polling-delay-passive = <250>; 6889 6890 thermal-sensors = <&tsens1 0>; 6891 6892 trips { 6893 aoss1_alert0: trip-point0 { 6894 temperature = <90000>; 6895 hysteresis = <2000>; 6896 type = "hot"; 6897 }; 6898 }; 6899 }; 6900 6901 wlan-thermal { 6902 polling-delay-passive = <250>; 6903 6904 thermal-sensors = <&tsens1 1>; 6905 6906 trips { 6907 wlan_alert0: trip-point0 { 6908 temperature = <90000>; 6909 hysteresis = <2000>; 6910 type = "hot"; 6911 }; 6912 }; 6913 }; 6914 6915 video-thermal { 6916 polling-delay-passive = <250>; 6917 6918 thermal-sensors = <&tsens1 2>; 6919 6920 trips { 6921 video_alert0: trip-point0 { 6922 temperature = <90000>; 6923 hysteresis = <2000>; 6924 type = "hot"; 6925 }; 6926 }; 6927 }; 6928 6929 mem-thermal { 6930 polling-delay-passive = <250>; 6931 6932 thermal-sensors = <&tsens1 3>; 6933 6934 trips { 6935 mem_alert0: trip-point0 { 6936 temperature = <90000>; 6937 hysteresis = <2000>; 6938 type = "hot"; 6939 }; 6940 }; 6941 }; 6942 6943 q6-hvx-thermal { 6944 polling-delay-passive = <250>; 6945 6946 thermal-sensors = <&tsens1 4>; 6947 6948 trips { 6949 q6_hvx_alert0: trip-point0 { 6950 temperature = <90000>; 6951 hysteresis = <2000>; 6952 type = "hot"; 6953 }; 6954 }; 6955 }; 6956 6957 camera-thermal { 6958 polling-delay-passive = <250>; 6959 6960 thermal-sensors = <&tsens1 5>; 6961 6962 trips { 6963 camera_alert0: trip-point0 { 6964 temperature = <90000>; 6965 hysteresis = <2000>; 6966 type = "hot"; 6967 }; 6968 }; 6969 }; 6970 6971 compute-thermal { 6972 polling-delay-passive = <250>; 6973 6974 thermal-sensors = <&tsens1 6>; 6975 6976 trips { 6977 compute_alert0: trip-point0 { 6978 temperature = <90000>; 6979 hysteresis = <2000>; 6980 type = "hot"; 6981 }; 6982 }; 6983 }; 6984 6985 npu-thermal { 6986 polling-delay-passive = <250>; 6987 6988 thermal-sensors = <&tsens1 7>; 6989 6990 trips { 6991 npu_alert0: trip-point0 { 6992 temperature = <90000>; 6993 hysteresis = <2000>; 6994 type = "hot"; 6995 }; 6996 }; 6997 }; 6998 6999 gpu-bottom-thermal { 7000 polling-delay-passive = <250>; 7001 7002 thermal-sensors = <&tsens1 8>; 7003 7004 cooling-maps { 7005 map0 { 7006 trip = <&gpu_bottom_alert0>; 7007 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7008 }; 7009 }; 7010 7011 trips { 7012 gpu_bottom_alert0: trip-point0 { 7013 temperature = <85000>; 7014 hysteresis = <1000>; 7015 type = "passive"; 7016 }; 7017 7018 trip-point1 { 7019 temperature = <90000>; 7020 hysteresis = <1000>; 7021 type = "hot"; 7022 }; 7023 7024 trip-point2 { 7025 temperature = <110000>; 7026 hysteresis = <1000>; 7027 type = "critical"; 7028 }; 7029 }; 7030 }; 7031 }; 7032}; 7033