1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm6350.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sm6350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm6350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,sm6350-camcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,sm6350.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/phy/phy-qcom-qmp.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,apr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <76800000>; 37 clock-output-names = "xo_board"; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 clock-frequency = <32764>; 43 #clock-cells = <0>; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "qcom,kryo560"; 54 reg = <0x0 0x0>; 55 clocks = <&cpufreq_hw 0>; 56 enable-method = "psci"; 57 capacity-dmips-mhz = <1024>; 58 dynamic-power-coefficient = <100>; 59 next-level-cache = <&l2_0>; 60 qcom,freq-domain = <&cpufreq_hw 0>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 63 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 64 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 65 power-domains = <&cpu_pd0>; 66 power-domain-names = "psci"; 67 #cooling-cells = <2>; 68 l2_0: l2-cache { 69 compatible = "cache"; 70 cache-level = <2>; 71 cache-unified; 72 next-level-cache = <&l3_0>; 73 l3_0: l3-cache { 74 compatible = "cache"; 75 cache-level = <3>; 76 cache-unified; 77 }; 78 }; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo560"; 84 reg = <0x0 0x100>; 85 clocks = <&cpufreq_hw 0>; 86 enable-method = "psci"; 87 capacity-dmips-mhz = <1024>; 88 dynamic-power-coefficient = <100>; 89 next-level-cache = <&l2_100>; 90 qcom,freq-domain = <&cpufreq_hw 0>; 91 operating-points-v2 = <&cpu0_opp_table>; 92 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 93 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 94 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 95 power-domains = <&cpu_pd1>; 96 power-domain-names = "psci"; 97 #cooling-cells = <2>; 98 l2_100: l2-cache { 99 compatible = "cache"; 100 cache-level = <2>; 101 cache-unified; 102 next-level-cache = <&l3_0>; 103 }; 104 }; 105 106 cpu2: cpu@200 { 107 device_type = "cpu"; 108 compatible = "qcom,kryo560"; 109 reg = <0x0 0x200>; 110 clocks = <&cpufreq_hw 0>; 111 enable-method = "psci"; 112 capacity-dmips-mhz = <1024>; 113 dynamic-power-coefficient = <100>; 114 next-level-cache = <&l2_200>; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 operating-points-v2 = <&cpu0_opp_table>; 117 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 118 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 119 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 120 power-domains = <&cpu_pd2>; 121 power-domain-names = "psci"; 122 #cooling-cells = <2>; 123 l2_200: l2-cache { 124 compatible = "cache"; 125 cache-level = <2>; 126 cache-unified; 127 next-level-cache = <&l3_0>; 128 }; 129 }; 130 131 cpu3: cpu@300 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo560"; 134 reg = <0x0 0x300>; 135 clocks = <&cpufreq_hw 0>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <1024>; 138 dynamic-power-coefficient = <100>; 139 next-level-cache = <&l2_300>; 140 qcom,freq-domain = <&cpufreq_hw 0>; 141 operating-points-v2 = <&cpu0_opp_table>; 142 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 143 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 144 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 145 power-domains = <&cpu_pd3>; 146 power-domain-names = "psci"; 147 #cooling-cells = <2>; 148 l2_300: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-unified; 152 next-level-cache = <&l3_0>; 153 }; 154 }; 155 156 cpu4: cpu@400 { 157 device_type = "cpu"; 158 compatible = "qcom,kryo560"; 159 reg = <0x0 0x400>; 160 clocks = <&cpufreq_hw 0>; 161 enable-method = "psci"; 162 capacity-dmips-mhz = <1024>; 163 dynamic-power-coefficient = <100>; 164 next-level-cache = <&l2_400>; 165 qcom,freq-domain = <&cpufreq_hw 0>; 166 operating-points-v2 = <&cpu0_opp_table>; 167 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 168 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 170 power-domains = <&cpu_pd4>; 171 power-domain-names = "psci"; 172 #cooling-cells = <2>; 173 l2_400: l2-cache { 174 compatible = "cache"; 175 cache-level = <2>; 176 cache-unified; 177 next-level-cache = <&l3_0>; 178 }; 179 }; 180 181 cpu5: cpu@500 { 182 device_type = "cpu"; 183 compatible = "qcom,kryo560"; 184 reg = <0x0 0x500>; 185 clocks = <&cpufreq_hw 0>; 186 enable-method = "psci"; 187 capacity-dmips-mhz = <1024>; 188 dynamic-power-coefficient = <100>; 189 next-level-cache = <&l2_500>; 190 qcom,freq-domain = <&cpufreq_hw 0>; 191 operating-points-v2 = <&cpu0_opp_table>; 192 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 193 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 194 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 195 power-domains = <&cpu_pd5>; 196 power-domain-names = "psci"; 197 #cooling-cells = <2>; 198 l2_500: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&l3_0>; 203 }; 204 }; 205 206 cpu6: cpu@600 { 207 device_type = "cpu"; 208 compatible = "qcom,kryo560"; 209 reg = <0x0 0x600>; 210 clocks = <&cpufreq_hw 1>; 211 enable-method = "psci"; 212 capacity-dmips-mhz = <1894>; 213 dynamic-power-coefficient = <703>; 214 next-level-cache = <&l2_600>; 215 qcom,freq-domain = <&cpufreq_hw 1>; 216 operating-points-v2 = <&cpu6_opp_table>; 217 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 218 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 219 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 220 power-domains = <&cpu_pd6>; 221 power-domain-names = "psci"; 222 #cooling-cells = <2>; 223 l2_600: l2-cache { 224 compatible = "cache"; 225 cache-level = <2>; 226 cache-unified; 227 next-level-cache = <&l3_0>; 228 }; 229 }; 230 231 cpu7: cpu@700 { 232 device_type = "cpu"; 233 compatible = "qcom,kryo560"; 234 reg = <0x0 0x700>; 235 clocks = <&cpufreq_hw 1>; 236 enable-method = "psci"; 237 capacity-dmips-mhz = <1894>; 238 dynamic-power-coefficient = <703>; 239 next-level-cache = <&l2_700>; 240 qcom,freq-domain = <&cpufreq_hw 1>; 241 operating-points-v2 = <&cpu6_opp_table>; 242 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 243 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 244 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 245 power-domains = <&cpu_pd7>; 246 power-domain-names = "psci"; 247 #cooling-cells = <2>; 248 l2_700: l2-cache { 249 compatible = "cache"; 250 cache-level = <2>; 251 cache-unified; 252 next-level-cache = <&l3_0>; 253 }; 254 }; 255 256 cpu-map { 257 cluster0 { 258 core0 { 259 cpu = <&cpu0>; 260 }; 261 262 core1 { 263 cpu = <&cpu1>; 264 }; 265 266 core2 { 267 cpu = <&cpu2>; 268 }; 269 270 core3 { 271 cpu = <&cpu3>; 272 }; 273 274 core4 { 275 cpu = <&cpu4>; 276 }; 277 278 core5 { 279 cpu = <&cpu5>; 280 }; 281 282 core6 { 283 cpu = <&cpu6>; 284 }; 285 286 core7 { 287 cpu = <&cpu7>; 288 }; 289 }; 290 }; 291 292 domain-idle-states { 293 cluster_sleep_pc: cluster-sleep-0 { 294 compatible = "domain-idle-state"; 295 arm,psci-suspend-param = <0x41000044>; 296 entry-latency-us = <2752>; 297 exit-latency-us = <3048>; 298 min-residency-us = <6118>; 299 }; 300 301 cluster_sleep_cx_ret: cluster-sleep-1 { 302 compatible = "domain-idle-state"; 303 arm,psci-suspend-param = <0x41001244>; 304 entry-latency-us = <3638>; 305 exit-latency-us = <4562>; 306 min-residency-us = <8467>; 307 }; 308 309 cluster_aoss_sleep: cluster-sleep-2 { 310 compatible = "domain-idle-state"; 311 arm,psci-suspend-param = <0x4100b244>; 312 entry-latency-us = <3263>; 313 exit-latency-us = <6562>; 314 min-residency-us = <9987>; 315 }; 316 }; 317 318 cpu_idle_states: idle-states { 319 entry-method = "psci"; 320 321 little_cpu_sleep_0: cpu-sleep-0-0 { 322 compatible = "arm,idle-state"; 323 idle-state-name = "little-power-collapse"; 324 arm,psci-suspend-param = <0x40000003>; 325 entry-latency-us = <549>; 326 exit-latency-us = <901>; 327 min-residency-us = <1774>; 328 local-timer-stop; 329 }; 330 331 little_cpu_sleep_1: cpu-sleep-0-1 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "little-rail-power-collapse"; 334 arm,psci-suspend-param = <0x40000004>; 335 entry-latency-us = <702>; 336 exit-latency-us = <915>; 337 min-residency-us = <4001>; 338 local-timer-stop; 339 }; 340 341 big_cpu_sleep_0: cpu-sleep-1-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "big-power-collapse"; 344 arm,psci-suspend-param = <0x40000003>; 345 entry-latency-us = <523>; 346 exit-latency-us = <1244>; 347 min-residency-us = <2207>; 348 local-timer-stop; 349 }; 350 351 big_cpu_sleep_1: cpu-sleep-1-1 { 352 compatible = "arm,idle-state"; 353 idle-state-name = "big-rail-power-collapse"; 354 arm,psci-suspend-param = <0x40000004>; 355 entry-latency-us = <526>; 356 exit-latency-us = <1854>; 357 min-residency-us = <5555>; 358 local-timer-stop; 359 }; 360 }; 361 }; 362 363 firmware { 364 scm: scm { 365 compatible = "qcom,scm-sm6350", "qcom,scm"; 366 #reset-cells = <1>; 367 }; 368 }; 369 370 memory@80000000 { 371 device_type = "memory"; 372 /* We expect the bootloader to fill in the size */ 373 reg = <0x0 0x80000000 0x0 0x0>; 374 }; 375 376 cpu0_opp_table: opp-table-cpu0 { 377 compatible = "operating-points-v2"; 378 opp-shared; 379 380 opp-300000000 { 381 opp-hz = /bits/ 64 <300000000>; 382 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 383 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 384 }; 385 386 opp-576000000 { 387 opp-hz = /bits/ 64 <576000000>; 388 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 389 }; 390 391 opp-768000000 { 392 opp-hz = /bits/ 64 <768000000>; 393 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 394 }; 395 396 opp-1017600000 { 397 opp-hz = /bits/ 64 <1017600000>; 398 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 399 }; 400 401 opp-1248000000 { 402 opp-hz = /bits/ 64 <1248000000>; 403 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 404 }; 405 406 opp-1324800000 { 407 opp-hz = /bits/ 64 <1324800000>; 408 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 409 }; 410 411 opp-1516800000 { 412 opp-hz = /bits/ 64 <1516800000>; 413 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 414 }; 415 416 opp-1612800000 { 417 opp-hz = /bits/ 64 <1612800000>; 418 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 419 }; 420 421 opp-1708800000 { 422 opp-hz = /bits/ 64 <1708800000>; 423 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 424 }; 425 }; 426 427 cpu6_opp_table: opp-table-cpu6 { 428 compatible = "operating-points-v2"; 429 opp-shared; 430 431 opp-300000000 { 432 opp-hz = /bits/ 64 <300000000>; 433 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 434 }; 435 436 opp-787200000 { 437 opp-hz = /bits/ 64 <787200000>; 438 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 439 }; 440 441 opp-979200000 { 442 opp-hz = /bits/ 64 <979200000>; 443 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 444 }; 445 446 opp-1036800000 { 447 opp-hz = /bits/ 64 <1036800000>; 448 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 449 }; 450 451 opp-1248000000 { 452 opp-hz = /bits/ 64 <1248000000>; 453 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 454 }; 455 456 opp-1401600000 { 457 opp-hz = /bits/ 64 <1401600000>; 458 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 459 }; 460 461 opp-1555200000 { 462 opp-hz = /bits/ 64 <1555200000>; 463 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 464 }; 465 466 opp-1766400000 { 467 opp-hz = /bits/ 64 <1766400000>; 468 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 469 }; 470 471 opp-1900800000 { 472 opp-hz = /bits/ 64 <1900800000>; 473 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 474 }; 475 476 opp-2073600000 { 477 opp-hz = /bits/ 64 <2073600000>; 478 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 479 }; 480 }; 481 482 qup_opp_table: opp-table-qup { 483 compatible = "operating-points-v2"; 484 485 opp-75000000 { 486 opp-hz = /bits/ 64 <75000000>; 487 required-opps = <&rpmhpd_opp_low_svs>; 488 }; 489 490 opp-100000000 { 491 opp-hz = /bits/ 64 <100000000>; 492 required-opps = <&rpmhpd_opp_svs>; 493 }; 494 495 opp-128000000 { 496 opp-hz = /bits/ 64 <128000000>; 497 required-opps = <&rpmhpd_opp_nom>; 498 }; 499 }; 500 501 pmu { 502 compatible = "arm,armv8-pmuv3"; 503 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 504 }; 505 506 psci { 507 compatible = "arm,psci-1.0"; 508 method = "smc"; 509 510 cpu_pd0: power-domain-cpu0 { 511 #power-domain-cells = <0>; 512 power-domains = <&cluster_pd>; 513 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 514 }; 515 516 cpu_pd1: power-domain-cpu1 { 517 #power-domain-cells = <0>; 518 power-domains = <&cluster_pd>; 519 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 520 }; 521 522 cpu_pd2: power-domain-cpu2 { 523 #power-domain-cells = <0>; 524 power-domains = <&cluster_pd>; 525 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 526 }; 527 528 cpu_pd3: power-domain-cpu3 { 529 #power-domain-cells = <0>; 530 power-domains = <&cluster_pd>; 531 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 532 }; 533 534 cpu_pd4: power-domain-cpu4 { 535 #power-domain-cells = <0>; 536 power-domains = <&cluster_pd>; 537 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 538 }; 539 540 cpu_pd5: power-domain-cpu5 { 541 #power-domain-cells = <0>; 542 power-domains = <&cluster_pd>; 543 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 544 }; 545 546 cpu_pd6: power-domain-cpu6 { 547 #power-domain-cells = <0>; 548 power-domains = <&cluster_pd>; 549 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 550 }; 551 552 cpu_pd7: power-domain-cpu7 { 553 #power-domain-cells = <0>; 554 power-domains = <&cluster_pd>; 555 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 556 }; 557 558 cluster_pd: power-domain-cpu-cluster0 { 559 #power-domain-cells = <0>; 560 domain-idle-states = <&cluster_sleep_pc 561 &cluster_sleep_cx_ret 562 &cluster_aoss_sleep>; 563 }; 564 }; 565 566 reserved_memory: reserved-memory { 567 #address-cells = <2>; 568 #size-cells = <2>; 569 ranges; 570 571 hyp_mem: memory@80000000 { 572 reg = <0x0 0x80000000 0x0 0x600000>; 573 no-map; 574 }; 575 576 xbl_aop_mem: memory@80700000 { 577 reg = <0x0 0x80700000 0x0 0x160000>; 578 no-map; 579 }; 580 581 cmd_db: memory@80860000 { 582 compatible = "qcom,cmd-db"; 583 reg = <0x0 0x80860000 0x0 0x20000>; 584 no-map; 585 }; 586 587 sec_apps_mem: memory@808ff000 { 588 reg = <0x0 0x808ff000 0x0 0x1000>; 589 no-map; 590 }; 591 592 smem_mem: memory@80900000 { 593 reg = <0x0 0x80900000 0x0 0x200000>; 594 no-map; 595 }; 596 597 cdsp_sec_mem: memory@80b00000 { 598 reg = <0x0 0x80b00000 0x0 0x1e00000>; 599 no-map; 600 }; 601 602 pil_camera_mem: memory@86000000 { 603 reg = <0x0 0x86000000 0x0 0x500000>; 604 no-map; 605 }; 606 607 pil_npu_mem: memory@86500000 { 608 reg = <0x0 0x86500000 0x0 0x500000>; 609 no-map; 610 }; 611 612 pil_video_mem: memory@86a00000 { 613 reg = <0x0 0x86a00000 0x0 0x500000>; 614 no-map; 615 }; 616 617 pil_cdsp_mem: memory@86f00000 { 618 reg = <0x0 0x86f00000 0x0 0x1e00000>; 619 no-map; 620 }; 621 622 pil_adsp_mem: memory@88d00000 { 623 reg = <0x0 0x88d00000 0x0 0x2800000>; 624 no-map; 625 }; 626 627 wlan_fw_mem: memory@8b500000 { 628 reg = <0x0 0x8b500000 0x0 0x200000>; 629 no-map; 630 }; 631 632 pil_ipa_fw_mem: memory@8b700000 { 633 reg = <0x0 0x8b700000 0x0 0x10000>; 634 no-map; 635 }; 636 637 pil_ipa_gsi_mem: memory@8b710000 { 638 reg = <0x0 0x8b710000 0x0 0x5400>; 639 no-map; 640 }; 641 642 pil_modem_mem: memory@8b800000 { 643 reg = <0x0 0x8b800000 0x0 0xf800000>; 644 no-map; 645 }; 646 647 cont_splash_memory: memory@a0000000 { 648 reg = <0x0 0xa0000000 0x0 0x2300000>; 649 no-map; 650 }; 651 652 dfps_data_memory: memory@a2300000 { 653 reg = <0x0 0xa2300000 0x0 0x100000>; 654 no-map; 655 }; 656 657 removed_region: memory@c0000000 { 658 reg = <0x0 0xc0000000 0x0 0x3900000>; 659 no-map; 660 }; 661 662 pil_gpu_mem: memory@f0d00000 { 663 reg = <0x0 0xf0d00000 0x0 0x1000>; 664 no-map; 665 }; 666 667 debug_region: memory@ffb00000 { 668 reg = <0x0 0xffb00000 0x0 0xc0000>; 669 no-map; 670 }; 671 672 last_log_region: memory@ffbc0000 { 673 reg = <0x0 0xffbc0000 0x0 0x40000>; 674 no-map; 675 }; 676 677 ramoops: ramoops@ffc00000 { 678 compatible = "ramoops"; 679 reg = <0x0 0xffc00000 0x0 0x100000>; 680 record-size = <0x1000>; 681 console-size = <0x40000>; 682 pmsg-size = <0x20000>; 683 ecc-size = <16>; 684 no-map; 685 }; 686 687 cmdline_region: memory@ffd00000 { 688 reg = <0x0 0xffd00000 0x0 0x1000>; 689 no-map; 690 }; 691 }; 692 693 smem { 694 compatible = "qcom,smem"; 695 memory-region = <&smem_mem>; 696 hwlocks = <&tcsr_mutex 3>; 697 }; 698 699 smp2p-adsp { 700 compatible = "qcom,smp2p"; 701 qcom,smem = <443>, <429>; 702 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 703 IPCC_MPROC_SIGNAL_SMP2P 704 IRQ_TYPE_EDGE_RISING>; 705 mboxes = <&ipcc IPCC_CLIENT_LPASS 706 IPCC_MPROC_SIGNAL_SMP2P>; 707 708 qcom,local-pid = <0>; 709 qcom,remote-pid = <2>; 710 711 smp2p_adsp_out: master-kernel { 712 qcom,entry-name = "master-kernel"; 713 #qcom,smem-state-cells = <1>; 714 }; 715 716 smp2p_adsp_in: slave-kernel { 717 qcom,entry-name = "slave-kernel"; 718 interrupt-controller; 719 #interrupt-cells = <2>; 720 }; 721 }; 722 723 smp2p-cdsp { 724 compatible = "qcom,smp2p"; 725 qcom,smem = <94>, <432>; 726 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 727 IPCC_MPROC_SIGNAL_SMP2P 728 IRQ_TYPE_EDGE_RISING>; 729 mboxes = <&ipcc IPCC_CLIENT_CDSP 730 IPCC_MPROC_SIGNAL_SMP2P>; 731 732 qcom,local-pid = <0>; 733 qcom,remote-pid = <5>; 734 735 smp2p_cdsp_out: master-kernel { 736 qcom,entry-name = "master-kernel"; 737 #qcom,smem-state-cells = <1>; 738 }; 739 740 smp2p_cdsp_in: slave-kernel { 741 qcom,entry-name = "slave-kernel"; 742 interrupt-controller; 743 #interrupt-cells = <2>; 744 }; 745 }; 746 747 smp2p-mpss { 748 compatible = "qcom,smp2p"; 749 qcom,smem = <435>, <428>; 750 751 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 752 IPCC_MPROC_SIGNAL_SMP2P 753 IRQ_TYPE_EDGE_RISING>; 754 mboxes = <&ipcc IPCC_CLIENT_MPSS 755 IPCC_MPROC_SIGNAL_SMP2P>; 756 757 qcom,local-pid = <0>; 758 qcom,remote-pid = <1>; 759 760 modem_smp2p_out: master-kernel { 761 qcom,entry-name = "master-kernel"; 762 #qcom,smem-state-cells = <1>; 763 }; 764 765 modem_smp2p_in: slave-kernel { 766 qcom,entry-name = "slave-kernel"; 767 interrupt-controller; 768 #interrupt-cells = <2>; 769 }; 770 771 ipa_smp2p_out: ipa-ap-to-modem { 772 qcom,entry-name = "ipa"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 ipa_smp2p_in: ipa-modem-to-ap { 777 qcom,entry-name = "ipa"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 }; 782 783 soc: soc@0 { 784 #address-cells = <2>; 785 #size-cells = <2>; 786 ranges = <0 0 0 0 0x10 0>; 787 dma-ranges = <0 0 0 0 0x10 0>; 788 compatible = "simple-bus"; 789 790 gcc: clock-controller@100000 { 791 compatible = "qcom,gcc-sm6350"; 792 reg = <0x0 0x00100000 0x0 0x1f0000>; 793 #clock-cells = <1>; 794 #reset-cells = <1>; 795 #power-domain-cells = <1>; 796 clock-names = "bi_tcxo", 797 "bi_tcxo_ao", 798 "sleep_clk"; 799 clocks = <&rpmhcc RPMH_CXO_CLK>, 800 <&rpmhcc RPMH_CXO_CLK_A>, 801 <&sleep_clk>; 802 }; 803 804 ipcc: mailbox@408000 { 805 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 806 reg = <0x0 0x00408000 0x0 0x1000>; 807 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 808 interrupt-controller; 809 #interrupt-cells = <3>; 810 #mbox-cells = <2>; 811 }; 812 813 qfprom: qfprom@784000 { 814 compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; 815 reg = <0x0 0x00784000 0x0 0x3000>; 816 #address-cells = <1>; 817 #size-cells = <1>; 818 819 gpu_speed_bin: gpu-speed-bin@2015 { 820 reg = <0x2015 0x1>; 821 bits = <0 8>; 822 }; 823 }; 824 825 rng: rng@793000 { 826 compatible = "qcom,prng-ee"; 827 reg = <0x0 0x00793000 0x0 0x1000>; 828 clocks = <&gcc GCC_PRNG_AHB_CLK>; 829 clock-names = "core"; 830 }; 831 832 sdhc_1: mmc@7c4000 { 833 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 834 reg = <0x0 0x007c4000 0x0 0x1000>, 835 <0x0 0x007c5000 0x0 0x1000>, 836 <0x0 0x007c8000 0x0 0x8000>; 837 reg-names = "hc", "cqhci", "ice"; 838 839 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 841 interrupt-names = "hc_irq", "pwr_irq"; 842 iommus = <&apps_smmu 0x60 0x0>; 843 844 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 845 <&gcc GCC_SDCC1_APPS_CLK>, 846 <&rpmhcc RPMH_CXO_CLK>; 847 clock-names = "iface", "core", "xo"; 848 resets = <&gcc GCC_SDCC1_BCR>; 849 qcom,dll-config = <0x000f642c>; 850 qcom,ddr-config = <0x80040868>; 851 power-domains = <&rpmhpd SM6350_CX>; 852 operating-points-v2 = <&sdhc1_opp_table>; 853 bus-width = <8>; 854 non-removable; 855 supports-cqe; 856 857 status = "disabled"; 858 859 sdhc1_opp_table: opp-table { 860 compatible = "operating-points-v2"; 861 862 opp-19200000 { 863 opp-hz = /bits/ 64 <19200000>; 864 required-opps = <&rpmhpd_opp_min_svs>; 865 }; 866 867 opp-100000000 { 868 opp-hz = /bits/ 64 <100000000>; 869 required-opps = <&rpmhpd_opp_low_svs>; 870 }; 871 872 opp-384000000 { 873 opp-hz = /bits/ 64 <384000000>; 874 required-opps = <&rpmhpd_opp_svs_l1>; 875 }; 876 }; 877 }; 878 879 gpi_dma0: dma-controller@800000 { 880 compatible = "qcom,sm6350-gpi-dma"; 881 reg = <0x0 0x00800000 0x0 0x60000>; 882 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 892 dma-channels = <10>; 893 dma-channel-mask = <0x1f>; 894 iommus = <&apps_smmu 0x56 0x0>; 895 #dma-cells = <3>; 896 status = "disabled"; 897 }; 898 899 qupv3_id_0: geniqup@8c0000 { 900 compatible = "qcom,geni-se-qup"; 901 reg = <0x0 0x008c0000 0x0 0x2000>; 902 clock-names = "m-ahb", "s-ahb"; 903 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 904 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 905 #address-cells = <2>; 906 #size-cells = <2>; 907 iommus = <&apps_smmu 0x43 0x0>; 908 ranges; 909 status = "disabled"; 910 911 i2c0: i2c@880000 { 912 compatible = "qcom,geni-i2c"; 913 reg = <0x0 0x00880000 0x0 0x4000>; 914 clock-names = "se"; 915 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 916 pinctrl-names = "default"; 917 pinctrl-0 = <&qup_i2c0_default>; 918 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 919 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 920 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 921 dma-names = "tx", "rx"; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 925 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 926 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 927 interconnect-names = "qup-core", "qup-config", "qup-memory"; 928 status = "disabled"; 929 }; 930 931 uart1: serial@884000 { 932 compatible = "qcom,geni-uart"; 933 reg = <0x0 0x00884000 0x0 0x4000>; 934 clock-names = "se"; 935 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 938 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 939 power-domains = <&rpmhpd SM6350_CX>; 940 operating-points-v2 = <&qup_opp_table>; 941 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 942 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 943 interconnect-names = "qup-core", "qup-config"; 944 status = "disabled"; 945 }; 946 947 i2c2: i2c@888000 { 948 compatible = "qcom,geni-i2c"; 949 reg = <0x0 0x00888000 0x0 0x4000>; 950 clock-names = "se"; 951 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&qup_i2c2_default>; 954 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 955 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 956 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 957 dma-names = "tx", "rx"; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 961 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 962 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 963 interconnect-names = "qup-core", "qup-config", "qup-memory"; 964 status = "disabled"; 965 }; 966 }; 967 968 gpi_dma1: dma-controller@900000 { 969 compatible = "qcom,sm6350-gpi-dma"; 970 reg = <0x0 0x00900000 0x0 0x60000>; 971 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 981 dma-channels = <10>; 982 dma-channel-mask = <0x3f>; 983 iommus = <&apps_smmu 0x4d6 0x0>; 984 #dma-cells = <3>; 985 status = "disabled"; 986 }; 987 988 qupv3_id_1: geniqup@9c0000 { 989 compatible = "qcom,geni-se-qup"; 990 reg = <0x0 0x009c0000 0x0 0x2000>; 991 clock-names = "m-ahb", "s-ahb"; 992 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 993 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 994 #address-cells = <2>; 995 #size-cells = <2>; 996 iommus = <&apps_smmu 0x4c3 0x0>; 997 ranges; 998 status = "disabled"; 999 1000 i2c6: i2c@980000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0x0 0x00980000 0x0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_i2c6_default>; 1007 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1008 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1009 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1010 dma-names = "tx", "rx"; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1014 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1015 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1016 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1017 status = "disabled"; 1018 }; 1019 1020 i2c7: i2c@984000 { 1021 compatible = "qcom,geni-i2c"; 1022 reg = <0x0 0x00984000 0x0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&qup_i2c7_default>; 1027 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1028 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1029 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1030 dma-names = "tx", "rx"; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1034 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1035 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1036 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1037 status = "disabled"; 1038 }; 1039 1040 i2c8: i2c@988000 { 1041 compatible = "qcom,geni-i2c"; 1042 reg = <0x0 0x00988000 0x0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_i2c8_default>; 1047 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1048 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1049 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1050 dma-names = "tx", "rx"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1054 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1055 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1056 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1057 status = "disabled"; 1058 }; 1059 1060 uart9: serial@98c000 { 1061 compatible = "qcom,geni-debug-uart"; 1062 reg = <0x0 0x0098c000 0x0 0x4000>; 1063 clock-names = "se"; 1064 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1065 pinctrl-names = "default"; 1066 pinctrl-0 = <&qup_uart9_default>; 1067 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1068 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1069 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1070 interconnect-names = "qup-core", "qup-config"; 1071 status = "disabled"; 1072 }; 1073 1074 i2c10: i2c@990000 { 1075 compatible = "qcom,geni-i2c"; 1076 reg = <0x0 0x00990000 0x0 0x4000>; 1077 clock-names = "se"; 1078 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&qup_i2c10_default>; 1081 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1082 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1083 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1084 dma-names = "tx", "rx"; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1088 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1089 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1090 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1091 status = "disabled"; 1092 }; 1093 }; 1094 1095 config_noc: interconnect@1500000 { 1096 compatible = "qcom,sm6350-config-noc"; 1097 reg = <0x0 0x01500000 0x0 0x28000>; 1098 #interconnect-cells = <2>; 1099 qcom,bcm-voters = <&apps_bcm_voter>; 1100 }; 1101 1102 system_noc: interconnect@1620000 { 1103 compatible = "qcom,sm6350-system-noc"; 1104 reg = <0x0 0x01620000 0x0 0x17080>; 1105 #interconnect-cells = <2>; 1106 qcom,bcm-voters = <&apps_bcm_voter>; 1107 1108 clk_virt: interconnect-clk-virt { 1109 compatible = "qcom,sm6350-clk-virt"; 1110 #interconnect-cells = <2>; 1111 qcom,bcm-voters = <&apps_bcm_voter>; 1112 }; 1113 }; 1114 1115 aggre1_noc: interconnect@16e0000 { 1116 compatible = "qcom,sm6350-aggre1-noc"; 1117 reg = <0x0 0x016e0000 0x0 0x15080>; 1118 #interconnect-cells = <2>; 1119 qcom,bcm-voters = <&apps_bcm_voter>; 1120 }; 1121 1122 aggre2_noc: interconnect@1700000 { 1123 compatible = "qcom,sm6350-aggre2-noc"; 1124 reg = <0x0 0x01700000 0x0 0x1f880>; 1125 #interconnect-cells = <2>; 1126 qcom,bcm-voters = <&apps_bcm_voter>; 1127 1128 compute_noc: interconnect-compute-noc { 1129 compatible = "qcom,sm6350-compute-noc"; 1130 #interconnect-cells = <2>; 1131 qcom,bcm-voters = <&apps_bcm_voter>; 1132 }; 1133 }; 1134 1135 mmss_noc: interconnect@1740000 { 1136 compatible = "qcom,sm6350-mmss-noc"; 1137 reg = <0x0 0x01740000 0x0 0x1c100>; 1138 #interconnect-cells = <2>; 1139 qcom,bcm-voters = <&apps_bcm_voter>; 1140 }; 1141 1142 ufs_mem_hc: ufshc@1d84000 { 1143 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 1144 "jedec,ufs-2.0"; 1145 reg = <0x0 0x01d84000 0x0 0x3000>, 1146 <0x0 0x01d90000 0x0 0x8000>; 1147 reg-names = "std", "ice"; 1148 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1149 phys = <&ufs_mem_phy>; 1150 phy-names = "ufsphy"; 1151 lanes-per-direction = <2>; 1152 #reset-cells = <1>; 1153 resets = <&gcc GCC_UFS_PHY_BCR>; 1154 reset-names = "rst"; 1155 1156 power-domains = <&gcc UFS_PHY_GDSC>; 1157 1158 iommus = <&apps_smmu 0x80 0x0>; 1159 1160 clock-names = "core_clk", 1161 "bus_aggr_clk", 1162 "iface_clk", 1163 "core_clk_unipro", 1164 "ref_clk", 1165 "tx_lane0_sync_clk", 1166 "rx_lane0_sync_clk", 1167 "rx_lane1_sync_clk", 1168 "ice_core_clk"; 1169 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1170 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1171 <&gcc GCC_UFS_PHY_AHB_CLK>, 1172 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1173 <&rpmhcc RPMH_QLINK_CLK>, 1174 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1175 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1176 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1177 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1178 1179 operating-points-v2 = <&ufs_opp_table>; 1180 1181 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1182 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 1183 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 1184 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1185 interconnect-names = "ufs-ddr", 1186 "cpu-ufs"; 1187 1188 status = "disabled"; 1189 1190 ufs_opp_table: opp-table { 1191 compatible = "operating-points-v2"; 1192 1193 opp-50000000 { 1194 opp-hz = /bits/ 64 <50000000>, 1195 /bits/ 64 <0>, 1196 /bits/ 64 <0>, 1197 /bits/ 64 <37500000>, 1198 /bits/ 64 <0>, 1199 /bits/ 64 <0>, 1200 /bits/ 64 <0>, 1201 /bits/ 64 <0>, 1202 /bits/ 64 <75000000>; 1203 required-opps = <&rpmhpd_opp_low_svs>; 1204 }; 1205 1206 opp-200000000 { 1207 opp-hz = /bits/ 64 <200000000>, 1208 /bits/ 64 <0>, 1209 /bits/ 64 <0>, 1210 /bits/ 64 <150000000>, 1211 /bits/ 64 <0>, 1212 /bits/ 64 <0>, 1213 /bits/ 64 <0>, 1214 /bits/ 64 <0>, 1215 /bits/ 64 <300000000>; 1216 required-opps = <&rpmhpd_opp_nom>; 1217 }; 1218 }; 1219 }; 1220 1221 ufs_mem_phy: phy@1d87000 { 1222 compatible = "qcom,sm6350-qmp-ufs-phy"; 1223 reg = <0x0 0x01d87000 0x0 0x1000>; 1224 1225 clocks = <&rpmhcc RPMH_CXO_CLK>, 1226 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1227 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1228 clock-names = "ref", 1229 "ref_aux", 1230 "qref"; 1231 1232 power-domains = <&gcc UFS_PHY_GDSC>; 1233 1234 resets = <&ufs_mem_hc 0>; 1235 reset-names = "ufsphy"; 1236 1237 #phy-cells = <0>; 1238 1239 status = "disabled"; 1240 }; 1241 1242 cryptobam: dma-controller@1dc4000 { 1243 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1244 reg = <0x0 0x01dc4000 0x0 0x24000>; 1245 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1246 #dma-cells = <1>; 1247 qcom,ee = <0>; 1248 qcom,controlled-remotely; 1249 num-channels = <16>; 1250 qcom,num-ees = <4>; 1251 iommus = <&apps_smmu 0x426 0x11>, 1252 <&apps_smmu 0x432 0x0>, 1253 <&apps_smmu 0x436 0x11>, 1254 <&apps_smmu 0x438 0x1>, 1255 <&apps_smmu 0x43f 0x0>; 1256 }; 1257 1258 crypto: crypto@1dfa000 { 1259 compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce"; 1260 reg = <0x0 0x01dfa000 0x0 0x6000>; 1261 dmas = <&cryptobam 4>, <&cryptobam 5>; 1262 dma-names = "rx", "tx"; 1263 iommus = <&apps_smmu 0x426 0x11>, 1264 <&apps_smmu 0x432 0x0>, 1265 <&apps_smmu 0x436 0x11>, 1266 <&apps_smmu 0x438 0x1>, 1267 <&apps_smmu 0x43f 0x0>; 1268 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS 1269 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; 1270 interconnect-names = "memory"; 1271 }; 1272 1273 ipa: ipa@1e40000 { 1274 compatible = "qcom,sm6350-ipa"; 1275 1276 iommus = <&apps_smmu 0x440 0x0>, 1277 <&apps_smmu 0x442 0x0>; 1278 reg = <0x0 0x01e40000 0x0 0x8000>, 1279 <0x0 0x01e50000 0x0 0x3000>, 1280 <0x0 0x01e04000 0x0 0x23000>; 1281 reg-names = "ipa-reg", 1282 "ipa-shared", 1283 "gsi"; 1284 1285 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1286 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1287 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1288 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1289 interrupt-names = "ipa", 1290 "gsi", 1291 "ipa-clock-query", 1292 "ipa-setup-ready"; 1293 1294 clocks = <&rpmhcc RPMH_IPA_CLK>; 1295 clock-names = "core"; 1296 1297 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1298 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1299 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1300 interconnect-names = "memory", "imem", "config"; 1301 1302 qcom,smem-states = <&ipa_smp2p_out 0>, 1303 <&ipa_smp2p_out 1>; 1304 qcom,smem-state-names = "ipa-clock-enabled-valid", 1305 "ipa-clock-enabled"; 1306 1307 status = "disabled"; 1308 }; 1309 1310 tcsr_mutex: hwlock@1f40000 { 1311 compatible = "qcom,tcsr-mutex"; 1312 reg = <0x0 0x01f40000 0x0 0x40000>; 1313 #hwlock-cells = <1>; 1314 }; 1315 1316 adsp: remoteproc@3000000 { 1317 compatible = "qcom,sm6350-adsp-pas"; 1318 reg = <0x0 0x03000000 0x0 0x10000>; 1319 1320 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1321 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1322 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1323 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1324 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1325 interrupt-names = "wdog", "fatal", "ready", 1326 "handover", "stop-ack"; 1327 1328 clocks = <&rpmhcc RPMH_CXO_CLK>; 1329 clock-names = "xo"; 1330 1331 power-domains = <&rpmhpd SM6350_LCX>, 1332 <&rpmhpd SM6350_LMX>; 1333 power-domain-names = "lcx", "lmx"; 1334 1335 memory-region = <&pil_adsp_mem>; 1336 1337 qcom,qmp = <&aoss_qmp>; 1338 1339 qcom,smem-states = <&smp2p_adsp_out 0>; 1340 qcom,smem-state-names = "stop"; 1341 1342 status = "disabled"; 1343 1344 glink-edge { 1345 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1346 IPCC_MPROC_SIGNAL_GLINK_QMP 1347 IRQ_TYPE_EDGE_RISING>; 1348 mboxes = <&ipcc IPCC_CLIENT_LPASS 1349 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1350 1351 label = "lpass"; 1352 qcom,remote-pid = <2>; 1353 1354 apr { 1355 compatible = "qcom,apr-v2"; 1356 qcom,glink-channels = "apr_audio_svc"; 1357 qcom,domain = <APR_DOMAIN_ADSP>; 1358 #address-cells = <1>; 1359 #size-cells = <0>; 1360 1361 service@3 { 1362 reg = <APR_SVC_ADSP_CORE>; 1363 compatible = "qcom,q6core"; 1364 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1365 }; 1366 1367 q6afe: service@4 { 1368 compatible = "qcom,q6afe"; 1369 reg = <APR_SVC_AFE>; 1370 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1371 1372 q6afedai: dais { 1373 compatible = "qcom,q6afe-dais"; 1374 #address-cells = <1>; 1375 #size-cells = <0>; 1376 #sound-dai-cells = <1>; 1377 }; 1378 1379 q6afecc: clock-controller { 1380 compatible = "qcom,q6afe-clocks"; 1381 #clock-cells = <2>; 1382 }; 1383 1384 q6usbdai: usbd { 1385 compatible = "qcom,q6usb"; 1386 iommus = <&apps_smmu 0x100f 0x0>; 1387 #sound-dai-cells = <1>; 1388 qcom,usb-audio-intr-idx = /bits/ 16 <2>; 1389 }; 1390 }; 1391 1392 q6asm: service@7 { 1393 compatible = "qcom,q6asm"; 1394 reg = <APR_SVC_ASM>; 1395 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1396 1397 q6asmdai: dais { 1398 compatible = "qcom,q6asm-dais"; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 #sound-dai-cells = <1>; 1402 iommus = <&apps_smmu 0x1001 0x0>; 1403 }; 1404 }; 1405 1406 q6adm: service@8 { 1407 compatible = "qcom,q6adm"; 1408 reg = <APR_SVC_ADM>; 1409 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1410 1411 q6routing: routing { 1412 compatible = "qcom,q6adm-routing"; 1413 #sound-dai-cells = <0>; 1414 }; 1415 }; 1416 }; 1417 1418 fastrpc { 1419 compatible = "qcom,fastrpc"; 1420 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1421 label = "adsp"; 1422 qcom,non-secure-domain; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 1426 compute-cb@3 { 1427 compatible = "qcom,fastrpc-compute-cb"; 1428 reg = <3>; 1429 iommus = <&apps_smmu 0x1003 0x0>; 1430 }; 1431 1432 compute-cb@4 { 1433 compatible = "qcom,fastrpc-compute-cb"; 1434 reg = <4>; 1435 iommus = <&apps_smmu 0x1004 0x0>; 1436 }; 1437 1438 compute-cb@5 { 1439 compatible = "qcom,fastrpc-compute-cb"; 1440 reg = <5>; 1441 iommus = <&apps_smmu 0x1005 0x0>; 1442 qcom,nsessions = <5>; 1443 }; 1444 }; 1445 }; 1446 }; 1447 1448 gpu: gpu@3d00000 { 1449 compatible = "qcom,adreno-619.0", "qcom,adreno"; 1450 reg = <0x0 0x03d00000 0x0 0x40000>, 1451 <0x0 0x03d9e000 0x0 0x1000>; 1452 reg-names = "kgsl_3d0_reg_memory", 1453 "cx_mem"; 1454 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1455 1456 iommus = <&adreno_smmu 0>; 1457 operating-points-v2 = <&gpu_opp_table>; 1458 qcom,gmu = <&gmu>; 1459 nvmem-cells = <&gpu_speed_bin>; 1460 nvmem-cell-names = "speed_bin"; 1461 #cooling-cells = <2>; 1462 1463 status = "disabled"; 1464 1465 gpu_zap_shader: zap-shader { 1466 memory-region = <&pil_gpu_mem>; 1467 }; 1468 1469 gpu_opp_table: opp-table { 1470 compatible = "operating-points-v2"; 1471 1472 opp-850000000 { 1473 opp-hz = /bits/ 64 <850000000>; 1474 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1475 opp-supported-hw = <0x03>; 1476 }; 1477 1478 opp-800000000 { 1479 opp-hz = /bits/ 64 <800000000>; 1480 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1481 opp-supported-hw = <0x07>; 1482 }; 1483 1484 opp-650000000 { 1485 opp-hz = /bits/ 64 <650000000>; 1486 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1487 opp-supported-hw = <0x0f>; 1488 }; 1489 1490 opp-565000000 { 1491 opp-hz = /bits/ 64 <565000000>; 1492 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1493 opp-supported-hw = <0x1f>; 1494 }; 1495 1496 opp-430000000 { 1497 opp-hz = /bits/ 64 <430000000>; 1498 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1499 opp-supported-hw = <0x1f>; 1500 }; 1501 1502 opp-355000000 { 1503 opp-hz = /bits/ 64 <355000000>; 1504 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1505 opp-supported-hw = <0x1f>; 1506 }; 1507 1508 opp-253000000 { 1509 opp-hz = /bits/ 64 <253000000>; 1510 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1511 opp-supported-hw = <0x1f>; 1512 }; 1513 }; 1514 }; 1515 1516 adreno_smmu: iommu@3d40000 { 1517 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1518 reg = <0x0 0x03d40000 0x0 0x10000>; 1519 #iommu-cells = <1>; 1520 #global-interrupts = <2>; 1521 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1531 1532 clocks = <&gpucc GPU_CC_AHB_CLK>, 1533 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1534 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1535 clock-names = "ahb", 1536 "bus", 1537 "iface"; 1538 1539 power-domains = <&gpucc GPU_CX_GDSC>; 1540 }; 1541 1542 gmu: gmu@3d6a000 { 1543 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; 1544 reg = <0x0 0x03d6a000 0x0 0x31000>, 1545 <0x0 0x0b290000 0x0 0x10000>, 1546 <0x0 0x0b490000 0x0 0x10000>; 1547 reg-names = "gmu", 1548 "gmu_pdc", 1549 "gmu_pdc_seq"; 1550 1551 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1552 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1553 interrupt-names = "hfi", 1554 "gmu"; 1555 1556 clocks = <&gpucc GPU_CC_AHB_CLK>, 1557 <&gpucc GPU_CC_CX_GMU_CLK>, 1558 <&gpucc GPU_CC_CXO_CLK>, 1559 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1560 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1561 clock-names = "ahb", 1562 "gmu", 1563 "cxo", 1564 "axi", 1565 "memnoc"; 1566 1567 power-domains = <&gpucc GPU_CX_GDSC>, 1568 <&gpucc GPU_GX_GDSC>; 1569 power-domain-names = "cx", 1570 "gx"; 1571 1572 iommus = <&adreno_smmu 5>; 1573 1574 operating-points-v2 = <&gmu_opp_table>; 1575 1576 gmu_opp_table: opp-table { 1577 compatible = "operating-points-v2"; 1578 1579 opp-200000000 { 1580 opp-hz = /bits/ 64 <200000000>; 1581 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1582 }; 1583 }; 1584 }; 1585 1586 gpucc: clock-controller@3d90000 { 1587 compatible = "qcom,sm6350-gpucc"; 1588 reg = <0x0 0x03d90000 0x0 0x9000>; 1589 clocks = <&rpmhcc RPMH_CXO_CLK>, 1590 <&gcc GCC_GPU_GPLL0_CLK>, 1591 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1592 clock-names = "bi_tcxo", 1593 "gcc_gpu_gpll0_clk_src", 1594 "gcc_gpu_gpll0_div_clk_src"; 1595 #clock-cells = <1>; 1596 #reset-cells = <1>; 1597 #power-domain-cells = <1>; 1598 }; 1599 1600 mpss: remoteproc@4080000 { 1601 compatible = "qcom,sm6350-mpss-pas"; 1602 reg = <0x0 0x04080000 0x0 0x10000>; 1603 1604 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1605 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1606 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1607 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1608 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1609 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1610 interrupt-names = "wdog", "fatal", "ready", "handover", 1611 "stop-ack", "shutdown-ack"; 1612 1613 clocks = <&rpmhcc RPMH_CXO_CLK>; 1614 clock-names = "xo"; 1615 1616 power-domains = <&rpmhpd SM6350_CX>, 1617 <&rpmhpd SM6350_MSS>; 1618 power-domain-names = "cx", "mss"; 1619 1620 memory-region = <&pil_modem_mem>; 1621 1622 qcom,qmp = <&aoss_qmp>; 1623 1624 qcom,smem-states = <&modem_smp2p_out 0>; 1625 qcom,smem-state-names = "stop"; 1626 1627 status = "disabled"; 1628 1629 glink-edge { 1630 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1631 IPCC_MPROC_SIGNAL_GLINK_QMP 1632 IRQ_TYPE_EDGE_RISING>; 1633 mboxes = <&ipcc IPCC_CLIENT_MPSS 1634 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1635 label = "modem"; 1636 qcom,remote-pid = <1>; 1637 }; 1638 }; 1639 1640 cdsp: remoteproc@8300000 { 1641 compatible = "qcom,sm6350-cdsp-pas"; 1642 reg = <0x0 0x08300000 0x0 0x10000>; 1643 1644 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1645 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1646 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1647 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1648 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1649 interrupt-names = "wdog", "fatal", "ready", 1650 "handover", "stop-ack"; 1651 1652 clocks = <&rpmhcc RPMH_CXO_CLK>; 1653 clock-names = "xo"; 1654 1655 power-domains = <&rpmhpd SM6350_CX>, 1656 <&rpmhpd SM6350_MX>; 1657 power-domain-names = "cx", "mx"; 1658 1659 memory-region = <&pil_cdsp_mem>; 1660 1661 qcom,qmp = <&aoss_qmp>; 1662 1663 qcom,smem-states = <&smp2p_cdsp_out 0>; 1664 qcom,smem-state-names = "stop"; 1665 1666 status = "disabled"; 1667 1668 glink-edge { 1669 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1670 IPCC_MPROC_SIGNAL_GLINK_QMP 1671 IRQ_TYPE_EDGE_RISING>; 1672 mboxes = <&ipcc IPCC_CLIENT_CDSP 1673 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1674 1675 label = "cdsp"; 1676 qcom,remote-pid = <5>; 1677 1678 fastrpc { 1679 compatible = "qcom,fastrpc"; 1680 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1681 label = "cdsp"; 1682 qcom,non-secure-domain; 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 1686 compute-cb@1 { 1687 compatible = "qcom,fastrpc-compute-cb"; 1688 reg = <1>; 1689 iommus = <&apps_smmu 0x1401 0x20>; 1690 }; 1691 1692 compute-cb@2 { 1693 compatible = "qcom,fastrpc-compute-cb"; 1694 reg = <2>; 1695 iommus = <&apps_smmu 0x1402 0x20>; 1696 }; 1697 1698 compute-cb@3 { 1699 compatible = "qcom,fastrpc-compute-cb"; 1700 reg = <3>; 1701 iommus = <&apps_smmu 0x1403 0x20>; 1702 }; 1703 1704 compute-cb@4 { 1705 compatible = "qcom,fastrpc-compute-cb"; 1706 reg = <4>; 1707 iommus = <&apps_smmu 0x1404 0x20>; 1708 }; 1709 1710 compute-cb@5 { 1711 compatible = "qcom,fastrpc-compute-cb"; 1712 reg = <5>; 1713 iommus = <&apps_smmu 0x1405 0x20>; 1714 }; 1715 1716 compute-cb@6 { 1717 compatible = "qcom,fastrpc-compute-cb"; 1718 reg = <6>; 1719 iommus = <&apps_smmu 0x1406 0x20>; 1720 }; 1721 1722 compute-cb@7 { 1723 compatible = "qcom,fastrpc-compute-cb"; 1724 reg = <7>; 1725 iommus = <&apps_smmu 0x1407 0x20>; 1726 }; 1727 1728 compute-cb@8 { 1729 compatible = "qcom,fastrpc-compute-cb"; 1730 reg = <8>; 1731 iommus = <&apps_smmu 0x1408 0x20>; 1732 }; 1733 1734 /* note: secure cb9 in downstream */ 1735 }; 1736 }; 1737 }; 1738 1739 sdhc_2: mmc@8804000 { 1740 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1741 reg = <0x0 0x08804000 0x0 0x1000>; 1742 1743 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1744 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1745 interrupt-names = "hc_irq", "pwr_irq"; 1746 iommus = <&apps_smmu 0x560 0x0>; 1747 1748 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1749 <&gcc GCC_SDCC2_APPS_CLK>, 1750 <&rpmhcc RPMH_CXO_CLK>; 1751 clock-names = "iface", "core", "xo"; 1752 resets = <&gcc GCC_SDCC2_BCR>; 1753 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1754 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1755 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1756 1757 pinctrl-0 = <&sdc2_on_state>; 1758 pinctrl-1 = <&sdc2_off_state>; 1759 pinctrl-names = "default", "sleep"; 1760 1761 qcom,dll-config = <0x0007642c>; 1762 qcom,ddr-config = <0x80040868>; 1763 power-domains = <&rpmhpd SM6350_CX>; 1764 operating-points-v2 = <&sdhc2_opp_table>; 1765 bus-width = <4>; 1766 1767 status = "disabled"; 1768 1769 sdhc2_opp_table: opp-table { 1770 compatible = "operating-points-v2"; 1771 1772 opp-100000000 { 1773 opp-hz = /bits/ 64 <100000000>; 1774 required-opps = <&rpmhpd_opp_svs_l1>; 1775 opp-peak-kBps = <790000 131000>; 1776 opp-avg-kBps = <50000 50000>; 1777 }; 1778 1779 opp-202000000 { 1780 opp-hz = /bits/ 64 <202000000>; 1781 required-opps = <&rpmhpd_opp_nom>; 1782 opp-peak-kBps = <3190000 294000>; 1783 opp-avg-kBps = <261438 300000>; 1784 }; 1785 }; 1786 }; 1787 1788 usb_1_hsphy: phy@88e3000 { 1789 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1790 reg = <0x0 0x088e3000 0x0 0x400>; 1791 status = "disabled"; 1792 #phy-cells = <0>; 1793 1794 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1795 clock-names = "cfg_ahb", "ref"; 1796 1797 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1798 }; 1799 1800 refgen: regulator@88e7000 { 1801 compatible = "qcom,sm6350-refgen-regulator", 1802 "qcom,sm8250-refgen-regulator"; 1803 reg = <0x0 0x088e7000 0x0 0x84>; 1804 }; 1805 1806 usb_1_qmpphy: phy@88e8000 { 1807 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1808 reg = <0x0 0x088e8000 0x0 0x3000>; 1809 1810 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1811 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1812 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1813 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1814 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1815 1816 power-domains = <&gcc USB30_PRIM_GDSC>; 1817 1818 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1819 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1820 reset-names = "phy", "common"; 1821 1822 orientation-switch; 1823 1824 #clock-cells = <1>; 1825 #phy-cells = <1>; 1826 1827 status = "disabled"; 1828 1829 ports { 1830 #address-cells = <1>; 1831 #size-cells = <0>; 1832 1833 port@0 { 1834 reg = <0>; 1835 1836 usb_1_qmpphy_out: endpoint { 1837 }; 1838 }; 1839 1840 port@1 { 1841 reg = <1>; 1842 1843 usb_1_qmpphy_usb_ss_in: endpoint { 1844 remote-endpoint = <&usb_1_dwc3_ss_out>; 1845 }; 1846 }; 1847 1848 port@2 { 1849 reg = <2>; 1850 1851 usb_1_qmpphy_dp_in: endpoint { 1852 }; 1853 }; 1854 }; 1855 }; 1856 1857 dc_noc: interconnect@9160000 { 1858 compatible = "qcom,sm6350-dc-noc"; 1859 reg = <0x0 0x09160000 0x0 0x3200>; 1860 #interconnect-cells = <2>; 1861 qcom,bcm-voters = <&apps_bcm_voter>; 1862 }; 1863 1864 system-cache-controller@9200000 { 1865 compatible = "qcom,sm6350-llcc"; 1866 reg = <0x0 0x09200000 0x0 0x50000>, <0x0 0x09600000 0x0 0x50000>; 1867 reg-names = "llcc0_base", "llcc_broadcast_base"; 1868 }; 1869 1870 gem_noc: interconnect@9680000 { 1871 compatible = "qcom,sm6350-gem-noc"; 1872 reg = <0x0 0x09680000 0x0 0x3e200>; 1873 #interconnect-cells = <2>; 1874 qcom,bcm-voters = <&apps_bcm_voter>; 1875 }; 1876 1877 npu_noc: interconnect@9990000 { 1878 compatible = "qcom,sm6350-npu-noc"; 1879 reg = <0x0 0x09990000 0x0 0x1600>; 1880 #interconnect-cells = <2>; 1881 qcom,bcm-voters = <&apps_bcm_voter>; 1882 }; 1883 1884 pmu@90b6300 { 1885 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon"; 1886 reg = <0x0 0x090b6300 0x0 0x600>; 1887 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 1888 1889 operating-points-v2 = <&llcc_bwmon_opp_table>; 1890 interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 1891 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1892 1893 llcc_bwmon_opp_table: opp-table { 1894 compatible = "operating-points-v2"; 1895 1896 opp-0 { 1897 opp-peak-kBps = <2288000>; 1898 }; 1899 1900 opp-1 { 1901 opp-peak-kBps = <4577000>; 1902 }; 1903 1904 opp-2 { 1905 opp-peak-kBps = <7110000>; 1906 }; 1907 1908 opp-3 { 1909 opp-peak-kBps = <9155000>; 1910 }; 1911 1912 opp-4 { 1913 opp-peak-kBps = <12298000>; 1914 }; 1915 1916 opp-5 { 1917 opp-peak-kBps = <14236000>; 1918 }; 1919 1920 }; 1921 }; 1922 1923 pmu@90cd000 { 1924 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; 1925 reg = <0x0 0x090cd000 0x0 0x1000>; 1926 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1927 1928 operating-points-v2 = <&cpu_bwmon_opp_table>; 1929 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 1930 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1931 1932 cpu_bwmon_opp_table: opp-table { 1933 compatible = "operating-points-v2"; 1934 1935 opp-0 { 1936 opp-peak-kBps = <762000>; 1937 }; 1938 1939 opp-1 { 1940 opp-peak-kBps = <1144000>; 1941 }; 1942 1943 opp-2 { 1944 opp-peak-kBps = <1720000>; 1945 }; 1946 1947 opp-3 { 1948 opp-peak-kBps = <2086000>; 1949 }; 1950 1951 opp-4 { 1952 opp-peak-kBps = <2597000>; 1953 }; 1954 1955 opp-5 { 1956 opp-peak-kBps = <2929000>; 1957 }; 1958 1959 opp-6 { 1960 opp-peak-kBps = <3879000>; 1961 }; 1962 1963 opp-7 { 1964 opp-peak-kBps = <5161000>; 1965 }; 1966 1967 opp-8 { 1968 opp-peak-kBps = <5931000>; 1969 }; 1970 1971 opp-9 { 1972 opp-peak-kBps = <6881000>; 1973 }; 1974 1975 opp-10 { 1976 opp-peak-kBps = <7980000>; 1977 }; 1978 }; 1979 }; 1980 1981 usb_1: usb@a6f8800 { 1982 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1983 reg = <0x0 0x0a6f8800 0x0 0x400>; 1984 status = "disabled"; 1985 #address-cells = <2>; 1986 #size-cells = <2>; 1987 ranges; 1988 1989 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1990 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1991 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1992 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1993 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1994 clock-names = "cfg_noc", 1995 "core", 1996 "iface", 1997 "sleep", 1998 "mock_utmi"; 1999 2000 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2001 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2002 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2003 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2004 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2005 interrupt-names = "pwr_event", 2006 "hs_phy_irq", 2007 "dp_hs_phy_irq", 2008 "dm_hs_phy_irq", 2009 "ss_phy_irq"; 2010 2011 power-domains = <&gcc USB30_PRIM_GDSC>; 2012 2013 resets = <&gcc GCC_USB30_PRIM_BCR>; 2014 2015 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 2016 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 2017 interconnect-names = "usb-ddr", "apps-usb"; 2018 2019 usb_1_dwc3: usb@a600000 { 2020 compatible = "snps,dwc3"; 2021 reg = <0x0 0x0a600000 0x0 0xcd00>; 2022 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2023 iommus = <&apps_smmu 0x540 0x0>; 2024 num-hc-interrupters = /bits/ 16 <3>; 2025 snps,dis_u2_susphy_quirk; 2026 snps,dis_enblslpm_quirk; 2027 snps,has-lpm-erratum; 2028 snps,hird-threshold = /bits/ 8 <0x10>; 2029 snps,parkmode-disable-ss-quirk; 2030 snps,dis-u1-entry-quirk; 2031 snps,dis-u2-entry-quirk; 2032 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2033 phy-names = "usb2-phy", "usb3-phy"; 2034 usb-role-switch; 2035 2036 ports { 2037 #address-cells = <1>; 2038 #size-cells = <0>; 2039 2040 port@0 { 2041 reg = <0>; 2042 2043 usb_1_dwc3_hs_out: endpoint { 2044 }; 2045 }; 2046 2047 port@1 { 2048 reg = <1>; 2049 2050 usb_1_dwc3_ss_out: endpoint { 2051 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 2052 }; 2053 }; 2054 }; 2055 }; 2056 }; 2057 2058 videocc: clock-controller@aaf0000 { 2059 compatible = "qcom,sm6350-videocc"; 2060 reg = <0x0 0x0aaf0000 0x0 0x10000>; 2061 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 2062 <&rpmhcc RPMH_CXO_CLK>, 2063 <&sleep_clk>; 2064 clock-names = "iface", 2065 "bi_tcxo", 2066 "sleep_clk"; 2067 #clock-cells = <1>; 2068 #reset-cells = <1>; 2069 #power-domain-cells = <1>; 2070 }; 2071 2072 cci0: cci@ac4a000 { 2073 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 2074 reg = <0x0 0x0ac4a000 0x0 0x1000>; 2075 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 2076 power-domains = <&camcc TITAN_TOP_GDSC>; 2077 2078 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2079 <&camcc CAMCC_SOC_AHB_CLK>, 2080 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 2081 <&camcc CAMCC_CPAS_AHB_CLK>, 2082 <&camcc CAMCC_CCI_0_CLK>, 2083 <&camcc CAMCC_CCI_0_CLK_SRC>; 2084 clock-names = "camnoc_axi", 2085 "soc_ahb", 2086 "slow_ahb_src", 2087 "cpas_ahb", 2088 "cci", 2089 "cci_src"; 2090 2091 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2092 <&camcc CAMCC_CCI_0_CLK>; 2093 assigned-clock-rates = <80000000>, <37500000>; 2094 2095 pinctrl-0 = <&cci0_default &cci1_default>; 2096 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2097 pinctrl-names = "default", "sleep"; 2098 2099 #address-cells = <1>; 2100 #size-cells = <0>; 2101 2102 status = "disabled"; 2103 2104 cci0_i2c0: i2c-bus@0 { 2105 reg = <0>; 2106 clock-frequency = <1000000>; 2107 #address-cells = <1>; 2108 #size-cells = <0>; 2109 }; 2110 2111 cci0_i2c1: i2c-bus@1 { 2112 reg = <1>; 2113 clock-frequency = <1000000>; 2114 #address-cells = <1>; 2115 #size-cells = <0>; 2116 }; 2117 }; 2118 2119 cci1: cci@ac4b000 { 2120 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 2121 reg = <0x0 0x0ac4b000 0x0 0x1000>; 2122 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 2123 power-domains = <&camcc TITAN_TOP_GDSC>; 2124 2125 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2126 <&camcc CAMCC_SOC_AHB_CLK>, 2127 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 2128 <&camcc CAMCC_CPAS_AHB_CLK>, 2129 <&camcc CAMCC_CCI_1_CLK>, 2130 <&camcc CAMCC_CCI_1_CLK_SRC>; 2131 clock-names = "camnoc_axi", 2132 "soc_ahb", 2133 "slow_ahb_src", 2134 "cpas_ahb", 2135 "cci", 2136 "cci_src"; 2137 2138 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2139 <&camcc CAMCC_CCI_1_CLK>; 2140 assigned-clock-rates = <80000000>, <37500000>; 2141 2142 pinctrl-0 = <&cci2_default>; 2143 pinctrl-1 = <&cci2_sleep>; 2144 pinctrl-names = "default", "sleep"; 2145 2146 #address-cells = <1>; 2147 #size-cells = <0>; 2148 2149 status = "disabled"; 2150 2151 cci1_i2c0: i2c-bus@0 { 2152 reg = <0>; 2153 clock-frequency = <1000000>; 2154 #address-cells = <1>; 2155 #size-cells = <0>; 2156 }; 2157 2158 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 2159 }; 2160 2161 camcc: clock-controller@ad00000 { 2162 compatible = "qcom,sm6350-camcc"; 2163 reg = <0x0 0x0ad00000 0x0 0x16000>; 2164 clocks = <&rpmhcc RPMH_CXO_CLK>; 2165 #clock-cells = <1>; 2166 #reset-cells = <1>; 2167 #power-domain-cells = <1>; 2168 }; 2169 2170 mdss: display-subsystem@ae00000 { 2171 compatible = "qcom,sm6350-mdss"; 2172 reg = <0x0 0x0ae00000 0x0 0x1000>; 2173 reg-names = "mdss"; 2174 2175 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2176 interrupt-controller; 2177 #interrupt-cells = <1>; 2178 2179 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS 2180 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2181 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 2182 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2183 interconnect-names = "mdp0-mem", 2184 "cpu-cfg"; 2185 2186 clocks = <&gcc GCC_DISP_AHB_CLK>, 2187 <&gcc GCC_DISP_AXI_CLK>, 2188 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2189 clock-names = "iface", 2190 "bus", 2191 "core"; 2192 2193 power-domains = <&dispcc MDSS_GDSC>; 2194 iommus = <&apps_smmu 0x800 0x2>; 2195 2196 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2197 2198 #address-cells = <2>; 2199 #size-cells = <2>; 2200 ranges; 2201 2202 status = "disabled"; 2203 2204 mdss_mdp: display-controller@ae01000 { 2205 compatible = "qcom,sm6350-dpu"; 2206 reg = <0x0 0x0ae01000 0x0 0x8f000>, 2207 <0x0 0x0aeb0000 0x0 0x2008>; 2208 reg-names = "mdp", "vbif"; 2209 2210 interrupt-parent = <&mdss>; 2211 interrupts = <0>; 2212 2213 clocks = <&gcc GCC_DISP_AXI_CLK>, 2214 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2215 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2216 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2217 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2218 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2219 clock-names = "bus", 2220 "iface", 2221 "rot", 2222 "lut", 2223 "core", 2224 "vsync"; 2225 2226 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2227 assigned-clock-rates = <19200000>; 2228 2229 operating-points-v2 = <&mdp_opp_table>; 2230 power-domains = <&rpmhpd SM6350_CX>; 2231 2232 ports { 2233 #address-cells = <1>; 2234 #size-cells = <0>; 2235 2236 port@0 { 2237 reg = <0>; 2238 2239 dpu_intf1_out: endpoint { 2240 remote-endpoint = <&mdss_dsi0_in>; 2241 }; 2242 }; 2243 2244 port@2 { 2245 reg = <2>; 2246 2247 dpu_intf0_out: endpoint { 2248 remote-endpoint = <&mdss_dp_in>; 2249 }; 2250 }; 2251 }; 2252 2253 mdp_opp_table: opp-table { 2254 compatible = "operating-points-v2"; 2255 2256 opp-19200000 { 2257 opp-hz = /bits/ 64 <19200000>; 2258 required-opps = <&rpmhpd_opp_min_svs>; 2259 }; 2260 2261 opp-200000000 { 2262 opp-hz = /bits/ 64 <200000000>; 2263 required-opps = <&rpmhpd_opp_low_svs>; 2264 }; 2265 2266 opp-300000000 { 2267 opp-hz = /bits/ 64 <300000000>; 2268 required-opps = <&rpmhpd_opp_svs>; 2269 }; 2270 2271 opp-373333333 { 2272 opp-hz = /bits/ 64 <373333333>; 2273 required-opps = <&rpmhpd_opp_svs_l1>; 2274 }; 2275 2276 opp-448000000 { 2277 opp-hz = /bits/ 64 <448000000>; 2278 required-opps = <&rpmhpd_opp_nom>; 2279 }; 2280 2281 opp-560000000 { 2282 opp-hz = /bits/ 64 <560000000>; 2283 required-opps = <&rpmhpd_opp_turbo>; 2284 }; 2285 }; 2286 }; 2287 2288 mdss_dp: displayport-controller@ae90000 { 2289 compatible = "qcom,sm6350-dp", "qcom,sc7180-dp"; 2290 reg = <0x0 0xae90000 0x0 0x200>, 2291 <0x0 0xae90200 0x0 0x200>, 2292 <0x0 0xae90400 0x0 0x600>, 2293 <0x0 0xae91000 0x0 0x400>, 2294 <0x0 0xae91400 0x0 0x400>; 2295 interrupt-parent = <&mdss>; 2296 interrupts = <12>; 2297 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2298 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2299 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2300 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2301 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2302 clock-names = "core_iface", 2303 "core_aux", 2304 "ctrl_link", 2305 "ctrl_link_iface", 2306 "stream_pixel"; 2307 2308 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2309 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2310 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2311 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2312 2313 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2314 phy-names = "dp"; 2315 2316 #sound-dai-cells = <0>; 2317 2318 operating-points-v2 = <&dp_opp_table>; 2319 power-domains = <&rpmhpd SM6350_CX>; 2320 2321 status = "disabled"; 2322 2323 ports { 2324 #address-cells = <1>; 2325 #size-cells = <0>; 2326 2327 port@0 { 2328 reg = <0>; 2329 2330 mdss_dp_in: endpoint { 2331 remote-endpoint = <&dpu_intf0_out>; 2332 }; 2333 }; 2334 2335 port@1 { 2336 reg = <1>; 2337 2338 mdss_dp_out: endpoint { 2339 }; 2340 }; 2341 }; 2342 2343 dp_opp_table: opp-table { 2344 compatible = "operating-points-v2"; 2345 2346 opp-160000000 { 2347 opp-hz = /bits/ 64 <160000000>; 2348 required-opps = <&rpmhpd_opp_low_svs>; 2349 }; 2350 2351 opp-270000000 { 2352 opp-hz = /bits/ 64 <270000000>; 2353 required-opps = <&rpmhpd_opp_svs>; 2354 }; 2355 2356 opp-540000000 { 2357 opp-hz = /bits/ 64 <540000000>; 2358 required-opps = <&rpmhpd_opp_svs_l1>; 2359 }; 2360 2361 opp-810000000 { 2362 opp-hz = /bits/ 64 <810000000>; 2363 required-opps = <&rpmhpd_opp_nom>; 2364 }; 2365 }; 2366 }; 2367 2368 mdss_dsi0: dsi@ae94000 { 2369 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2370 reg = <0x0 0x0ae94000 0x0 0x400>; 2371 reg-names = "dsi_ctrl"; 2372 2373 interrupt-parent = <&mdss>; 2374 interrupts = <4>; 2375 2376 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2377 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2378 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2379 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2380 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2381 <&gcc GCC_DISP_AXI_CLK>; 2382 clock-names = "byte", 2383 "byte_intf", 2384 "pixel", 2385 "core", 2386 "iface", 2387 "bus"; 2388 2389 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2390 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2391 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2392 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2393 2394 operating-points-v2 = <&mdss_dsi_opp_table>; 2395 power-domains = <&rpmhpd SM6350_MX>; 2396 2397 phys = <&mdss_dsi0_phy>; 2398 phy-names = "dsi"; 2399 2400 refgen-supply = <&refgen>; 2401 2402 #address-cells = <1>; 2403 #size-cells = <0>; 2404 2405 status = "disabled"; 2406 2407 ports { 2408 #address-cells = <1>; 2409 #size-cells = <0>; 2410 2411 port@0 { 2412 reg = <0>; 2413 2414 mdss_dsi0_in: endpoint { 2415 remote-endpoint = <&dpu_intf1_out>; 2416 }; 2417 }; 2418 2419 port@1 { 2420 reg = <1>; 2421 2422 mdss_dsi0_out: endpoint { 2423 }; 2424 }; 2425 }; 2426 2427 mdss_dsi_opp_table: opp-table { 2428 compatible = "operating-points-v2"; 2429 2430 opp-187500000 { 2431 opp-hz = /bits/ 64 <187500000>; 2432 required-opps = <&rpmhpd_opp_low_svs>; 2433 }; 2434 2435 opp-300000000 { 2436 opp-hz = /bits/ 64 <300000000>; 2437 required-opps = <&rpmhpd_opp_svs>; 2438 }; 2439 2440 opp-358000000 { 2441 opp-hz = /bits/ 64 <358000000>; 2442 required-opps = <&rpmhpd_opp_svs_l1>; 2443 }; 2444 }; 2445 }; 2446 2447 mdss_dsi0_phy: phy@ae94400 { 2448 compatible = "qcom,dsi-phy-10nm"; 2449 reg = <0x0 0x0ae94400 0x0 0x200>, 2450 <0x0 0x0ae94600 0x0 0x280>, 2451 <0x0 0x0ae94a00 0x0 0x1e0>; 2452 reg-names = "dsi_phy", 2453 "dsi_phy_lane", 2454 "dsi_pll"; 2455 2456 #clock-cells = <1>; 2457 #phy-cells = <0>; 2458 2459 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2460 <&rpmhcc RPMH_CXO_CLK>; 2461 clock-names = "iface", "ref"; 2462 2463 status = "disabled"; 2464 }; 2465 }; 2466 2467 dispcc: clock-controller@af00000 { 2468 compatible = "qcom,sm6350-dispcc"; 2469 reg = <0x0 0x0af00000 0x0 0x20000>; 2470 clocks = <&rpmhcc RPMH_CXO_CLK>, 2471 <&gcc GCC_DISP_GPLL0_CLK>, 2472 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2473 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2474 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2475 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2476 clock-names = "bi_tcxo", 2477 "gcc_disp_gpll0_clk", 2478 "dsi0_phy_pll_out_byteclk", 2479 "dsi0_phy_pll_out_dsiclk", 2480 "dp_phy_pll_link_clk", 2481 "dp_phy_pll_vco_div_clk"; 2482 #clock-cells = <1>; 2483 #reset-cells = <1>; 2484 #power-domain-cells = <1>; 2485 }; 2486 2487 pdc: interrupt-controller@b220000 { 2488 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 2489 reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x17c000f0 0x0 0x64>; 2490 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2491 <125 63 1>, <126 655 12>, <138 139 15>; 2492 #interrupt-cells = <2>; 2493 interrupt-parent = <&intc>; 2494 interrupt-controller; 2495 }; 2496 2497 tsens0: thermal-sensor@c263000 { 2498 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2499 reg = <0x0 0x0c263000 0x0 0x1ff>, /* TM */ 2500 <0x0 0x0c222000 0x0 0x8>; /* SROT */ 2501 #qcom,sensors = <16>; 2502 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2503 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2504 interrupt-names = "uplow", "critical"; 2505 #thermal-sensor-cells = <1>; 2506 }; 2507 2508 tsens1: thermal-sensor@c265000 { 2509 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2510 reg = <0x0 0x0c265000 0x0 0x1ff>, /* TM */ 2511 <0x0 0x0c223000 0x0 0x8>; /* SROT */ 2512 #qcom,sensors = <16>; 2513 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2514 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2515 interrupt-names = "uplow", "critical"; 2516 #thermal-sensor-cells = <1>; 2517 }; 2518 2519 aoss_qmp: power-management@c300000 { 2520 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 2521 reg = <0x0 0x0c300000 0x0 0x1000>; 2522 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2523 IRQ_TYPE_EDGE_RISING>; 2524 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2525 2526 #clock-cells = <0>; 2527 }; 2528 2529 sram@c3f0000 { 2530 compatible = "qcom,rpmh-stats"; 2531 reg = <0x0 0x0c3f0000 0x0 0x400>; 2532 }; 2533 2534 spmi_bus: spmi@c440000 { 2535 compatible = "qcom,spmi-pmic-arb"; 2536 reg = <0x0 0x0c440000 0x0 0x1100>, 2537 <0x0 0x0c600000 0x0 0x2000000>, 2538 <0x0 0x0e600000 0x0 0x100000>, 2539 <0x0 0x0e700000 0x0 0xa0000>, 2540 <0x0 0x0c40a000 0x0 0x26000>; 2541 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2542 interrupt-names = "periph_irq"; 2543 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2544 qcom,ee = <0>; 2545 qcom,channel = <0>; 2546 #address-cells = <2>; 2547 #size-cells = <0>; 2548 interrupt-controller; 2549 #interrupt-cells = <4>; 2550 }; 2551 2552 tlmm: pinctrl@f100000 { 2553 compatible = "qcom,sm6350-tlmm"; 2554 reg = <0x0 0x0f100000 0x0 0x300000>; 2555 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 2556 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 2557 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 2558 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 2559 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 2560 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 2561 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 2562 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 2563 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 2564 gpio-controller; 2565 #gpio-cells = <2>; 2566 interrupt-controller; 2567 #interrupt-cells = <2>; 2568 gpio-ranges = <&tlmm 0 0 157>; 2569 wakeup-parent = <&pdc>; 2570 2571 cci0_default: cci0-default-state { 2572 pins = "gpio39", "gpio40"; 2573 function = "cci_i2c"; 2574 drive-strength = <2>; 2575 bias-pull-up; 2576 }; 2577 2578 cci0_sleep: cci0-sleep-state { 2579 pins = "gpio39", "gpio40"; 2580 function = "cci_i2c"; 2581 drive-strength = <2>; 2582 bias-pull-down; 2583 }; 2584 2585 cci1_default: cci1-default-state { 2586 pins = "gpio41", "gpio42"; 2587 function = "cci_i2c"; 2588 drive-strength = <2>; 2589 bias-pull-up; 2590 }; 2591 2592 cci1_sleep: cci1-sleep-state { 2593 pins = "gpio41", "gpio42"; 2594 function = "cci_i2c"; 2595 drive-strength = <2>; 2596 bias-pull-down; 2597 }; 2598 2599 cci2_default: cci2-default-state { 2600 pins = "gpio43", "gpio44"; 2601 function = "cci_i2c"; 2602 drive-strength = <2>; 2603 bias-pull-up; 2604 }; 2605 2606 cci2_sleep: cci2-sleep-state { 2607 pins = "gpio43", "gpio44"; 2608 function = "cci_i2c"; 2609 drive-strength = <2>; 2610 bias-pull-down; 2611 }; 2612 2613 sdc2_off_state: sdc2-off-state { 2614 clk-pins { 2615 pins = "sdc2_clk"; 2616 drive-strength = <2>; 2617 bias-disable; 2618 }; 2619 2620 cmd-pins { 2621 pins = "sdc2_cmd"; 2622 drive-strength = <2>; 2623 bias-pull-up; 2624 }; 2625 2626 data-pins { 2627 pins = "sdc2_data"; 2628 drive-strength = <2>; 2629 bias-pull-up; 2630 }; 2631 }; 2632 2633 sdc2_on_state: sdc2-on-state { 2634 clk-pins { 2635 pins = "sdc2_clk"; 2636 drive-strength = <16>; 2637 bias-disable; 2638 }; 2639 2640 cmd-pins { 2641 pins = "sdc2_cmd"; 2642 drive-strength = <10>; 2643 bias-pull-up; 2644 }; 2645 2646 data-pins { 2647 pins = "sdc2_data"; 2648 drive-strength = <10>; 2649 bias-pull-up; 2650 }; 2651 }; 2652 2653 qup_uart9_default: qup-uart9-default-state { 2654 pins = "gpio25", "gpio26"; 2655 function = "qup13_f2"; 2656 drive-strength = <2>; 2657 bias-disable; 2658 }; 2659 2660 qup_i2c0_default: qup-i2c0-default-state { 2661 pins = "gpio0", "gpio1"; 2662 function = "qup00"; 2663 drive-strength = <2>; 2664 bias-pull-up; 2665 }; 2666 2667 qup_i2c2_default: qup-i2c2-default-state { 2668 pins = "gpio45", "gpio46"; 2669 function = "qup02"; 2670 drive-strength = <2>; 2671 bias-pull-up; 2672 }; 2673 2674 qup_i2c6_default: qup-i2c6-default-state { 2675 pins = "gpio13", "gpio14"; 2676 function = "qup10"; 2677 drive-strength = <2>; 2678 bias-pull-up; 2679 }; 2680 2681 qup_i2c7_default: qup-i2c7-default-state { 2682 pins = "gpio27", "gpio28"; 2683 function = "qup11"; 2684 drive-strength = <2>; 2685 bias-pull-up; 2686 }; 2687 2688 qup_i2c8_default: qup-i2c8-default-state { 2689 pins = "gpio19", "gpio20"; 2690 function = "qup12"; 2691 drive-strength = <2>; 2692 bias-pull-up; 2693 }; 2694 2695 qup_i2c10_default: qup-i2c10-default-state { 2696 pins = "gpio4", "gpio5"; 2697 function = "qup14"; 2698 drive-strength = <2>; 2699 bias-pull-up; 2700 }; 2701 2702 qup_uart1_cts: qup-uart1-cts-default-state { 2703 pins = "gpio61"; 2704 function = "qup01"; 2705 drive-strength = <2>; 2706 bias-disable; 2707 }; 2708 2709 qup_uart1_rts: qup-uart1-rts-default-state { 2710 pins = "gpio62"; 2711 function = "qup01"; 2712 drive-strength = <2>; 2713 bias-pull-down; 2714 }; 2715 2716 qup_uart1_rx: qup-uart1-rx-default-state { 2717 pins = "gpio64"; 2718 function = "qup01"; 2719 drive-strength = <2>; 2720 bias-disable; 2721 }; 2722 2723 qup_uart1_tx: qup-uart1-tx-default-state { 2724 pins = "gpio63"; 2725 function = "qup01"; 2726 drive-strength = <2>; 2727 bias-pull-up; 2728 }; 2729 }; 2730 2731 apps_smmu: iommu@15000000 { 2732 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 2733 reg = <0x0 0x15000000 0x0 0x100000>; 2734 #iommu-cells = <2>; 2735 #global-interrupts = <1>; 2736 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2737 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2738 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2739 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2740 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2741 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2742 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2743 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2744 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2745 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2746 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2747 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2748 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2749 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2750 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2751 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2752 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2753 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2754 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2755 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2756 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2757 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2758 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2759 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2760 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2761 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2762 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2763 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2764 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2765 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2766 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2767 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2768 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2769 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2770 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2771 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2772 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2773 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2774 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2775 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2776 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2777 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2778 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2779 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2780 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2781 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2782 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2783 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2784 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2785 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2786 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2787 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2788 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2789 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2790 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2791 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2792 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2793 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2794 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2795 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2796 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2797 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2798 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2799 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2800 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2801 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2802 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2803 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2804 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2805 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2806 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2807 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2808 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2809 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2810 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2811 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2812 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2813 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2814 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2815 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2816 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 2817 dma-coherent; 2818 }; 2819 2820 intc: interrupt-controller@17a00000 { 2821 compatible = "arm,gic-v3"; 2822 #interrupt-cells = <3>; 2823 interrupt-controller; 2824 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2825 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2826 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 2827 }; 2828 2829 watchdog@17c10000 { 2830 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 2831 reg = <0x0 0x17c10000 0x0 0x1000>; 2832 clocks = <&sleep_clk>; 2833 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 2834 }; 2835 2836 timer@17c20000 { 2837 compatible = "arm,armv7-timer-mem"; 2838 reg = <0x0 0x17c20000 0x0 0x1000>; 2839 clock-frequency = <19200000>; 2840 #address-cells = <1>; 2841 #size-cells = <1>; 2842 ranges = <0 0 0 0x20000000>; 2843 2844 frame@17c21000 { 2845 frame-number = <0>; 2846 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2847 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2848 reg = <0x17c21000 0x1000>, 2849 <0x17c22000 0x1000>; 2850 }; 2851 2852 frame@17c23000 { 2853 frame-number = <1>; 2854 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2855 reg = <0x17c23000 0x1000>; 2856 status = "disabled"; 2857 }; 2858 2859 frame@17c25000 { 2860 frame-number = <2>; 2861 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2862 reg = <0x17c25000 0x1000>; 2863 status = "disabled"; 2864 }; 2865 2866 frame@17c27000 { 2867 frame-number = <3>; 2868 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2869 reg = <0x17c27000 0x1000>; 2870 status = "disabled"; 2871 }; 2872 2873 frame@17c29000 { 2874 frame-number = <4>; 2875 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2876 reg = <0x17c29000 0x1000>; 2877 status = "disabled"; 2878 }; 2879 2880 frame@17c2b000 { 2881 frame-number = <5>; 2882 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2883 reg = <0x17c2b000 0x1000>; 2884 status = "disabled"; 2885 }; 2886 2887 frame@17c2d000 { 2888 frame-number = <6>; 2889 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2890 reg = <0x17c2d000 0x1000>; 2891 status = "disabled"; 2892 }; 2893 }; 2894 2895 apps_rsc: rsc@18200000 { 2896 compatible = "qcom,rpmh-rsc"; 2897 label = "apps_rsc"; 2898 reg = <0x0 0x18200000 0x0 0x10000>, 2899 <0x0 0x18210000 0x0 0x10000>, 2900 <0x0 0x18220000 0x0 0x10000>; 2901 reg-names = "drv-0", "drv-1", "drv-2"; 2902 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2903 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2904 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2905 qcom,tcs-offset = <0xd00>; 2906 qcom,drv-id = <2>; 2907 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 2908 <WAKE_TCS 3>, <CONTROL_TCS 1>; 2909 power-domains = <&cluster_pd>; 2910 2911 rpmhcc: clock-controller { 2912 compatible = "qcom,sm6350-rpmh-clk"; 2913 #clock-cells = <1>; 2914 clock-names = "xo"; 2915 clocks = <&xo_board>; 2916 }; 2917 2918 rpmhpd: power-controller { 2919 compatible = "qcom,sm6350-rpmhpd"; 2920 #power-domain-cells = <1>; 2921 operating-points-v2 = <&rpmhpd_opp_table>; 2922 2923 rpmhpd_opp_table: opp-table { 2924 compatible = "operating-points-v2"; 2925 2926 rpmhpd_opp_ret: opp1 { 2927 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2928 }; 2929 2930 rpmhpd_opp_min_svs: opp2 { 2931 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2932 }; 2933 2934 rpmhpd_opp_low_svs: opp3 { 2935 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2936 }; 2937 2938 rpmhpd_opp_svs: opp4 { 2939 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2940 }; 2941 2942 rpmhpd_opp_svs_l1: opp5 { 2943 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2944 }; 2945 2946 rpmhpd_opp_nom: opp6 { 2947 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2948 }; 2949 2950 rpmhpd_opp_nom_l1: opp7 { 2951 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2952 }; 2953 2954 rpmhpd_opp_nom_l2: opp8 { 2955 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2956 }; 2957 2958 rpmhpd_opp_turbo: opp9 { 2959 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2960 }; 2961 2962 rpmhpd_opp_turbo_l1: opp10 { 2963 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2964 }; 2965 }; 2966 }; 2967 2968 apps_bcm_voter: bcm-voter { 2969 compatible = "qcom,bcm-voter"; 2970 }; 2971 }; 2972 2973 osm_l3: interconnect@18321000 { 2974 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 2975 reg = <0x0 0x18321000 0x0 0x1000>; 2976 2977 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2978 clock-names = "xo", "alternate"; 2979 2980 #interconnect-cells = <1>; 2981 }; 2982 2983 cpufreq_hw: cpufreq@18323000 { 2984 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 2985 reg = <0x0 0x18323000 0x0 0x1000>, <0x0 0x18325800 0x0 0x1000>; 2986 reg-names = "freq-domain0", "freq-domain1"; 2987 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2988 clock-names = "xo", "alternate"; 2989 2990 #freq-domain-cells = <1>; 2991 #clock-cells = <1>; 2992 }; 2993 2994 wifi: wifi@18800000 { 2995 compatible = "qcom,wcn3990-wifi"; 2996 reg = <0x0 0x18800000 0x0 0x800000>; 2997 reg-names = "membase"; 2998 memory-region = <&wlan_fw_mem>; 2999 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3000 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3001 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3002 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3003 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3004 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3005 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3006 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3007 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3008 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3009 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3010 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3011 iommus = <&apps_smmu 0x20 0x1>; 3012 qcom,msa-fixed-perm; 3013 status = "disabled"; 3014 }; 3015 }; 3016 3017 sound: sound { 3018 }; 3019 3020 thermal-zones { 3021 aoss0-thermal { 3022 thermal-sensors = <&tsens0 0>; 3023 3024 trips { 3025 aoss0-crit { 3026 temperature = <125000>; 3027 hysteresis = <0>; 3028 type = "critical"; 3029 }; 3030 }; 3031 }; 3032 3033 aoss1-thermal { 3034 thermal-sensors = <&tsens1 0>; 3035 3036 trips { 3037 aoss1-crit { 3038 temperature = <125000>; 3039 hysteresis = <0>; 3040 type = "critical"; 3041 }; 3042 }; 3043 }; 3044 3045 audio-thermal { 3046 thermal-sensors = <&tsens1 2>; 3047 3048 trips { 3049 audio-crit { 3050 temperature = <125000>; 3051 hysteresis = <0>; 3052 type = "critical"; 3053 }; 3054 }; 3055 }; 3056 3057 camera-thermal { 3058 thermal-sensors = <&tsens1 5>; 3059 3060 trips { 3061 camera-crit { 3062 temperature = <125000>; 3063 hysteresis = <0>; 3064 type = "critical"; 3065 }; 3066 }; 3067 }; 3068 3069 cpu0-thermal { 3070 thermal-sensors = <&tsens0 1>; 3071 3072 trips { 3073 cpu0_alert0: trip-point0 { 3074 temperature = <95000>; 3075 hysteresis = <2000>; 3076 type = "passive"; 3077 }; 3078 3079 cpu0-crit { 3080 temperature = <115000>; 3081 hysteresis = <0>; 3082 type = "critical"; 3083 }; 3084 }; 3085 3086 cooling-maps { 3087 map0 { 3088 trip = <&cpu0_alert0>; 3089 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3090 }; 3091 }; 3092 }; 3093 3094 cpu1-thermal { 3095 thermal-sensors = <&tsens0 2>; 3096 3097 trips { 3098 cpu1_alert0: trip-point0 { 3099 temperature = <95000>; 3100 hysteresis = <2000>; 3101 type = "passive"; 3102 }; 3103 3104 cpu1-crit { 3105 temperature = <115000>; 3106 hysteresis = <0>; 3107 type = "critical"; 3108 }; 3109 }; 3110 3111 cooling-maps { 3112 map0 { 3113 trip = <&cpu1_alert0>; 3114 cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3115 }; 3116 }; 3117 }; 3118 3119 cpu2-thermal { 3120 thermal-sensors = <&tsens0 3>; 3121 3122 trips { 3123 cpu2_alert0: trip-point0 { 3124 temperature = <95000>; 3125 hysteresis = <2000>; 3126 type = "passive"; 3127 }; 3128 3129 cpu2-crit { 3130 temperature = <115000>; 3131 hysteresis = <0>; 3132 type = "critical"; 3133 }; 3134 }; 3135 3136 cooling-maps { 3137 map0 { 3138 trip = <&cpu2_alert0>; 3139 cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3140 }; 3141 }; 3142 }; 3143 3144 cpu3-thermal { 3145 thermal-sensors = <&tsens0 4>; 3146 3147 trips { 3148 cpu3_alert0: trip-point0 { 3149 temperature = <95000>; 3150 hysteresis = <2000>; 3151 type = "passive"; 3152 }; 3153 3154 cpu3-crit { 3155 temperature = <115000>; 3156 hysteresis = <0>; 3157 type = "critical"; 3158 }; 3159 }; 3160 3161 cooling-maps { 3162 map0 { 3163 trip = <&cpu3_alert0>; 3164 cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3165 }; 3166 }; 3167 }; 3168 3169 cpu4-thermal { 3170 thermal-sensors = <&tsens0 5>; 3171 3172 trips { 3173 cpu4_alert0: trip-point0 { 3174 temperature = <95000>; 3175 hysteresis = <2000>; 3176 type = "passive"; 3177 }; 3178 3179 cpu4-crit { 3180 temperature = <115000>; 3181 hysteresis = <0>; 3182 type = "critical"; 3183 }; 3184 }; 3185 3186 cooling-maps { 3187 map0 { 3188 trip = <&cpu4_alert0>; 3189 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3190 }; 3191 }; 3192 }; 3193 3194 cpu5-thermal { 3195 thermal-sensors = <&tsens0 6>; 3196 3197 trips { 3198 cpu5_alert0: trip-point0 { 3199 temperature = <95000>; 3200 hysteresis = <2000>; 3201 type = "passive"; 3202 }; 3203 3204 cpu5-crit { 3205 temperature = <115000>; 3206 hysteresis = <0>; 3207 type = "critical"; 3208 }; 3209 }; 3210 3211 cooling-maps { 3212 map0 { 3213 trip = <&cpu5_alert0>; 3214 cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3215 }; 3216 }; 3217 }; 3218 3219 cpu6-left-thermal { 3220 thermal-sensors = <&tsens0 9>; 3221 3222 trips { 3223 cpu6_left_alert0: trip-point0 { 3224 temperature = <95000>; 3225 hysteresis = <2000>; 3226 type = "passive"; 3227 }; 3228 3229 cpu6-left-crit { 3230 temperature = <115000>; 3231 hysteresis = <0>; 3232 type = "critical"; 3233 }; 3234 }; 3235 3236 cooling-maps { 3237 map0 { 3238 trip = <&cpu6_left_alert0>; 3239 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3240 }; 3241 }; 3242 }; 3243 3244 cpu6-right-thermal { 3245 thermal-sensors = <&tsens0 10>; 3246 3247 trips { 3248 cpu6_right_alert0: trip-point0 { 3249 temperature = <95000>; 3250 hysteresis = <2000>; 3251 type = "passive"; 3252 }; 3253 3254 cpu6-right-crit { 3255 temperature = <115000>; 3256 hysteresis = <0>; 3257 type = "critical"; 3258 }; 3259 }; 3260 3261 cooling-maps { 3262 map0 { 3263 trip = <&cpu6_right_alert0>; 3264 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3265 }; 3266 }; 3267 }; 3268 3269 cpu7-left-thermal { 3270 thermal-sensors = <&tsens0 11>; 3271 3272 trips { 3273 cpu7_left_alert0: trip-point0 { 3274 temperature = <95000>; 3275 hysteresis = <2000>; 3276 type = "passive"; 3277 }; 3278 3279 cpu7-left-crit { 3280 temperature = <115000>; 3281 hysteresis = <0>; 3282 type = "critical"; 3283 }; 3284 }; 3285 3286 cooling-maps { 3287 map0 { 3288 trip = <&cpu7_left_alert0>; 3289 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3290 }; 3291 }; 3292 }; 3293 3294 cpu7-right-thermal { 3295 thermal-sensors = <&tsens0 12>; 3296 3297 trips { 3298 cpu7_right_alert0: trip-point0 { 3299 temperature = <95000>; 3300 hysteresis = <2000>; 3301 type = "passive"; 3302 }; 3303 3304 cpu7-right-crit { 3305 temperature = <115000>; 3306 hysteresis = <0>; 3307 type = "critical"; 3308 }; 3309 }; 3310 3311 cooling-maps { 3312 map0 { 3313 trip = <&cpu7_right_alert0>; 3314 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3315 }; 3316 }; 3317 }; 3318 3319 cpuss0-thermal { 3320 thermal-sensors = <&tsens0 7>; 3321 3322 trips { 3323 cpuss0-crit { 3324 temperature = <125000>; 3325 hysteresis = <0>; 3326 type = "critical"; 3327 }; 3328 }; 3329 }; 3330 3331 cpuss1-thermal { 3332 thermal-sensors = <&tsens0 8>; 3333 3334 trips { 3335 cpuss1-crit { 3336 temperature = <125000>; 3337 hysteresis = <0>; 3338 type = "critical"; 3339 }; 3340 }; 3341 }; 3342 3343 cwlan-thermal { 3344 thermal-sensors = <&tsens1 1>; 3345 3346 trips { 3347 cwlan-crit { 3348 temperature = <125000>; 3349 hysteresis = <0>; 3350 type = "critical"; 3351 }; 3352 }; 3353 }; 3354 3355 ddr-thermal { 3356 thermal-sensors = <&tsens1 3>; 3357 3358 trips { 3359 ddr-crit { 3360 temperature = <125000>; 3361 hysteresis = <0>; 3362 type = "critical"; 3363 }; 3364 }; 3365 }; 3366 3367 gpuss0-thermal { 3368 polling-delay-passive = <250>; 3369 3370 thermal-sensors = <&tsens0 13>; 3371 3372 trips { 3373 gpuss0_alert0: trip-point0 { 3374 temperature = <85000>; 3375 hysteresis = <2000>; 3376 type = "passive"; 3377 }; 3378 3379 gpuss0-crit { 3380 temperature = <110000>; 3381 hysteresis = <1000>; 3382 type = "critical"; 3383 }; 3384 }; 3385 3386 cooling-maps { 3387 map0 { 3388 trip = <&gpuss0_alert0>; 3389 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3390 }; 3391 }; 3392 }; 3393 3394 gpuss1-thermal { 3395 polling-delay-passive = <250>; 3396 3397 thermal-sensors = <&tsens0 14>; 3398 3399 trips { 3400 gpuss1_alert0: trip-point0 { 3401 temperature = <85000>; 3402 hysteresis = <2000>; 3403 type = "passive"; 3404 }; 3405 3406 gpuss1-crit { 3407 temperature = <110000>; 3408 hysteresis = <1000>; 3409 type = "critical"; 3410 }; 3411 }; 3412 3413 cooling-maps { 3414 map0 { 3415 trip = <&gpuss1_alert0>; 3416 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3417 }; 3418 }; 3419 }; 3420 3421 modem-core0-thermal { 3422 thermal-sensors = <&tsens1 6>; 3423 3424 trips { 3425 modem-core0-crit { 3426 temperature = <125000>; 3427 hysteresis = <0>; 3428 type = "critical"; 3429 }; 3430 }; 3431 }; 3432 3433 modem-core1-thermal { 3434 thermal-sensors = <&tsens1 7>; 3435 3436 trips { 3437 modem-core1-crit { 3438 temperature = <125000>; 3439 hysteresis = <0>; 3440 type = "critical"; 3441 }; 3442 }; 3443 }; 3444 3445 modem-scl-thermal { 3446 thermal-sensors = <&tsens1 9>; 3447 3448 trips { 3449 modem-scl-crit { 3450 temperature = <125000>; 3451 hysteresis = <0>; 3452 type = "critical"; 3453 }; 3454 }; 3455 }; 3456 3457 modem-vec-thermal { 3458 thermal-sensors = <&tsens1 8>; 3459 3460 trips { 3461 modem-vec-crit { 3462 temperature = <125000>; 3463 hysteresis = <0>; 3464 type = "critical"; 3465 }; 3466 }; 3467 }; 3468 3469 npu-thermal { 3470 thermal-sensors = <&tsens1 10>; 3471 3472 trips { 3473 npu-crit { 3474 temperature = <125000>; 3475 hysteresis = <0>; 3476 type = "critical"; 3477 }; 3478 }; 3479 }; 3480 3481 q6-hvx-thermal { 3482 thermal-sensors = <&tsens1 4>; 3483 3484 trips { 3485 q6-hvx-crit { 3486 temperature = <125000>; 3487 hysteresis = <0>; 3488 type = "critical"; 3489 }; 3490 }; 3491 }; 3492 3493 video-thermal { 3494 thermal-sensors = <&tsens1 11>; 3495 3496 trips { 3497 video-crit { 3498 temperature = <125000>; 3499 hysteresis = <0>; 3500 type = "critical"; 3501 }; 3502 }; 3503 }; 3504 }; 3505 3506 timer { 3507 compatible = "arm,armv8-timer"; 3508 clock-frequency = <19200000>; 3509 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3510 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3511 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3512 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3513 }; 3514}; 3515