1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,gcc-sm6115.h> 8#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 9#include <dt-bindings/clock/qcom,sm6115-gpucc.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/firmware/qcom,scm.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,rpm-icc.h> 15#include <dt-bindings/interconnect/qcom,sm6115.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,apr.h> 19#include <dt-bindings/sound/qcom,q6asm.h> 20#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 clocks { 32 xo_board: xo-board { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo260"; 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 52 capacity-dmips-mhz = <1024>; 53 dynamic-power-coefficient = <100>; 54 enable-method = "psci"; 55 next-level-cache = <&l2_0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 power-domains = <&cpu_pd0>; 58 power-domain-names = "psci"; 59 l2_0: l2-cache { 60 compatible = "cache"; 61 cache-level = <2>; 62 cache-unified; 63 }; 64 }; 65 66 cpu1: cpu@1 { 67 device_type = "cpu"; 68 compatible = "qcom,kryo260"; 69 reg = <0x0 0x1>; 70 clocks = <&cpufreq_hw 0>; 71 capacity-dmips-mhz = <1024>; 72 dynamic-power-coefficient = <100>; 73 enable-method = "psci"; 74 next-level-cache = <&l2_0>; 75 qcom,freq-domain = <&cpufreq_hw 0>; 76 power-domains = <&cpu_pd1>; 77 power-domain-names = "psci"; 78 }; 79 80 cpu2: cpu@2 { 81 device_type = "cpu"; 82 compatible = "qcom,kryo260"; 83 reg = <0x0 0x2>; 84 clocks = <&cpufreq_hw 0>; 85 capacity-dmips-mhz = <1024>; 86 dynamic-power-coefficient = <100>; 87 enable-method = "psci"; 88 next-level-cache = <&l2_0>; 89 qcom,freq-domain = <&cpufreq_hw 0>; 90 power-domains = <&cpu_pd2>; 91 power-domain-names = "psci"; 92 }; 93 94 cpu3: cpu@3 { 95 device_type = "cpu"; 96 compatible = "qcom,kryo260"; 97 reg = <0x0 0x3>; 98 clocks = <&cpufreq_hw 0>; 99 capacity-dmips-mhz = <1024>; 100 dynamic-power-coefficient = <100>; 101 enable-method = "psci"; 102 next-level-cache = <&l2_0>; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 power-domains = <&cpu_pd3>; 105 power-domain-names = "psci"; 106 }; 107 108 cpu4: cpu@100 { 109 device_type = "cpu"; 110 compatible = "qcom,kryo260"; 111 reg = <0x0 0x100>; 112 clocks = <&cpufreq_hw 1>; 113 enable-method = "psci"; 114 capacity-dmips-mhz = <1638>; 115 dynamic-power-coefficient = <282>; 116 next-level-cache = <&l2_1>; 117 qcom,freq-domain = <&cpufreq_hw 1>; 118 power-domains = <&cpu_pd4>; 119 power-domain-names = "psci"; 120 l2_1: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 cache-unified; 124 }; 125 }; 126 127 cpu5: cpu@101 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo260"; 130 reg = <0x0 0x101>; 131 clocks = <&cpufreq_hw 1>; 132 capacity-dmips-mhz = <1638>; 133 dynamic-power-coefficient = <282>; 134 enable-method = "psci"; 135 next-level-cache = <&l2_1>; 136 qcom,freq-domain = <&cpufreq_hw 1>; 137 power-domains = <&cpu_pd5>; 138 power-domain-names = "psci"; 139 }; 140 141 cpu6: cpu@102 { 142 device_type = "cpu"; 143 compatible = "qcom,kryo260"; 144 reg = <0x0 0x102>; 145 clocks = <&cpufreq_hw 1>; 146 capacity-dmips-mhz = <1638>; 147 dynamic-power-coefficient = <282>; 148 enable-method = "psci"; 149 next-level-cache = <&l2_1>; 150 qcom,freq-domain = <&cpufreq_hw 1>; 151 power-domains = <&cpu_pd6>; 152 power-domain-names = "psci"; 153 }; 154 155 cpu7: cpu@103 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo260"; 158 reg = <0x0 0x103>; 159 clocks = <&cpufreq_hw 1>; 160 capacity-dmips-mhz = <1638>; 161 dynamic-power-coefficient = <282>; 162 enable-method = "psci"; 163 next-level-cache = <&l2_1>; 164 qcom,freq-domain = <&cpufreq_hw 1>; 165 power-domains = <&cpu_pd7>; 166 power-domain-names = "psci"; 167 }; 168 169 cpu-map { 170 cluster0 { 171 core0 { 172 cpu = <&cpu0>; 173 }; 174 175 core1 { 176 cpu = <&cpu1>; 177 }; 178 179 core2 { 180 cpu = <&cpu2>; 181 }; 182 183 core3 { 184 cpu = <&cpu3>; 185 }; 186 }; 187 188 cluster1 { 189 core0 { 190 cpu = <&cpu4>; 191 }; 192 193 core1 { 194 cpu = <&cpu5>; 195 }; 196 197 core2 { 198 cpu = <&cpu6>; 199 }; 200 201 core3 { 202 cpu = <&cpu7>; 203 }; 204 }; 205 }; 206 207 idle-states { 208 entry-method = "psci"; 209 210 little_cpu_sleep_0: cpu-sleep-0-0 { 211 compatible = "arm,idle-state"; 212 idle-state-name = "silver-rail-power-collapse"; 213 arm,psci-suspend-param = <0x40000003>; 214 entry-latency-us = <290>; 215 exit-latency-us = <376>; 216 min-residency-us = <1182>; 217 local-timer-stop; 218 }; 219 220 big_cpu_sleep_0: cpu-sleep-1-0 { 221 compatible = "arm,idle-state"; 222 idle-state-name = "gold-rail-power-collapse"; 223 arm,psci-suspend-param = <0x40000003>; 224 entry-latency-us = <297>; 225 exit-latency-us = <324>; 226 min-residency-us = <1110>; 227 local-timer-stop; 228 }; 229 }; 230 231 domain-idle-states { 232 cluster_0_sleep_0: cluster-sleep-0-0 { 233 /* GDHS */ 234 compatible = "domain-idle-state"; 235 arm,psci-suspend-param = <0x40000022>; 236 entry-latency-us = <360>; 237 exit-latency-us = <421>; 238 min-residency-us = <782>; 239 }; 240 241 cluster_0_sleep_1: cluster-sleep-0-1 { 242 /* Power Collapse */ 243 compatible = "domain-idle-state"; 244 arm,psci-suspend-param = <0x41000044>; 245 entry-latency-us = <800>; 246 exit-latency-us = <2118>; 247 min-residency-us = <7376>; 248 }; 249 250 cluster_1_sleep_0: cluster-sleep-1-0 { 251 /* GDHS */ 252 compatible = "domain-idle-state"; 253 arm,psci-suspend-param = <0x40000042>; 254 entry-latency-us = <314>; 255 exit-latency-us = <345>; 256 min-residency-us = <660>; 257 }; 258 259 cluster_1_sleep_1: cluster-sleep-1-1 { 260 /* Power Collapse */ 261 compatible = "domain-idle-state"; 262 arm,psci-suspend-param = <0x41000044>; 263 entry-latency-us = <640>; 264 exit-latency-us = <1654>; 265 min-residency-us = <8094>; 266 }; 267 }; 268 }; 269 270 firmware { 271 scm: scm { 272 compatible = "qcom,scm-sm6115", "qcom,scm"; 273 #reset-cells = <1>; 274 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 275 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 276 }; 277 }; 278 279 memory@80000000 { 280 device_type = "memory"; 281 /* We expect the bootloader to fill in the size */ 282 reg = <0 0x80000000 0 0>; 283 }; 284 285 qup_opp_table: opp-table-qup { 286 compatible = "operating-points-v2"; 287 288 opp-75000000 { 289 opp-hz = /bits/ 64 <75000000>; 290 required-opps = <&rpmpd_opp_low_svs>; 291 }; 292 293 opp-100000000 { 294 opp-hz = /bits/ 64 <100000000>; 295 required-opps = <&rpmpd_opp_svs>; 296 }; 297 298 opp-128000000 { 299 opp-hz = /bits/ 64 <128000000>; 300 required-opps = <&rpmpd_opp_nom>; 301 }; 302 }; 303 304 pmu { 305 compatible = "arm,armv8-pmuv3"; 306 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 307 }; 308 309 psci { 310 compatible = "arm,psci-1.0"; 311 method = "smc"; 312 313 cpu_pd0: power-domain-cpu0 { 314 #power-domain-cells = <0>; 315 power-domains = <&cluster_0_pd>; 316 domain-idle-states = <&little_cpu_sleep_0>; 317 }; 318 319 cpu_pd1: power-domain-cpu1 { 320 #power-domain-cells = <0>; 321 power-domains = <&cluster_0_pd>; 322 domain-idle-states = <&little_cpu_sleep_0>; 323 }; 324 325 cpu_pd2: power-domain-cpu2 { 326 #power-domain-cells = <0>; 327 power-domains = <&cluster_0_pd>; 328 domain-idle-states = <&little_cpu_sleep_0>; 329 }; 330 331 cpu_pd3: power-domain-cpu3 { 332 #power-domain-cells = <0>; 333 power-domains = <&cluster_0_pd>; 334 domain-idle-states = <&little_cpu_sleep_0>; 335 }; 336 337 cpu_pd4: power-domain-cpu4 { 338 #power-domain-cells = <0>; 339 power-domains = <&cluster_1_pd>; 340 domain-idle-states = <&big_cpu_sleep_0>; 341 }; 342 343 cpu_pd5: power-domain-cpu5 { 344 #power-domain-cells = <0>; 345 power-domains = <&cluster_1_pd>; 346 domain-idle-states = <&big_cpu_sleep_0>; 347 }; 348 349 cpu_pd6: power-domain-cpu6 { 350 #power-domain-cells = <0>; 351 power-domains = <&cluster_1_pd>; 352 domain-idle-states = <&big_cpu_sleep_0>; 353 }; 354 355 cpu_pd7: power-domain-cpu7 { 356 #power-domain-cells = <0>; 357 power-domains = <&cluster_1_pd>; 358 domain-idle-states = <&big_cpu_sleep_0>; 359 }; 360 361 cluster_0_pd: power-domain-cpu-cluster0 { 362 #power-domain-cells = <0>; 363 domain-idle-states = <&cluster_0_sleep_0>, <&cluster_0_sleep_1>; 364 }; 365 366 cluster_1_pd: power-domain-cpu-cluster1 { 367 #power-domain-cells = <0>; 368 domain-idle-states = <&cluster_1_sleep_0>, <&cluster_1_sleep_1>; 369 }; 370 }; 371 372 rpm: remoteproc { 373 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc"; 374 375 glink-edge { 376 compatible = "qcom,glink-rpm"; 377 378 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 379 qcom,rpm-msg-ram = <&rpm_msg_ram>; 380 mboxes = <&apcs_glb 0>; 381 382 rpm_requests: rpm-requests { 383 compatible = "qcom,rpm-sm6115", "qcom,glink-smd-rpm"; 384 qcom,glink-channels = "rpm_requests"; 385 386 rpmcc: clock-controller { 387 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 388 clocks = <&xo_board>; 389 clock-names = "xo"; 390 #clock-cells = <1>; 391 }; 392 393 rpmpd: power-controller { 394 compatible = "qcom,sm6115-rpmpd"; 395 #power-domain-cells = <1>; 396 operating-points-v2 = <&rpmpd_opp_table>; 397 398 rpmpd_opp_table: opp-table { 399 compatible = "operating-points-v2"; 400 401 rpmpd_opp_min_svs: opp1 { 402 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 403 }; 404 405 rpmpd_opp_low_svs: opp2 { 406 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 407 }; 408 409 rpmpd_opp_svs: opp3 { 410 opp-level = <RPM_SMD_LEVEL_SVS>; 411 }; 412 413 rpmpd_opp_svs_plus: opp4 { 414 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 415 }; 416 417 rpmpd_opp_nom: opp5 { 418 opp-level = <RPM_SMD_LEVEL_NOM>; 419 }; 420 421 rpmpd_opp_nom_plus: opp6 { 422 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 423 }; 424 425 rpmpd_opp_turbo: opp7 { 426 opp-level = <RPM_SMD_LEVEL_TURBO>; 427 }; 428 429 rpmpd_opp_turbo_plus: opp8 { 430 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 431 }; 432 }; 433 }; 434 }; 435 }; 436 }; 437 438 reserved_memory: reserved-memory { 439 #address-cells = <2>; 440 #size-cells = <2>; 441 ranges; 442 443 hyp_mem: memory@45700000 { 444 reg = <0x0 0x45700000 0x0 0x600000>; 445 no-map; 446 }; 447 448 xbl_aop_mem: memory@45e00000 { 449 reg = <0x0 0x45e00000 0x0 0x140000>; 450 no-map; 451 }; 452 453 sec_apps_mem: memory@45fff000 { 454 reg = <0x0 0x45fff000 0x0 0x1000>; 455 no-map; 456 }; 457 458 smem_mem: memory@46000000 { 459 compatible = "qcom,smem"; 460 reg = <0x0 0x46000000 0x0 0x200000>; 461 no-map; 462 463 hwlocks = <&tcsr_mutex 3>; 464 qcom,rpm-msg-ram = <&rpm_msg_ram>; 465 }; 466 467 cdsp_sec_mem: memory@46200000 { 468 reg = <0x0 0x46200000 0x0 0x1e00000>; 469 no-map; 470 }; 471 472 pil_modem_mem: memory@4ab00000 { 473 reg = <0x0 0x4ab00000 0x0 0x6900000>; 474 no-map; 475 }; 476 477 pil_video_mem: memory@51400000 { 478 reg = <0x0 0x51400000 0x0 0x500000>; 479 no-map; 480 }; 481 482 wlan_msa_mem: memory@51900000 { 483 reg = <0x0 0x51900000 0x0 0x100000>; 484 no-map; 485 }; 486 487 pil_cdsp_mem: memory@51a00000 { 488 reg = <0x0 0x51a00000 0x0 0x1e00000>; 489 no-map; 490 }; 491 492 pil_adsp_mem: memory@53800000 { 493 reg = <0x0 0x53800000 0x0 0x2800000>; 494 no-map; 495 }; 496 497 pil_ipa_fw_mem: memory@56100000 { 498 reg = <0x0 0x56100000 0x0 0x10000>; 499 no-map; 500 }; 501 502 pil_ipa_gsi_mem: memory@56110000 { 503 reg = <0x0 0x56110000 0x0 0x5000>; 504 no-map; 505 }; 506 507 pil_gpu_mem: memory@56115000 { 508 reg = <0x0 0x56115000 0x0 0x2000>; 509 no-map; 510 }; 511 512 cont_splash_memory: memory@5c000000 { 513 reg = <0x0 0x5c000000 0x0 0x00f00000>; 514 no-map; 515 }; 516 517 dfps_data_memory: memory@5cf00000 { 518 reg = <0x0 0x5cf00000 0x0 0x0100000>; 519 no-map; 520 }; 521 522 removed_mem: memory@60000000 { 523 reg = <0x0 0x60000000 0x0 0x3900000>; 524 no-map; 525 }; 526 527 rmtfs_mem: memory@89b01000 { 528 compatible = "qcom,rmtfs-mem"; 529 reg = <0x0 0x89b01000 0x0 0x200000>; 530 no-map; 531 532 qcom,client-id = <1>; 533 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 534 }; 535 }; 536 537 smp2p-adsp { 538 compatible = "qcom,smp2p"; 539 qcom,smem = <443>, <429>; 540 541 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 542 543 mboxes = <&apcs_glb 10>; 544 545 qcom,local-pid = <0>; 546 qcom,remote-pid = <2>; 547 548 adsp_smp2p_out: master-kernel { 549 qcom,entry-name = "master-kernel"; 550 #qcom,smem-state-cells = <1>; 551 }; 552 553 adsp_smp2p_in: slave-kernel { 554 qcom,entry-name = "slave-kernel"; 555 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 }; 559 }; 560 561 smp2p-cdsp { 562 compatible = "qcom,smp2p"; 563 qcom,smem = <94>, <432>; 564 565 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; 566 567 mboxes = <&apcs_glb 30>; 568 569 qcom,local-pid = <0>; 570 qcom,remote-pid = <5>; 571 572 cdsp_smp2p_out: master-kernel { 573 qcom,entry-name = "master-kernel"; 574 #qcom,smem-state-cells = <1>; 575 }; 576 577 cdsp_smp2p_in: slave-kernel { 578 qcom,entry-name = "slave-kernel"; 579 580 interrupt-controller; 581 #interrupt-cells = <2>; 582 }; 583 }; 584 585 smp2p-mpss { 586 compatible = "qcom,smp2p"; 587 qcom,smem = <435>, <428>; 588 589 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 590 591 mboxes = <&apcs_glb 14>; 592 593 qcom,local-pid = <0>; 594 qcom,remote-pid = <1>; 595 596 modem_smp2p_out: master-kernel { 597 qcom,entry-name = "master-kernel"; 598 #qcom,smem-state-cells = <1>; 599 }; 600 601 modem_smp2p_in: slave-kernel { 602 qcom,entry-name = "slave-kernel"; 603 604 interrupt-controller; 605 #interrupt-cells = <2>; 606 }; 607 }; 608 609 soc: soc@0 { 610 compatible = "simple-bus"; 611 #address-cells = <2>; 612 #size-cells = <2>; 613 ranges = <0 0 0 0 0x10 0>; 614 dma-ranges = <0 0 0 0 0x10 0>; 615 616 tcsr_mutex: hwlock@340000 { 617 compatible = "qcom,tcsr-mutex"; 618 reg = <0x0 0x00340000 0x0 0x20000>; 619 #hwlock-cells = <1>; 620 }; 621 622 tcsr_regs: syscon@3c0000 { 623 compatible = "qcom,sm6115-tcsr", "syscon"; 624 reg = <0x0 0x003c0000 0x0 0x40000>; 625 }; 626 627 tlmm: pinctrl@500000 { 628 compatible = "qcom,sm6115-tlmm"; 629 reg = <0x0 0x00500000 0x0 0x400000>, 630 <0x0 0x00900000 0x0 0x400000>, 631 <0x0 0x00d00000 0x0 0x400000>; 632 reg-names = "west", "south", "east"; 633 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 634 gpio-controller; 635 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ 636 #gpio-cells = <2>; 637 interrupt-controller; 638 #interrupt-cells = <2>; 639 640 qup_i2c0_default: qup-i2c0-default-state { 641 pins = "gpio0", "gpio1"; 642 function = "qup0"; 643 drive-strength = <2>; 644 bias-pull-up; 645 }; 646 647 qup_i2c1_default: qup-i2c1-default-state { 648 pins = "gpio4", "gpio5"; 649 function = "qup1"; 650 drive-strength = <2>; 651 bias-pull-up; 652 }; 653 654 qup_i2c2_default: qup-i2c2-default-state { 655 pins = "gpio6", "gpio7"; 656 function = "qup2"; 657 drive-strength = <2>; 658 bias-pull-up; 659 }; 660 661 qup_i2c3_default: qup-i2c3-default-state { 662 pins = "gpio8", "gpio9"; 663 function = "qup3"; 664 drive-strength = <2>; 665 bias-pull-up; 666 }; 667 668 qup_i2c4_default: qup-i2c4-default-state { 669 pins = "gpio12", "gpio13"; 670 function = "qup4"; 671 drive-strength = <2>; 672 bias-pull-up; 673 }; 674 675 qup_i2c5_default: qup-i2c5-default-state { 676 pins = "gpio14", "gpio15"; 677 function = "qup5"; 678 drive-strength = <2>; 679 bias-pull-up; 680 }; 681 682 qup_spi0_default: qup-spi0-default-state { 683 pins = "gpio0", "gpio1","gpio2", "gpio3"; 684 function = "qup0"; 685 drive-strength = <2>; 686 bias-pull-up; 687 }; 688 689 qup_spi1_default: qup-spi1-default-state { 690 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 691 function = "qup1"; 692 drive-strength = <2>; 693 bias-pull-up; 694 }; 695 696 qup_spi2_default: qup-spi2-default-state { 697 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 698 function = "qup2"; 699 drive-strength = <2>; 700 bias-pull-up; 701 }; 702 703 qup_spi3_default: qup-spi3-default-state { 704 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 705 function = "qup3"; 706 drive-strength = <2>; 707 bias-pull-up; 708 }; 709 710 qup_spi4_default: qup-spi4-default-state { 711 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 712 function = "qup4"; 713 drive-strength = <2>; 714 bias-pull-up; 715 }; 716 717 qup_spi5_default: qup-spi5-default-state { 718 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 719 function = "qup5"; 720 drive-strength = <2>; 721 bias-pull-up; 722 }; 723 724 sdc1_state_on: sdc1-on-state { 725 clk-pins { 726 pins = "sdc1_clk"; 727 bias-disable; 728 drive-strength = <16>; 729 }; 730 731 cmd-pins { 732 pins = "sdc1_cmd"; 733 bias-pull-up; 734 drive-strength = <10>; 735 }; 736 737 data-pins { 738 pins = "sdc1_data"; 739 bias-pull-up; 740 drive-strength = <10>; 741 }; 742 743 rclk-pins { 744 pins = "sdc1_rclk"; 745 bias-pull-down; 746 }; 747 }; 748 749 sdc1_state_off: sdc1-off-state { 750 clk-pins { 751 pins = "sdc1_clk"; 752 bias-disable; 753 drive-strength = <2>; 754 }; 755 756 cmd-pins { 757 pins = "sdc1_cmd"; 758 bias-pull-up; 759 drive-strength = <2>; 760 }; 761 762 data-pins { 763 pins = "sdc1_data"; 764 bias-pull-up; 765 drive-strength = <2>; 766 }; 767 768 rclk-pins { 769 pins = "sdc1_rclk"; 770 bias-pull-down; 771 }; 772 }; 773 774 sdc2_state_on: sdc2-on-state { 775 clk-pins { 776 pins = "sdc2_clk"; 777 bias-disable; 778 drive-strength = <16>; 779 }; 780 781 cmd-pins { 782 pins = "sdc2_cmd"; 783 bias-pull-up; 784 drive-strength = <10>; 785 }; 786 787 data-pins { 788 pins = "sdc2_data"; 789 bias-pull-up; 790 drive-strength = <10>; 791 }; 792 }; 793 794 sdc2_state_off: sdc2-off-state { 795 clk-pins { 796 pins = "sdc2_clk"; 797 bias-disable; 798 drive-strength = <2>; 799 }; 800 801 cmd-pins { 802 pins = "sdc2_cmd"; 803 bias-pull-up; 804 drive-strength = <2>; 805 }; 806 807 data-pins { 808 pins = "sdc2_data"; 809 bias-pull-up; 810 drive-strength = <2>; 811 }; 812 }; 813 }; 814 815 lpass_tlmm: pinctrl@a7c0000 { 816 compatible = "qcom,sm6115-lpass-lpi-pinctrl"; 817 reg = <0x0 0x0a7c0000 0x0 0x20000>, 818 <0x0 0x0a950000 0x0 0x10000>; 819 820 clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 821 clock-names = "audio"; 822 823 gpio-controller; 824 #gpio-cells = <2>; 825 gpio-ranges = <&lpass_tlmm 0 0 19>; 826 827 }; 828 829 gcc: clock-controller@1400000 { 830 compatible = "qcom,gcc-sm6115"; 831 reg = <0x0 0x01400000 0x0 0x1f0000>; 832 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 833 clock-names = "bi_tcxo", "sleep_clk"; 834 #clock-cells = <1>; 835 #reset-cells = <1>; 836 #power-domain-cells = <1>; 837 }; 838 839 usb_hsphy: phy@1613000 { 840 compatible = "qcom,sm6115-qusb2-phy"; 841 reg = <0x0 0x01613000 0x0 0x180>; 842 #phy-cells = <0>; 843 844 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 845 clock-names = "cfg_ahb", "ref"; 846 847 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 848 nvmem-cells = <&qusb2_hstx_trim>; 849 850 status = "disabled"; 851 }; 852 853 cryptobam: dma-controller@1b04000 { 854 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 855 reg = <0x0 0x01b04000 0x0 0x24000>; 856 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 858 clock-names = "bam_clk"; 859 #dma-cells = <1>; 860 qcom,ee = <0>; 861 qcom,controlled-remotely; 862 iommus = <&apps_smmu 0x92 0>, 863 <&apps_smmu 0x94 0x11>, 864 <&apps_smmu 0x96 0x11>, 865 <&apps_smmu 0x98 0x1>, 866 <&apps_smmu 0x9F 0>; 867 }; 868 869 crypto: crypto@1b3a000 { 870 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce"; 871 reg = <0x0 0x01b3a000 0x0 0x6000>; 872 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 873 clock-names = "core"; 874 875 dmas = <&cryptobam 6>, <&cryptobam 7>; 876 dma-names = "rx", "tx"; 877 iommus = <&apps_smmu 0x92 0>, 878 <&apps_smmu 0x94 0x11>, 879 <&apps_smmu 0x96 0x11>, 880 <&apps_smmu 0x98 0x1>, 881 <&apps_smmu 0x9F 0>; 882 }; 883 884 usb_qmpphy: phy@1615000 { 885 compatible = "qcom,sm6115-qmp-usb3-phy"; 886 reg = <0x0 0x01615000 0x0 0x1000>; 887 888 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 889 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 890 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 891 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 892 clock-names = "cfg_ahb", 893 "ref", 894 "com_aux", 895 "pipe"; 896 897 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 898 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 899 reset-names = "phy", "phy_phy"; 900 901 #clock-cells = <0>; 902 clock-output-names = "usb3_phy_pipe_clk_src"; 903 904 #phy-cells = <0>; 905 orientation-switch; 906 907 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 908 909 status = "disabled"; 910 911 ports { 912 #address-cells = <1>; 913 #size-cells = <0>; 914 915 port@0 { 916 reg = <0>; 917 918 usb_qmpphy_out: endpoint { 919 }; 920 }; 921 922 port@1 { 923 reg = <1>; 924 925 usb_qmpphy_usb_ss_in: endpoint { 926 remote-endpoint = <&usb_dwc3_ss>; 927 }; 928 }; 929 }; 930 }; 931 932 system_noc: interconnect@1880000 { 933 compatible = "qcom,sm6115-snoc"; 934 reg = <0x0 0x01880000 0x0 0x5f080>; 935 clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>, 936 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 937 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 938 <&rpmcc RPM_SMD_IPA_CLK>; 939 clock-names = "cpu_axi", 940 "ufs_axi", 941 "usb_axi", 942 "ipa"; 943 #interconnect-cells = <2>; 944 945 clk_virt: interconnect-clk { 946 compatible = "qcom,sm6115-clk-virt"; 947 #interconnect-cells = <2>; 948 }; 949 950 mmrt_virt: interconnect-mmrt { 951 compatible = "qcom,sm6115-mmrt-virt"; 952 #interconnect-cells = <2>; 953 }; 954 955 mmnrt_virt: interconnect-mmnrt { 956 compatible = "qcom,sm6115-mmnrt-virt"; 957 #interconnect-cells = <2>; 958 }; 959 }; 960 961 config_noc: interconnect@1900000 { 962 compatible = "qcom,sm6115-cnoc"; 963 reg = <0x0 0x01900000 0x0 0x6200>; 964 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>; 965 clock-names = "usb_axi"; 966 #interconnect-cells = <2>; 967 }; 968 969 qfprom@1b40000 { 970 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 971 reg = <0x0 0x01b40000 0x0 0x7000>; 972 #address-cells = <1>; 973 #size-cells = <1>; 974 975 qusb2_hstx_trim: hstx-trim@25b { 976 reg = <0x25b 0x1>; 977 bits = <1 4>; 978 }; 979 980 gpu_speed_bin: gpu-speed-bin@6006 { 981 reg = <0x6006 0x2>; 982 bits = <5 8>; 983 }; 984 }; 985 986 rng: rng@1b53000 { 987 compatible = "qcom,prng-ee"; 988 reg = <0x0 0x01b53000 0x0 0x1000>; 989 clocks = <&gcc GCC_PRNG_AHB_CLK>; 990 clock-names = "core"; 991 }; 992 993 pmu@1b8e300 { 994 compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon"; 995 reg = <0x0 0x01b8e300 0x0 0x600>; 996 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 997 998 operating-points-v2 = <&cpu_bwmon_opp_table>; 999 interconnects = <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG 1000 &bimc SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; 1001 1002 cpu_bwmon_opp_table: opp-table { 1003 compatible = "operating-points-v2"; 1004 1005 opp-0 { 1006 opp-peak-kBps = <(200 * 4 * 1000)>; 1007 }; 1008 1009 opp-1 { 1010 opp-peak-kBps = <(300 * 4 * 1000)>; 1011 }; 1012 1013 opp-2 { 1014 opp-peak-kBps = <(451 * 4 * 1000)>; 1015 }; 1016 1017 opp-3 { 1018 opp-peak-kBps = <(547 * 4 * 1000)>; 1019 }; 1020 1021 opp-4 { 1022 opp-peak-kBps = <(681 * 4 * 1000)>; 1023 }; 1024 1025 opp-5 { 1026 opp-peak-kBps = <(768 * 4 * 1000)>; 1027 }; 1028 1029 opp-6 { 1030 opp-peak-kBps = <(1017 * 4 * 1000)>; 1031 }; 1032 1033 opp-7 { 1034 opp-peak-kBps = <(1353 * 4 * 1000)>; 1035 }; 1036 1037 opp-8 { 1038 opp-peak-kBps = <(1555 * 4 * 1000)>; 1039 }; 1040 1041 opp-9 { 1042 opp-peak-kBps = <(1804 * 4 * 1000)>; 1043 }; 1044 }; 1045 }; 1046 1047 spmi_bus: spmi@1c40000 { 1048 compatible = "qcom,spmi-pmic-arb"; 1049 reg = <0x0 0x01c40000 0x0 0x1100>, 1050 <0x0 0x01e00000 0x0 0x2000000>, 1051 <0x0 0x03e00000 0x0 0x100000>, 1052 <0x0 0x03f00000 0x0 0xa0000>, 1053 <0x0 0x01c0a000 0x0 0x26000>; 1054 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1055 interrupt-names = "periph_irq"; 1056 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1057 qcom,ee = <0>; 1058 qcom,channel = <0>; 1059 #address-cells = <2>; 1060 #size-cells = <0>; 1061 interrupt-controller; 1062 #interrupt-cells = <4>; 1063 }; 1064 1065 tsens0: thermal-sensor@4411000 { 1066 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 1067 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ 1068 <0x0 0x04410000 0x0 0x8>; /* SROT */ 1069 #qcom,sensors = <16>; 1070 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1072 interrupt-names = "uplow", "critical"; 1073 #thermal-sensor-cells = <1>; 1074 }; 1075 1076 bimc: interconnect@4480000 { 1077 compatible = "qcom,sm6115-bimc"; 1078 reg = <0x0 0x04480000 0x0 0x80000>; 1079 #interconnect-cells = <2>; 1080 }; 1081 1082 rpm_msg_ram: sram@45f0000 { 1083 compatible = "qcom,rpm-msg-ram"; 1084 reg = <0x0 0x045f0000 0x0 0x7000>; 1085 }; 1086 1087 sram@4690000 { 1088 compatible = "qcom,rpm-stats"; 1089 reg = <0x0 0x04690000 0x0 0x10000>; 1090 }; 1091 1092 sdhc_1: mmc@4744000 { 1093 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 1094 reg = <0x0 0x04744000 0x0 0x1000>, 1095 <0x0 0x04745000 0x0 0x1000>, 1096 <0x0 0x04748000 0x0 0x8000>; 1097 reg-names = "hc", "cqhci", "ice"; 1098 1099 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1101 interrupt-names = "hc_irq", "pwr_irq"; 1102 1103 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1104 <&gcc GCC_SDCC1_APPS_CLK>, 1105 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1106 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1107 clock-names = "iface", "core", "xo", "ice"; 1108 1109 resets = <&gcc GCC_SDCC1_BCR>; 1110 1111 power-domains = <&rpmpd SM6115_VDDCX>; 1112 operating-points-v2 = <&sdhc1_opp_table>; 1113 iommus = <&apps_smmu 0x00c0 0x0>; 1114 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 1115 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1116 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1117 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; 1118 interconnect-names = "sdhc-ddr", 1119 "cpu-sdhc"; 1120 1121 bus-width = <8>; 1122 status = "disabled"; 1123 1124 sdhc1_opp_table: opp-table { 1125 compatible = "operating-points-v2"; 1126 1127 opp-100000000 { 1128 opp-hz = /bits/ 64 <100000000>; 1129 required-opps = <&rpmpd_opp_low_svs>; 1130 opp-peak-kBps = <250000 133320>; 1131 opp-avg-kBps = <102400 65000>; 1132 }; 1133 1134 opp-192000000 { 1135 opp-hz = /bits/ 64 <192000000>; 1136 required-opps = <&rpmpd_opp_low_svs>; 1137 opp-peak-kBps = <800000 300000>; 1138 opp-avg-kBps = <204800 200000>; 1139 }; 1140 1141 opp-384000000 { 1142 opp-hz = /bits/ 64 <384000000>; 1143 required-opps = <&rpmpd_opp_svs_plus>; 1144 opp-peak-kBps = <800000 300000>; 1145 opp-avg-kBps = <204800 200000>; 1146 }; 1147 }; 1148 }; 1149 1150 sdhc_2: mmc@4784000 { 1151 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 1152 reg = <0x0 0x04784000 0x0 0x1000>; 1153 reg-names = "hc"; 1154 1155 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1157 interrupt-names = "hc_irq", "pwr_irq"; 1158 1159 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1160 <&gcc GCC_SDCC2_APPS_CLK>, 1161 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1162 clock-names = "iface", "core", "xo"; 1163 1164 power-domains = <&rpmpd SM6115_VDDCX>; 1165 operating-points-v2 = <&sdhc2_opp_table>; 1166 iommus = <&apps_smmu 0x00a0 0x0>; 1167 resets = <&gcc GCC_SDCC2_BCR>; 1168 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG 1169 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1170 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1171 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; 1172 interconnect-names = "sdhc-ddr", 1173 "cpu-sdhc"; 1174 1175 bus-width = <4>; 1176 qcom,dll-config = <0x0007642c>; 1177 qcom,ddr-config = <0x80040868>; 1178 status = "disabled"; 1179 1180 sdhc2_opp_table: opp-table { 1181 compatible = "operating-points-v2"; 1182 1183 opp-100000000 { 1184 opp-hz = /bits/ 64 <100000000>; 1185 required-opps = <&rpmpd_opp_low_svs>; 1186 opp-peak-kBps = <250000 133320>; 1187 opp-avg-kBps = <261438 150000>; 1188 }; 1189 1190 opp-202000000 { 1191 opp-hz = /bits/ 64 <202000000>; 1192 required-opps = <&rpmpd_opp_nom>; 1193 opp-peak-kBps = <800000 300000>; 1194 opp-avg-kBps = <261438 300000>; 1195 }; 1196 }; 1197 }; 1198 1199 ufs_mem_hc: ufshc@4804000 { 1200 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1201 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; 1202 reg-names = "std", "ice"; 1203 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1204 phys = <&ufs_mem_phy>; 1205 phy-names = "ufsphy"; 1206 lanes-per-direction = <1>; 1207 #reset-cells = <1>; 1208 resets = <&gcc GCC_UFS_PHY_BCR>; 1209 reset-names = "rst"; 1210 1211 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1212 iommus = <&apps_smmu 0x100 0>; 1213 1214 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1215 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 1216 <&gcc GCC_UFS_PHY_AHB_CLK>, 1217 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1218 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1219 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1220 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1221 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1222 clock-names = "core_clk", 1223 "bus_aggr_clk", 1224 "iface_clk", 1225 "core_clk_unipro", 1226 "ref_clk", 1227 "tx_lane0_sync_clk", 1228 "rx_lane0_sync_clk", 1229 "ice_core_clk"; 1230 1231 freq-table-hz = <50000000 200000000>, 1232 <0 0>, 1233 <0 0>, 1234 <37500000 150000000>, 1235 <0 0>, 1236 <0 0>, 1237 <0 0>, 1238 <75000000 300000000>; 1239 1240 status = "disabled"; 1241 }; 1242 1243 ufs_mem_phy: phy@4807000 { 1244 compatible = "qcom,sm6115-qmp-ufs-phy"; 1245 reg = <0x0 0x04807000 0x0 0x1000>; 1246 1247 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1248 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1249 <&gcc GCC_UFS_CLKREF_CLK>; 1250 clock-names = "ref", 1251 "ref_aux", 1252 "qref"; 1253 1254 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1255 1256 resets = <&ufs_mem_hc 0>; 1257 reset-names = "ufsphy"; 1258 1259 #phy-cells = <0>; 1260 1261 status = "disabled"; 1262 }; 1263 1264 gpi_dma0: dma-controller@4a00000 { 1265 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 1266 reg = <0x0 0x04a00000 0x0 0x60000>; 1267 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1277 dma-channels = <10>; 1278 dma-channel-mask = <0xf>; 1279 iommus = <&apps_smmu 0xf6 0x0>; 1280 #dma-cells = <3>; 1281 status = "disabled"; 1282 }; 1283 1284 qupv3_id_0: geniqup@4ac0000 { 1285 compatible = "qcom,geni-se-qup"; 1286 reg = <0x0 0x04ac0000 0x0 0x2000>; 1287 clock-names = "m-ahb", "s-ahb"; 1288 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1289 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1290 #address-cells = <2>; 1291 #size-cells = <2>; 1292 iommus = <&apps_smmu 0xe3 0x0>; 1293 ranges; 1294 status = "disabled"; 1295 1296 i2c0: i2c@4a80000 { 1297 compatible = "qcom,geni-i2c"; 1298 reg = <0x0 0x04a80000 0x0 0x4000>; 1299 clock-names = "se"; 1300 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1301 pinctrl-names = "default"; 1302 pinctrl-0 = <&qup_i2c0_default>; 1303 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1304 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1305 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1306 dma-names = "tx", "rx"; 1307 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1308 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1309 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1310 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1311 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1312 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1313 interconnect-names = "qup-core", 1314 "qup-config", 1315 "qup-memory"; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 status = "disabled"; 1319 }; 1320 1321 spi0: spi@4a80000 { 1322 compatible = "qcom,geni-spi"; 1323 reg = <0x0 0x04a80000 0x0 0x4000>; 1324 clock-names = "se"; 1325 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1326 pinctrl-names = "default"; 1327 pinctrl-0 = <&qup_spi0_default>; 1328 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1329 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1330 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1331 dma-names = "tx", "rx"; 1332 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1333 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1334 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1335 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1336 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1337 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1338 interconnect-names = "qup-core", 1339 "qup-config", 1340 "qup-memory"; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 status = "disabled"; 1344 }; 1345 1346 i2c1: i2c@4a84000 { 1347 compatible = "qcom,geni-i2c"; 1348 reg = <0x0 0x04a84000 0x0 0x4000>; 1349 clock-names = "se"; 1350 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1351 pinctrl-names = "default"; 1352 pinctrl-0 = <&qup_i2c1_default>; 1353 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1354 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1355 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1356 dma-names = "tx", "rx"; 1357 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1358 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1359 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1360 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1361 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1362 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1363 interconnect-names = "qup-core", 1364 "qup-config", 1365 "qup-memory"; 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 status = "disabled"; 1369 }; 1370 1371 spi1: spi@4a84000 { 1372 compatible = "qcom,geni-spi"; 1373 reg = <0x0 0x04a84000 0x0 0x4000>; 1374 clock-names = "se"; 1375 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1376 pinctrl-names = "default"; 1377 pinctrl-0 = <&qup_spi1_default>; 1378 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1379 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1380 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1381 dma-names = "tx", "rx"; 1382 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1383 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1384 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1385 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1386 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1387 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1388 interconnect-names = "qup-core", 1389 "qup-config", 1390 "qup-memory"; 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 status = "disabled"; 1394 }; 1395 1396 i2c2: i2c@4a88000 { 1397 compatible = "qcom,geni-i2c"; 1398 reg = <0x0 0x04a88000 0x0 0x4000>; 1399 clock-names = "se"; 1400 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1401 pinctrl-names = "default"; 1402 pinctrl-0 = <&qup_i2c2_default>; 1403 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1404 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1405 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1406 dma-names = "tx", "rx"; 1407 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1408 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1409 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1410 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1411 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1412 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1413 interconnect-names = "qup-core", 1414 "qup-config", 1415 "qup-memory"; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 status = "disabled"; 1419 }; 1420 1421 spi2: spi@4a88000 { 1422 compatible = "qcom,geni-spi"; 1423 reg = <0x0 0x04a88000 0x0 0x4000>; 1424 clock-names = "se"; 1425 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1426 pinctrl-names = "default"; 1427 pinctrl-0 = <&qup_spi2_default>; 1428 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1429 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1430 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1431 dma-names = "tx", "rx"; 1432 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1433 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1434 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1435 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1436 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1437 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1438 interconnect-names = "qup-core", 1439 "qup-config", 1440 "qup-memory"; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 status = "disabled"; 1444 }; 1445 1446 i2c3: i2c@4a8c000 { 1447 compatible = "qcom,geni-i2c"; 1448 reg = <0x0 0x04a8c000 0x0 0x4000>; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1451 pinctrl-names = "default"; 1452 pinctrl-0 = <&qup_i2c3_default>; 1453 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1454 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1455 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1456 dma-names = "tx", "rx"; 1457 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1458 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1459 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1460 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1461 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1462 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1463 interconnect-names = "qup-core", 1464 "qup-config", 1465 "qup-memory"; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 status = "disabled"; 1469 }; 1470 1471 spi3: spi@4a8c000 { 1472 compatible = "qcom,geni-spi"; 1473 reg = <0x0 0x04a8c000 0x0 0x4000>; 1474 clock-names = "se"; 1475 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1476 pinctrl-names = "default"; 1477 pinctrl-0 = <&qup_spi3_default>; 1478 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1479 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1480 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1481 dma-names = "tx", "rx"; 1482 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1483 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1484 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1485 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1486 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1487 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1488 interconnect-names = "qup-core", 1489 "qup-config", 1490 "qup-memory"; 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 status = "disabled"; 1494 }; 1495 1496 uart3: serial@4a8c000 { 1497 compatible = "qcom,geni-uart"; 1498 reg = <0x0 0x04a8c000 0x0 0x4000>; 1499 interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1500 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1501 clock-names = "se"; 1502 power-domains = <&rpmpd SM6115_VDDCX>; 1503 operating-points-v2 = <&qup_opp_table>; 1504 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1505 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1506 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1507 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1508 interconnect-names = "qup-core", 1509 "qup-config"; 1510 status = "disabled"; 1511 }; 1512 1513 i2c4: i2c@4a90000 { 1514 compatible = "qcom,geni-i2c"; 1515 reg = <0x0 0x04a90000 0x0 0x4000>; 1516 clock-names = "se"; 1517 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1518 pinctrl-names = "default"; 1519 pinctrl-0 = <&qup_i2c4_default>; 1520 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1521 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1522 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1523 dma-names = "tx", "rx"; 1524 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1525 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1526 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1527 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1528 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1529 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1530 interconnect-names = "qup-core", 1531 "qup-config", 1532 "qup-memory"; 1533 #address-cells = <1>; 1534 #size-cells = <0>; 1535 status = "disabled"; 1536 }; 1537 1538 spi4: spi@4a90000 { 1539 compatible = "qcom,geni-spi"; 1540 reg = <0x0 0x04a90000 0x0 0x4000>; 1541 clock-names = "se"; 1542 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1543 pinctrl-names = "default"; 1544 pinctrl-0 = <&qup_spi4_default>; 1545 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1546 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1547 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1548 dma-names = "tx", "rx"; 1549 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1550 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1551 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1552 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1553 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1554 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1555 interconnect-names = "qup-core", 1556 "qup-config", 1557 "qup-memory"; 1558 #address-cells = <1>; 1559 #size-cells = <0>; 1560 status = "disabled"; 1561 }; 1562 1563 uart4: serial@4a90000 { 1564 compatible = "qcom,geni-debug-uart"; 1565 reg = <0x0 0x04a90000 0x0 0x4000>; 1566 clock-names = "se"; 1567 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1568 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1569 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1570 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1571 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1572 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1573 interconnect-names = "qup-core", 1574 "qup-config"; 1575 status = "disabled"; 1576 }; 1577 1578 i2c5: i2c@4a94000 { 1579 compatible = "qcom,geni-i2c"; 1580 reg = <0x0 0x04a94000 0x0 0x4000>; 1581 clock-names = "se"; 1582 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1583 pinctrl-names = "default"; 1584 pinctrl-0 = <&qup_i2c5_default>; 1585 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1586 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1587 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1588 dma-names = "tx", "rx"; 1589 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1590 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1591 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1592 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1593 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1594 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1595 interconnect-names = "qup-core", 1596 "qup-config", 1597 "qup-memory"; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 status = "disabled"; 1601 }; 1602 1603 spi5: spi@4a94000 { 1604 compatible = "qcom,geni-spi"; 1605 reg = <0x0 0x04a94000 0x0 0x4000>; 1606 clock-names = "se"; 1607 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1608 pinctrl-names = "default"; 1609 pinctrl-0 = <&qup_spi5_default>; 1610 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1611 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1612 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1613 dma-names = "tx", "rx"; 1614 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1615 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1616 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1617 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1618 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1619 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1620 interconnect-names = "qup-core", 1621 "qup-config", 1622 "qup-memory"; 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 status = "disabled"; 1626 }; 1627 }; 1628 1629 usb: usb@4ef8800 { 1630 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1631 reg = <0x0 0x04ef8800 0x0 0x400>; 1632 #address-cells = <2>; 1633 #size-cells = <2>; 1634 ranges; 1635 1636 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1637 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1638 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1639 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1640 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1641 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1642 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1643 1644 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1645 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1646 assigned-clock-rates = <19200000>, <66666667>; 1647 1648 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1652 interrupt-names = "pwr_event", 1653 "qusb2_phy", 1654 "hs_phy_irq", 1655 "ss_phy_irq"; 1656 1657 resets = <&gcc GCC_USB30_PRIM_BCR>; 1658 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1659 /* TODO: USB<->IPA path */ 1660 interconnects = <&system_noc MASTER_USB3 RPM_ALWAYS_TAG 1661 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1662 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1663 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; 1664 interconnect-names = "usb-ddr", 1665 "apps-usb"; 1666 1667 status = "disabled"; 1668 1669 usb_dwc3: usb@4e00000 { 1670 compatible = "snps,dwc3"; 1671 reg = <0x0 0x04e00000 0x0 0xcd00>; 1672 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1673 phys = <&usb_hsphy>, <&usb_qmpphy>; 1674 phy-names = "usb2-phy", "usb3-phy"; 1675 iommus = <&apps_smmu 0x120 0x0>; 1676 snps,dis_u2_susphy_quirk; 1677 snps,dis_enblslpm_quirk; 1678 snps,has-lpm-erratum; 1679 snps,hird-threshold = /bits/ 8 <0x10>; 1680 snps,usb3_lpm_capable; 1681 snps,parkmode-disable-ss-quirk; 1682 1683 usb-role-switch; 1684 1685 ports { 1686 #address-cells = <1>; 1687 #size-cells = <0>; 1688 1689 port@0 { 1690 reg = <0>; 1691 1692 usb_dwc3_hs: endpoint { 1693 }; 1694 }; 1695 1696 port@1 { 1697 reg = <1>; 1698 1699 usb_dwc3_ss: endpoint { 1700 remote-endpoint = <&usb_qmpphy_usb_ss_in>; 1701 }; 1702 }; 1703 }; 1704 }; 1705 }; 1706 1707 gpu: gpu@5900000 { 1708 compatible = "qcom,adreno-610.0", "qcom,adreno"; 1709 reg = <0x0 0x05900000 0x0 0x40000>; 1710 reg-names = "kgsl_3d0_reg_memory"; 1711 1712 /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ 1713 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1714 <&gpucc GPU_CC_AHB_CLK>, 1715 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1716 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1717 <&gpucc GPU_CC_CX_GMU_CLK>, 1718 <&gpucc GPU_CC_CXO_CLK>; 1719 clock-names = "core", 1720 "iface", 1721 "mem_iface", 1722 "alt_mem_iface", 1723 "gmu", 1724 "xo"; 1725 1726 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1727 1728 iommus = <&adreno_smmu 0 1>; 1729 operating-points-v2 = <&gpu_opp_table>; 1730 power-domains = <&rpmpd SM6115_VDDCX>; 1731 qcom,gmu = <&gmu_wrapper>; 1732 1733 nvmem-cells = <&gpu_speed_bin>; 1734 nvmem-cell-names = "speed_bin"; 1735 #cooling-cells = <2>; 1736 1737 status = "disabled"; 1738 1739 zap-shader { 1740 memory-region = <&pil_gpu_mem>; 1741 }; 1742 1743 gpu_opp_table: opp-table { 1744 compatible = "operating-points-v2"; 1745 1746 opp-320000000 { 1747 opp-hz = /bits/ 64 <320000000>; 1748 required-opps = <&rpmpd_opp_low_svs>; 1749 opp-supported-hw = <0x1f>; 1750 }; 1751 1752 opp-465000000 { 1753 opp-hz = /bits/ 64 <465000000>; 1754 required-opps = <&rpmpd_opp_svs>; 1755 opp-supported-hw = <0x1f>; 1756 }; 1757 1758 opp-600000000 { 1759 opp-hz = /bits/ 64 <600000000>; 1760 required-opps = <&rpmpd_opp_svs_plus>; 1761 opp-supported-hw = <0x1f>; 1762 }; 1763 1764 opp-745000000 { 1765 opp-hz = /bits/ 64 <745000000>; 1766 required-opps = <&rpmpd_opp_nom>; 1767 opp-supported-hw = <0xf>; 1768 }; 1769 1770 opp-820000000 { 1771 opp-hz = /bits/ 64 <820000000>; 1772 required-opps = <&rpmpd_opp_nom_plus>; 1773 opp-supported-hw = <0x7>; 1774 }; 1775 1776 opp-900000000 { 1777 opp-hz = /bits/ 64 <900000000>; 1778 required-opps = <&rpmpd_opp_turbo>; 1779 opp-supported-hw = <0x7>; 1780 }; 1781 1782 /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */ 1783 opp-950000000 { 1784 opp-hz = /bits/ 64 <950000000>; 1785 required-opps = <&rpmpd_opp_turbo_plus>; 1786 opp-supported-hw = <0x4>; 1787 }; 1788 1789 opp-980000000 { 1790 opp-hz = /bits/ 64 <980000000>; 1791 required-opps = <&rpmpd_opp_turbo_plus>; 1792 opp-supported-hw = <0x3>; 1793 }; 1794 }; 1795 }; 1796 1797 gmu_wrapper: gmu@596a000 { 1798 compatible = "qcom,adreno-gmu-wrapper"; 1799 reg = <0x0 0x0596a000 0x0 0x30000>; 1800 reg-names = "gmu"; 1801 power-domains = <&gpucc GPU_CX_GDSC>, 1802 <&gpucc GPU_GX_GDSC>; 1803 power-domain-names = "cx", "gx"; 1804 }; 1805 1806 gpucc: clock-controller@5990000 { 1807 compatible = "qcom,sm6115-gpucc"; 1808 reg = <0x0 0x05990000 0x0 0x9000>; 1809 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1810 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1811 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1812 #clock-cells = <1>; 1813 #reset-cells = <1>; 1814 #power-domain-cells = <1>; 1815 }; 1816 1817 adreno_smmu: iommu@59a0000 { 1818 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", 1819 "qcom,smmu-500", "arm,mmu-500"; 1820 reg = <0x0 0x059a0000 0x0 0x10000>; 1821 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1823 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1824 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1826 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1827 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1828 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1829 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1830 1831 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1832 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1833 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1834 clock-names = "mem", 1835 "hlos", 1836 "iface"; 1837 power-domains = <&gpucc GPU_CX_GDSC>; 1838 1839 #global-interrupts = <1>; 1840 #iommu-cells = <2>; 1841 }; 1842 1843 mdss: display-subsystem@5e00000 { 1844 compatible = "qcom,sm6115-mdss"; 1845 reg = <0x0 0x05e00000 0x0 0x1000>; 1846 reg-names = "mdss"; 1847 1848 power-domains = <&dispcc MDSS_GDSC>; 1849 1850 clocks = <&gcc GCC_DISP_AHB_CLK>, 1851 <&gcc GCC_DISP_HF_AXI_CLK>, 1852 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1853 1854 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1855 interrupt-controller; 1856 #interrupt-cells = <1>; 1857 1858 iommus = <&apps_smmu 0x420 0x2>, 1859 <&apps_smmu 0x421 0x0>; 1860 1861 interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG 1862 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1863 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1864 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; 1865 interconnect-names = "mdp0-mem", 1866 "cpu-cfg"; 1867 1868 #address-cells = <2>; 1869 #size-cells = <2>; 1870 ranges; 1871 1872 status = "disabled"; 1873 1874 mdp: display-controller@5e01000 { 1875 compatible = "qcom,sm6115-dpu"; 1876 reg = <0x0 0x05e01000 0x0 0x8f000>, 1877 <0x0 0x05eb0000 0x0 0x3000>; 1878 reg-names = "mdp", "vbif"; 1879 1880 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1881 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1882 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1883 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1884 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1885 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1886 clock-names = "bus", 1887 "iface", 1888 "core", 1889 "lut", 1890 "rot", 1891 "vsync"; 1892 1893 operating-points-v2 = <&mdp_opp_table>; 1894 power-domains = <&rpmpd SM6115_VDDCX>; 1895 1896 interrupt-parent = <&mdss>; 1897 interrupts = <0>; 1898 1899 ports { 1900 #address-cells = <1>; 1901 #size-cells = <0>; 1902 1903 port@0 { 1904 reg = <0>; 1905 dpu_intf1_out: endpoint { 1906 remote-endpoint = <&mdss_dsi0_in>; 1907 }; 1908 }; 1909 }; 1910 1911 mdp_opp_table: opp-table { 1912 compatible = "operating-points-v2"; 1913 1914 opp-19200000 { 1915 opp-hz = /bits/ 64 <19200000>; 1916 required-opps = <&rpmpd_opp_min_svs>; 1917 }; 1918 1919 opp-192000000 { 1920 opp-hz = /bits/ 64 <192000000>; 1921 required-opps = <&rpmpd_opp_low_svs>; 1922 }; 1923 1924 opp-256000000 { 1925 opp-hz = /bits/ 64 <256000000>; 1926 required-opps = <&rpmpd_opp_svs>; 1927 }; 1928 1929 opp-307200000 { 1930 opp-hz = /bits/ 64 <307200000>; 1931 required-opps = <&rpmpd_opp_svs_plus>; 1932 }; 1933 1934 opp-384000000 { 1935 opp-hz = /bits/ 64 <384000000>; 1936 required-opps = <&rpmpd_opp_nom>; 1937 }; 1938 }; 1939 }; 1940 1941 mdss_dsi0: dsi@5e94000 { 1942 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1943 reg = <0x0 0x05e94000 0x0 0x400>; 1944 reg-names = "dsi_ctrl"; 1945 1946 interrupt-parent = <&mdss>; 1947 interrupts = <4>; 1948 1949 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1950 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1951 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1952 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1953 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1954 <&gcc GCC_DISP_HF_AXI_CLK>; 1955 clock-names = "byte", 1956 "byte_intf", 1957 "pixel", 1958 "core", 1959 "iface", 1960 "bus"; 1961 1962 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1963 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1964 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1965 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1966 1967 operating-points-v2 = <&dsi_opp_table>; 1968 power-domains = <&rpmpd SM6115_VDDCX>; 1969 phys = <&mdss_dsi0_phy>; 1970 1971 #address-cells = <1>; 1972 #size-cells = <0>; 1973 1974 status = "disabled"; 1975 1976 ports { 1977 #address-cells = <1>; 1978 #size-cells = <0>; 1979 1980 port@0 { 1981 reg = <0>; 1982 mdss_dsi0_in: endpoint { 1983 remote-endpoint = <&dpu_intf1_out>; 1984 }; 1985 }; 1986 1987 port@1 { 1988 reg = <1>; 1989 mdss_dsi0_out: endpoint { 1990 }; 1991 }; 1992 }; 1993 1994 dsi_opp_table: opp-table { 1995 compatible = "operating-points-v2"; 1996 1997 opp-19200000 { 1998 opp-hz = /bits/ 64 <19200000>; 1999 required-opps = <&rpmpd_opp_min_svs>; 2000 }; 2001 2002 opp-164000000 { 2003 opp-hz = /bits/ 64 <164000000>; 2004 required-opps = <&rpmpd_opp_low_svs>; 2005 }; 2006 2007 opp-187500000 { 2008 opp-hz = /bits/ 64 <187500000>; 2009 required-opps = <&rpmpd_opp_svs>; 2010 }; 2011 }; 2012 }; 2013 2014 mdss_dsi0_phy: phy@5e94400 { 2015 compatible = "qcom,dsi-phy-14nm-2290"; 2016 reg = <0x0 0x05e94400 0x0 0x100>, 2017 <0x0 0x05e94500 0x0 0x300>, 2018 <0x0 0x05e94800 0x0 0x188>; 2019 reg-names = "dsi_phy", 2020 "dsi_phy_lane", 2021 "dsi_pll"; 2022 2023 #clock-cells = <1>; 2024 #phy-cells = <0>; 2025 2026 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2027 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2028 clock-names = "iface", "ref"; 2029 2030 status = "disabled"; 2031 }; 2032 }; 2033 2034 dispcc: clock-controller@5f00000 { 2035 compatible = "qcom,sm6115-dispcc"; 2036 reg = <0x0 0x05f00000 0 0x20000>; 2037 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2038 <&sleep_clk>, 2039 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2040 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2041 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 2042 #clock-cells = <1>; 2043 #reset-cells = <1>; 2044 #power-domain-cells = <1>; 2045 }; 2046 2047 remoteproc_mpss: remoteproc@6080000 { 2048 compatible = "qcom,sm6115-mpss-pas"; 2049 reg = <0x0 0x06080000 0x0 0x10000>; 2050 2051 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 2052 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2053 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2054 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2055 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2056 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2057 interrupt-names = "wdog", "fatal", "ready", "handover", 2058 "stop-ack", "shutdown-ack"; 2059 2060 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2061 clock-names = "xo"; 2062 2063 power-domains = <&rpmpd SM6115_VDDCX>; 2064 2065 memory-region = <&pil_modem_mem>; 2066 2067 qcom,smem-states = <&modem_smp2p_out 0>; 2068 qcom,smem-state-names = "stop"; 2069 2070 status = "disabled"; 2071 2072 glink-edge { 2073 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 2074 label = "mpss"; 2075 qcom,remote-pid = <1>; 2076 mboxes = <&apcs_glb 12>; 2077 }; 2078 }; 2079 2080 stm@8002000 { 2081 compatible = "arm,coresight-stm", "arm,primecell"; 2082 reg = <0x0 0x08002000 0x0 0x1000>, 2083 <0x0 0x0e280000 0x0 0x180000>; 2084 reg-names = "stm-base", "stm-stimulus-base"; 2085 2086 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2087 clock-names = "apb_pclk"; 2088 2089 status = "disabled"; 2090 2091 out-ports { 2092 port { 2093 stm_out: endpoint { 2094 remote-endpoint = <&funnel_in0_in>; 2095 }; 2096 }; 2097 }; 2098 }; 2099 2100 cti0: cti@8010000 { 2101 compatible = "arm,coresight-cti", "arm,primecell"; 2102 reg = <0x0 0x08010000 0x0 0x1000>; 2103 2104 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2105 clock-names = "apb_pclk"; 2106 2107 status = "disabled"; 2108 }; 2109 2110 cti1: cti@8011000 { 2111 compatible = "arm,coresight-cti", "arm,primecell"; 2112 reg = <0x0 0x08011000 0x0 0x1000>; 2113 2114 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2115 clock-names = "apb_pclk"; 2116 2117 status = "disabled"; 2118 }; 2119 2120 cti2: cti@8012000 { 2121 compatible = "arm,coresight-cti", "arm,primecell"; 2122 reg = <0x0 0x08012000 0x0 0x1000>; 2123 2124 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2125 clock-names = "apb_pclk"; 2126 2127 status = "disabled"; 2128 }; 2129 2130 cti3: cti@8013000 { 2131 compatible = "arm,coresight-cti", "arm,primecell"; 2132 reg = <0x0 0x08013000 0x0 0x1000>; 2133 2134 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2135 clock-names = "apb_pclk"; 2136 2137 status = "disabled"; 2138 }; 2139 2140 cti4: cti@8014000 { 2141 compatible = "arm,coresight-cti", "arm,primecell"; 2142 reg = <0x0 0x08014000 0x0 0x1000>; 2143 2144 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2145 clock-names = "apb_pclk"; 2146 2147 status = "disabled"; 2148 }; 2149 2150 cti5: cti@8015000 { 2151 compatible = "arm,coresight-cti", "arm,primecell"; 2152 reg = <0x0 0x08015000 0x0 0x1000>; 2153 2154 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2155 clock-names = "apb_pclk"; 2156 2157 status = "disabled"; 2158 }; 2159 2160 cti6: cti@8016000 { 2161 compatible = "arm,coresight-cti", "arm,primecell"; 2162 reg = <0x0 0x08016000 0x0 0x1000>; 2163 2164 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2165 clock-names = "apb_pclk"; 2166 2167 status = "disabled"; 2168 }; 2169 2170 cti7: cti@8017000 { 2171 compatible = "arm,coresight-cti", "arm,primecell"; 2172 reg = <0x0 0x08017000 0x0 0x1000>; 2173 2174 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2175 clock-names = "apb_pclk"; 2176 2177 status = "disabled"; 2178 }; 2179 2180 cti8: cti@8018000 { 2181 compatible = "arm,coresight-cti", "arm,primecell"; 2182 reg = <0x0 0x08018000 0x0 0x1000>; 2183 2184 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2185 clock-names = "apb_pclk"; 2186 2187 status = "disabled"; 2188 }; 2189 2190 cti9: cti@8019000 { 2191 compatible = "arm,coresight-cti", "arm,primecell"; 2192 reg = <0x0 0x08019000 0x0 0x1000>; 2193 2194 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2195 clock-names = "apb_pclk"; 2196 2197 status = "disabled"; 2198 }; 2199 2200 cti10: cti@801a000 { 2201 compatible = "arm,coresight-cti", "arm,primecell"; 2202 reg = <0x0 0x0801a000 0x0 0x1000>; 2203 2204 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2205 clock-names = "apb_pclk"; 2206 2207 status = "disabled"; 2208 }; 2209 2210 cti11: cti@801b000 { 2211 compatible = "arm,coresight-cti", "arm,primecell"; 2212 reg = <0x0 0x0801b000 0x0 0x1000>; 2213 2214 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2215 clock-names = "apb_pclk"; 2216 2217 status = "disabled"; 2218 }; 2219 2220 cti12: cti@801c000 { 2221 compatible = "arm,coresight-cti", "arm,primecell"; 2222 reg = <0x0 0x0801c000 0x0 0x1000>; 2223 2224 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2225 clock-names = "apb_pclk"; 2226 2227 status = "disabled"; 2228 }; 2229 2230 cti13: cti@801d000 { 2231 compatible = "arm,coresight-cti", "arm,primecell"; 2232 reg = <0x0 0x0801d000 0x0 0x1000>; 2233 2234 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2235 clock-names = "apb_pclk"; 2236 2237 status = "disabled"; 2238 }; 2239 2240 cti14: cti@801e000 { 2241 compatible = "arm,coresight-cti", "arm,primecell"; 2242 reg = <0x0 0x0801e000 0x0 0x1000>; 2243 2244 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2245 clock-names = "apb_pclk"; 2246 2247 status = "disabled"; 2248 }; 2249 2250 cti15: cti@801f000 { 2251 compatible = "arm,coresight-cti", "arm,primecell"; 2252 reg = <0x0 0x0801f000 0x0 0x1000>; 2253 2254 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2255 clock-names = "apb_pclk"; 2256 2257 status = "disabled"; 2258 }; 2259 2260 replicator@8046000 { 2261 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2262 reg = <0x0 0x08046000 0x0 0x1000>; 2263 2264 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2265 clock-names = "apb_pclk"; 2266 2267 status = "disabled"; 2268 2269 out-ports { 2270 port { 2271 replicator_out: endpoint { 2272 remote-endpoint = <&etr_in>; 2273 }; 2274 }; 2275 }; 2276 2277 in-ports { 2278 port { 2279 replicator_in: endpoint { 2280 remote-endpoint = <&etf_out>; 2281 }; 2282 }; 2283 }; 2284 }; 2285 2286 etf@8047000 { 2287 compatible = "arm,coresight-tmc", "arm,primecell"; 2288 reg = <0x0 0x08047000 0x0 0x1000>; 2289 2290 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2291 clock-names = "apb_pclk"; 2292 2293 status = "disabled"; 2294 2295 in-ports { 2296 port { 2297 etf_in: endpoint { 2298 remote-endpoint = <&merge_funnel_out>; 2299 }; 2300 }; 2301 }; 2302 2303 out-ports { 2304 port { 2305 etf_out: endpoint { 2306 remote-endpoint = <&replicator_in>; 2307 }; 2308 }; 2309 }; 2310 }; 2311 2312 etr@8048000 { 2313 compatible = "arm,coresight-tmc", "arm,primecell"; 2314 reg = <0x0 0x08048000 0x0 0x1000>; 2315 2316 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2317 clock-names = "apb_pclk"; 2318 2319 status = "disabled"; 2320 2321 in-ports { 2322 port { 2323 etr_in: endpoint { 2324 remote-endpoint = <&replicator_out>; 2325 }; 2326 }; 2327 }; 2328 }; 2329 2330 funnel@8041000 { 2331 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2332 reg = <0x0 0x08041000 0x0 0x1000>; 2333 2334 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2335 clock-names = "apb_pclk"; 2336 2337 status = "disabled"; 2338 2339 out-ports { 2340 port { 2341 funnel_in0_out: endpoint { 2342 remote-endpoint = <&merge_funnel_in0>; 2343 }; 2344 }; 2345 }; 2346 2347 in-ports { 2348 port { 2349 funnel_in0_in: endpoint { 2350 remote-endpoint = <&stm_out>; 2351 }; 2352 }; 2353 }; 2354 }; 2355 2356 funnel@8042000 { 2357 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2358 reg = <0x0 0x08042000 0x0 0x1000>; 2359 2360 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2361 clock-names = "apb_pclk"; 2362 2363 status = "disabled"; 2364 2365 out-ports { 2366 port { 2367 funnel_in1_out: endpoint { 2368 remote-endpoint = <&merge_funnel_in1>; 2369 }; 2370 }; 2371 }; 2372 2373 in-ports { 2374 port { 2375 funnel_in1_in: endpoint { 2376 remote-endpoint = <&funnel_apss1_out>; 2377 }; 2378 }; 2379 }; 2380 }; 2381 2382 funnel@8045000 { 2383 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2384 reg = <0x0 0x08045000 0x0 0x1000>; 2385 2386 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2387 clock-names = "apb_pclk"; 2388 2389 status = "disabled"; 2390 2391 out-ports { 2392 port { 2393 merge_funnel_out: endpoint { 2394 remote-endpoint = <&etf_in>; 2395 }; 2396 }; 2397 }; 2398 2399 in-ports { 2400 #address-cells = <1>; 2401 #size-cells = <0>; 2402 2403 port@0 { 2404 reg = <0>; 2405 merge_funnel_in0: endpoint { 2406 remote-endpoint = <&funnel_in0_out>; 2407 }; 2408 }; 2409 2410 port@1 { 2411 reg = <1>; 2412 merge_funnel_in1: endpoint { 2413 remote-endpoint = <&funnel_in1_out>; 2414 }; 2415 }; 2416 }; 2417 }; 2418 2419 etm@9040000 { 2420 compatible = "arm,coresight-etm4x", "arm,primecell"; 2421 reg = <0x0 0x09040000 0x0 0x1000>; 2422 2423 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2424 clock-names = "apb_pclk"; 2425 arm,coresight-loses-context-with-cpu; 2426 2427 cpu = <&cpu0>; 2428 2429 status = "disabled"; 2430 2431 out-ports { 2432 port { 2433 etm0_out: endpoint { 2434 remote-endpoint = <&funnel_apss0_in0>; 2435 }; 2436 }; 2437 }; 2438 }; 2439 2440 etm@9140000 { 2441 compatible = "arm,coresight-etm4x", "arm,primecell"; 2442 reg = <0x0 0x09140000 0x0 0x1000>; 2443 2444 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2445 clock-names = "apb_pclk"; 2446 arm,coresight-loses-context-with-cpu; 2447 2448 cpu = <&cpu1>; 2449 2450 status = "disabled"; 2451 2452 out-ports { 2453 port { 2454 etm1_out: endpoint { 2455 remote-endpoint = <&funnel_apss0_in1>; 2456 }; 2457 }; 2458 }; 2459 }; 2460 2461 etm@9240000 { 2462 compatible = "arm,coresight-etm4x", "arm,primecell"; 2463 reg = <0x0 0x09240000 0x0 0x1000>; 2464 2465 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2466 clock-names = "apb_pclk"; 2467 arm,coresight-loses-context-with-cpu; 2468 2469 cpu = <&cpu2>; 2470 2471 status = "disabled"; 2472 2473 out-ports { 2474 port { 2475 etm2_out: endpoint { 2476 remote-endpoint = <&funnel_apss0_in2>; 2477 }; 2478 }; 2479 }; 2480 }; 2481 2482 etm@9340000 { 2483 compatible = "arm,coresight-etm4x", "arm,primecell"; 2484 reg = <0x0 0x09340000 0x0 0x1000>; 2485 2486 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2487 clock-names = "apb_pclk"; 2488 arm,coresight-loses-context-with-cpu; 2489 2490 cpu = <&cpu3>; 2491 2492 status = "disabled"; 2493 2494 out-ports { 2495 port { 2496 etm3_out: endpoint { 2497 remote-endpoint = <&funnel_apss0_in3>; 2498 }; 2499 }; 2500 }; 2501 }; 2502 2503 etm@9440000 { 2504 compatible = "arm,coresight-etm4x", "arm,primecell"; 2505 reg = <0x0 0x09440000 0x0 0x1000>; 2506 2507 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2508 clock-names = "apb_pclk"; 2509 arm,coresight-loses-context-with-cpu; 2510 2511 cpu = <&cpu4>; 2512 2513 status = "disabled"; 2514 2515 out-ports { 2516 port { 2517 etm4_out: endpoint { 2518 remote-endpoint = <&funnel_apss0_in4>; 2519 }; 2520 }; 2521 }; 2522 }; 2523 2524 etm@9540000 { 2525 compatible = "arm,coresight-etm4x", "arm,primecell"; 2526 reg = <0x0 0x09540000 0x0 0x1000>; 2527 2528 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2529 clock-names = "apb_pclk"; 2530 arm,coresight-loses-context-with-cpu; 2531 2532 cpu = <&cpu5>; 2533 2534 status = "disabled"; 2535 2536 out-ports { 2537 port { 2538 etm5_out: endpoint { 2539 remote-endpoint = <&funnel_apss0_in5>; 2540 }; 2541 }; 2542 }; 2543 }; 2544 2545 etm@9640000 { 2546 compatible = "arm,coresight-etm4x", "arm,primecell"; 2547 reg = <0x0 0x09640000 0x0 0x1000>; 2548 2549 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2550 clock-names = "apb_pclk"; 2551 arm,coresight-loses-context-with-cpu; 2552 2553 cpu = <&cpu6>; 2554 2555 status = "disabled"; 2556 2557 out-ports { 2558 port { 2559 etm6_out: endpoint { 2560 remote-endpoint = <&funnel_apss0_in6>; 2561 }; 2562 }; 2563 }; 2564 }; 2565 2566 etm@9740000 { 2567 compatible = "arm,coresight-etm4x", "arm,primecell"; 2568 reg = <0x0 0x09740000 0x0 0x1000>; 2569 2570 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2571 clock-names = "apb_pclk"; 2572 arm,coresight-loses-context-with-cpu; 2573 2574 cpu = <&cpu7>; 2575 2576 status = "disabled"; 2577 2578 out-ports { 2579 port { 2580 etm7_out: endpoint { 2581 remote-endpoint = <&funnel_apss0_in7>; 2582 }; 2583 }; 2584 }; 2585 }; 2586 2587 funnel@9800000 { 2588 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2589 reg = <0x0 0x09800000 0x0 0x1000>; 2590 2591 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2592 clock-names = "apb_pclk"; 2593 2594 status = "disabled"; 2595 2596 out-ports { 2597 port { 2598 funnel_apss0_out: endpoint { 2599 remote-endpoint = <&funnel_apss1_in>; 2600 }; 2601 }; 2602 }; 2603 2604 in-ports { 2605 #address-cells = <1>; 2606 #size-cells = <0>; 2607 2608 port@0 { 2609 reg = <0>; 2610 funnel_apss0_in0: endpoint { 2611 remote-endpoint = <&etm0_out>; 2612 }; 2613 }; 2614 2615 port@1 { 2616 reg = <1>; 2617 funnel_apss0_in1: endpoint { 2618 remote-endpoint = <&etm1_out>; 2619 }; 2620 }; 2621 2622 port@2 { 2623 reg = <2>; 2624 funnel_apss0_in2: endpoint { 2625 remote-endpoint = <&etm2_out>; 2626 }; 2627 }; 2628 2629 port@3 { 2630 reg = <3>; 2631 funnel_apss0_in3: endpoint { 2632 remote-endpoint = <&etm3_out>; 2633 }; 2634 }; 2635 2636 port@4 { 2637 reg = <4>; 2638 funnel_apss0_in4: endpoint { 2639 remote-endpoint = <&etm4_out>; 2640 }; 2641 }; 2642 2643 port@5 { 2644 reg = <5>; 2645 funnel_apss0_in5: endpoint { 2646 remote-endpoint = <&etm5_out>; 2647 }; 2648 }; 2649 2650 port@6 { 2651 reg = <6>; 2652 funnel_apss0_in6: endpoint { 2653 remote-endpoint = <&etm6_out>; 2654 }; 2655 }; 2656 2657 port@7 { 2658 reg = <7>; 2659 funnel_apss0_in7: endpoint { 2660 remote-endpoint = <&etm7_out>; 2661 }; 2662 }; 2663 }; 2664 }; 2665 2666 funnel@9810000 { 2667 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2668 reg = <0x0 0x09810000 0x0 0x1000>; 2669 2670 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2671 clock-names = "apb_pclk"; 2672 2673 status = "disabled"; 2674 2675 out-ports { 2676 port { 2677 funnel_apss1_out: endpoint { 2678 remote-endpoint = <&funnel_in1_in>; 2679 }; 2680 }; 2681 }; 2682 2683 in-ports { 2684 port { 2685 funnel_apss1_in: endpoint { 2686 remote-endpoint = <&funnel_apss0_out>; 2687 }; 2688 }; 2689 }; 2690 }; 2691 2692 remoteproc_adsp: remoteproc@a400000 { 2693 compatible = "qcom,sm6115-adsp-pas"; 2694 reg = <0x0 0x0a400000 0x0 0x4040>; 2695 2696 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2697 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2698 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2699 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2700 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2701 interrupt-names = "wdog", "fatal", "ready", 2702 "handover", "stop-ack"; 2703 2704 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2705 clock-names = "xo"; 2706 2707 power-domains = <&rpmpd SM6115_VDD_LPI_CX>, 2708 <&rpmpd SM6115_VDD_LPI_MX>; 2709 2710 memory-region = <&pil_adsp_mem>; 2711 2712 qcom,smem-states = <&adsp_smp2p_out 0>; 2713 qcom,smem-state-names = "stop"; 2714 2715 status = "disabled"; 2716 2717 glink-edge { 2718 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2719 label = "lpass"; 2720 qcom,remote-pid = <2>; 2721 mboxes = <&apcs_glb 8>; 2722 2723 apr { 2724 compatible = "qcom,apr-v2"; 2725 qcom,glink-channels = "apr_audio_svc"; 2726 qcom,domain = <APR_DOMAIN_ADSP>; 2727 #address-cells = <1>; 2728 #size-cells = <0>; 2729 2730 service@3 { 2731 reg = <APR_SVC_ADSP_CORE>; 2732 compatible = "qcom,q6core"; 2733 qcom,protection-domain = "avs/audio", 2734 "msm/adsp/audio_pd"; 2735 }; 2736 2737 q6afe: service@4 { 2738 compatible = "qcom,q6afe"; 2739 reg = <APR_SVC_AFE>; 2740 qcom,protection-domain = "avs/audio", 2741 "msm/adsp/audio_pd"; 2742 q6afedai: dais { 2743 compatible = "qcom,q6afe-dais"; 2744 #address-cells = <1>; 2745 #size-cells = <0>; 2746 #sound-dai-cells = <1>; 2747 }; 2748 2749 q6afecc: clock-controller { 2750 compatible = "qcom,q6afe-clocks"; 2751 #clock-cells = <2>; 2752 }; 2753 }; 2754 2755 q6asm: service@7 { 2756 compatible = "qcom,q6asm"; 2757 reg = <APR_SVC_ASM>; 2758 qcom,protection-domain = "avs/audio", 2759 "msm/adsp/audio_pd"; 2760 q6asmdai: dais { 2761 compatible = "qcom,q6asm-dais"; 2762 #address-cells = <1>; 2763 #size-cells = <0>; 2764 #sound-dai-cells = <1>; 2765 iommus = <&apps_smmu 0x1c1 0x0>; 2766 2767 dai@0 { 2768 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 2769 }; 2770 2771 dai@1 { 2772 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 2773 }; 2774 2775 dai@2 { 2776 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 2777 }; 2778 }; 2779 }; 2780 2781 q6adm: service@8 { 2782 compatible = "qcom,q6adm"; 2783 reg = <APR_SVC_ADM>; 2784 qcom,protection-domain = "avs/audio", 2785 "msm/adsp/audio_pd"; 2786 q6routing: routing { 2787 compatible = "qcom,q6adm-routing"; 2788 #sound-dai-cells = <0>; 2789 }; 2790 }; 2791 }; 2792 2793 fastrpc { 2794 compatible = "qcom,fastrpc"; 2795 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2796 label = "adsp"; 2797 qcom,non-secure-domain; 2798 #address-cells = <1>; 2799 #size-cells = <0>; 2800 2801 compute-cb@3 { 2802 compatible = "qcom,fastrpc-compute-cb"; 2803 reg = <3>; 2804 iommus = <&apps_smmu 0x01c3 0x0>; 2805 }; 2806 2807 compute-cb@4 { 2808 compatible = "qcom,fastrpc-compute-cb"; 2809 reg = <4>; 2810 iommus = <&apps_smmu 0x01c4 0x0>; 2811 }; 2812 2813 compute-cb@5 { 2814 compatible = "qcom,fastrpc-compute-cb"; 2815 reg = <5>; 2816 iommus = <&apps_smmu 0x01c5 0x0>; 2817 }; 2818 2819 compute-cb@6 { 2820 compatible = "qcom,fastrpc-compute-cb"; 2821 reg = <6>; 2822 iommus = <&apps_smmu 0x01c6 0x0>; 2823 }; 2824 2825 compute-cb@7 { 2826 compatible = "qcom,fastrpc-compute-cb"; 2827 reg = <7>; 2828 iommus = <&apps_smmu 0x01c7 0x0>; 2829 }; 2830 }; 2831 }; 2832 }; 2833 2834 remoteproc_cdsp: remoteproc@b300000 { 2835 compatible = "qcom,sm6115-cdsp-pas"; 2836 reg = <0x0 0x0b300000 0x0 0x4040>; 2837 2838 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 2839 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2840 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2841 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2842 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2843 interrupt-names = "wdog", "fatal", "ready", 2844 "handover", "stop-ack"; 2845 2846 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2847 clock-names = "xo"; 2848 2849 power-domains = <&rpmpd SM6115_VDDCX>; 2850 2851 memory-region = <&pil_cdsp_mem>; 2852 2853 qcom,smem-states = <&cdsp_smp2p_out 0>; 2854 qcom,smem-state-names = "stop"; 2855 2856 status = "disabled"; 2857 2858 glink-edge { 2859 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>; 2860 label = "cdsp"; 2861 qcom,remote-pid = <5>; 2862 mboxes = <&apcs_glb 28>; 2863 2864 fastrpc { 2865 compatible = "qcom,fastrpc"; 2866 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2867 label = "cdsp"; 2868 qcom,non-secure-domain; 2869 #address-cells = <1>; 2870 #size-cells = <0>; 2871 2872 compute-cb@1 { 2873 compatible = "qcom,fastrpc-compute-cb"; 2874 reg = <1>; 2875 iommus = <&apps_smmu 0x0c01 0x0>; 2876 }; 2877 2878 compute-cb@2 { 2879 compatible = "qcom,fastrpc-compute-cb"; 2880 reg = <2>; 2881 iommus = <&apps_smmu 0x0c02 0x0>; 2882 }; 2883 2884 compute-cb@3 { 2885 compatible = "qcom,fastrpc-compute-cb"; 2886 reg = <3>; 2887 iommus = <&apps_smmu 0x0c03 0x0>; 2888 }; 2889 2890 compute-cb@4 { 2891 compatible = "qcom,fastrpc-compute-cb"; 2892 reg = <4>; 2893 iommus = <&apps_smmu 0x0c04 0x0>; 2894 }; 2895 2896 compute-cb@5 { 2897 compatible = "qcom,fastrpc-compute-cb"; 2898 reg = <5>; 2899 iommus = <&apps_smmu 0x0c05 0x0>; 2900 }; 2901 2902 compute-cb@6 { 2903 compatible = "qcom,fastrpc-compute-cb"; 2904 reg = <6>; 2905 iommus = <&apps_smmu 0x0c06 0x0>; 2906 }; 2907 2908 /* note: secure cb9 in downstream */ 2909 }; 2910 }; 2911 }; 2912 2913 apps_smmu: iommu@c600000 { 2914 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2915 reg = <0x0 0x0c600000 0x0 0x80000>; 2916 #iommu-cells = <2>; 2917 #global-interrupts = <1>; 2918 2919 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2920 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2921 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2922 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2923 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2924 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2925 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2926 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2927 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2928 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2929 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2930 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2931 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2932 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2933 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2934 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2935 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2936 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2937 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2938 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2939 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2940 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2941 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2942 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2943 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2944 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2945 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2946 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2947 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2948 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2949 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2950 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2951 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2952 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2953 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2954 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2955 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2956 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2957 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2958 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2959 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2960 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2961 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2962 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2963 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2964 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2965 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2966 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2967 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2968 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2969 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2970 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2971 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2972 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2973 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2974 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2975 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2976 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2977 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2978 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2979 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2980 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2981 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2982 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2983 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2984 }; 2985 2986 wifi: wifi@c800000 { 2987 compatible = "qcom,wcn3990-wifi"; 2988 reg = <0x0 0x0c800000 0x0 0x800000>; 2989 reg-names = "membase"; 2990 memory-region = <&wlan_msa_mem>; 2991 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2992 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2993 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2994 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2995 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2996 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2997 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2998 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2999 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 3000 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 3001 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 3002 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 3003 iommus = <&apps_smmu 0x1a0 0x1>; 3004 qcom,msa-fixed-perm; 3005 status = "disabled"; 3006 }; 3007 3008 watchdog@f017000 { 3009 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; 3010 reg = <0x0 0x0f017000 0x0 0x1000>; 3011 clocks = <&sleep_clk>; 3012 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 3013 }; 3014 3015 apcs_glb: mailbox@f111000 { 3016 compatible = "qcom,sm6115-apcs-hmss-global", 3017 "qcom,msm8994-apcs-kpss-global"; 3018 reg = <0x0 0x0f111000 0x0 0x1000>; 3019 3020 #mbox-cells = <1>; 3021 }; 3022 3023 timer@f120000 { 3024 compatible = "arm,armv7-timer-mem"; 3025 reg = <0x0 0x0f120000 0x0 0x1000>; 3026 #address-cells = <2>; 3027 #size-cells = <1>; 3028 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 3029 clock-frequency = <19200000>; 3030 3031 frame@f121000 { 3032 reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>; 3033 frame-number = <0>; 3034 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3035 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 3036 }; 3037 3038 frame@f123000 { 3039 reg = <0x0 0x0f123000 0x1000>; 3040 frame-number = <1>; 3041 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3042 status = "disabled"; 3043 }; 3044 3045 frame@f124000 { 3046 reg = <0x0 0x0f124000 0x1000>; 3047 frame-number = <2>; 3048 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3049 status = "disabled"; 3050 }; 3051 3052 frame@f125000 { 3053 reg = <0x0 0x0f125000 0x1000>; 3054 frame-number = <3>; 3055 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3056 status = "disabled"; 3057 }; 3058 3059 frame@f126000 { 3060 reg = <0x0 0x0f126000 0x1000>; 3061 frame-number = <4>; 3062 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3063 status = "disabled"; 3064 }; 3065 3066 frame@f127000 { 3067 reg = <0x0 0x0f127000 0x1000>; 3068 frame-number = <5>; 3069 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3070 status = "disabled"; 3071 }; 3072 3073 frame@f128000 { 3074 reg = <0x0 0x0f128000 0x1000>; 3075 frame-number = <6>; 3076 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3077 status = "disabled"; 3078 }; 3079 }; 3080 3081 intc: interrupt-controller@f200000 { 3082 compatible = "arm,gic-v3"; 3083 reg = <0x0 0x0f200000 0x0 0x10000>, 3084 <0x0 0x0f300000 0x0 0x100000>; 3085 #interrupt-cells = <3>; 3086 interrupt-controller; 3087 interrupt-parent = <&intc>; 3088 #redistributor-regions = <1>; 3089 redistributor-stride = <0x0 0x20000>; 3090 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3091 }; 3092 3093 cpufreq_hw: cpufreq@f521000 { 3094 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; 3095 reg = <0x0 0x0f521000 0x0 0x1000>, 3096 <0x0 0x0f523000 0x0 0x1000>; 3097 3098 reg-names = "freq-domain0", "freq-domain1"; 3099 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 3100 clock-names = "xo", "alternate"; 3101 3102 #freq-domain-cells = <1>; 3103 #clock-cells = <1>; 3104 }; 3105 }; 3106 3107 thermal-zones { 3108 mapss-thermal { 3109 thermal-sensors = <&tsens0 0>; 3110 3111 trips { 3112 trip-point0 { 3113 temperature = <115000>; 3114 hysteresis = <5000>; 3115 type = "passive"; 3116 }; 3117 3118 trip-point1 { 3119 temperature = <125000>; 3120 hysteresis = <1000>; 3121 type = "passive"; 3122 }; 3123 }; 3124 }; 3125 3126 cdsp-hvx-thermal { 3127 thermal-sensors = <&tsens0 1>; 3128 3129 trips { 3130 trip-point0 { 3131 temperature = <115000>; 3132 hysteresis = <5000>; 3133 type = "passive"; 3134 }; 3135 3136 trip-point1 { 3137 temperature = <125000>; 3138 hysteresis = <1000>; 3139 type = "passive"; 3140 }; 3141 }; 3142 }; 3143 3144 wlan-thermal { 3145 thermal-sensors = <&tsens0 2>; 3146 3147 trips { 3148 trip-point0 { 3149 temperature = <115000>; 3150 hysteresis = <5000>; 3151 type = "passive"; 3152 }; 3153 3154 trip-point1 { 3155 temperature = <125000>; 3156 hysteresis = <1000>; 3157 type = "passive"; 3158 }; 3159 }; 3160 }; 3161 3162 camera-thermal { 3163 thermal-sensors = <&tsens0 3>; 3164 3165 trips { 3166 trip-point0 { 3167 temperature = <115000>; 3168 hysteresis = <5000>; 3169 type = "passive"; 3170 }; 3171 3172 trip-point1 { 3173 temperature = <125000>; 3174 hysteresis = <1000>; 3175 type = "passive"; 3176 }; 3177 }; 3178 }; 3179 3180 video-thermal { 3181 thermal-sensors = <&tsens0 4>; 3182 3183 trips { 3184 trip-point0 { 3185 temperature = <115000>; 3186 hysteresis = <5000>; 3187 type = "passive"; 3188 }; 3189 3190 trip-point1 { 3191 temperature = <125000>; 3192 hysteresis = <1000>; 3193 type = "passive"; 3194 }; 3195 }; 3196 }; 3197 3198 modem1-thermal { 3199 thermal-sensors = <&tsens0 5>; 3200 3201 trips { 3202 trip-point0 { 3203 temperature = <115000>; 3204 hysteresis = <5000>; 3205 type = "passive"; 3206 }; 3207 3208 trip-point1 { 3209 temperature = <125000>; 3210 hysteresis = <1000>; 3211 type = "passive"; 3212 }; 3213 }; 3214 }; 3215 3216 cpu4-thermal { 3217 thermal-sensors = <&tsens0 6>; 3218 3219 trips { 3220 cpu4_alert0: trip-point0 { 3221 temperature = <90000>; 3222 hysteresis = <2000>; 3223 type = "passive"; 3224 }; 3225 3226 cpu4_alert1: trip-point1 { 3227 temperature = <95000>; 3228 hysteresis = <2000>; 3229 type = "passive"; 3230 }; 3231 3232 cpu4_crit: cpu-crit { 3233 temperature = <110000>; 3234 hysteresis = <1000>; 3235 type = "critical"; 3236 }; 3237 }; 3238 }; 3239 3240 cpu5-thermal { 3241 thermal-sensors = <&tsens0 7>; 3242 3243 trips { 3244 cpu5_alert0: trip-point0 { 3245 temperature = <90000>; 3246 hysteresis = <2000>; 3247 type = "passive"; 3248 }; 3249 3250 cpu5_alert1: trip-point1 { 3251 temperature = <95000>; 3252 hysteresis = <2000>; 3253 type = "passive"; 3254 }; 3255 3256 cpu5_crit: cpu-crit { 3257 temperature = <110000>; 3258 hysteresis = <1000>; 3259 type = "critical"; 3260 }; 3261 }; 3262 }; 3263 3264 cpu6-thermal { 3265 thermal-sensors = <&tsens0 8>; 3266 3267 trips { 3268 cpu6_alert0: trip-point0 { 3269 temperature = <90000>; 3270 hysteresis = <2000>; 3271 type = "passive"; 3272 }; 3273 3274 cpu6_alert1: trip-point1 { 3275 temperature = <95000>; 3276 hysteresis = <2000>; 3277 type = "passive"; 3278 }; 3279 3280 cpu6_crit: cpu-crit { 3281 temperature = <110000>; 3282 hysteresis = <1000>; 3283 type = "critical"; 3284 }; 3285 }; 3286 }; 3287 3288 cpu7-thermal { 3289 thermal-sensors = <&tsens0 9>; 3290 3291 trips { 3292 cpu7_alert0: trip-point0 { 3293 temperature = <90000>; 3294 hysteresis = <2000>; 3295 type = "passive"; 3296 }; 3297 3298 cpu7_alert1: trip-point1 { 3299 temperature = <95000>; 3300 hysteresis = <2000>; 3301 type = "passive"; 3302 }; 3303 3304 cpu7_crit: cpu-crit { 3305 temperature = <110000>; 3306 hysteresis = <1000>; 3307 type = "critical"; 3308 }; 3309 }; 3310 }; 3311 3312 cpu45-thermal { 3313 thermal-sensors = <&tsens0 10>; 3314 3315 trips { 3316 cpu45_alert0: trip-point0 { 3317 temperature = <90000>; 3318 hysteresis = <2000>; 3319 type = "passive"; 3320 }; 3321 3322 cpu45_alert1: trip-point1 { 3323 temperature = <95000>; 3324 hysteresis = <2000>; 3325 type = "passive"; 3326 }; 3327 3328 cpu45_crit: cpu-crit { 3329 temperature = <110000>; 3330 hysteresis = <1000>; 3331 type = "critical"; 3332 }; 3333 }; 3334 }; 3335 3336 cpu67-thermal { 3337 thermal-sensors = <&tsens0 11>; 3338 3339 trips { 3340 cpu67_alert0: trip-point0 { 3341 temperature = <90000>; 3342 hysteresis = <2000>; 3343 type = "passive"; 3344 }; 3345 3346 cpu67_alert1: trip-point1 { 3347 temperature = <95000>; 3348 hysteresis = <2000>; 3349 type = "passive"; 3350 }; 3351 3352 cpu67_crit: cpu-crit { 3353 temperature = <110000>; 3354 hysteresis = <1000>; 3355 type = "critical"; 3356 }; 3357 }; 3358 }; 3359 3360 cpu0123-thermal { 3361 thermal-sensors = <&tsens0 12>; 3362 3363 trips { 3364 cpu0123_alert0: trip-point0 { 3365 temperature = <90000>; 3366 hysteresis = <2000>; 3367 type = "passive"; 3368 }; 3369 3370 cpu0123_alert1: trip-point1 { 3371 temperature = <95000>; 3372 hysteresis = <2000>; 3373 type = "passive"; 3374 }; 3375 3376 cpu0123_crit: cpu-crit { 3377 temperature = <110000>; 3378 hysteresis = <1000>; 3379 type = "critical"; 3380 }; 3381 }; 3382 }; 3383 3384 modem0-thermal { 3385 thermal-sensors = <&tsens0 13>; 3386 3387 trips { 3388 trip-point0 { 3389 temperature = <115000>; 3390 hysteresis = <5000>; 3391 type = "passive"; 3392 }; 3393 3394 trip-point1 { 3395 temperature = <125000>; 3396 hysteresis = <1000>; 3397 type = "passive"; 3398 }; 3399 }; 3400 }; 3401 3402 display-thermal { 3403 thermal-sensors = <&tsens0 14>; 3404 3405 trips { 3406 trip-point0 { 3407 temperature = <115000>; 3408 hysteresis = <5000>; 3409 type = "passive"; 3410 }; 3411 3412 trip-point1 { 3413 temperature = <125000>; 3414 hysteresis = <1000>; 3415 type = "passive"; 3416 }; 3417 }; 3418 }; 3419 3420 gpu-thermal { 3421 polling-delay-passive = <250>; 3422 3423 thermal-sensors = <&tsens0 15>; 3424 3425 cooling-maps { 3426 map0 { 3427 trip = <&gpu_alert0>; 3428 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3429 }; 3430 }; 3431 3432 trips { 3433 gpu_alert0: trip-point0 { 3434 temperature = <85000>; 3435 hysteresis = <1000>; 3436 type = "passive"; 3437 }; 3438 3439 trip-point1 { 3440 temperature = <110000>; 3441 hysteresis = <1000>; 3442 type = "critical"; 3443 }; 3444 }; 3445 }; 3446 }; 3447 3448 timer { 3449 compatible = "arm,armv8-timer"; 3450 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3451 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3452 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3453 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3454 }; 3455}; 3456