1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm4450-camcc.h> 8#include <dt-bindings/clock/qcom,sm4450-dispcc.h> 9#include <dt-bindings/clock/qcom,sm4450-gcc.h> 10#include <dt-bindings/clock/qcom,sm4450-gpucc.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/power/qcom,rpmhpd.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,rpmh-rsc.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 chosen { }; 24 25 clocks { 26 xo_board: xo-board { 27 compatible = "fixed-clock"; 28 clock-frequency = <76800000>; 29 #clock-cells = <0>; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 clock-frequency = <32764>; 35 #clock-cells = <0>; 36 }; 37 38 bi_tcxo_div2: bi-tcxo-div2-clk { 39 #clock-cells = <0>; 40 compatible = "fixed-factor-clock"; 41 clocks = <&rpmhcc RPMH_CXO_CLK>; 42 clock-mult = <1>; 43 clock-div = <2>; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a55"; 54 reg = <0x0 0x0>; 55 clocks = <&cpufreq_hw 0>; 56 enable-method = "psci"; 57 next-level-cache = <&l2_0>; 58 power-domains = <&cpu_pd0>; 59 power-domain-names = "psci"; 60 qcom,freq-domain = <&cpufreq_hw 0>; 61 #cooling-cells = <2>; 62 63 l2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&l3_0>; 68 69 l3_0: l3-cache { 70 compatible = "cache"; 71 cache-level = <3>; 72 cache-unified; 73 }; 74 }; 75 }; 76 77 cpu1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a55"; 80 reg = <0x0 0x100>; 81 clocks = <&cpufreq_hw 0>; 82 enable-method = "psci"; 83 next-level-cache = <&l2_100>; 84 power-domains = <&cpu_pd0>; 85 power-domain-names = "psci"; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 #cooling-cells = <2>; 88 89 l2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&l3_0>; 94 }; 95 }; 96 97 cpu2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a55"; 100 reg = <0x0 0x200>; 101 clocks = <&cpufreq_hw 0>; 102 enable-method = "psci"; 103 next-level-cache = <&l2_200>; 104 power-domains = <&cpu_pd0>; 105 power-domain-names = "psci"; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 #cooling-cells = <2>; 108 109 l2_200: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 next-level-cache = <&l3_0>; 114 }; 115 }; 116 117 cpu3: cpu@300 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a55"; 120 reg = <0x0 0x300>; 121 clocks = <&cpufreq_hw 0>; 122 enable-method = "psci"; 123 next-level-cache = <&l2_300>; 124 power-domains = <&cpu_pd0>; 125 power-domain-names = "psci"; 126 qcom,freq-domain = <&cpufreq_hw 0>; 127 #cooling-cells = <2>; 128 129 l2_300: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&l3_0>; 134 }; 135 }; 136 137 cpu4: cpu@400 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a55"; 140 reg = <0x0 0x400>; 141 clocks = <&cpufreq_hw 0>; 142 enable-method = "psci"; 143 next-level-cache = <&l2_400>; 144 power-domains = <&cpu_pd0>; 145 power-domain-names = "psci"; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 #cooling-cells = <2>; 148 149 l2_400: l2-cache { 150 compatible = "cache"; 151 cache-level = <2>; 152 cache-unified; 153 next-level-cache = <&l3_0>; 154 }; 155 }; 156 157 cpu5: cpu@500 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a55"; 160 reg = <0x0 0x500>; 161 clocks = <&cpufreq_hw 0>; 162 enable-method = "psci"; 163 next-level-cache = <&l2_500>; 164 power-domains = <&cpu_pd0>; 165 power-domain-names = "psci"; 166 qcom,freq-domain = <&cpufreq_hw 0>; 167 #cooling-cells = <2>; 168 169 l2_500: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-unified; 173 next-level-cache = <&l3_0>; 174 }; 175 }; 176 177 cpu6: cpu@600 { 178 device_type = "cpu"; 179 compatible = "arm,cortex-a78"; 180 reg = <0x0 0x600>; 181 clocks = <&cpufreq_hw 1>; 182 enable-method = "psci"; 183 next-level-cache = <&l2_600>; 184 power-domains = <&cpu_pd0>; 185 power-domain-names = "psci"; 186 qcom,freq-domain = <&cpufreq_hw 1>; 187 #cooling-cells = <2>; 188 189 l2_600: l2-cache { 190 compatible = "cache"; 191 cache-level = <2>; 192 cache-unified; 193 next-level-cache = <&l3_0>; 194 }; 195 }; 196 197 cpu7: cpu@700 { 198 device_type = "cpu"; 199 compatible = "arm,cortex-a78"; 200 reg = <0x0 0x700>; 201 clocks = <&cpufreq_hw 1>; 202 enable-method = "psci"; 203 next-level-cache = <&l2_700>; 204 power-domains = <&cpu_pd0>; 205 power-domain-names = "psci"; 206 qcom,freq-domain = <&cpufreq_hw 1>; 207 #cooling-cells = <2>; 208 209 l2_700: l2-cache { 210 compatible = "cache"; 211 cache-level = <2>; 212 cache-unified; 213 next-level-cache = <&l3_0>; 214 }; 215 }; 216 217 cpu-map { 218 cluster0 { 219 core0 { 220 cpu = <&cpu0>; 221 }; 222 223 core1 { 224 cpu = <&cpu1>; 225 }; 226 227 core2 { 228 cpu = <&cpu2>; 229 }; 230 231 core3 { 232 cpu = <&cpu3>; 233 }; 234 235 core4 { 236 cpu = <&cpu4>; 237 }; 238 239 core5 { 240 cpu = <&cpu5>; 241 }; 242 243 core6 { 244 cpu = <&cpu6>; 245 }; 246 247 core7 { 248 cpu = <&cpu7>; 249 }; 250 }; 251 }; 252 253 idle-states { 254 entry-method = "psci"; 255 256 little_cpu_sleep_0: cpu-sleep-0-0 { 257 compatible = "arm,idle-state"; 258 arm,psci-suspend-param = <0x40000004>; 259 entry-latency-us = <800>; 260 exit-latency-us = <750>; 261 min-residency-us = <4090>; 262 local-timer-stop; 263 }; 264 265 big_cpu_sleep_0: cpu-sleep-1-0 { 266 compatible = "arm,idle-state"; 267 arm,psci-suspend-param = <0x40000004>; 268 entry-latency-us = <600>; 269 exit-latency-us = <1550>; 270 min-residency-us = <4791>; 271 local-timer-stop; 272 }; 273 }; 274 275 domain-idle-states { 276 cluster_sleep_0: cluster-sleep-0 { 277 compatible = "domain-idle-state"; 278 arm,psci-suspend-param = <0x41000044>; 279 entry-latency-us = <1050>; 280 exit-latency-us = <2500>; 281 min-residency-us = <5309>; 282 }; 283 284 cluster_sleep_1: cluster-sleep-1 { 285 compatible = "domain-idle-state"; 286 arm,psci-suspend-param = <0x41003344>; 287 entry-latency-us = <1561>; 288 exit-latency-us = <2801>; 289 min-residency-us = <8550>; 290 }; 291 }; 292 }; 293 294 memory@a0000000 { 295 device_type = "memory"; 296 /* We expect the bootloader to fill in the size */ 297 reg = <0x0 0xa0000000 0x0 0x0>; 298 }; 299 300 pmu-a55 { 301 compatible = "arm,cortex-a55-pmu"; 302 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 303 }; 304 305 pmu-a78 { 306 compatible = "arm,cortex-a78-pmu"; 307 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 308 }; 309 310 psci { 311 compatible = "arm,psci-1.0"; 312 method = "smc"; 313 314 cpu_pd0: power-domain-cpu0 { 315 #power-domain-cells = <0>; 316 power-domains = <&cluster_pd>; 317 domain-idle-states = <&little_cpu_sleep_0>; 318 }; 319 320 cpu_pd1: power-domain-cpu1 { 321 #power-domain-cells = <0>; 322 power-domains = <&cluster_pd>; 323 domain-idle-states = <&little_cpu_sleep_0>; 324 }; 325 326 cpu_pd2: power-domain-cpu2 { 327 #power-domain-cells = <0>; 328 power-domains = <&cluster_pd>; 329 domain-idle-states = <&little_cpu_sleep_0>; 330 }; 331 332 cpu_pd3: power-domain-cpu3 { 333 #power-domain-cells = <0>; 334 power-domains = <&cluster_pd>; 335 domain-idle-states = <&little_cpu_sleep_0>; 336 }; 337 338 cpu_pd4: power-domain-cpu4 { 339 #power-domain-cells = <0>; 340 power-domains = <&cluster_pd>; 341 domain-idle-states = <&big_cpu_sleep_0>; 342 }; 343 344 cpu_pd5: power-domain-cpu5 { 345 #power-domain-cells = <0>; 346 power-domains = <&cluster_pd>; 347 domain-idle-states = <&big_cpu_sleep_0>; 348 }; 349 350 cpu_pd6: power-domain-cpu6 { 351 #power-domain-cells = <0>; 352 power-domains = <&cluster_pd>; 353 domain-idle-states = <&big_cpu_sleep_0>; 354 }; 355 356 cpu_pd7: power-domain-cpu7 { 357 #power-domain-cells = <0>; 358 power-domains = <&cluster_pd>; 359 domain-idle-states = <&big_cpu_sleep_0>; 360 }; 361 362 cluster_pd: power-domain-cpu-cluster0 { 363 #power-domain-cells = <0>; 364 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 365 }; 366 }; 367 368 reserved_memory: reserved-memory { 369 #address-cells = <2>; 370 #size-cells = <2>; 371 ranges; 372 373 aop_cmd_db_mem: cmd-db@80860000 { 374 compatible = "qcom,cmd-db"; 375 reg = <0x0 0x80860000 0x0 0x20000>; 376 no-map; 377 }; 378 }; 379 380 soc: soc@0 { 381 #address-cells = <2>; 382 #size-cells = <2>; 383 ranges = <0 0 0 0 0x10 0>; 384 dma-ranges = <0 0 0 0 0x10 0>; 385 compatible = "simple-bus"; 386 387 gcc: clock-controller@100000 { 388 compatible = "qcom,sm4450-gcc"; 389 reg = <0x0 0x00100000 0x0 0x1f4200>; 390 #clock-cells = <1>; 391 #reset-cells = <1>; 392 #power-domain-cells = <1>; 393 clocks = <&rpmhcc RPMH_CXO_CLK>, 394 <&sleep_clk>, 395 <0>, 396 <0>, 397 <0>, 398 <0>; 399 }; 400 401 qupv3_id_0: geniqup@ac0000 { 402 compatible = "qcom,geni-se-qup"; 403 reg = <0x0 0x00ac0000 0x0 0x2000>; 404 ranges; 405 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 406 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 407 clock-names = "m-ahb", "s-ahb"; 408 #address-cells = <2>; 409 #size-cells = <2>; 410 status = "disabled"; 411 412 uart7: serial@a88000 { 413 compatible = "qcom,geni-debug-uart"; 414 reg = <0x0 0x00a88000 0x0 0x4000>; 415 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 416 clock-names = "se"; 417 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 418 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 419 pinctrl-names = "default"; 420 status = "disabled"; 421 }; 422 }; 423 424 tcsr_mutex: hwlock@1f40000 { 425 compatible = "qcom,tcsr-mutex"; 426 reg = <0x0 0x01f40000 0x0 0x40000>; 427 #hwlock-cells = <1>; 428 }; 429 430 gpucc: clock-controller@3d90000 { 431 compatible = "qcom,sm4450-gpucc"; 432 reg = <0x0 0x03d90000 0x0 0xa000>; 433 clocks = <&rpmhcc RPMH_CXO_CLK>, 434 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 435 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 436 #clock-cells = <1>; 437 #reset-cells = <1>; 438 #power-domain-cells = <1>; 439 }; 440 441 camcc: clock-controller@ade0000 { 442 compatible = "qcom,sm4450-camcc"; 443 reg = <0x0 0x0ade0000 0x0 0x20000>; 444 clocks = <&rpmhcc RPMH_CXO_CLK>, 445 <&gcc GCC_CAMERA_AHB_CLK>; 446 #clock-cells = <1>; 447 #reset-cells = <1>; 448 #power-domain-cells = <1>; 449 }; 450 451 dispcc: clock-controller@af00000 { 452 compatible = "qcom,sm4450-dispcc"; 453 reg = <0x0 0x0af00000 0x0 0x20000>; 454 clocks = <&rpmhcc RPMH_CXO_CLK>, 455 <&rpmhcc RPMH_CXO_CLK_A>, 456 <&gcc GCC_DISP_AHB_CLK>, 457 <&sleep_clk>, 458 <0>, 459 <0>; 460 #clock-cells = <1>; 461 #reset-cells = <1>; 462 #power-domain-cells = <1>; 463 }; 464 465 pdc: interrupt-controller@b220000 { 466 compatible = "qcom,sm4450-pdc", "qcom,pdc"; 467 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 468 qcom,pdc-ranges = <0 480 94>, <94 494 31>, 469 <125 63 1>; 470 #interrupt-cells = <2>; 471 interrupt-parent = <&intc>; 472 interrupt-controller; 473 }; 474 475 tlmm: pinctrl@f100000 { 476 compatible = "qcom,sm4450-tlmm"; 477 reg = <0x0 0x0f100000 0x0 0x300000>; 478 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 479 gpio-controller; 480 #gpio-cells = <2>; 481 interrupt-controller; 482 #interrupt-cells = <2>; 483 gpio-ranges = <&tlmm 0 0 137>; 484 wakeup-parent = <&pdc>; 485 486 qup_uart7_rx: qup-uart7-rx-state { 487 pins = "gpio23"; 488 function = "qup1_se2_l2"; 489 drive-strength = <2>; 490 bias-disable; 491 }; 492 493 qup_uart7_tx: qup-uart7-tx-state { 494 pins = "gpio22"; 495 function = "qup1_se2_l2"; 496 drive-strength = <2>; 497 bias-disable; 498 }; 499 }; 500 501 intc: interrupt-controller@17200000 { 502 compatible = "arm,gic-v3"; 503 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ 504 <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */ 505 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 506 #interrupt-cells = <3>; 507 interrupt-controller; 508 #redistributor-regions = <1>; 509 redistributor-stride = <0x0 0x20000>; 510 }; 511 512 timer@17420000 { 513 compatible = "arm,armv7-timer-mem"; 514 reg = <0x0 0x17420000 0x0 0x1000>; 515 ranges = <0 0 0 0x20000000>; 516 #address-cells = <1>; 517 #size-cells = <1>; 518 519 frame@17421000 { 520 reg = <0x17421000 0x1000>, 521 <0x17422000 0x1000>; 522 frame-number = <0>; 523 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 525 }; 526 527 frame@17423000 { 528 reg = <0x17423000 0x1000>; 529 frame-number = <1>; 530 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 531 status = "disabled"; 532 }; 533 534 frame@17425000 { 535 reg = <0x17425000 0x1000>; 536 frame-number = <2>; 537 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 538 status = "disabled"; 539 }; 540 541 frame@17427000 { 542 reg = <0x17427000 0x1000>; 543 frame-number = <3>; 544 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 545 status = "disabled"; 546 }; 547 548 frame@17429000 { 549 reg = <0x17429000 0x1000>; 550 frame-number = <4>; 551 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 552 status = "disabled"; 553 }; 554 555 frame@1742b000 { 556 reg = <0x1742b000 0x1000>; 557 frame-number = <5>; 558 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 559 status = "disabled"; 560 }; 561 562 frame@1742d000 { 563 reg = <0x1742d000 0x1000>; 564 frame-number = <6>; 565 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 566 status = "disabled"; 567 }; 568 }; 569 570 apps_rsc: rsc@17a00000 { 571 compatible = "qcom,rpmh-rsc"; 572 reg = <0x0 0x17a00000 0x0 0x10000>, 573 <0x0 0x17a10000 0x0 0x10000>, 574 <0x0 0x17a20000 0x0 0x10000>; 575 reg-names = "drv-0", "drv-1", "drv-2"; 576 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 579 label = "apps_rsc"; 580 qcom,tcs-offset = <0xd00>; 581 qcom,drv-id = <2>; 582 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 583 <WAKE_TCS 3>, <CONTROL_TCS 0>; 584 power-domains = <&cluster_pd>; 585 586 apps_bcm_voter: bcm-voter { 587 compatible = "qcom,bcm-voter"; 588 }; 589 590 rpmhcc: clock-controller { 591 compatible = "qcom,sm4450-rpmh-clk"; 592 #clock-cells = <1>; 593 clocks = <&xo_board>; 594 clock-names = "xo"; 595 }; 596 597 rpmhpd: power-controller { 598 compatible = "qcom,sm4450-rpmhpd"; 599 #power-domain-cells = <1>; 600 operating-points-v2 = <&rpmhpd_opp_table>; 601 602 rpmhpd_opp_table: opp-table { 603 compatible = "operating-points-v2"; 604 605 rpmhpd_opp_ret: opp-16 { 606 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 607 }; 608 609 rpmhpd_opp_min_svs: opp-48 { 610 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 611 }; 612 613 rpmhpd_opp_low_svs_d1: opp-56 { 614 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 615 }; 616 617 rpmhpd_opp_low_svs: opp-64 { 618 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 619 }; 620 621 rpmhpd_opp_low_svs_l1: opp-80 { 622 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 623 }; 624 625 rpmhpd_opp_low_svs_l2: opp-96 { 626 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>; 627 }; 628 629 rpmhpd_opp_svs: opp-128 { 630 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 631 }; 632 633 rpmhpd_opp_svs_l1: opp-192 { 634 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 635 }; 636 637 rpmhpd_opp_svs_l2: opp-224 { 638 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 639 }; 640 641 rpmhpd_opp_nom: opp-256 { 642 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 643 }; 644 645 rpmhpd_opp_nom_l1: opp-320 { 646 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 647 }; 648 649 rpmhpd_opp_nom_l2: opp-336 { 650 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 651 }; 652 653 rpmhpd_opp_turbo: opp-384 { 654 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 655 }; 656 657 rpmhpd_opp_turbo_l1: opp-416 { 658 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 659 }; 660 }; 661 }; 662 }; 663 664 cpufreq_hw: cpufreq@17d91000 { 665 compatible = "qcom,sm4450-cpufreq-epss", "qcom,cpufreq-epss"; 666 reg = <0 0x17d91000 0 0x1000>, 667 <0 0x17d92000 0 0x1000>; 668 reg-names = "freq-domain0", "freq-domain1"; 669 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 670 clock-names = "xo", "alternate"; 671 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 673 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 674 #freq-domain-cells = <1>; 675 #clock-cells = <1>; 676 }; 677 }; 678 679 timer { 680 compatible = "arm,armv8-timer"; 681 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 682 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 683 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 684 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 685 }; 686}; 687