1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. 4 */ 5 6/dts-v1/; 7#include <dt-bindings/clock/sophgo,sg2042-clkgen.h> 8#include <dt-bindings/clock/sophgo,sg2042-pll.h> 9#include <dt-bindings/clock/sophgo,sg2042-rpgate.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/pinctrl/pinctrl-sg2042.h> 12#include <dt-bindings/reset/sophgo,sg2042-reset.h> 13 14#include "sg2042-cpus.dtsi" 15 16/ { 17 compatible = "sophgo,sg2042"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 dma-noncoherent; 21 22 aliases { 23 serial0 = &uart0; 24 }; 25 26 cgi_main: oscillator0 { 27 compatible = "fixed-clock"; 28 clock-output-names = "cgi_main"; 29 #clock-cells = <0>; 30 }; 31 32 cgi_dpll0: oscillator1 { 33 compatible = "fixed-clock"; 34 clock-output-names = "cgi_dpll0"; 35 #clock-cells = <0>; 36 }; 37 38 cgi_dpll1: oscillator2 { 39 compatible = "fixed-clock"; 40 clock-output-names = "cgi_dpll1"; 41 #clock-cells = <0>; 42 }; 43 44 soc: soc { 45 compatible = "simple-bus"; 46 #address-cells = <2>; 47 #size-cells = <2>; 48 interrupt-parent = <&intc>; 49 ranges; 50 51 i2c0: i2c@7030005000 { 52 compatible = "snps,designware-i2c"; 53 reg = <0x70 0x30005000 0x0 0x1000>; 54 #address-cells = <1>; 55 #size-cells = <0>; 56 clocks = <&clkgen GATE_CLK_APB_I2C>; 57 clock-names = "ref"; 58 clock-frequency = <100000>; 59 interrupts = <101 IRQ_TYPE_LEVEL_HIGH>; 60 resets = <&rstgen RST_I2C0>; 61 status = "disabled"; 62 }; 63 64 i2c1: i2c@7030006000 { 65 compatible = "snps,designware-i2c"; 66 reg = <0x70 0x30006000 0x0 0x1000>; 67 #address-cells = <1>; 68 #size-cells = <0>; 69 clocks = <&clkgen GATE_CLK_APB_I2C>; 70 clock-names = "ref"; 71 clock-frequency = <100000>; 72 interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; 73 resets = <&rstgen RST_I2C1>; 74 status = "disabled"; 75 }; 76 77 i2c2: i2c@7030007000 { 78 compatible = "snps,designware-i2c"; 79 reg = <0x70 0x30007000 0x0 0x1000>; 80 #address-cells = <1>; 81 #size-cells = <0>; 82 clocks = <&clkgen GATE_CLK_APB_I2C>; 83 clock-names = "ref"; 84 clock-frequency = <100000>; 85 interrupts = <103 IRQ_TYPE_LEVEL_HIGH>; 86 resets = <&rstgen RST_I2C2>; 87 status = "disabled"; 88 }; 89 90 i2c3: i2c@7030008000 { 91 compatible = "snps,designware-i2c"; 92 reg = <0x70 0x30008000 0x0 0x1000>; 93 #address-cells = <1>; 94 #size-cells = <0>; 95 clocks = <&clkgen GATE_CLK_APB_I2C>; 96 clock-names = "ref"; 97 clock-frequency = <100000>; 98 interrupts = <104 IRQ_TYPE_LEVEL_HIGH>; 99 resets = <&rstgen RST_I2C3>; 100 status = "disabled"; 101 }; 102 103 gpio0: gpio@7030009000 { 104 compatible = "snps,dw-apb-gpio"; 105 reg = <0x70 0x30009000 0x0 0x400>; 106 #address-cells = <1>; 107 #size-cells = <0>; 108 clocks = <&clkgen GATE_CLK_APB_GPIO>, 109 <&clkgen GATE_CLK_GPIO_DB>; 110 clock-names = "bus", "db"; 111 112 port0a: gpio-controller@0 { 113 compatible = "snps,dw-apb-gpio-port"; 114 gpio-controller; 115 #gpio-cells = <2>; 116 ngpios = <32>; 117 reg = <0>; 118 interrupt-controller; 119 #interrupt-cells = <2>; 120 interrupt-parent = <&intc>; 121 interrupts = <96 IRQ_TYPE_LEVEL_HIGH>; 122 }; 123 }; 124 125 gpio1: gpio@703000a000 { 126 compatible = "snps,dw-apb-gpio"; 127 reg = <0x70 0x3000a000 0x0 0x400>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 clocks = <&clkgen GATE_CLK_APB_GPIO>, 131 <&clkgen GATE_CLK_GPIO_DB>; 132 clock-names = "bus", "db"; 133 134 port1a: gpio-controller@0 { 135 compatible = "snps,dw-apb-gpio-port"; 136 gpio-controller; 137 #gpio-cells = <2>; 138 ngpios = <32>; 139 reg = <0>; 140 interrupt-controller; 141 #interrupt-cells = <2>; 142 interrupt-parent = <&intc>; 143 interrupts = <97 IRQ_TYPE_LEVEL_HIGH>; 144 }; 145 }; 146 147 gpio2: gpio@703000b000 { 148 compatible = "snps,dw-apb-gpio"; 149 reg = <0x70 0x3000b000 0x0 0x400>; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 clocks = <&clkgen GATE_CLK_APB_GPIO>, 153 <&clkgen GATE_CLK_GPIO_DB>; 154 clock-names = "bus", "db"; 155 156 port2a: gpio-controller@0 { 157 compatible = "snps,dw-apb-gpio-port"; 158 gpio-controller; 159 #gpio-cells = <2>; 160 ngpios = <32>; 161 reg = <0>; 162 interrupt-controller; 163 #interrupt-cells = <2>; 164 interrupt-parent = <&intc>; 165 interrupts = <98 IRQ_TYPE_LEVEL_HIGH>; 166 }; 167 }; 168 169 pwm: pwm@703000c000 { 170 compatible = "sophgo,sg2042-pwm"; 171 reg = <0x70 0x3000c000 0x0 0x20>; 172 #pwm-cells = <3>; 173 clocks = <&clkgen GATE_CLK_APB_PWM>; 174 clock-names = "apb"; 175 resets = <&rstgen RST_PWM>; 176 }; 177 178 pllclk: clock-controller@70300100c0 { 179 compatible = "sophgo,sg2042-pll"; 180 reg = <0x70 0x300100c0 0x0 0x40>; 181 clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>; 182 clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1"; 183 #clock-cells = <1>; 184 }; 185 186 msi: msi-controller@7030010304 { 187 compatible = "sophgo,sg2042-msi"; 188 reg = <0x70 0x30010304 0x0 0x4>, 189 <0x70 0x30010300 0x0 0x4>; 190 reg-names = "clr", "doorbell"; 191 msi-controller; 192 #msi-cells = <0>; 193 msi-ranges = <&intc 64 IRQ_TYPE_LEVEL_HIGH 32>; 194 }; 195 196 rpgate: clock-controller@7030010368 { 197 compatible = "sophgo,sg2042-rpgate"; 198 reg = <0x70 0x30010368 0x0 0x98>; 199 clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>; 200 clock-names = "rpgate"; 201 #clock-cells = <1>; 202 }; 203 204 pinctrl: pinctrl@7030011000 { 205 compatible = "sophgo,sg2042-pinctrl"; 206 reg = <0x70 0x30011000 0x0 0x1000>; 207 }; 208 209 clkgen: clock-controller@7030012000 { 210 compatible = "sophgo,sg2042-clkgen"; 211 reg = <0x70 0x30012000 0x0 0x1000>; 212 clocks = <&pllclk MPLL_CLK>, 213 <&pllclk FPLL_CLK>, 214 <&pllclk DPLL0_CLK>, 215 <&pllclk DPLL1_CLK>; 216 clock-names = "mpll", 217 "fpll", 218 "dpll0", 219 "dpll1"; 220 #clock-cells = <1>; 221 }; 222 223 clint_mswi: interrupt-controller@7094000000 { 224 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; 225 reg = <0x00000070 0x94000000 0x00000000 0x00004000>; 226 interrupts-extended = <&cpu0_intc 3>, 227 <&cpu1_intc 3>, 228 <&cpu2_intc 3>, 229 <&cpu3_intc 3>, 230 <&cpu4_intc 3>, 231 <&cpu5_intc 3>, 232 <&cpu6_intc 3>, 233 <&cpu7_intc 3>, 234 <&cpu8_intc 3>, 235 <&cpu9_intc 3>, 236 <&cpu10_intc 3>, 237 <&cpu11_intc 3>, 238 <&cpu12_intc 3>, 239 <&cpu13_intc 3>, 240 <&cpu14_intc 3>, 241 <&cpu15_intc 3>, 242 <&cpu16_intc 3>, 243 <&cpu17_intc 3>, 244 <&cpu18_intc 3>, 245 <&cpu19_intc 3>, 246 <&cpu20_intc 3>, 247 <&cpu21_intc 3>, 248 <&cpu22_intc 3>, 249 <&cpu23_intc 3>, 250 <&cpu24_intc 3>, 251 <&cpu25_intc 3>, 252 <&cpu26_intc 3>, 253 <&cpu27_intc 3>, 254 <&cpu28_intc 3>, 255 <&cpu29_intc 3>, 256 <&cpu30_intc 3>, 257 <&cpu31_intc 3>, 258 <&cpu32_intc 3>, 259 <&cpu33_intc 3>, 260 <&cpu34_intc 3>, 261 <&cpu35_intc 3>, 262 <&cpu36_intc 3>, 263 <&cpu37_intc 3>, 264 <&cpu38_intc 3>, 265 <&cpu39_intc 3>, 266 <&cpu40_intc 3>, 267 <&cpu41_intc 3>, 268 <&cpu42_intc 3>, 269 <&cpu43_intc 3>, 270 <&cpu44_intc 3>, 271 <&cpu45_intc 3>, 272 <&cpu46_intc 3>, 273 <&cpu47_intc 3>, 274 <&cpu48_intc 3>, 275 <&cpu49_intc 3>, 276 <&cpu50_intc 3>, 277 <&cpu51_intc 3>, 278 <&cpu52_intc 3>, 279 <&cpu53_intc 3>, 280 <&cpu54_intc 3>, 281 <&cpu55_intc 3>, 282 <&cpu56_intc 3>, 283 <&cpu57_intc 3>, 284 <&cpu58_intc 3>, 285 <&cpu59_intc 3>, 286 <&cpu60_intc 3>, 287 <&cpu61_intc 3>, 288 <&cpu62_intc 3>, 289 <&cpu63_intc 3>; 290 }; 291 292 clint_mtimer0: timer@70ac004000 { 293 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 294 reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; 295 reg-names = "mtimecmp"; 296 interrupts-extended = <&cpu0_intc 7>, 297 <&cpu1_intc 7>, 298 <&cpu2_intc 7>, 299 <&cpu3_intc 7>; 300 }; 301 302 clint_mtimer1: timer@70ac014000 { 303 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 304 reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; 305 reg-names = "mtimecmp"; 306 interrupts-extended = <&cpu4_intc 7>, 307 <&cpu5_intc 7>, 308 <&cpu6_intc 7>, 309 <&cpu7_intc 7>; 310 }; 311 312 clint_mtimer2: timer@70ac024000 { 313 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 314 reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; 315 reg-names = "mtimecmp"; 316 interrupts-extended = <&cpu8_intc 7>, 317 <&cpu9_intc 7>, 318 <&cpu10_intc 7>, 319 <&cpu11_intc 7>; 320 }; 321 322 clint_mtimer3: timer@70ac034000 { 323 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 324 reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; 325 reg-names = "mtimecmp"; 326 interrupts-extended = <&cpu12_intc 7>, 327 <&cpu13_intc 7>, 328 <&cpu14_intc 7>, 329 <&cpu15_intc 7>; 330 }; 331 332 clint_mtimer4: timer@70ac044000 { 333 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 334 reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; 335 reg-names = "mtimecmp"; 336 interrupts-extended = <&cpu16_intc 7>, 337 <&cpu17_intc 7>, 338 <&cpu18_intc 7>, 339 <&cpu19_intc 7>; 340 }; 341 342 clint_mtimer5: timer@70ac054000 { 343 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 344 reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; 345 reg-names = "mtimecmp"; 346 interrupts-extended = <&cpu20_intc 7>, 347 <&cpu21_intc 7>, 348 <&cpu22_intc 7>, 349 <&cpu23_intc 7>; 350 }; 351 352 clint_mtimer6: timer@70ac064000 { 353 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 354 reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; 355 reg-names = "mtimecmp"; 356 interrupts-extended = <&cpu24_intc 7>, 357 <&cpu25_intc 7>, 358 <&cpu26_intc 7>, 359 <&cpu27_intc 7>; 360 }; 361 362 clint_mtimer7: timer@70ac074000 { 363 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 364 reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; 365 reg-names = "mtimecmp"; 366 interrupts-extended = <&cpu28_intc 7>, 367 <&cpu29_intc 7>, 368 <&cpu30_intc 7>, 369 <&cpu31_intc 7>; 370 }; 371 372 clint_mtimer8: timer@70ac084000 { 373 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 374 reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; 375 reg-names = "mtimecmp"; 376 interrupts-extended = <&cpu32_intc 7>, 377 <&cpu33_intc 7>, 378 <&cpu34_intc 7>, 379 <&cpu35_intc 7>; 380 }; 381 382 clint_mtimer9: timer@70ac094000 { 383 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 384 reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; 385 reg-names = "mtimecmp"; 386 interrupts-extended = <&cpu36_intc 7>, 387 <&cpu37_intc 7>, 388 <&cpu38_intc 7>, 389 <&cpu39_intc 7>; 390 }; 391 392 clint_mtimer10: timer@70ac0a4000 { 393 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 394 reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; 395 reg-names = "mtimecmp"; 396 interrupts-extended = <&cpu40_intc 7>, 397 <&cpu41_intc 7>, 398 <&cpu42_intc 7>, 399 <&cpu43_intc 7>; 400 }; 401 402 clint_mtimer11: timer@70ac0b4000 { 403 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 404 reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; 405 reg-names = "mtimecmp"; 406 interrupts-extended = <&cpu44_intc 7>, 407 <&cpu45_intc 7>, 408 <&cpu46_intc 7>, 409 <&cpu47_intc 7>; 410 }; 411 412 clint_mtimer12: timer@70ac0c4000 { 413 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 414 reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; 415 reg-names = "mtimecmp"; 416 interrupts-extended = <&cpu48_intc 7>, 417 <&cpu49_intc 7>, 418 <&cpu50_intc 7>, 419 <&cpu51_intc 7>; 420 }; 421 422 clint_mtimer13: timer@70ac0d4000 { 423 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 424 reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; 425 reg-names = "mtimecmp"; 426 interrupts-extended = <&cpu52_intc 7>, 427 <&cpu53_intc 7>, 428 <&cpu54_intc 7>, 429 <&cpu55_intc 7>; 430 }; 431 432 clint_mtimer14: timer@70ac0e4000 { 433 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 434 reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; 435 reg-names = "mtimecmp"; 436 interrupts-extended = <&cpu56_intc 7>, 437 <&cpu57_intc 7>, 438 <&cpu58_intc 7>, 439 <&cpu59_intc 7>; 440 }; 441 442 clint_mtimer15: timer@70ac0f4000 { 443 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 444 reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; 445 reg-names = "mtimecmp"; 446 interrupts-extended = <&cpu60_intc 7>, 447 <&cpu61_intc 7>, 448 <&cpu62_intc 7>, 449 <&cpu63_intc 7>; 450 }; 451 452 intc: interrupt-controller@7090000000 { 453 compatible = "sophgo,sg2042-plic", "thead,c900-plic"; 454 #address-cells = <0>; 455 #interrupt-cells = <2>; 456 reg = <0x00000070 0x90000000 0x00000000 0x04000000>; 457 interrupt-controller; 458 interrupts-extended = 459 <&cpu0_intc 11>, <&cpu0_intc 9>, 460 <&cpu1_intc 11>, <&cpu1_intc 9>, 461 <&cpu2_intc 11>, <&cpu2_intc 9>, 462 <&cpu3_intc 11>, <&cpu3_intc 9>, 463 <&cpu4_intc 11>, <&cpu4_intc 9>, 464 <&cpu5_intc 11>, <&cpu5_intc 9>, 465 <&cpu6_intc 11>, <&cpu6_intc 9>, 466 <&cpu7_intc 11>, <&cpu7_intc 9>, 467 <&cpu8_intc 11>, <&cpu8_intc 9>, 468 <&cpu9_intc 11>, <&cpu9_intc 9>, 469 <&cpu10_intc 11>, <&cpu10_intc 9>, 470 <&cpu11_intc 11>, <&cpu11_intc 9>, 471 <&cpu12_intc 11>, <&cpu12_intc 9>, 472 <&cpu13_intc 11>, <&cpu13_intc 9>, 473 <&cpu14_intc 11>, <&cpu14_intc 9>, 474 <&cpu15_intc 11>, <&cpu15_intc 9>, 475 <&cpu16_intc 11>, <&cpu16_intc 9>, 476 <&cpu17_intc 11>, <&cpu17_intc 9>, 477 <&cpu18_intc 11>, <&cpu18_intc 9>, 478 <&cpu19_intc 11>, <&cpu19_intc 9>, 479 <&cpu20_intc 11>, <&cpu20_intc 9>, 480 <&cpu21_intc 11>, <&cpu21_intc 9>, 481 <&cpu22_intc 11>, <&cpu22_intc 9>, 482 <&cpu23_intc 11>, <&cpu23_intc 9>, 483 <&cpu24_intc 11>, <&cpu24_intc 9>, 484 <&cpu25_intc 11>, <&cpu25_intc 9>, 485 <&cpu26_intc 11>, <&cpu26_intc 9>, 486 <&cpu27_intc 11>, <&cpu27_intc 9>, 487 <&cpu28_intc 11>, <&cpu28_intc 9>, 488 <&cpu29_intc 11>, <&cpu29_intc 9>, 489 <&cpu30_intc 11>, <&cpu30_intc 9>, 490 <&cpu31_intc 11>, <&cpu31_intc 9>, 491 <&cpu32_intc 11>, <&cpu32_intc 9>, 492 <&cpu33_intc 11>, <&cpu33_intc 9>, 493 <&cpu34_intc 11>, <&cpu34_intc 9>, 494 <&cpu35_intc 11>, <&cpu35_intc 9>, 495 <&cpu36_intc 11>, <&cpu36_intc 9>, 496 <&cpu37_intc 11>, <&cpu37_intc 9>, 497 <&cpu38_intc 11>, <&cpu38_intc 9>, 498 <&cpu39_intc 11>, <&cpu39_intc 9>, 499 <&cpu40_intc 11>, <&cpu40_intc 9>, 500 <&cpu41_intc 11>, <&cpu41_intc 9>, 501 <&cpu42_intc 11>, <&cpu42_intc 9>, 502 <&cpu43_intc 11>, <&cpu43_intc 9>, 503 <&cpu44_intc 11>, <&cpu44_intc 9>, 504 <&cpu45_intc 11>, <&cpu45_intc 9>, 505 <&cpu46_intc 11>, <&cpu46_intc 9>, 506 <&cpu47_intc 11>, <&cpu47_intc 9>, 507 <&cpu48_intc 11>, <&cpu48_intc 9>, 508 <&cpu49_intc 11>, <&cpu49_intc 9>, 509 <&cpu50_intc 11>, <&cpu50_intc 9>, 510 <&cpu51_intc 11>, <&cpu51_intc 9>, 511 <&cpu52_intc 11>, <&cpu52_intc 9>, 512 <&cpu53_intc 11>, <&cpu53_intc 9>, 513 <&cpu54_intc 11>, <&cpu54_intc 9>, 514 <&cpu55_intc 11>, <&cpu55_intc 9>, 515 <&cpu56_intc 11>, <&cpu56_intc 9>, 516 <&cpu57_intc 11>, <&cpu57_intc 9>, 517 <&cpu58_intc 11>, <&cpu58_intc 9>, 518 <&cpu59_intc 11>, <&cpu59_intc 9>, 519 <&cpu60_intc 11>, <&cpu60_intc 9>, 520 <&cpu61_intc 11>, <&cpu61_intc 9>, 521 <&cpu62_intc 11>, <&cpu62_intc 9>, 522 <&cpu63_intc 11>, <&cpu63_intc 9>; 523 riscv,ndev = <224>; 524 }; 525 526 rstgen: reset-controller@7030013000 { 527 compatible = "sophgo,sg2042-reset"; 528 reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; 529 #reset-cells = <1>; 530 }; 531 532 uart0: serial@7040000000 { 533 compatible = "snps,dw-apb-uart"; 534 reg = <0x00000070 0x40000000 0x00000000 0x00001000>; 535 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; 536 clock-frequency = <500000000>; 537 clocks = <&clkgen GATE_CLK_UART_500M>, 538 <&clkgen GATE_CLK_APB_UART>; 539 clock-names = "baudclk", "apb_pclk"; 540 reg-shift = <2>; 541 reg-io-width = <4>; 542 resets = <&rstgen RST_UART0>; 543 status = "disabled"; 544 }; 545 546 spi0: spi@7040004000 { 547 compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi"; 548 reg = <0x70 0x40004000 0x00 0x1000>; 549 clocks = <&clkgen GATE_CLK_APB_SPI>; 550 interrupt-parent = <&intc>; 551 interrupts = <110 IRQ_TYPE_LEVEL_HIGH>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 num-cs = <2>; 555 resets = <&rstgen RST_SPI0>; 556 status = "disabled"; 557 }; 558 559 spi1: spi@7040005000 { 560 compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi"; 561 reg = <0x70 0x40005000 0x00 0x1000>; 562 clocks = <&clkgen GATE_CLK_APB_SPI>; 563 interrupt-parent = <&intc>; 564 interrupts = <111 IRQ_TYPE_LEVEL_HIGH>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 num-cs = <2>; 568 resets = <&rstgen RST_SPI1>; 569 status = "disabled"; 570 }; 571 572 emmc: mmc@704002a000 { 573 compatible = "sophgo,sg2042-dwcmshc"; 574 reg = <0x70 0x4002a000 0x0 0x1000>; 575 interrupt-parent = <&intc>; 576 interrupts = <134 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&clkgen GATE_CLK_EMMC_100M>, 578 <&clkgen GATE_CLK_AXI_EMMC>, 579 <&clkgen GATE_CLK_100K_EMMC>; 580 clock-names = "core", 581 "bus", 582 "timer"; 583 status = "disabled"; 584 }; 585 586 sd: mmc@704002b000 { 587 compatible = "sophgo,sg2042-dwcmshc"; 588 reg = <0x70 0x4002b000 0x0 0x1000>; 589 interrupt-parent = <&intc>; 590 interrupts = <136 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&clkgen GATE_CLK_SD_100M>, 592 <&clkgen GATE_CLK_AXI_SD>, 593 <&clkgen GATE_CLK_100K_SD>; 594 clock-names = "core", 595 "bus", 596 "timer"; 597 status = "disabled"; 598 }; 599 }; 600}; 601