1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Marvell 88E6xxx SERDES manipulation, via SMI bus
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 */
9
10 #ifndef _MV88E6XXX_SERDES_H
11 #define _MV88E6XXX_SERDES_H
12
13 #include "chip.h"
14
15 struct phylink_link_state;
16
17 #define MV88E6352_ADDR_SERDES 0x0f
18 #define MV88E6352_SERDES_PAGE_FIBER 0x01
19 #define MV88E6352_SERDES_IRQ 0x0b
20 #define MV88E6352_SERDES_INT_ENABLE 0x12
21 #define MV88E6352_SERDES_INT_SPEED_CHANGE BIT(14)
22 #define MV88E6352_SERDES_INT_DUPLEX_CHANGE BIT(13)
23 #define MV88E6352_SERDES_INT_PAGE_RX BIT(12)
24 #define MV88E6352_SERDES_INT_AN_COMPLETE BIT(11)
25 #define MV88E6352_SERDES_INT_LINK_CHANGE BIT(10)
26 #define MV88E6352_SERDES_INT_SYMBOL_ERROR BIT(9)
27 #define MV88E6352_SERDES_INT_FALSE_CARRIER BIT(8)
28 #define MV88E6352_SERDES_INT_FIFO_OVER_UNDER BIT(7)
29 #define MV88E6352_SERDES_INT_FIBRE_ENERGY BIT(4)
30 #define MV88E6352_SERDES_INT_STATUS 0x13
31
32
33 #define MV88E6341_PORT5_LANE 0x15
34
35 #define MV88E6390_PORT9_LANE0 0x09
36 #define MV88E6390_PORT9_LANE1 0x12
37 #define MV88E6390_PORT9_LANE2 0x13
38 #define MV88E6390_PORT9_LANE3 0x14
39 #define MV88E6390_PORT10_LANE0 0x0a
40 #define MV88E6390_PORT10_LANE1 0x15
41 #define MV88E6390_PORT10_LANE2 0x16
42 #define MV88E6390_PORT10_LANE3 0x17
43
44 /* 10GBASE-R and 10GBASE-X4/X2 */
45 #define MV88E6390_10G_CTRL1 (0x1000 + MDIO_CTRL1)
46 #define MV88E6390_10G_STAT1 (0x1000 + MDIO_STAT1)
47 #define MV88E6390_10G_INT_ENABLE 0x9001
48 #define MV88E6390_10G_INT_LINK_DOWN BIT(3)
49 #define MV88E6390_10G_INT_LINK_UP BIT(2)
50 #define MV88E6390_10G_INT_STATUS 0x9003
51 #define MV88E6393X_10G_INT_ENABLE 0x9000
52 #define MV88E6393X_10G_INT_LINK_CHANGE BIT(2)
53 #define MV88E6393X_10G_INT_STATUS 0x9001
54
55 /* USXGMII */
56 #define MV88E6390_USXGMII_LP_STATUS 0xf0a2
57 #define MV88E6390_USXGMII_PHY_STATUS 0xf0a6
58
59 /* 1000BASE-X and SGMII */
60 #define MV88E6390_SGMII_BMCR (0x2000 + MII_BMCR)
61 #define MV88E6390_SGMII_BMSR (0x2000 + MII_BMSR)
62 #define MV88E6390_SGMII_ADVERTISE (0x2000 + MII_ADVERTISE)
63 #define MV88E6390_SGMII_LPA (0x2000 + MII_LPA)
64 #define MV88E6390_SGMII_INT_ENABLE 0xa001
65 #define MV88E6390_SGMII_INT_SPEED_CHANGE BIT(14)
66 #define MV88E6390_SGMII_INT_DUPLEX_CHANGE BIT(13)
67 #define MV88E6390_SGMII_INT_PAGE_RX BIT(12)
68 #define MV88E6390_SGMII_INT_AN_COMPLETE BIT(11)
69 #define MV88E6390_SGMII_INT_LINK_DOWN BIT(10)
70 #define MV88E6390_SGMII_INT_LINK_UP BIT(9)
71 #define MV88E6390_SGMII_INT_SYMBOL_ERROR BIT(8)
72 #define MV88E6390_SGMII_INT_FALSE_CARRIER BIT(7)
73 #define MV88E6390_SGMII_INT_STATUS 0xa002
74 #define MV88E6390_SGMII_PHY_STATUS 0xa003
75 #define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK GENMASK(15, 14)
76 #define MV88E6390_SGMII_PHY_STATUS_SPEED_1000 0x8000
77 #define MV88E6390_SGMII_PHY_STATUS_SPEED_100 0x4000
78 #define MV88E6390_SGMII_PHY_STATUS_SPEED_10 0x0000
79 #define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL BIT(13)
80 #define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11)
81 #define MV88E6390_SGMII_PHY_STATUS_LINK BIT(10)
82 #define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE BIT(3)
83 #define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE BIT(2)
84
85 /* Packet generator pad packet checker */
86 #define MV88E6390_PG_CONTROL 0xf010
87 #define MV88E6390_PG_CONTROL_ENABLE_PC BIT(0)
88
89 #define MV88E6393X_PORT0_LANE 0x00
90 #define MV88E6393X_PORT9_LANE 0x09
91 #define MV88E6393X_PORT10_LANE 0x0a
92
93 /* Port Operational Configuration */
94 #define MV88E6393X_SERDES_POC 0xf002
95 #define MV88E6393X_SERDES_POC_PCS_1000BASEX 0x0000
96 #define MV88E6393X_SERDES_POC_PCS_2500BASEX 0x0001
97 #define MV88E6393X_SERDES_POC_PCS_SGMII_PHY 0x0002
98 #define MV88E6393X_SERDES_POC_PCS_SGMII_MAC 0x0003
99 #define MV88E6393X_SERDES_POC_PCS_5GBASER 0x0004
100 #define MV88E6393X_SERDES_POC_PCS_10GBASER 0x0005
101 #define MV88E6393X_SERDES_POC_PCS_USXGMII_PHY 0x0006
102 #define MV88E6393X_SERDES_POC_PCS_USXGMII_MAC 0x0007
103 #define MV88E6393X_SERDES_POC_PCS_MASK 0x0007
104 #define MV88E6393X_SERDES_POC_RESET BIT(15)
105 #define MV88E6393X_SERDES_POC_PDOWN BIT(5)
106 #define MV88E6393X_SERDES_POC_AN BIT(3)
107 #define MV88E6393X_SERDES_CTRL1 0xf003
108 #define MV88E6393X_SERDES_CTRL1_TX_PDOWN BIT(9)
109 #define MV88E6393X_SERDES_CTRL1_RX_PDOWN BIT(8)
110
111 #define MV88E6393X_ERRATA_4_8_REG 0xF074
112 #define MV88E6393X_ERRATA_4_8_BIT BIT(14)
113
114 int mv88e6xxx_pcs_decode_state(struct device *dev, u16 bmsr, u16 lpa,
115 u16 status, struct phylink_link_state *state);
116
117 int mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
118 int mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
119 int mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
120 int mv88e6393x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
121 unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
122 int port);
123 unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
124 int port);
125 int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
126 int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip, int port,
127 uint8_t **data);
128 size_t mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
129 uint64_t *data);
130 int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
131 int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip, int port,
132 uint8_t **data);
133 size_t mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
134 uint64_t *data);
135
136 int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
137 void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
138 int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
139 void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
140
141 /* Return the (first) SERDES lane address a port is using, -errno otherwise. */
mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip * chip,int port)142 static inline int mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
143 int port)
144 {
145 if (!chip->info->ops->serdes_get_lane)
146 return -EOPNOTSUPP;
147
148 return chip->info->ops->serdes_get_lane(chip, port);
149 }
150
151 static inline unsigned int
mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip * chip,int port)152 mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
153 {
154 if (!chip->info->ops->serdes_irq_mapping)
155 return 0;
156
157 return chip->info->ops->serdes_irq_mapping(chip, port);
158 }
159
160 extern const struct mv88e6xxx_pcs_ops mv88e6185_pcs_ops;
161 extern const struct mv88e6xxx_pcs_ops mv88e6352_pcs_ops;
162 extern const struct mv88e6xxx_pcs_ops mv88e6390_pcs_ops;
163 extern const struct mv88e6xxx_pcs_ops mv88e6393x_pcs_ops;
164
165 #endif
166