1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sc8180x.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/interconnect/qcom,icc.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sc8180x.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19#include <dt-bindings/thermal/thermal.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 clocks { 28 xo_board_clk: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <38400000>; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32764>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "qcom,kryo485"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 capacity-dmips-mhz = <602>; 52 next-level-cache = <&l2_0>; 53 qcom,freq-domain = <&cpufreq_hw 0>; 54 operating-points-v2 = <&cpu0_opp_table>; 55 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 56 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 57 power-domains = <&cpu_pd0>; 58 power-domain-names = "psci"; 59 #cooling-cells = <2>; 60 clocks = <&cpufreq_hw 0>; 61 62 l2_0: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 cache-unified; 66 next-level-cache = <&l3_0>; 67 l3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 cache-unified; 71 }; 72 }; 73 }; 74 75 cpu1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "qcom,kryo485"; 78 reg = <0x0 0x100>; 79 enable-method = "psci"; 80 capacity-dmips-mhz = <602>; 81 next-level-cache = <&l2_100>; 82 qcom,freq-domain = <&cpufreq_hw 0>; 83 operating-points-v2 = <&cpu0_opp_table>; 84 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 85 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 86 power-domains = <&cpu_pd1>; 87 power-domain-names = "psci"; 88 #cooling-cells = <2>; 89 clocks = <&cpufreq_hw 0>; 90 91 l2_100: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 cache-unified; 95 next-level-cache = <&l3_0>; 96 }; 97 98 }; 99 100 cpu2: cpu@200 { 101 device_type = "cpu"; 102 compatible = "qcom,kryo485"; 103 reg = <0x0 0x200>; 104 enable-method = "psci"; 105 capacity-dmips-mhz = <602>; 106 next-level-cache = <&l2_200>; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 operating-points-v2 = <&cpu0_opp_table>; 109 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 110 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 111 power-domains = <&cpu_pd2>; 112 power-domain-names = "psci"; 113 #cooling-cells = <2>; 114 clocks = <&cpufreq_hw 0>; 115 116 l2_200: l2-cache { 117 compatible = "cache"; 118 cache-level = <2>; 119 cache-unified; 120 next-level-cache = <&l3_0>; 121 }; 122 }; 123 124 cpu3: cpu@300 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo485"; 127 reg = <0x0 0x300>; 128 enable-method = "psci"; 129 capacity-dmips-mhz = <602>; 130 next-level-cache = <&l2_300>; 131 qcom,freq-domain = <&cpufreq_hw 0>; 132 operating-points-v2 = <&cpu0_opp_table>; 133 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 134 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 135 power-domains = <&cpu_pd3>; 136 power-domain-names = "psci"; 137 #cooling-cells = <2>; 138 clocks = <&cpufreq_hw 0>; 139 140 l2_300: l2-cache { 141 compatible = "cache"; 142 cache-unified; 143 cache-level = <2>; 144 next-level-cache = <&l3_0>; 145 }; 146 }; 147 148 cpu4: cpu@400 { 149 device_type = "cpu"; 150 compatible = "qcom,kryo485"; 151 reg = <0x0 0x400>; 152 enable-method = "psci"; 153 capacity-dmips-mhz = <1024>; 154 next-level-cache = <&l2_400>; 155 qcom,freq-domain = <&cpufreq_hw 1>; 156 operating-points-v2 = <&cpu4_opp_table>; 157 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 158 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 159 power-domains = <&cpu_pd4>; 160 power-domain-names = "psci"; 161 #cooling-cells = <2>; 162 clocks = <&cpufreq_hw 1>; 163 164 l2_400: l2-cache { 165 compatible = "cache"; 166 cache-unified; 167 cache-level = <2>; 168 next-level-cache = <&l3_0>; 169 }; 170 }; 171 172 cpu5: cpu@500 { 173 device_type = "cpu"; 174 compatible = "qcom,kryo485"; 175 reg = <0x0 0x500>; 176 enable-method = "psci"; 177 capacity-dmips-mhz = <1024>; 178 next-level-cache = <&l2_500>; 179 qcom,freq-domain = <&cpufreq_hw 1>; 180 operating-points-v2 = <&cpu4_opp_table>; 181 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 182 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 183 power-domains = <&cpu_pd5>; 184 power-domain-names = "psci"; 185 #cooling-cells = <2>; 186 clocks = <&cpufreq_hw 1>; 187 188 l2_500: l2-cache { 189 compatible = "cache"; 190 cache-unified; 191 cache-level = <2>; 192 next-level-cache = <&l3_0>; 193 }; 194 }; 195 196 cpu6: cpu@600 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo485"; 199 reg = <0x0 0x600>; 200 enable-method = "psci"; 201 capacity-dmips-mhz = <1024>; 202 next-level-cache = <&l2_600>; 203 qcom,freq-domain = <&cpufreq_hw 1>; 204 operating-points-v2 = <&cpu4_opp_table>; 205 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 206 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 207 power-domains = <&cpu_pd6>; 208 power-domain-names = "psci"; 209 #cooling-cells = <2>; 210 clocks = <&cpufreq_hw 1>; 211 212 l2_600: l2-cache { 213 compatible = "cache"; 214 cache-unified; 215 cache-level = <2>; 216 next-level-cache = <&l3_0>; 217 }; 218 }; 219 220 cpu7: cpu@700 { 221 device_type = "cpu"; 222 compatible = "qcom,kryo485"; 223 reg = <0x0 0x700>; 224 enable-method = "psci"; 225 capacity-dmips-mhz = <1024>; 226 next-level-cache = <&l2_700>; 227 qcom,freq-domain = <&cpufreq_hw 1>; 228 operating-points-v2 = <&cpu4_opp_table>; 229 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 230 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 231 power-domains = <&cpu_pd7>; 232 power-domain-names = "psci"; 233 #cooling-cells = <2>; 234 clocks = <&cpufreq_hw 1>; 235 236 l2_700: l2-cache { 237 compatible = "cache"; 238 cache-unified; 239 cache-level = <2>; 240 next-level-cache = <&l3_0>; 241 }; 242 }; 243 244 cpu-map { 245 cluster0 { 246 core0 { 247 cpu = <&cpu0>; 248 }; 249 250 core1 { 251 cpu = <&cpu1>; 252 }; 253 254 core2 { 255 cpu = <&cpu2>; 256 }; 257 258 core3 { 259 cpu = <&cpu3>; 260 }; 261 262 core4 { 263 cpu = <&cpu4>; 264 }; 265 266 core5 { 267 cpu = <&cpu5>; 268 }; 269 270 core6 { 271 cpu = <&cpu6>; 272 }; 273 274 core7 { 275 cpu = <&cpu7>; 276 }; 277 }; 278 }; 279 280 idle-states { 281 entry-method = "psci"; 282 283 little_cpu_sleep_0: cpu-sleep-0-0 { 284 compatible = "arm,idle-state"; 285 arm,psci-suspend-param = <0x40000004>; 286 entry-latency-us = <355>; 287 exit-latency-us = <909>; 288 min-residency-us = <3934>; 289 local-timer-stop; 290 }; 291 292 big_cpu_sleep_0: cpu-sleep-1-0 { 293 compatible = "arm,idle-state"; 294 arm,psci-suspend-param = <0x40000004>; 295 entry-latency-us = <2411>; 296 exit-latency-us = <1461>; 297 min-residency-us = <4488>; 298 local-timer-stop; 299 }; 300 }; 301 302 domain-idle-states { 303 cluster_sleep_apss_off: cluster-sleep-0 { 304 compatible = "domain-idle-state"; 305 arm,psci-suspend-param = <0x41000044>; 306 entry-latency-us = <3300>; 307 exit-latency-us = <3300>; 308 min-residency-us = <6000>; 309 }; 310 311 cluster_sleep_aoss_sleep: cluster-sleep-1 { 312 compatible = "domain-idle-state"; 313 arm,psci-suspend-param = <0x4100a344>; 314 entry-latency-us = <3263>; 315 exit-latency-us = <6562>; 316 min-residency-us = <9987>; 317 }; 318 }; 319 }; 320 321 cpu0_opp_table: opp-table-cpu0 { 322 compatible = "operating-points-v2"; 323 opp-shared; 324 325 opp-300000000 { 326 opp-hz = /bits/ 64 <300000000>; 327 opp-peak-kBps = <800000 9600000>; 328 }; 329 330 opp-422400000 { 331 opp-hz = /bits/ 64 <422400000>; 332 opp-peak-kBps = <800000 9600000>; 333 }; 334 335 opp-537600000 { 336 opp-hz = /bits/ 64 <537600000>; 337 opp-peak-kBps = <800000 12902400>; 338 }; 339 340 opp-652800000 { 341 opp-hz = /bits/ 64 <652800000>; 342 opp-peak-kBps = <800000 12902400>; 343 }; 344 345 opp-768000000 { 346 opp-hz = /bits/ 64 <768000000>; 347 opp-peak-kBps = <800000 15974400>; 348 }; 349 350 opp-883200000 { 351 opp-hz = /bits/ 64 <883200000>; 352 opp-peak-kBps = <1804000 19660800>; 353 }; 354 355 opp-998400000 { 356 opp-hz = /bits/ 64 <998400000>; 357 opp-peak-kBps = <1804000 19660800>; 358 }; 359 360 opp-1113600000 { 361 opp-hz = /bits/ 64 <1113600000>; 362 opp-peak-kBps = <1804000 22732800>; 363 }; 364 365 opp-1228800000 { 366 opp-hz = /bits/ 64 <1228800000>; 367 opp-peak-kBps = <1804000 22732800>; 368 }; 369 370 opp-1363200000 { 371 opp-hz = /bits/ 64 <1363200000>; 372 opp-peak-kBps = <2188000 25804800>; 373 }; 374 375 opp-1478400000 { 376 opp-hz = /bits/ 64 <1478400000>; 377 opp-peak-kBps = <2188000 31948800>; 378 }; 379 380 opp-1574400000 { 381 opp-hz = /bits/ 64 <1574400000>; 382 opp-peak-kBps = <3072000 31948800>; 383 }; 384 385 opp-1670400000 { 386 opp-hz = /bits/ 64 <1670400000>; 387 opp-peak-kBps = <3072000 31948800>; 388 }; 389 390 opp-1766400000 { 391 opp-hz = /bits/ 64 <1766400000>; 392 opp-peak-kBps = <3072000 31948800>; 393 }; 394 }; 395 396 cpu4_opp_table: opp-table-cpu4 { 397 compatible = "operating-points-v2"; 398 opp-shared; 399 400 opp-825600000 { 401 opp-hz = /bits/ 64 <825600000>; 402 opp-peak-kBps = <1804000 15974400>; 403 }; 404 405 opp-940800000 { 406 opp-hz = /bits/ 64 <940800000>; 407 opp-peak-kBps = <2188000 19660800>; 408 }; 409 410 opp-1056000000 { 411 opp-hz = /bits/ 64 <1056000000>; 412 opp-peak-kBps = <2188000 22732800>; 413 }; 414 415 opp-1171200000 { 416 opp-hz = /bits/ 64 <1171200000>; 417 opp-peak-kBps = <3072000 25804800>; 418 }; 419 420 opp-1286400000 { 421 opp-hz = /bits/ 64 <1286400000>; 422 opp-peak-kBps = <3072000 31948800>; 423 }; 424 425 opp-1420800000 { 426 opp-hz = /bits/ 64 <1420800000>; 427 opp-peak-kBps = <4068000 31948800>; 428 }; 429 430 opp-1536000000 { 431 opp-hz = /bits/ 64 <1536000000>; 432 opp-peak-kBps = <4068000 31948800>; 433 }; 434 435 opp-1651200000 { 436 opp-hz = /bits/ 64 <1651200000>; 437 opp-peak-kBps = <4068000 40550400>; 438 }; 439 440 opp-1766400000 { 441 opp-hz = /bits/ 64 <1766400000>; 442 opp-peak-kBps = <4068000 40550400>; 443 }; 444 445 opp-1881600000 { 446 opp-hz = /bits/ 64 <1881600000>; 447 opp-peak-kBps = <4068000 43008000>; 448 }; 449 450 opp-1996800000 { 451 opp-hz = /bits/ 64 <1996800000>; 452 opp-peak-kBps = <6220000 43008000>; 453 }; 454 455 opp-2131200000 { 456 opp-hz = /bits/ 64 <2131200000>; 457 opp-peak-kBps = <6220000 49152000>; 458 }; 459 460 opp-2246400000 { 461 opp-hz = /bits/ 64 <2246400000>; 462 opp-peak-kBps = <7216000 49152000>; 463 }; 464 465 opp-2361600000 { 466 opp-hz = /bits/ 64 <2361600000>; 467 opp-peak-kBps = <8368000 49152000>; 468 }; 469 470 opp-2457600000 { 471 opp-hz = /bits/ 64 <2457600000>; 472 opp-peak-kBps = <8368000 51609600>; 473 }; 474 475 opp-2553600000 { 476 opp-hz = /bits/ 64 <2553600000>; 477 opp-peak-kBps = <8368000 51609600>; 478 }; 479 480 opp-2649600000 { 481 opp-hz = /bits/ 64 <2649600000>; 482 opp-peak-kBps = <8368000 51609600>; 483 }; 484 485 opp-2745600000 { 486 opp-hz = /bits/ 64 <2745600000>; 487 opp-peak-kBps = <8368000 51609600>; 488 }; 489 490 opp-2841600000 { 491 opp-hz = /bits/ 64 <2841600000>; 492 opp-peak-kBps = <8368000 51609600>; 493 }; 494 495 opp-2918400000 { 496 opp-hz = /bits/ 64 <2918400000>; 497 opp-peak-kBps = <8368000 51609600>; 498 }; 499 500 opp-2995200000 { 501 opp-hz = /bits/ 64 <2995200000>; 502 opp-peak-kBps = <8368000 51609600>; 503 }; 504 }; 505 506 firmware { 507 scm: scm { 508 compatible = "qcom,scm-sc8180x", "qcom,scm"; 509 }; 510 }; 511 512 camnoc_virt: interconnect-camnoc-virt { 513 compatible = "qcom,sc8180x-camnoc-virt"; 514 #interconnect-cells = <2>; 515 qcom,bcm-voters = <&apps_bcm_voter>; 516 }; 517 518 mc_virt: interconnect-mc-virt { 519 compatible = "qcom,sc8180x-mc-virt"; 520 #interconnect-cells = <2>; 521 qcom,bcm-voters = <&apps_bcm_voter>; 522 }; 523 524 qup_virt: interconnect-qup-virt { 525 compatible = "qcom,sc8180x-qup-virt"; 526 #interconnect-cells = <2>; 527 qcom,bcm-voters = <&apps_bcm_voter>; 528 }; 529 530 memory@80000000 { 531 device_type = "memory"; 532 /* We expect the bootloader to fill in the size */ 533 reg = <0x0 0x80000000 0x0 0x0>; 534 }; 535 536 pmu { 537 compatible = "arm,armv8-pmuv3"; 538 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 539 }; 540 541 psci { 542 compatible = "arm,psci-1.0"; 543 method = "smc"; 544 545 cpu_pd0: power-domain-cpu0 { 546 #power-domain-cells = <0>; 547 power-domains = <&cluster_pd>; 548 domain-idle-states = <&little_cpu_sleep_0>; 549 }; 550 551 cpu_pd1: power-domain-cpu1 { 552 #power-domain-cells = <0>; 553 power-domains = <&cluster_pd>; 554 domain-idle-states = <&little_cpu_sleep_0>; 555 }; 556 557 cpu_pd2: power-domain-cpu2 { 558 #power-domain-cells = <0>; 559 power-domains = <&cluster_pd>; 560 domain-idle-states = <&little_cpu_sleep_0>; 561 }; 562 563 cpu_pd3: power-domain-cpu3 { 564 #power-domain-cells = <0>; 565 power-domains = <&cluster_pd>; 566 domain-idle-states = <&little_cpu_sleep_0>; 567 }; 568 569 cpu_pd4: power-domain-cpu4 { 570 #power-domain-cells = <0>; 571 power-domains = <&cluster_pd>; 572 domain-idle-states = <&big_cpu_sleep_0>; 573 }; 574 575 cpu_pd5: power-domain-cpu5 { 576 #power-domain-cells = <0>; 577 power-domains = <&cluster_pd>; 578 domain-idle-states = <&big_cpu_sleep_0>; 579 }; 580 581 cpu_pd6: power-domain-cpu6 { 582 #power-domain-cells = <0>; 583 power-domains = <&cluster_pd>; 584 domain-idle-states = <&big_cpu_sleep_0>; 585 }; 586 587 cpu_pd7: power-domain-cpu7 { 588 #power-domain-cells = <0>; 589 power-domains = <&cluster_pd>; 590 domain-idle-states = <&big_cpu_sleep_0>; 591 }; 592 593 cluster_pd: power-domain-cpu-cluster0 { 594 #power-domain-cells = <0>; 595 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>; 596 }; 597 }; 598 599 reserved-memory { 600 #address-cells = <2>; 601 #size-cells = <2>; 602 ranges; 603 604 hyp_mem: hyp@85700000 { 605 reg = <0x0 0x85700000 0x0 0x600000>; 606 no-map; 607 }; 608 609 xbl_mem: xbl@85d00000 { 610 reg = <0x0 0x85d00000 0x0 0x140000>; 611 no-map; 612 }; 613 614 aop_mem: aop@85f00000 { 615 reg = <0x0 0x85f00000 0x0 0x20000>; 616 no-map; 617 }; 618 619 aop_cmd_db: cmd-db@85f20000 { 620 compatible = "qcom,cmd-db"; 621 reg = <0x0 0x85f20000 0x0 0x20000>; 622 no-map; 623 }; 624 625 reserved@85f40000 { 626 reg = <0x0 0x85f40000 0x0 0x10000>; 627 no-map; 628 }; 629 630 smem_mem: smem@86000000 { 631 compatible = "qcom,smem"; 632 reg = <0x0 0x86000000 0x0 0x200000>; 633 no-map; 634 hwlocks = <&tcsr_mutex 3>; 635 }; 636 637 reserved@86200000 { 638 reg = <0x0 0x86200000 0x0 0x3900000>; 639 no-map; 640 }; 641 642 reserved@89b00000 { 643 reg = <0x0 0x89b00000 0x0 0x1c00000>; 644 no-map; 645 }; 646 647 reserved@9d400000 { 648 reg = <0x0 0x9d400000 0x0 0x1000000>; 649 no-map; 650 }; 651 652 reserved@9e400000 { 653 reg = <0x0 0x9e400000 0x0 0x1400000>; 654 no-map; 655 }; 656 657 reserved@9f800000 { 658 reg = <0x0 0x9f800000 0x0 0x800000>; 659 no-map; 660 }; 661 }; 662 663 smp2p-cdsp { 664 compatible = "qcom,smp2p"; 665 qcom,smem = <94>, <432>; 666 667 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 668 669 mboxes = <&apss_shared 6>; 670 671 qcom,local-pid = <0>; 672 qcom,remote-pid = <5>; 673 674 cdsp_smp2p_out: master-kernel { 675 qcom,entry-name = "master-kernel"; 676 #qcom,smem-state-cells = <1>; 677 }; 678 679 cdsp_smp2p_in: slave-kernel { 680 qcom,entry-name = "slave-kernel"; 681 682 interrupt-controller; 683 #interrupt-cells = <2>; 684 }; 685 }; 686 687 smp2p-lpass { 688 compatible = "qcom,smp2p"; 689 qcom,smem = <443>, <429>; 690 691 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 692 693 mboxes = <&apss_shared 10>; 694 695 qcom,local-pid = <0>; 696 qcom,remote-pid = <2>; 697 698 adsp_smp2p_out: master-kernel { 699 qcom,entry-name = "master-kernel"; 700 #qcom,smem-state-cells = <1>; 701 }; 702 703 adsp_smp2p_in: slave-kernel { 704 qcom,entry-name = "slave-kernel"; 705 706 interrupt-controller; 707 #interrupt-cells = <2>; 708 }; 709 }; 710 711 smp2p-mpss { 712 compatible = "qcom,smp2p"; 713 qcom,smem = <435>, <428>; 714 715 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 716 717 mboxes = <&apss_shared 14>; 718 719 qcom,local-pid = <0>; 720 qcom,remote-pid = <1>; 721 722 modem_smp2p_out: master-kernel { 723 qcom,entry-name = "master-kernel"; 724 #qcom,smem-state-cells = <1>; 725 }; 726 727 modem_smp2p_in: slave-kernel { 728 qcom,entry-name = "slave-kernel"; 729 730 interrupt-controller; 731 #interrupt-cells = <2>; 732 }; 733 734 modem_smp2p_ipa_out: ipa-ap-to-modem { 735 qcom,entry-name = "ipa"; 736 #qcom,smem-state-cells = <1>; 737 }; 738 739 modem_smp2p_ipa_in: ipa-modem-to-ap { 740 qcom,entry-name = "ipa"; 741 interrupt-controller; 742 #interrupt-cells = <2>; 743 }; 744 745 modem_smp2p_wlan_in: wlan-wpss-to-ap { 746 qcom,entry-name = "wlan"; 747 interrupt-controller; 748 #interrupt-cells = <2>; 749 }; 750 }; 751 752 smp2p-slpi { 753 compatible = "qcom,smp2p"; 754 qcom,smem = <481>, <430>; 755 756 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 757 758 mboxes = <&apss_shared 26>; 759 760 qcom,local-pid = <0>; 761 qcom,remote-pid = <3>; 762 763 slpi_smp2p_out: master-kernel { 764 qcom,entry-name = "master-kernel"; 765 #qcom,smem-state-cells = <1>; 766 }; 767 768 slpi_smp2p_in: slave-kernel { 769 qcom,entry-name = "slave-kernel"; 770 771 interrupt-controller; 772 #interrupt-cells = <2>; 773 }; 774 }; 775 776 soc: soc@0 { 777 compatible = "simple-bus"; 778 #address-cells = <2>; 779 #size-cells = <2>; 780 ranges = <0 0 0 0 0x10 0>; 781 dma-ranges = <0 0 0 0 0x10 0>; 782 783 gcc: clock-controller@100000 { 784 compatible = "qcom,gcc-sc8180x"; 785 reg = <0x0 0x00100000 0x0 0x1f0000>; 786 #clock-cells = <1>; 787 #reset-cells = <1>; 788 #power-domain-cells = <1>; 789 clocks = <&rpmhcc RPMH_CXO_CLK>, 790 <&rpmhcc RPMH_CXO_CLK_A>, 791 <&sleep_clk>; 792 clock-names = "bi_tcxo", 793 "bi_tcxo_ao", 794 "sleep_clk"; 795 power-domains = <&rpmhpd SC8180X_CX>; 796 }; 797 798 qupv3_id_0: geniqup@8c0000 { 799 compatible = "qcom,geni-se-qup"; 800 reg = <0 0x008c0000 0 0x6000>; 801 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 802 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 803 clock-names = "m-ahb", "s-ahb"; 804 #address-cells = <2>; 805 #size-cells = <2>; 806 ranges; 807 iommus = <&apps_smmu 0x4c3 0>; 808 status = "disabled"; 809 810 i2c0: i2c@880000 { 811 compatible = "qcom,geni-i2c"; 812 reg = <0 0x00880000 0 0x4000>; 813 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 814 clock-names = "se"; 815 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 816 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 817 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 818 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 819 interconnect-names = "qup-core", "qup-config", "qup-memory"; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 status = "disabled"; 823 }; 824 825 spi0: spi@880000 { 826 compatible = "qcom,geni-spi"; 827 reg = <0 0x00880000 0 0x4000>; 828 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 829 clock-names = "se"; 830 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 831 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 832 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 833 interconnect-names = "qup-core", "qup-config"; 834 #address-cells = <1>; 835 #size-cells = <0>; 836 status = "disabled"; 837 }; 838 839 uart0: serial@880000 { 840 compatible = "qcom,geni-uart"; 841 reg = <0 0x00880000 0 0x4000>; 842 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 843 clock-names = "se"; 844 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 845 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 846 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 847 interconnect-names = "qup-core", "qup-config"; 848 status = "disabled"; 849 }; 850 851 i2c1: i2c@884000 { 852 compatible = "qcom,geni-i2c"; 853 reg = <0 0x00884000 0 0x4000>; 854 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 855 clock-names = "se"; 856 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 857 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 858 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 859 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 860 interconnect-names = "qup-core", "qup-config", "qup-memory"; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 status = "disabled"; 864 }; 865 866 spi1: spi@884000 { 867 compatible = "qcom,geni-spi"; 868 reg = <0 0x00884000 0 0x4000>; 869 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 870 clock-names = "se"; 871 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 872 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 873 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 874 interconnect-names = "qup-core", "qup-config"; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 status = "disabled"; 878 }; 879 880 uart1: serial@884000 { 881 compatible = "qcom,geni-uart"; 882 reg = <0 0x00884000 0 0x4000>; 883 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 884 clock-names = "se"; 885 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 886 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 887 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 888 interconnect-names = "qup-core", "qup-config"; 889 status = "disabled"; 890 }; 891 892 i2c2: i2c@888000 { 893 compatible = "qcom,geni-i2c"; 894 reg = <0 0x00888000 0 0x4000>; 895 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 896 clock-names = "se"; 897 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 898 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 899 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 900 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 901 interconnect-names = "qup-core", "qup-config", "qup-memory"; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 status = "disabled"; 905 }; 906 907 spi2: spi@888000 { 908 compatible = "qcom,geni-spi"; 909 reg = <0 0x00888000 0 0x4000>; 910 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 911 clock-names = "se"; 912 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 913 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 914 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 915 interconnect-names = "qup-core", "qup-config"; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 status = "disabled"; 919 }; 920 921 uart2: serial@888000 { 922 compatible = "qcom,geni-uart"; 923 reg = <0 0x00888000 0 0x4000>; 924 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 925 clock-names = "se"; 926 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 927 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 928 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 929 interconnect-names = "qup-core", "qup-config"; 930 status = "disabled"; 931 }; 932 933 i2c3: i2c@88c000 { 934 compatible = "qcom,geni-i2c"; 935 reg = <0 0x0088c000 0 0x4000>; 936 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 937 clock-names = "se"; 938 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 939 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 940 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 941 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 942 interconnect-names = "qup-core", "qup-config", "qup-memory"; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 status = "disabled"; 946 }; 947 948 spi3: spi@88c000 { 949 compatible = "qcom,geni-spi"; 950 reg = <0 0x0088c000 0 0x4000>; 951 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 952 clock-names = "se"; 953 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 954 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 955 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 956 interconnect-names = "qup-core", "qup-config"; 957 #address-cells = <1>; 958 #size-cells = <0>; 959 status = "disabled"; 960 }; 961 962 uart3: serial@88c000 { 963 compatible = "qcom,geni-uart"; 964 reg = <0 0x0088c000 0 0x4000>; 965 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 966 clock-names = "se"; 967 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 968 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 969 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 970 interconnect-names = "qup-core", "qup-config"; 971 status = "disabled"; 972 }; 973 974 i2c4: i2c@890000 { 975 compatible = "qcom,geni-i2c"; 976 reg = <0 0x00890000 0 0x4000>; 977 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 978 clock-names = "se"; 979 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 980 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 981 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 982 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 983 interconnect-names = "qup-core", "qup-config", "qup-memory"; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 status = "disabled"; 987 }; 988 989 spi4: spi@890000 { 990 compatible = "qcom,geni-spi"; 991 reg = <0 0x00890000 0 0x4000>; 992 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 993 clock-names = "se"; 994 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 995 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 996 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 997 interconnect-names = "qup-core", "qup-config"; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 uart4: serial@890000 { 1004 compatible = "qcom,geni-uart"; 1005 reg = <0 0x00890000 0 0x4000>; 1006 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1007 clock-names = "se"; 1008 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1009 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1010 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1011 interconnect-names = "qup-core", "qup-config"; 1012 status = "disabled"; 1013 }; 1014 1015 i2c5: i2c@894000 { 1016 compatible = "qcom,geni-i2c"; 1017 reg = <0 0x00894000 0 0x4000>; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1019 clock-names = "se"; 1020 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1021 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1022 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1023 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1024 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 status = "disabled"; 1028 }; 1029 1030 spi5: spi@894000 { 1031 compatible = "qcom,geni-spi"; 1032 reg = <0 0x00894000 0 0x4000>; 1033 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1034 clock-names = "se"; 1035 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1036 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1037 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1038 interconnect-names = "qup-core", "qup-config"; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 status = "disabled"; 1042 }; 1043 1044 uart5: serial@894000 { 1045 compatible = "qcom,geni-uart"; 1046 reg = <0 0x00894000 0 0x4000>; 1047 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1048 clock-names = "se"; 1049 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1050 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1051 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1052 interconnect-names = "qup-core", "qup-config"; 1053 status = "disabled"; 1054 }; 1055 1056 i2c6: i2c@898000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0 0x00898000 0 0x4000>; 1059 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1060 clock-names = "se"; 1061 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1062 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1063 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1064 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1065 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 status = "disabled"; 1069 }; 1070 1071 spi6: spi@898000 { 1072 compatible = "qcom,geni-spi"; 1073 reg = <0 0x00898000 0 0x4000>; 1074 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1075 clock-names = "se"; 1076 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1077 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1078 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1079 interconnect-names = "qup-core", "qup-config"; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 status = "disabled"; 1083 }; 1084 1085 uart6: serial@898000 { 1086 compatible = "qcom,geni-uart"; 1087 reg = <0 0x00898000 0 0x4000>; 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1089 clock-names = "se"; 1090 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1091 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1092 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1093 interconnect-names = "qup-core", "qup-config"; 1094 status = "disabled"; 1095 }; 1096 1097 i2c7: i2c@89c000 { 1098 compatible = "qcom,geni-i2c"; 1099 reg = <0 0x0089c000 0 0x4000>; 1100 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1101 clock-names = "se"; 1102 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1103 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1104 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1105 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1106 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 status = "disabled"; 1110 }; 1111 1112 spi7: spi@89c000 { 1113 compatible = "qcom,geni-spi"; 1114 reg = <0 0x0089c000 0 0x4000>; 1115 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1116 clock-names = "se"; 1117 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1118 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1119 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1120 interconnect-names = "qup-core", "qup-config"; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 uart7: serial@89c000 { 1127 compatible = "qcom,geni-uart"; 1128 reg = <0 0x0089c000 0 0x4000>; 1129 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1130 clock-names = "se"; 1131 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1132 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1133 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1134 interconnect-names = "qup-core", "qup-config"; 1135 status = "disabled"; 1136 }; 1137 }; 1138 1139 qupv3_id_1: geniqup@ac0000 { 1140 compatible = "qcom,geni-se-qup"; 1141 reg = <0x0 0x00ac0000 0x0 0x6000>; 1142 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1143 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1144 clock-names = "m-ahb", "s-ahb"; 1145 #address-cells = <2>; 1146 #size-cells = <2>; 1147 ranges; 1148 iommus = <&apps_smmu 0x603 0>; 1149 status = "disabled"; 1150 1151 i2c8: i2c@a80000 { 1152 compatible = "qcom,geni-i2c"; 1153 reg = <0 0x00a80000 0 0x4000>; 1154 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1155 clock-names = "se"; 1156 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1157 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1158 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1159 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1160 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 status = "disabled"; 1164 }; 1165 1166 spi8: spi@a80000 { 1167 compatible = "qcom,geni-spi"; 1168 reg = <0 0x00a80000 0 0x4000>; 1169 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1170 clock-names = "se"; 1171 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1172 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1173 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1174 interconnect-names = "qup-core", "qup-config"; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 status = "disabled"; 1178 }; 1179 1180 uart8: serial@a80000 { 1181 compatible = "qcom,geni-uart"; 1182 reg = <0 0x00a80000 0 0x4000>; 1183 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1184 clock-names = "se"; 1185 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1186 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1187 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1188 interconnect-names = "qup-core", "qup-config"; 1189 status = "disabled"; 1190 }; 1191 1192 i2c9: i2c@a84000 { 1193 compatible = "qcom,geni-i2c"; 1194 reg = <0 0x00a84000 0 0x4000>; 1195 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1196 clock-names = "se"; 1197 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1198 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1199 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1200 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1201 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 status = "disabled"; 1205 }; 1206 1207 spi9: spi@a84000 { 1208 compatible = "qcom,geni-spi"; 1209 reg = <0 0x00a84000 0 0x4000>; 1210 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1211 clock-names = "se"; 1212 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1213 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1214 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1215 interconnect-names = "qup-core", "qup-config"; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 status = "disabled"; 1219 }; 1220 1221 uart9: serial@a84000 { 1222 compatible = "qcom,geni-debug-uart"; 1223 reg = <0 0x00a84000 0 0x4000>; 1224 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1225 clock-names = "se"; 1226 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1227 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1228 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1229 interconnect-names = "qup-core", "qup-config"; 1230 status = "disabled"; 1231 }; 1232 1233 i2c10: i2c@a88000 { 1234 compatible = "qcom,geni-i2c"; 1235 reg = <0 0x00a88000 0 0x4000>; 1236 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1237 clock-names = "se"; 1238 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1239 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1240 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1241 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1242 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1243 #address-cells = <1>; 1244 #size-cells = <0>; 1245 status = "disabled"; 1246 }; 1247 1248 spi10: spi@a88000 { 1249 compatible = "qcom,geni-spi"; 1250 reg = <0 0x00a88000 0 0x4000>; 1251 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1252 clock-names = "se"; 1253 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1254 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1255 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1256 interconnect-names = "qup-core", "qup-config"; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 status = "disabled"; 1260 }; 1261 1262 uart10: serial@a88000 { 1263 compatible = "qcom,geni-uart"; 1264 reg = <0 0x00a88000 0 0x4000>; 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1266 clock-names = "se"; 1267 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1268 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1269 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1270 interconnect-names = "qup-core", "qup-config"; 1271 status = "disabled"; 1272 }; 1273 1274 i2c11: i2c@a8c000 { 1275 compatible = "qcom,geni-i2c"; 1276 reg = <0 0x00a8c000 0 0x4000>; 1277 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1278 clock-names = "se"; 1279 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1280 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1281 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1282 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1283 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 status = "disabled"; 1287 }; 1288 1289 spi11: spi@a8c000 { 1290 compatible = "qcom,geni-spi"; 1291 reg = <0 0x00a8c000 0 0x4000>; 1292 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1293 clock-names = "se"; 1294 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1295 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1296 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1297 interconnect-names = "qup-core", "qup-config"; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 status = "disabled"; 1301 }; 1302 1303 uart11: serial@a8c000 { 1304 compatible = "qcom,geni-uart"; 1305 reg = <0 0x00a8c000 0 0x4000>; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1307 clock-names = "se"; 1308 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1309 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1310 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1311 interconnect-names = "qup-core", "qup-config"; 1312 status = "disabled"; 1313 }; 1314 1315 i2c12: i2c@a90000 { 1316 compatible = "qcom,geni-i2c"; 1317 reg = <0 0x00a90000 0 0x4000>; 1318 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1319 clock-names = "se"; 1320 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1321 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1322 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1323 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1324 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 status = "disabled"; 1328 }; 1329 1330 spi12: spi@a90000 { 1331 compatible = "qcom,geni-spi"; 1332 reg = <0 0x00a90000 0 0x4000>; 1333 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1334 clock-names = "se"; 1335 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1336 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1337 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1338 interconnect-names = "qup-core", "qup-config"; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 status = "disabled"; 1342 }; 1343 1344 uart12: serial@a90000 { 1345 compatible = "qcom,geni-uart"; 1346 reg = <0 0x00a90000 0 0x4000>; 1347 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1348 clock-names = "se"; 1349 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1350 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1351 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1352 interconnect-names = "qup-core", "qup-config"; 1353 status = "disabled"; 1354 }; 1355 1356 i2c16: i2c@a94000 { 1357 compatible = "qcom,geni-i2c"; 1358 reg = <0 0x00a94000 0 0x4000>; 1359 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1360 clock-names = "se"; 1361 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1362 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1363 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1364 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1365 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 status = "disabled"; 1369 }; 1370 1371 spi16: spi@a94000 { 1372 compatible = "qcom,geni-spi"; 1373 reg = <0 0x00a94000 0 0x4000>; 1374 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1375 clock-names = "se"; 1376 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1377 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1378 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1379 interconnect-names = "qup-core", "qup-config"; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 status = "disabled"; 1383 }; 1384 1385 uart16: serial@a94000 { 1386 compatible = "qcom,geni-uart"; 1387 reg = <0 0x00a94000 0 0x4000>; 1388 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1389 clock-names = "se"; 1390 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1391 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1392 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1393 interconnect-names = "qup-core", "qup-config"; 1394 status = "disabled"; 1395 }; 1396 }; 1397 1398 qupv3_id_2: geniqup@cc0000 { 1399 compatible = "qcom,geni-se-qup"; 1400 reg = <0x0 0x00cc0000 0x0 0x6000>; 1401 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1402 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1403 clock-names = "m-ahb", "s-ahb"; 1404 #address-cells = <2>; 1405 #size-cells = <2>; 1406 ranges; 1407 iommus = <&apps_smmu 0x7a3 0>; 1408 status = "disabled"; 1409 1410 i2c17: i2c@c80000 { 1411 compatible = "qcom,geni-i2c"; 1412 reg = <0 0x00c80000 0 0x4000>; 1413 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1414 clock-names = "se"; 1415 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1416 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1417 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1418 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1419 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 status = "disabled"; 1423 }; 1424 1425 spi17: spi@c80000 { 1426 compatible = "qcom,geni-spi"; 1427 reg = <0 0x00c80000 0 0x4000>; 1428 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1429 clock-names = "se"; 1430 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1431 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1432 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1433 interconnect-names = "qup-core", "qup-config"; 1434 #address-cells = <1>; 1435 #size-cells = <0>; 1436 status = "disabled"; 1437 }; 1438 1439 uart17: serial@c80000 { 1440 compatible = "qcom,geni-uart"; 1441 reg = <0 0x00c80000 0 0x4000>; 1442 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1443 clock-names = "se"; 1444 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1445 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1446 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1447 interconnect-names = "qup-core", "qup-config"; 1448 status = "disabled"; 1449 }; 1450 1451 i2c18: i2c@c84000 { 1452 compatible = "qcom,geni-i2c"; 1453 reg = <0 0x00c84000 0 0x4000>; 1454 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1455 clock-names = "se"; 1456 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1457 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1458 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1459 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1460 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 status = "disabled"; 1464 }; 1465 1466 spi18: spi@c84000 { 1467 compatible = "qcom,geni-spi"; 1468 reg = <0 0x00c84000 0 0x4000>; 1469 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1470 clock-names = "se"; 1471 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1472 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1473 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1474 interconnect-names = "qup-core", "qup-config"; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 status = "disabled"; 1478 }; 1479 1480 uart18: serial@c84000 { 1481 compatible = "qcom,geni-uart"; 1482 reg = <0 0x00c84000 0 0x4000>; 1483 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1484 clock-names = "se"; 1485 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1486 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1487 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1488 interconnect-names = "qup-core", "qup-config"; 1489 status = "disabled"; 1490 }; 1491 1492 i2c19: i2c@c88000 { 1493 compatible = "qcom,geni-i2c"; 1494 reg = <0 0x00c88000 0 0x4000>; 1495 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1496 clock-names = "se"; 1497 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1498 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1499 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1500 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1501 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1502 #address-cells = <1>; 1503 #size-cells = <0>; 1504 status = "disabled"; 1505 }; 1506 1507 spi19: spi@c88000 { 1508 compatible = "qcom,geni-spi"; 1509 reg = <0 0x00c88000 0 0x4000>; 1510 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1511 clock-names = "se"; 1512 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1513 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1514 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1515 interconnect-names = "qup-core", "qup-config"; 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 status = "disabled"; 1519 }; 1520 1521 uart19: serial@c88000 { 1522 compatible = "qcom,geni-uart"; 1523 reg = <0 0x00c88000 0 0x4000>; 1524 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1525 clock-names = "se"; 1526 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1527 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1528 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1529 interconnect-names = "qup-core", "qup-config"; 1530 status = "disabled"; 1531 }; 1532 1533 i2c13: i2c@c8c000 { 1534 compatible = "qcom,geni-i2c"; 1535 reg = <0 0x00c8c000 0 0x4000>; 1536 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1537 clock-names = "se"; 1538 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1539 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1540 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1541 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1542 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1543 #address-cells = <1>; 1544 #size-cells = <0>; 1545 status = "disabled"; 1546 }; 1547 1548 spi13: spi@c8c000 { 1549 compatible = "qcom,geni-spi"; 1550 reg = <0 0x00c8c000 0 0x4000>; 1551 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1552 clock-names = "se"; 1553 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1554 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1555 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1556 interconnect-names = "qup-core", "qup-config"; 1557 #address-cells = <1>; 1558 #size-cells = <0>; 1559 status = "disabled"; 1560 }; 1561 1562 uart13: serial@c8c000 { 1563 compatible = "qcom,geni-uart"; 1564 reg = <0 0x00c8c000 0 0x4000>; 1565 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1566 clock-names = "se"; 1567 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1568 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1569 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1570 interconnect-names = "qup-core", "qup-config"; 1571 status = "disabled"; 1572 }; 1573 1574 i2c14: i2c@c90000 { 1575 compatible = "qcom,geni-i2c"; 1576 reg = <0 0x00c90000 0 0x4000>; 1577 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1578 clock-names = "se"; 1579 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1580 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1581 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1582 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1583 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1584 #address-cells = <1>; 1585 #size-cells = <0>; 1586 status = "disabled"; 1587 }; 1588 1589 spi14: spi@c90000 { 1590 compatible = "qcom,geni-spi"; 1591 reg = <0 0x00c90000 0 0x4000>; 1592 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1593 clock-names = "se"; 1594 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1595 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1596 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1597 interconnect-names = "qup-core", "qup-config"; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 status = "disabled"; 1601 }; 1602 1603 uart14: serial@c90000 { 1604 compatible = "qcom,geni-uart"; 1605 reg = <0 0x00c90000 0 0x4000>; 1606 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1607 clock-names = "se"; 1608 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1609 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1610 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1611 interconnect-names = "qup-core", "qup-config"; 1612 status = "disabled"; 1613 }; 1614 1615 i2c15: i2c@c94000 { 1616 compatible = "qcom,geni-i2c"; 1617 reg = <0 0x00c94000 0 0x4000>; 1618 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1619 clock-names = "se"; 1620 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1621 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1622 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1623 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1624 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 status = "disabled"; 1628 }; 1629 1630 spi15: spi@c94000 { 1631 compatible = "qcom,geni-spi"; 1632 reg = <0 0x00c94000 0 0x4000>; 1633 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1634 clock-names = "se"; 1635 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1636 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1637 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1638 interconnect-names = "qup-core", "qup-config"; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 status = "disabled"; 1642 }; 1643 1644 uart15: serial@c94000 { 1645 compatible = "qcom,geni-uart"; 1646 reg = <0 0x00c94000 0 0x4000>; 1647 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1648 clock-names = "se"; 1649 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1650 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1651 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1652 interconnect-names = "qup-core", "qup-config"; 1653 status = "disabled"; 1654 }; 1655 }; 1656 1657 config_noc: interconnect@1500000 { 1658 compatible = "qcom,sc8180x-config-noc"; 1659 reg = <0 0x01500000 0 0x7400>; 1660 #interconnect-cells = <2>; 1661 qcom,bcm-voters = <&apps_bcm_voter>; 1662 }; 1663 1664 system_noc: interconnect@1620000 { 1665 compatible = "qcom,sc8180x-system-noc"; 1666 reg = <0 0x01620000 0 0x19400>; 1667 #interconnect-cells = <2>; 1668 qcom,bcm-voters = <&apps_bcm_voter>; 1669 }; 1670 1671 aggre1_noc: interconnect@16e0000 { 1672 compatible = "qcom,sc8180x-aggre1-noc"; 1673 reg = <0 0x016e0000 0 0xd080>; 1674 #interconnect-cells = <2>; 1675 qcom,bcm-voters = <&apps_bcm_voter>; 1676 }; 1677 1678 aggre2_noc: interconnect@1700000 { 1679 compatible = "qcom,sc8180x-aggre2-noc"; 1680 reg = <0 0x01700000 0 0x20000>; 1681 #interconnect-cells = <2>; 1682 qcom,bcm-voters = <&apps_bcm_voter>; 1683 }; 1684 1685 compute_noc: interconnect@1720000 { 1686 compatible = "qcom,sc8180x-compute-noc"; 1687 reg = <0 0x01720000 0 0x7000>; 1688 #interconnect-cells = <2>; 1689 qcom,bcm-voters = <&apps_bcm_voter>; 1690 }; 1691 1692 mmss_noc: interconnect@1740000 { 1693 compatible = "qcom,sc8180x-mmss-noc"; 1694 reg = <0 0x01740000 0 0x1c100>; 1695 #interconnect-cells = <2>; 1696 qcom,bcm-voters = <&apps_bcm_voter>; 1697 }; 1698 1699 pcie0: pcie@1c00000 { 1700 compatible = "qcom,pcie-sc8180x"; 1701 reg = <0 0x01c00000 0 0x3000>, 1702 <0 0x60000000 0 0xf1d>, 1703 <0 0x60000f20 0 0xa8>, 1704 <0 0x60001000 0 0x1000>, 1705 <0 0x60100000 0 0x100000>; 1706 reg-names = "parf", 1707 "dbi", 1708 "elbi", 1709 "atu", 1710 "config"; 1711 device_type = "pci"; 1712 linux,pci-domain = <0>; 1713 bus-range = <0x00 0xff>; 1714 num-lanes = <2>; 1715 1716 #address-cells = <3>; 1717 #size-cells = <2>; 1718 1719 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, 1720 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1721 1722 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1730 interrupt-names = "msi0", 1731 "msi1", 1732 "msi2", 1733 "msi3", 1734 "msi4", 1735 "msi5", 1736 "msi6", 1737 "msi7"; 1738 #interrupt-cells = <1>; 1739 interrupt-map-mask = <0 0 0 0x7>; 1740 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1741 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1742 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1743 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1744 1745 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1746 <&gcc GCC_PCIE_0_AUX_CLK>, 1747 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1748 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1749 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1750 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1751 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1752 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1753 clock-names = "pipe", 1754 "aux", 1755 "cfg", 1756 "bus_master", 1757 "bus_slave", 1758 "slave_q2a", 1759 "ref", 1760 "tbu"; 1761 1762 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1763 assigned-clock-rates = <19200000>; 1764 1765 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1766 <0x100 &apps_smmu 0x1d81 0x1>; 1767 1768 resets = <&gcc GCC_PCIE_0_BCR>; 1769 reset-names = "pci"; 1770 1771 power-domains = <&gcc PCIE_0_GDSC>; 1772 1773 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, 1774 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1775 interconnect-names = "pcie-mem", "cpu-pcie"; 1776 1777 phys = <&pcie0_phy>; 1778 phy-names = "pciephy"; 1779 dma-coherent; 1780 1781 status = "disabled"; 1782 1783 pcie@0 { 1784 device_type = "pci"; 1785 reg = <0x0 0x0 0x0 0x0 0x0>; 1786 bus-range = <0x01 0xff>; 1787 1788 #address-cells = <3>; 1789 #size-cells = <2>; 1790 ranges; 1791 }; 1792 }; 1793 1794 pcie0_phy: phy@1c06000 { 1795 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1796 reg = <0 0x01c06000 0 0x1000>; 1797 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1798 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1799 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1800 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1801 <&gcc GCC_PCIE_0_PIPE_CLK>; 1802 clock-names = "aux", 1803 "cfg_ahb", 1804 "ref", 1805 "refgen", 1806 "pipe"; 1807 #clock-cells = <0>; 1808 clock-output-names = "pcie_0_pipe_clk"; 1809 #phy-cells = <0>; 1810 1811 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1812 reset-names = "phy"; 1813 1814 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1815 assigned-clock-rates = <100000000>; 1816 1817 status = "disabled"; 1818 }; 1819 1820 pcie3: pcie@1c08000 { 1821 compatible = "qcom,pcie-sc8180x"; 1822 reg = <0 0x01c08000 0 0x3000>, 1823 <0 0x40000000 0 0xf1d>, 1824 <0 0x40000f20 0 0xa8>, 1825 <0 0x40001000 0 0x1000>, 1826 <0 0x40100000 0 0x100000>; 1827 reg-names = "parf", 1828 "dbi", 1829 "elbi", 1830 "atu", 1831 "config"; 1832 device_type = "pci"; 1833 linux,pci-domain = <3>; 1834 bus-range = <0x00 0xff>; 1835 num-lanes = <2>; 1836 1837 #address-cells = <3>; 1838 #size-cells = <2>; 1839 1840 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1841 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1842 1843 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1851 interrupt-names = "msi0", 1852 "msi1", 1853 "msi2", 1854 "msi3", 1855 "msi4", 1856 "msi5", 1857 "msi6", 1858 "msi7"; 1859 #interrupt-cells = <1>; 1860 interrupt-map-mask = <0 0 0 0x7>; 1861 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1862 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1863 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1864 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1865 1866 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, 1867 <&gcc GCC_PCIE_3_AUX_CLK>, 1868 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1869 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 1870 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 1871 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 1872 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1873 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1874 clock-names = "pipe", 1875 "aux", 1876 "cfg", 1877 "bus_master", 1878 "bus_slave", 1879 "slave_q2a", 1880 "ref", 1881 "tbu"; 1882 1883 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 1884 assigned-clock-rates = <19200000>; 1885 1886 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1887 <0x100 &apps_smmu 0x1e01 0x1>; 1888 1889 resets = <&gcc GCC_PCIE_3_BCR>; 1890 reset-names = "pci"; 1891 1892 power-domains = <&gcc PCIE_3_GDSC>; 1893 1894 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, 1895 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>; 1896 interconnect-names = "pcie-mem", "cpu-pcie"; 1897 1898 phys = <&pcie3_phy>; 1899 phy-names = "pciephy"; 1900 dma-coherent; 1901 1902 status = "disabled"; 1903 1904 pcie@0 { 1905 device_type = "pci"; 1906 reg = <0x0 0x0 0x0 0x0 0x0>; 1907 bus-range = <0x01 0xff>; 1908 1909 #address-cells = <3>; 1910 #size-cells = <2>; 1911 ranges; 1912 }; 1913 }; 1914 1915 pcie3_phy: phy@1c0c000 { 1916 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1917 reg = <0 0x01c0c000 0 0x1000>; 1918 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1919 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1920 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1921 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, 1922 <&gcc GCC_PCIE_3_PIPE_CLK>; 1923 clock-names = "aux", 1924 "cfg_ahb", 1925 "ref", 1926 "refgen", 1927 "pipe"; 1928 #clock-cells = <0>; 1929 clock-output-names = "pcie_3_pipe_clk"; 1930 1931 #phy-cells = <0>; 1932 1933 resets = <&gcc GCC_PCIE_3_PHY_BCR>; 1934 reset-names = "phy"; 1935 1936 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; 1937 assigned-clock-rates = <100000000>; 1938 1939 status = "disabled"; 1940 }; 1941 1942 pcie1: pcie@1c10000 { 1943 compatible = "qcom,pcie-sc8180x"; 1944 reg = <0 0x01c10000 0 0x3000>, 1945 <0 0x68000000 0 0xf1d>, 1946 <0 0x68000f20 0 0xa8>, 1947 <0 0x68001000 0 0x1000>, 1948 <0 0x68100000 0 0x100000>; 1949 reg-names = "parf", 1950 "dbi", 1951 "elbi", 1952 "atu", 1953 "config"; 1954 device_type = "pci"; 1955 linux,pci-domain = <1>; 1956 bus-range = <0x00 0xff>; 1957 num-lanes = <2>; 1958 1959 #address-cells = <3>; 1960 #size-cells = <2>; 1961 1962 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, 1963 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; 1964 1965 interrupts = <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>; 1973 interrupt-names = "msi0", 1974 "msi1", 1975 "msi2", 1976 "msi3", 1977 "msi4", 1978 "msi5", 1979 "msi6", 1980 "msi7"; 1981 #interrupt-cells = <1>; 1982 interrupt-map-mask = <0 0 0 0x7>; 1983 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1984 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1985 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1986 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1987 1988 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1989 <&gcc GCC_PCIE_1_AUX_CLK>, 1990 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1991 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1992 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1993 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1994 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1995 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1996 clock-names = "pipe", 1997 "aux", 1998 "cfg", 1999 "bus_master", 2000 "bus_slave", 2001 "slave_q2a", 2002 "ref", 2003 "tbu"; 2004 2005 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2006 assigned-clock-rates = <19200000>; 2007 2008 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2009 <0x100 &apps_smmu 0x1c81 0x1>; 2010 2011 resets = <&gcc GCC_PCIE_1_BCR>; 2012 reset-names = "pci"; 2013 2014 power-domains = <&gcc PCIE_1_GDSC>; 2015 2016 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2017 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>; 2018 interconnect-names = "pcie-mem", "cpu-pcie"; 2019 2020 phys = <&pcie1_phy>; 2021 phy-names = "pciephy"; 2022 dma-coherent; 2023 2024 status = "disabled"; 2025 2026 pcie@0 { 2027 device_type = "pci"; 2028 reg = <0x0 0x0 0x0 0x0 0x0>; 2029 bus-range = <0x01 0xff>; 2030 2031 #address-cells = <3>; 2032 #size-cells = <2>; 2033 ranges; 2034 }; 2035 }; 2036 2037 pcie1_phy: phy@1c16000 { 2038 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2039 reg = <0 0x01c16000 0 0x1000>; 2040 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2041 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2042 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2043 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2044 <&gcc GCC_PCIE_1_PIPE_CLK>; 2045 clock-names = "aux", 2046 "cfg_ahb", 2047 "ref", 2048 "refgen", 2049 "pipe"; 2050 #clock-cells = <0>; 2051 clock-output-names = "pcie_1_pipe_clk"; 2052 2053 #phy-cells = <0>; 2054 2055 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2056 reset-names = "phy"; 2057 2058 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2059 assigned-clock-rates = <100000000>; 2060 2061 status = "disabled"; 2062 }; 2063 2064 pcie2: pcie@1c18000 { 2065 compatible = "qcom,pcie-sc8180x"; 2066 reg = <0 0x01c18000 0 0x3000>, 2067 <0 0x70000000 0 0xf1d>, 2068 <0 0x70000f20 0 0xa8>, 2069 <0 0x70001000 0 0x1000>, 2070 <0 0x70100000 0 0x100000>; 2071 reg-names = "parf", 2072 "dbi", 2073 "elbi", 2074 "atu", 2075 "config"; 2076 device_type = "pci"; 2077 linux,pci-domain = <2>; 2078 bus-range = <0x00 0xff>; 2079 num-lanes = <4>; 2080 2081 #address-cells = <3>; 2082 #size-cells = <2>; 2083 2084 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, 2085 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 2086 2087 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>; 2095 interrupt-names = "msi0", 2096 "msi1", 2097 "msi2", 2098 "msi3", 2099 "msi4", 2100 "msi5", 2101 "msi6", 2102 "msi7"; 2103 #interrupt-cells = <1>; 2104 interrupt-map-mask = <0 0 0 0x7>; 2105 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2106 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2107 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2108 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2109 2110 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2111 <&gcc GCC_PCIE_2_AUX_CLK>, 2112 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2113 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2114 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2115 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2116 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2117 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2118 clock-names = "pipe", 2119 "aux", 2120 "cfg", 2121 "bus_master", 2122 "bus_slave", 2123 "slave_q2a", 2124 "ref", 2125 "tbu"; 2126 2127 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2128 assigned-clock-rates = <19200000>; 2129 2130 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2131 <0x100 &apps_smmu 0x1d01 0x1>; 2132 2133 resets = <&gcc GCC_PCIE_2_BCR>; 2134 reset-names = "pci"; 2135 2136 power-domains = <&gcc PCIE_2_GDSC>; 2137 2138 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2139 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>; 2140 interconnect-names = "pcie-mem", "cpu-pcie"; 2141 2142 phys = <&pcie2_phy>; 2143 phy-names = "pciephy"; 2144 dma-coherent; 2145 2146 status = "disabled"; 2147 2148 pcie@0 { 2149 device_type = "pci"; 2150 reg = <0x0 0x0 0x0 0x0 0x0>; 2151 bus-range = <0x01 0xff>; 2152 2153 #address-cells = <3>; 2154 #size-cells = <2>; 2155 ranges; 2156 }; 2157 }; 2158 2159 pcie2_phy: phy@1c1c000 { 2160 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2161 reg = <0 0x01c1c000 0 0x1000>; 2162 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2163 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2164 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2165 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2166 <&gcc GCC_PCIE_2_PIPE_CLK>; 2167 clock-names = "aux", 2168 "cfg_ahb", 2169 "ref", 2170 "refgen", 2171 "pipe"; 2172 #clock-cells = <0>; 2173 clock-output-names = "pcie_2_pipe_clk"; 2174 2175 #phy-cells = <0>; 2176 2177 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2178 reset-names = "phy"; 2179 2180 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2181 assigned-clock-rates = <100000000>; 2182 2183 status = "disabled"; 2184 }; 2185 2186 ufs_mem_hc: ufshc@1d84000 { 2187 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", 2188 "jedec,ufs-2.0"; 2189 reg = <0 0x01d84000 0 0x2500>; 2190 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2191 phys = <&ufs_mem_phy>; 2192 phy-names = "ufsphy"; 2193 lanes-per-direction = <2>; 2194 #reset-cells = <1>; 2195 resets = <&gcc GCC_UFS_PHY_BCR>; 2196 reset-names = "rst"; 2197 2198 iommus = <&apps_smmu 0x300 0>; 2199 2200 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2201 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2202 <&gcc GCC_UFS_PHY_AHB_CLK>, 2203 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2204 <&rpmhcc RPMH_CXO_CLK>, 2205 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2206 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2207 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2208 clock-names = "core_clk", 2209 "bus_aggr_clk", 2210 "iface_clk", 2211 "core_clk_unipro", 2212 "ref_clk", 2213 "tx_lane0_sync_clk", 2214 "rx_lane0_sync_clk", 2215 "rx_lane1_sync_clk"; 2216 freq-table-hz = <37500000 300000000>, 2217 <0 0>, 2218 <0 0>, 2219 <37500000 300000000>, 2220 <0 0>, 2221 <0 0>, 2222 <0 0>, 2223 <0 0>; 2224 2225 power-domains = <&gcc UFS_PHY_GDSC>; 2226 2227 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2228 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2229 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS 2230 &config_noc SLAVE_UFS_MEM_0_CFG QCOM_ICC_TAG_ALWAYS>; 2231 interconnect-names = "ufs-ddr", "cpu-ufs"; 2232 2233 status = "disabled"; 2234 }; 2235 2236 ufs_mem_phy: phy-wrapper@1d87000 { 2237 compatible = "qcom,sc8180x-qmp-ufs-phy"; 2238 reg = <0 0x01d87000 0 0x1000>; 2239 2240 clocks = <&rpmhcc RPMH_CXO_CLK>, 2241 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2242 <&gcc GCC_UFS_MEM_CLKREF_EN>; 2243 clock-names = "ref", 2244 "ref_aux", 2245 "qref"; 2246 2247 resets = <&ufs_mem_hc 0>; 2248 reset-names = "ufsphy"; 2249 2250 power-domains = <&gcc UFS_PHY_GDSC>; 2251 2252 #phy-cells = <0>; 2253 2254 status = "disabled"; 2255 }; 2256 2257 tcsr_mutex: hwlock@1f40000 { 2258 compatible = "qcom,tcsr-mutex"; 2259 reg = <0x0 0x01f40000 0x0 0x40000>; 2260 #hwlock-cells = <1>; 2261 }; 2262 2263 gpu: gpu@2c00000 { 2264 compatible = "qcom,adreno-680.1", "qcom,adreno"; 2265 2266 reg = <0 0x02c00000 0 0x40000>; 2267 reg-names = "kgsl_3d0_reg_memory"; 2268 2269 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2270 2271 iommus = <&adreno_smmu 0 0xc01>; 2272 2273 operating-points-v2 = <&gpu_opp_table>; 2274 2275 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; 2276 interconnect-names = "gfx-mem"; 2277 2278 qcom,gmu = <&gmu>; 2279 #cooling-cells = <2>; 2280 2281 status = "disabled"; 2282 2283 gpu_opp_table: opp-table { 2284 compatible = "operating-points-v2"; 2285 2286 opp-514000000 { 2287 opp-hz = /bits/ 64 <514000000>; 2288 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2289 }; 2290 2291 opp-500000000 { 2292 opp-hz = /bits/ 64 <500000000>; 2293 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2294 }; 2295 2296 opp-461000000 { 2297 opp-hz = /bits/ 64 <461000000>; 2298 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2299 }; 2300 2301 opp-405000000 { 2302 opp-hz = /bits/ 64 <405000000>; 2303 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2304 }; 2305 2306 opp-315000000 { 2307 opp-hz = /bits/ 64 <315000000>; 2308 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2309 }; 2310 2311 opp-256000000 { 2312 opp-hz = /bits/ 64 <256000000>; 2313 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2314 }; 2315 2316 opp-177000000 { 2317 opp-hz = /bits/ 64 <177000000>; 2318 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2319 }; 2320 }; 2321 }; 2322 2323 gmu: gmu@2c6a000 { 2324 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; 2325 2326 reg = <0 0x02c6a000 0 0x30000>, 2327 <0 0x0b290000 0 0x10000>, 2328 <0 0x0b490000 0 0x10000>; 2329 reg-names = "gmu", 2330 "gmu_pdc", 2331 "gmu_pdc_seq"; 2332 2333 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2334 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2335 interrupt-names = "hfi", "gmu"; 2336 2337 clocks = <&gpucc GPU_CC_AHB_CLK>, 2338 <&gpucc GPU_CC_CX_GMU_CLK>, 2339 <&gpucc GPU_CC_CXO_CLK>, 2340 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2341 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2342 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2343 2344 power-domains = <&gpucc GPU_CX_GDSC>, 2345 <&gpucc GPU_GX_GDSC>; 2346 power-domain-names = "cx", "gx"; 2347 2348 iommus = <&adreno_smmu 5 0xc00>; 2349 2350 operating-points-v2 = <&gmu_opp_table>; 2351 2352 gmu_opp_table: opp-table { 2353 compatible = "operating-points-v2"; 2354 2355 opp-200000000 { 2356 opp-hz = /bits/ 64 <200000000>; 2357 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2358 }; 2359 2360 opp-500000000 { 2361 opp-hz = /bits/ 64 <500000000>; 2362 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2363 }; 2364 }; 2365 }; 2366 2367 gpucc: clock-controller@2c90000 { 2368 compatible = "qcom,sc8180x-gpucc"; 2369 reg = <0 0x02c90000 0 0x9000>; 2370 clocks = <&rpmhcc RPMH_CXO_CLK>, 2371 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2372 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2373 clock-names = "bi_tcxo", 2374 "gcc_gpu_gpll0_clk_src", 2375 "gcc_gpu_gpll0_div_clk_src"; 2376 #clock-cells = <1>; 2377 #reset-cells = <1>; 2378 #power-domain-cells = <1>; 2379 }; 2380 2381 adreno_smmu: iommu@2ca0000 { 2382 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu", 2383 "qcom,smmu-500", "arm,mmu-500"; 2384 reg = <0 0x02ca0000 0 0x10000>; 2385 #iommu-cells = <2>; 2386 #global-interrupts = <1>; 2387 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2388 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2389 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2390 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2391 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2392 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2393 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2394 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2395 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2396 clocks = <&gpucc GPU_CC_AHB_CLK>, 2397 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2398 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2399 clock-names = "ahb", "bus", "iface"; 2400 2401 power-domains = <&gpucc GPU_CX_GDSC>; 2402 }; 2403 2404 tlmm: pinctrl@3100000 { 2405 compatible = "qcom,sc8180x-tlmm"; 2406 reg = <0 0x03100000 0 0x300000>, 2407 <0 0x03500000 0 0x700000>, 2408 <0 0x03d00000 0 0x300000>; 2409 reg-names = "west", "east", "south"; 2410 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2411 gpio-controller; 2412 #gpio-cells = <2>; 2413 interrupt-controller; 2414 #interrupt-cells = <2>; 2415 gpio-ranges = <&tlmm 0 0 191>; 2416 wakeup-parent = <&pdc>; 2417 }; 2418 2419 remoteproc_mpss: remoteproc@4080000 { 2420 compatible = "qcom,sc8180x-mpss-pas"; 2421 reg = <0x0 0x04080000 0x0 0x4040>; 2422 2423 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2424 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2425 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2426 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2427 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2428 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2429 interrupt-names = "wdog", "fatal", "ready", "handover", 2430 "stop-ack", "shutdown-ack"; 2431 2432 clocks = <&rpmhcc RPMH_CXO_CLK>; 2433 clock-names = "xo"; 2434 2435 power-domains = <&rpmhpd SC8180X_CX>, 2436 <&rpmhpd SC8180X_MSS>; 2437 power-domain-names = "cx", "mss"; 2438 2439 qcom,qmp = <&aoss_qmp>; 2440 2441 qcom,smem-states = <&modem_smp2p_out 0>; 2442 qcom,smem-state-names = "stop"; 2443 2444 glink-edge { 2445 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2446 label = "modem"; 2447 qcom,remote-pid = <1>; 2448 mboxes = <&apss_shared 12>; 2449 }; 2450 }; 2451 2452 remoteproc_cdsp: remoteproc@8300000 { 2453 compatible = "qcom,sc8180x-cdsp-pas"; 2454 reg = <0x0 0x08300000 0x0 0x4040>; 2455 2456 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2457 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2458 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2459 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2460 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2461 interrupt-names = "wdog", "fatal", "ready", 2462 "handover", "stop-ack"; 2463 2464 clocks = <&rpmhcc RPMH_CXO_CLK>; 2465 clock-names = "xo"; 2466 2467 power-domains = <&rpmhpd SC8180X_CX>; 2468 power-domain-names = "cx"; 2469 2470 qcom,qmp = <&aoss_qmp>; 2471 2472 qcom,smem-states = <&cdsp_smp2p_out 0>; 2473 qcom,smem-state-names = "stop"; 2474 2475 status = "disabled"; 2476 2477 glink-edge { 2478 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2479 label = "cdsp"; 2480 qcom,remote-pid = <5>; 2481 mboxes = <&apss_shared 4>; 2482 }; 2483 }; 2484 2485 usb_prim_hsphy: phy@88e2000 { 2486 compatible = "qcom,sc8180x-usb-hs-phy", 2487 "qcom,usb-snps-hs-7nm-phy"; 2488 reg = <0 0x088e2000 0 0x400>; 2489 clocks = <&rpmhcc RPMH_CXO_CLK>; 2490 clock-names = "ref"; 2491 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2492 2493 #phy-cells = <0>; 2494 2495 status = "disabled"; 2496 }; 2497 2498 usb_sec_hsphy: phy@88e3000 { 2499 compatible = "qcom,sc8180x-usb-hs-phy", 2500 "qcom,usb-snps-hs-7nm-phy"; 2501 reg = <0 0x088e3000 0 0x400>; 2502 clocks = <&rpmhcc RPMH_CXO_CLK>; 2503 clock-names = "ref"; 2504 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2505 2506 #phy-cells = <0>; 2507 2508 status = "disabled"; 2509 }; 2510 2511 usb_mp_hsphy0: phy@88e4000 { 2512 compatible = "qcom,sc8180x-usb-hs-phy", 2513 "qcom,usb-snps-hs-7nm-phy"; 2514 reg = <0 0x088e4000 0 0x400>; 2515 #phy-cells = <0>; 2516 2517 clocks = <&rpmhcc RPMH_CXO_CLK>; 2518 clock-names = "ref"; 2519 2520 resets = <&gcc GCC_QUSB2PHY_MP0_BCR>; 2521 2522 status = "disabled"; 2523 }; 2524 2525 usb_mp_hsphy1: phy@88e5000 { 2526 compatible = "qcom,sc8180x-usb-hs-phy", 2527 "qcom,usb-snps-hs-7nm-phy"; 2528 reg = <0 0x088e5000 0 0x400>; 2529 #phy-cells = <0>; 2530 2531 clocks = <&rpmhcc RPMH_CXO_CLK>; 2532 clock-names = "ref"; 2533 2534 resets = <&gcc GCC_QUSB2PHY_MP1_BCR>; 2535 2536 status = "disabled"; 2537 }; 2538 2539 usb_prim_qmpphy: phy@88e8000 { 2540 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2541 reg = <0 0x088e8000 0 0x3000>; 2542 2543 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2544 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2545 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2546 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2547 clock-names = "aux", 2548 "ref", 2549 "com_aux", 2550 "usb3_pipe"; 2551 2552 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, 2553 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; 2554 reset-names = "phy", "common"; 2555 2556 #clock-cells = <1>; 2557 #phy-cells = <1>; 2558 2559 status = "disabled"; 2560 2561 ports { 2562 #address-cells = <1>; 2563 #size-cells = <0>; 2564 2565 port@0 { 2566 reg = <0>; 2567 2568 usb_prim_qmpphy_out: endpoint {}; 2569 }; 2570 2571 port@1 { 2572 reg = <1>; 2573 2574 usb_prim_qmpphy_usb_ss_in: endpoint { 2575 remote-endpoint = <&usb_prim_dwc3_ss>; 2576 }; 2577 }; 2578 2579 port@2 { 2580 reg = <2>; 2581 2582 usb_prim_qmpphy_dp_in: endpoint {}; 2583 }; 2584 }; 2585 }; 2586 2587 usb_mp_qmpphy0: phy@88eb000 { 2588 compatible = "qcom,sc8180x-qmp-usb3-uni-phy"; 2589 reg = <0 0x088eb000 0 0x1000>; 2590 2591 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2592 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2593 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2594 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2595 clock-names = "aux", 2596 "ref", 2597 "com_aux", 2598 "pipe"; 2599 2600 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2601 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2602 reset-names = "phy", "phy_phy"; 2603 2604 power-domains = <&gcc USB30_MP_GDSC>; 2605 2606 #clock-cells = <0>; 2607 clock-output-names = "usb2_phy0_pipe_clk"; 2608 2609 #phy-cells = <0>; 2610 2611 status = "disabled"; 2612 }; 2613 2614 usb_mp_qmpphy1: phy@88ec000 { 2615 compatible = "qcom,sc8180x-qmp-usb3-uni-phy"; 2616 reg = <0 0x088ec000 0 0x1000>; 2617 2618 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2619 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2620 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2621 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2622 clock-names = "aux", 2623 "ref", 2624 "com_aux", 2625 "pipe"; 2626 2627 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2628 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2629 reset-names = "phy", "phy_phy"; 2630 2631 power-domains = <&gcc USB30_MP_GDSC>; 2632 2633 #clock-cells = <0>; 2634 clock-output-names = "usb2_phy1_pipe_clk"; 2635 2636 #phy-cells = <0>; 2637 2638 status = "disabled"; 2639 }; 2640 2641 usb_sec_qmpphy: phy@88ee000 { 2642 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2643 reg = <0 0x088ed000 0 0x3000>; 2644 2645 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2646 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2647 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2648 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2649 clock-names = "aux", 2650 "ref", 2651 "com_aux", 2652 "usb3_pipe"; 2653 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, 2654 <&gcc GCC_USB3_PHY_SEC_BCR>; 2655 reset-names = "phy", "common"; 2656 2657 #clock-cells = <1>; 2658 #phy-cells = <1>; 2659 2660 status = "disabled"; 2661 2662 ports { 2663 #address-cells = <1>; 2664 #size-cells = <0>; 2665 2666 port@0 { 2667 reg = <0>; 2668 2669 usb_sec_qmpphy_out: endpoint {}; 2670 }; 2671 2672 port@1 { 2673 reg = <1>; 2674 2675 usb_sec_qmpphy_usb_ss_in: endpoint { 2676 remote-endpoint = <&usb_sec_dwc3_ss>; 2677 }; 2678 }; 2679 2680 port@2 { 2681 reg = <2>; 2682 2683 usb_sec_qmpphy_dp_in: endpoint {}; 2684 }; 2685 }; 2686 }; 2687 2688 system-cache-controller@9200000 { 2689 compatible = "qcom,sc8180x-llcc"; 2690 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2691 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2692 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 2693 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 2694 <0 0x09600000 0 0x58000>; 2695 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2696 "llcc3_base", "llcc4_base", "llcc5_base", 2697 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 2698 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2699 }; 2700 2701 gem_noc: interconnect@9680000 { 2702 compatible = "qcom,sc8180x-gem-noc"; 2703 reg = <0 0x09680000 0 0x58200>; 2704 #interconnect-cells = <2>; 2705 qcom,bcm-voters = <&apps_bcm_voter>; 2706 }; 2707 2708 usb_mp: usb@a4f8800 { 2709 compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3"; 2710 reg = <0 0x0a4f8800 0 0x400>; 2711 #address-cells = <2>; 2712 #size-cells = <2>; 2713 ranges; 2714 dma-ranges; 2715 2716 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 2717 <&gcc GCC_USB30_MP_MASTER_CLK>, 2718 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 2719 <&gcc GCC_USB30_MP_SLEEP_CLK>, 2720 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 2721 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2722 clock-names = "cfg_noc", 2723 "core", 2724 "iface", 2725 "sleep", 2726 "mock_utmi", 2727 "xo"; 2728 2729 interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2730 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>; 2731 interconnect-names = "usb-ddr", "apps-usb"; 2732 2733 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 2734 <&gcc GCC_USB30_MP_MASTER_CLK>; 2735 assigned-clock-rates = <19200000>, <200000000>; 2736 2737 interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>, 2738 <&intc GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>, 2739 <&intc GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH>, 2740 <&intc GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>, 2741 <&pdc 59 IRQ_TYPE_EDGE_BOTH>, 2742 <&pdc 46 IRQ_TYPE_EDGE_BOTH>, 2743 <&pdc 71 IRQ_TYPE_EDGE_BOTH>, 2744 <&pdc 68 IRQ_TYPE_EDGE_BOTH>, 2745 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, 2746 <&pdc 30 IRQ_TYPE_LEVEL_HIGH>; 2747 interrupt-names = "pwr_event_1", "pwr_event_2", 2748 "hs_phy_1", "hs_phy_2", 2749 "dp_hs_phy_1", "dm_hs_phy_1", 2750 "dp_hs_phy_2", "dm_hs_phy_2", 2751 "ss_phy_1", "ss_phy_2"; 2752 2753 power-domains = <&gcc USB30_MP_GDSC>; 2754 2755 resets = <&gcc GCC_USB30_MP_BCR>; 2756 2757 status = "disabled"; 2758 2759 usb_mp_dwc3: usb@a400000 { 2760 compatible = "snps,dwc3"; 2761 reg = <0 0x0a400000 0 0xcd00>; 2762 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 2763 iommus = <&apps_smmu 0x60 0>; 2764 snps,dis_u2_susphy_quirk; 2765 snps,dis_enblslpm_quirk; 2766 snps,dis-u1-entry-quirk; 2767 snps,dis-u2-entry-quirk; 2768 phys = <&usb_mp_hsphy0>, 2769 <&usb_mp_qmpphy0>, 2770 <&usb_mp_hsphy1>, 2771 <&usb_mp_qmpphy1>; 2772 phy-names = "usb2-0", 2773 "usb3-0", 2774 "usb2-1", 2775 "usb3-1"; 2776 dr_mode = "host"; 2777 }; 2778 }; 2779 2780 usb_prim: usb@a6f8800 { 2781 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2782 reg = <0 0x0a6f8800 0 0x400>; 2783 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2784 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2785 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 2786 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2787 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 2788 interrupt-names = "pwr_event", 2789 "hs_phy_irq", 2790 "dp_hs_phy_irq", 2791 "dm_hs_phy_irq", 2792 "ss_phy_irq"; 2793 2794 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2795 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2796 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2797 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2798 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2799 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2800 clock-names = "cfg_noc", 2801 "core", 2802 "iface", 2803 "sleep", 2804 "mock_utmi", 2805 "xo"; 2806 resets = <&gcc GCC_USB30_PRIM_BCR>; 2807 power-domains = <&gcc USB30_PRIM_GDSC>; 2808 2809 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 2810 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 2811 interconnect-names = "usb-ddr", "apps-usb"; 2812 2813 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2814 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2815 assigned-clock-rates = <19200000>, <200000000>; 2816 2817 #address-cells = <2>; 2818 #size-cells = <2>; 2819 ranges; 2820 dma-ranges; 2821 2822 status = "disabled"; 2823 2824 usb_prim_dwc3: usb@a600000 { 2825 compatible = "snps,dwc3"; 2826 reg = <0 0x0a600000 0 0xcd00>; 2827 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2828 iommus = <&apps_smmu 0x140 0>; 2829 snps,dis_u2_susphy_quirk; 2830 snps,dis_enblslpm_quirk; 2831 snps,dis-u1-entry-quirk; 2832 snps,dis-u2-entry-quirk; 2833 phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>; 2834 phy-names = "usb2-phy", "usb3-phy"; 2835 2836 ports { 2837 #address-cells = <1>; 2838 #size-cells = <0>; 2839 2840 port@0 { 2841 reg = <0>; 2842 2843 usb_prim_dwc3_hs: endpoint { 2844 }; 2845 }; 2846 2847 port@1 { 2848 reg = <1>; 2849 2850 usb_prim_dwc3_ss: endpoint { 2851 remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>; 2852 }; 2853 }; 2854 }; 2855 }; 2856 }; 2857 2858 usb_sec: usb@a8f8800 { 2859 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2860 reg = <0 0x0a8f8800 0 0x400>; 2861 2862 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2863 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2864 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2865 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2866 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2867 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2868 clock-names = "cfg_noc", 2869 "core", 2870 "iface", 2871 "sleep", 2872 "mock_utmi", 2873 "xo"; 2874 resets = <&gcc GCC_USB30_SEC_BCR>; 2875 power-domains = <&gcc USB30_SEC_GDSC>; 2876 2877 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2878 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2879 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 2880 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 2881 <&pdc 40 IRQ_TYPE_LEVEL_HIGH>; 2882 interrupt-names = "pwr_event", 2883 "hs_phy_irq", 2884 "dp_hs_phy_irq", 2885 "dm_hs_phy_irq", 2886 "ss_phy_irq"; 2887 2888 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2889 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2890 assigned-clock-rates = <19200000>, <200000000>; 2891 2892 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2893 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 2894 interconnect-names = "usb-ddr", "apps-usb"; 2895 2896 #address-cells = <2>; 2897 #size-cells = <2>; 2898 ranges; 2899 dma-ranges; 2900 2901 status = "disabled"; 2902 2903 usb_sec_dwc3: usb@a800000 { 2904 compatible = "snps,dwc3"; 2905 reg = <0 0x0a800000 0 0xcd00>; 2906 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2907 iommus = <&apps_smmu 0x160 0>; 2908 snps,dis_u2_susphy_quirk; 2909 snps,dis_enblslpm_quirk; 2910 snps,dis-u1-entry-quirk; 2911 snps,dis-u2-entry-quirk; 2912 phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>; 2913 phy-names = "usb2-phy", "usb3-phy"; 2914 2915 ports { 2916 #address-cells = <1>; 2917 #size-cells = <0>; 2918 2919 port@0 { 2920 reg = <0>; 2921 2922 usb_sec_dwc3_hs: endpoint { 2923 }; 2924 }; 2925 2926 port@1 { 2927 reg = <1>; 2928 2929 usb_sec_dwc3_ss: endpoint { 2930 remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>; 2931 }; 2932 }; 2933 }; 2934 }; 2935 }; 2936 2937 mdss: mdss@ae00000 { 2938 compatible = "qcom,sc8180x-mdss"; 2939 reg = <0 0x0ae00000 0 0x1000>; 2940 reg-names = "mdss"; 2941 2942 power-domains = <&dispcc MDSS_GDSC>; 2943 2944 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2945 <&gcc GCC_DISP_HF_AXI_CLK>, 2946 <&gcc GCC_DISP_SF_AXI_CLK>, 2947 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2948 clock-names = "iface", 2949 "bus", 2950 "nrt_bus", 2951 "core"; 2952 2953 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2954 2955 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2956 interrupt-controller; 2957 #interrupt-cells = <1>; 2958 2959 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS 2960 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2961 <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS 2962 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2963 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS 2964 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 2965 interconnect-names = "mdp0-mem", 2966 "mdp1-mem", 2967 "cpu-cfg"; 2968 2969 iommus = <&apps_smmu 0x800 0x420>; 2970 2971 #address-cells = <2>; 2972 #size-cells = <2>; 2973 ranges; 2974 2975 status = "disabled"; 2976 2977 mdss_mdp: mdp@ae01000 { 2978 compatible = "qcom,sc8180x-dpu"; 2979 reg = <0 0x0ae01000 0 0x8f000>, 2980 <0 0x0aeb0000 0 0x3000>; 2981 reg-names = "mdp", "vbif"; 2982 2983 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2984 <&gcc GCC_DISP_HF_AXI_CLK>, 2985 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2986 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2987 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2988 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; 2989 clock-names = "iface", 2990 "bus", 2991 "core", 2992 "vsync", 2993 "rot", 2994 "lut"; 2995 2996 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2997 assigned-clock-rates = <19200000>; 2998 2999 operating-points-v2 = <&mdp_opp_table>; 3000 power-domains = <&rpmhpd SC8180X_MMCX>; 3001 3002 interrupt-parent = <&mdss>; 3003 interrupts = <0>; 3004 3005 ports { 3006 #address-cells = <1>; 3007 #size-cells = <0>; 3008 3009 port@0 { 3010 reg = <0>; 3011 dpu_intf0_out: endpoint { 3012 remote-endpoint = <&dp0_in>; 3013 }; 3014 }; 3015 3016 port@1 { 3017 reg = <1>; 3018 dpu_intf1_out: endpoint { 3019 remote-endpoint = <&mdss_dsi0_in>; 3020 }; 3021 }; 3022 3023 port@2 { 3024 reg = <2>; 3025 dpu_intf2_out: endpoint { 3026 remote-endpoint = <&mdss_dsi1_in>; 3027 }; 3028 }; 3029 3030 port@4 { 3031 reg = <4>; 3032 dpu_intf4_out: endpoint { 3033 remote-endpoint = <&dp1_in>; 3034 }; 3035 }; 3036 3037 port@5 { 3038 reg = <5>; 3039 dpu_intf5_out: endpoint { 3040 remote-endpoint = <&edp_in>; 3041 }; 3042 }; 3043 }; 3044 3045 mdp_opp_table: opp-table { 3046 compatible = "operating-points-v2"; 3047 3048 opp-200000000 { 3049 opp-hz = /bits/ 64 <200000000>; 3050 required-opps = <&rpmhpd_opp_low_svs>; 3051 }; 3052 3053 opp-300000000 { 3054 opp-hz = /bits/ 64 <300000000>; 3055 required-opps = <&rpmhpd_opp_svs>; 3056 }; 3057 3058 opp-345000000 { 3059 opp-hz = /bits/ 64 <345000000>; 3060 required-opps = <&rpmhpd_opp_svs_l1>; 3061 }; 3062 3063 opp-460000000 { 3064 opp-hz = /bits/ 64 <460000000>; 3065 required-opps = <&rpmhpd_opp_nom>; 3066 }; 3067 }; 3068 }; 3069 3070 mdss_dsi0: dsi@ae94000 { 3071 compatible = "qcom,mdss-dsi-ctrl"; 3072 reg = <0 0x0ae94000 0 0x400>; 3073 reg-names = "dsi_ctrl"; 3074 3075 interrupt-parent = <&mdss>; 3076 interrupts = <4>; 3077 3078 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3079 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3080 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3081 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3082 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3083 <&gcc GCC_DISP_HF_AXI_CLK>; 3084 clock-names = "byte", 3085 "byte_intf", 3086 "pixel", 3087 "core", 3088 "iface", 3089 "bus"; 3090 3091 operating-points-v2 = <&dsi_opp_table>; 3092 power-domains = <&rpmhpd SC8180X_MMCX>; 3093 3094 phys = <&mdss_dsi0_phy>; 3095 phy-names = "dsi"; 3096 3097 status = "disabled"; 3098 3099 ports { 3100 #address-cells = <1>; 3101 #size-cells = <0>; 3102 3103 port@0 { 3104 reg = <0>; 3105 mdss_dsi0_in: endpoint { 3106 remote-endpoint = <&dpu_intf1_out>; 3107 }; 3108 }; 3109 3110 port@1 { 3111 reg = <1>; 3112 mdss_dsi0_out: endpoint { 3113 }; 3114 }; 3115 }; 3116 3117 dsi_opp_table: opp-table { 3118 compatible = "operating-points-v2"; 3119 3120 opp-187500000 { 3121 opp-hz = /bits/ 64 <187500000>; 3122 required-opps = <&rpmhpd_opp_low_svs>; 3123 }; 3124 3125 opp-300000000 { 3126 opp-hz = /bits/ 64 <300000000>; 3127 required-opps = <&rpmhpd_opp_svs>; 3128 }; 3129 3130 opp-358000000 { 3131 opp-hz = /bits/ 64 <358000000>; 3132 required-opps = <&rpmhpd_opp_svs_l1>; 3133 }; 3134 }; 3135 }; 3136 3137 mdss_dsi0_phy: dsi-phy@ae94400 { 3138 compatible = "qcom,dsi-phy-7nm"; 3139 reg = <0 0x0ae94400 0 0x200>, 3140 <0 0x0ae94600 0 0x280>, 3141 <0 0x0ae94900 0 0x260>; 3142 reg-names = "dsi_phy", 3143 "dsi_phy_lane", 3144 "dsi_pll"; 3145 3146 #clock-cells = <1>; 3147 #phy-cells = <0>; 3148 3149 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3150 <&rpmhcc RPMH_CXO_CLK>; 3151 clock-names = "iface", "ref"; 3152 3153 status = "disabled"; 3154 }; 3155 3156 mdss_dsi1: dsi@ae96000 { 3157 compatible = "qcom,mdss-dsi-ctrl"; 3158 reg = <0 0x0ae96000 0 0x400>; 3159 reg-names = "dsi_ctrl"; 3160 3161 interrupt-parent = <&mdss>; 3162 interrupts = <5>; 3163 3164 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3165 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3166 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3167 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3168 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3169 <&gcc GCC_DISP_HF_AXI_CLK>; 3170 clock-names = "byte", 3171 "byte_intf", 3172 "pixel", 3173 "core", 3174 "iface", 3175 "bus"; 3176 3177 operating-points-v2 = <&dsi_opp_table>; 3178 power-domains = <&rpmhpd SC8180X_MMCX>; 3179 3180 phys = <&mdss_dsi1_phy>; 3181 phy-names = "dsi"; 3182 3183 status = "disabled"; 3184 3185 ports { 3186 #address-cells = <1>; 3187 #size-cells = <0>; 3188 3189 port@0 { 3190 reg = <0>; 3191 mdss_dsi1_in: endpoint { 3192 remote-endpoint = <&dpu_intf2_out>; 3193 }; 3194 }; 3195 3196 port@1 { 3197 reg = <1>; 3198 mdss_dsi1_out: endpoint { 3199 }; 3200 }; 3201 }; 3202 }; 3203 3204 mdss_dsi1_phy: dsi-phy@ae96400 { 3205 compatible = "qcom,dsi-phy-7nm"; 3206 reg = <0 0x0ae96400 0 0x200>, 3207 <0 0x0ae96600 0 0x280>, 3208 <0 0x0ae96900 0 0x260>; 3209 reg-names = "dsi_phy", 3210 "dsi_phy_lane", 3211 "dsi_pll"; 3212 3213 #clock-cells = <1>; 3214 #phy-cells = <0>; 3215 3216 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3217 <&rpmhcc RPMH_CXO_CLK>; 3218 clock-names = "iface", "ref"; 3219 3220 status = "disabled"; 3221 }; 3222 3223 mdss_dp0: displayport-controller@ae90000 { 3224 compatible = "qcom,sc8180x-dp"; 3225 reg = <0 0xae90000 0 0x200>, 3226 <0 0xae90200 0 0x200>, 3227 <0 0xae90400 0 0x600>, 3228 <0 0xae90a00 0 0x400>, 3229 <0 0xae91000 0 0x400>; 3230 interrupt-parent = <&mdss>; 3231 interrupts = <12>; 3232 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3233 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3234 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3235 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3236 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3237 clock-names = "core_iface", 3238 "core_aux", 3239 "ctrl_link", 3240 "ctrl_link_iface", 3241 "stream_pixel"; 3242 3243 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3244 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3245 assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3246 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3247 3248 phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>; 3249 phy-names = "dp"; 3250 3251 #sound-dai-cells = <0>; 3252 3253 operating-points-v2 = <&dp0_opp_table>; 3254 power-domains = <&rpmhpd SC8180X_MMCX>; 3255 3256 status = "disabled"; 3257 3258 ports { 3259 #address-cells = <1>; 3260 #size-cells = <0>; 3261 3262 port@0 { 3263 reg = <0>; 3264 dp0_in: endpoint { 3265 remote-endpoint = <&dpu_intf0_out>; 3266 }; 3267 }; 3268 3269 port@1 { 3270 reg = <1>; 3271 mdss_dp0_out: endpoint { 3272 }; 3273 }; 3274 }; 3275 3276 dp0_opp_table: opp-table { 3277 compatible = "operating-points-v2"; 3278 3279 opp-160000000 { 3280 opp-hz = /bits/ 64 <160000000>; 3281 required-opps = <&rpmhpd_opp_low_svs>; 3282 }; 3283 3284 opp-270000000 { 3285 opp-hz = /bits/ 64 <270000000>; 3286 required-opps = <&rpmhpd_opp_svs>; 3287 }; 3288 3289 opp-540000000 { 3290 opp-hz = /bits/ 64 <540000000>; 3291 required-opps = <&rpmhpd_opp_svs_l1>; 3292 }; 3293 3294 opp-810000000 { 3295 opp-hz = /bits/ 64 <810000000>; 3296 required-opps = <&rpmhpd_opp_nom>; 3297 }; 3298 }; 3299 }; 3300 3301 mdss_dp1: displayport-controller@ae98000 { 3302 compatible = "qcom,sc8180x-dp"; 3303 reg = <0 0xae98000 0 0x200>, 3304 <0 0xae98200 0 0x200>, 3305 <0 0xae98400 0 0x600>, 3306 <0 0xae98a00 0 0x400>, 3307 <0 0xae99000 0 0x400>; 3308 interrupt-parent = <&mdss>; 3309 interrupts = <13>; 3310 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3311 <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, 3312 <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, 3313 <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, 3314 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; 3315 clock-names = "core_iface", 3316 "core_aux", 3317 "ctrl_link", 3318 "ctrl_link_iface", 3319 "stream_pixel"; 3320 3321 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, 3322 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; 3323 assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3324 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3325 3326 phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>; 3327 phy-names = "dp"; 3328 3329 #sound-dai-cells = <0>; 3330 3331 operating-points-v2 = <&dp0_opp_table>; 3332 power-domains = <&rpmhpd SC8180X_MMCX>; 3333 3334 status = "disabled"; 3335 3336 ports { 3337 #address-cells = <1>; 3338 #size-cells = <0>; 3339 3340 port@0 { 3341 reg = <0>; 3342 dp1_in: endpoint { 3343 remote-endpoint = <&dpu_intf4_out>; 3344 }; 3345 }; 3346 3347 port@1 { 3348 reg = <1>; 3349 mdss_dp1_out: endpoint { 3350 }; 3351 }; 3352 }; 3353 3354 dp1_opp_table: opp-table { 3355 compatible = "operating-points-v2"; 3356 3357 opp-160000000 { 3358 opp-hz = /bits/ 64 <160000000>; 3359 required-opps = <&rpmhpd_opp_low_svs>; 3360 }; 3361 3362 opp-270000000 { 3363 opp-hz = /bits/ 64 <270000000>; 3364 required-opps = <&rpmhpd_opp_svs>; 3365 }; 3366 3367 opp-540000000 { 3368 opp-hz = /bits/ 64 <540000000>; 3369 required-opps = <&rpmhpd_opp_svs_l1>; 3370 }; 3371 3372 opp-810000000 { 3373 opp-hz = /bits/ 64 <810000000>; 3374 required-opps = <&rpmhpd_opp_nom>; 3375 }; 3376 }; 3377 }; 3378 3379 mdss_edp: displayport-controller@ae9a000 { 3380 compatible = "qcom,sc8180x-edp"; 3381 reg = <0 0xae9a000 0 0x200>, 3382 <0 0xae9a200 0 0x200>, 3383 <0 0xae9a400 0 0x600>, 3384 <0 0xae9aa00 0 0x400>; 3385 interrupt-parent = <&mdss>; 3386 interrupts = <14>; 3387 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3388 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3389 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3390 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3391 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3392 clock-names = "core_iface", 3393 "core_aux", 3394 "ctrl_link", 3395 "ctrl_link_iface", 3396 "stream_pixel"; 3397 3398 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3399 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3400 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; 3401 3402 phys = <&edp_phy>; 3403 phy-names = "dp"; 3404 3405 operating-points-v2 = <&edp_opp_table>; 3406 power-domains = <&rpmhpd SC8180X_MMCX>; 3407 3408 status = "disabled"; 3409 3410 ports { 3411 #address-cells = <1>; 3412 #size-cells = <0>; 3413 3414 port@0 { 3415 reg = <0>; 3416 edp_in: endpoint { 3417 remote-endpoint = <&dpu_intf5_out>; 3418 }; 3419 }; 3420 }; 3421 3422 edp_opp_table: opp-table { 3423 compatible = "operating-points-v2"; 3424 3425 opp-160000000 { 3426 opp-hz = /bits/ 64 <160000000>; 3427 required-opps = <&rpmhpd_opp_low_svs>; 3428 }; 3429 3430 opp-270000000 { 3431 opp-hz = /bits/ 64 <270000000>; 3432 required-opps = <&rpmhpd_opp_svs>; 3433 }; 3434 3435 opp-540000000 { 3436 opp-hz = /bits/ 64 <540000000>; 3437 required-opps = <&rpmhpd_opp_svs_l1>; 3438 }; 3439 3440 opp-810000000 { 3441 opp-hz = /bits/ 64 <810000000>; 3442 required-opps = <&rpmhpd_opp_nom>; 3443 }; 3444 }; 3445 }; 3446 }; 3447 3448 edp_phy: phy@aec2a00 { 3449 compatible = "qcom,sc8180x-edp-phy"; 3450 reg = <0 0x0aec2a00 0 0x1c0>, 3451 <0 0x0aec2200 0 0xa0>, 3452 <0 0x0aec2600 0 0xa0>, 3453 <0 0x0aec2000 0 0x19c>; 3454 3455 clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3456 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3457 clock-names = "aux", "cfg_ahb"; 3458 3459 power-domains = <&rpmhpd SC8180X_MX>; 3460 3461 #clock-cells = <1>; 3462 #phy-cells = <0>; 3463 }; 3464 3465 dispcc: clock-controller@af00000 { 3466 compatible = "qcom,sc8180x-dispcc"; 3467 reg = <0 0x0af00000 0 0x20000>; 3468 clocks = <&rpmhcc RPMH_CXO_CLK>, 3469 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3470 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3471 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3472 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 3473 <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3474 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3475 <&edp_phy 0>, 3476 <&edp_phy 1>, 3477 <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3478 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3479 clock-names = "bi_tcxo", 3480 "dsi0_phy_pll_out_byteclk", 3481 "dsi0_phy_pll_out_dsiclk", 3482 "dsi1_phy_pll_out_byteclk", 3483 "dsi1_phy_pll_out_dsiclk", 3484 "dp_phy_pll_link_clk", 3485 "dp_phy_pll_vco_div_clk", 3486 "edp_phy_pll_link_clk", 3487 "edp_phy_pll_vco_div_clk", 3488 "dptx1_phy_pll_link_clk", 3489 "dptx1_phy_pll_vco_div_clk"; 3490 power-domains = <&rpmhpd SC8180X_MMCX>; 3491 required-opps = <&rpmhpd_opp_low_svs>; 3492 #clock-cells = <1>; 3493 #reset-cells = <1>; 3494 #power-domain-cells = <1>; 3495 }; 3496 3497 pdc: interrupt-controller@b220000 { 3498 compatible = "qcom,sc8180x-pdc", "qcom,pdc"; 3499 reg = <0 0x0b220000 0 0x30000>; 3500 qcom,pdc-ranges = <0 480 94>, <94 609 31>; 3501 #interrupt-cells = <2>; 3502 interrupt-parent = <&intc>; 3503 interrupt-controller; 3504 }; 3505 3506 tsens0: thermal-sensor@c263000 { 3507 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3508 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3509 <0 0x0c222000 0 0x1ff>; /* SROT */ 3510 #qcom,sensors = <16>; 3511 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3513 interrupt-names = "uplow", "critical"; 3514 #thermal-sensor-cells = <1>; 3515 }; 3516 3517 tsens1: thermal-sensor@c265000 { 3518 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3519 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3520 <0 0x0c223000 0 0x1ff>; /* SROT */ 3521 #qcom,sensors = <9>; 3522 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3524 interrupt-names = "uplow", "critical"; 3525 #thermal-sensor-cells = <1>; 3526 }; 3527 3528 aoss_qmp: power-management@c300000 { 3529 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; 3530 reg = <0x0 0x0c300000 0x0 0x400>; 3531 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3532 mboxes = <&apss_shared 0>; 3533 3534 #clock-cells = <0>; 3535 }; 3536 3537 sram@c3f0000 { 3538 compatible = "qcom,rpmh-stats"; 3539 reg = <0x0 0x0c3f0000 0x0 0x400>; 3540 }; 3541 3542 spmi_bus: spmi@c440000 { 3543 compatible = "qcom,spmi-pmic-arb"; 3544 reg = <0x0 0x0c440000 0x0 0x0001100>, 3545 <0x0 0x0c600000 0x0 0x2000000>, 3546 <0x0 0x0e600000 0x0 0x0100000>, 3547 <0x0 0x0e700000 0x0 0x00a0000>, 3548 <0x0 0x0c40a000 0x0 0x0026000>; 3549 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3550 interrupt-names = "periph_irq"; 3551 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3552 qcom,ee = <0>; 3553 qcom,channel = <0>; 3554 #address-cells = <2>; 3555 #size-cells = <0>; 3556 interrupt-controller; 3557 #interrupt-cells = <4>; 3558 }; 3559 3560 apps_smmu: iommu@15000000 { 3561 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; 3562 reg = <0 0x15000000 0 0x100000>; 3563 #iommu-cells = <2>; 3564 #global-interrupts = <1>; 3565 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3566 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3567 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3568 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3569 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3570 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3571 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3572 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3573 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3574 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3575 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3576 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3577 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3578 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3579 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3580 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3581 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3582 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3583 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3584 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3585 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3586 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3587 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3588 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3589 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3590 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3591 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3592 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3593 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3594 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3595 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3596 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3597 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3598 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3599 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3600 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3601 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3602 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3603 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3604 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3605 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3631 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3632 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3654 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3660 <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3670 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3671 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>; 3672 dma-coherent; 3673 }; 3674 3675 remoteproc_adsp: remoteproc@17300000 { 3676 compatible = "qcom,sc8180x-adsp-pas"; 3677 reg = <0x0 0x17300000 0x0 0x4040>; 3678 3679 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3680 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3681 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3682 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3683 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3684 interrupt-names = "wdog", "fatal", "ready", 3685 "handover", "stop-ack"; 3686 3687 clocks = <&rpmhcc RPMH_CXO_CLK>; 3688 clock-names = "xo"; 3689 3690 power-domains = <&rpmhpd SC8180X_CX>; 3691 power-domain-names = "cx"; 3692 3693 qcom,qmp = <&aoss_qmp>; 3694 3695 qcom,smem-states = <&adsp_smp2p_out 0>; 3696 qcom,smem-state-names = "stop"; 3697 3698 status = "disabled"; 3699 3700 remoteproc_adsp_glink: glink-edge { 3701 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3702 label = "lpass"; 3703 qcom,remote-pid = <2>; 3704 mboxes = <&apss_shared 8>; 3705 }; 3706 }; 3707 3708 intc: interrupt-controller@17a00000 { 3709 compatible = "arm,gic-v3"; 3710 interrupt-controller; 3711 #interrupt-cells = <3>; 3712 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3713 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3714 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3715 #redistributor-regions = <1>; 3716 redistributor-stride = <0 0x20000>; 3717 }; 3718 3719 apss_shared: mailbox@17c00000 { 3720 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared"; 3721 reg = <0x0 0x17c00000 0x0 0x1000>; 3722 #mbox-cells = <1>; 3723 }; 3724 3725 timer@17c20000 { 3726 compatible = "arm,armv7-timer-mem"; 3727 reg = <0x0 0x17c20000 0x0 0x1000>; 3728 3729 #address-cells = <1>; 3730 #size-cells = <1>; 3731 ranges = <0 0 0 0x20000000>; 3732 3733 frame@17c21000 { 3734 reg = <0x17c21000 0x1000>, 3735 <0x17c22000 0x1000>; 3736 frame-number = <0>; 3737 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3739 }; 3740 3741 frame@17c23000 { 3742 reg = <0x17c23000 0x1000>; 3743 frame-number = <1>; 3744 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3745 status = "disabled"; 3746 }; 3747 3748 frame@17c25000 { 3749 reg = <0x17c25000 0x1000>; 3750 frame-number = <2>; 3751 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3752 status = "disabled"; 3753 }; 3754 3755 frame@17c27000 { 3756 reg = <0x17c26000 0x1000>; 3757 frame-number = <3>; 3758 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3759 status = "disabled"; 3760 }; 3761 3762 frame@17c29000 { 3763 reg = <0x17c29000 0x1000>; 3764 frame-number = <4>; 3765 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3766 status = "disabled"; 3767 }; 3768 3769 frame@17c2b000 { 3770 reg = <0x17c2b000 0x1000>; 3771 frame-number = <5>; 3772 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3773 status = "disabled"; 3774 }; 3775 3776 frame@17c2d000 { 3777 reg = <0x17c2d000 0x1000>; 3778 frame-number = <6>; 3779 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3780 status = "disabled"; 3781 }; 3782 }; 3783 3784 apps_rsc: rsc@18200000 { 3785 compatible = "qcom,rpmh-rsc"; 3786 reg = <0x0 0x18200000 0x0 0x10000>, 3787 <0x0 0x18210000 0x0 0x10000>, 3788 <0x0 0x18220000 0x0 0x10000>; 3789 reg-names = "drv-0", "drv-1", "drv-2"; 3790 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3791 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3792 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3793 qcom,tcs-offset = <0xd00>; 3794 qcom,drv-id = <2>; 3795 qcom,tcs-config = <ACTIVE_TCS 2>, 3796 <SLEEP_TCS 1>, 3797 <WAKE_TCS 1>, 3798 <CONTROL_TCS 0>; 3799 label = "apps_rsc"; 3800 power-domains = <&cluster_pd>; 3801 3802 apps_bcm_voter: bcm-voter { 3803 compatible = "qcom,bcm-voter"; 3804 }; 3805 3806 rpmhcc: clock-controller { 3807 compatible = "qcom,sc8180x-rpmh-clk"; 3808 #clock-cells = <1>; 3809 clock-names = "xo"; 3810 clocks = <&xo_board_clk>; 3811 }; 3812 3813 rpmhpd: power-controller { 3814 compatible = "qcom,sc8180x-rpmhpd"; 3815 #power-domain-cells = <1>; 3816 operating-points-v2 = <&rpmhpd_opp_table>; 3817 3818 rpmhpd_opp_table: opp-table { 3819 compatible = "operating-points-v2"; 3820 3821 rpmhpd_opp_ret: opp1 { 3822 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3823 }; 3824 3825 rpmhpd_opp_min_svs: opp2 { 3826 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3827 }; 3828 3829 rpmhpd_opp_low_svs: opp3 { 3830 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3831 }; 3832 3833 rpmhpd_opp_svs: opp4 { 3834 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3835 }; 3836 3837 rpmhpd_opp_svs_l1: opp5 { 3838 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3839 }; 3840 3841 rpmhpd_opp_nom: opp6 { 3842 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3843 }; 3844 3845 rpmhpd_opp_nom_l1: opp7 { 3846 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3847 }; 3848 3849 rpmhpd_opp_nom_l2: opp8 { 3850 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3851 }; 3852 3853 rpmhpd_opp_turbo: opp9 { 3854 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3855 }; 3856 3857 rpmhpd_opp_turbo_l1: opp10 { 3858 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3859 }; 3860 }; 3861 }; 3862 }; 3863 3864 osm_l3: interconnect@18321000 { 3865 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3"; 3866 reg = <0 0x18321000 0 0x1400>; 3867 3868 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3869 clock-names = "xo", "alternate"; 3870 3871 #interconnect-cells = <1>; 3872 }; 3873 3874 lmh@18350800 { 3875 compatible = "qcom,sc8180x-lmh"; 3876 reg = <0 0x18350800 0 0x400>; 3877 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3878 cpus = <&cpu4>; 3879 qcom,lmh-temp-arm-millicelsius = <65000>; 3880 qcom,lmh-temp-low-millicelsius = <94500>; 3881 qcom,lmh-temp-high-millicelsius = <95000>; 3882 interrupt-controller; 3883 #interrupt-cells = <1>; 3884 }; 3885 3886 lmh@18358800 { 3887 compatible = "qcom,sc8180x-lmh"; 3888 reg = <0 0x18358800 0 0x400>; 3889 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3890 cpus = <&cpu0>; 3891 qcom,lmh-temp-arm-millicelsius = <65000>; 3892 qcom,lmh-temp-low-millicelsius = <94500>; 3893 qcom,lmh-temp-high-millicelsius = <95000>; 3894 interrupt-controller; 3895 #interrupt-cells = <1>; 3896 }; 3897 3898 cpufreq_hw: cpufreq@18323000 { 3899 compatible = "qcom,sc8180x-cpufreq-hw", "qcom,cpufreq-hw"; 3900 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3901 reg-names = "freq-domain0", "freq-domain1"; 3902 3903 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3904 clock-names = "xo", "alternate"; 3905 3906 #freq-domain-cells = <1>; 3907 #clock-cells = <1>; 3908 }; 3909 3910 wifi: wifi@18800000 { 3911 compatible = "qcom,wcn3990-wifi"; 3912 reg = <0 0x18800000 0 0x800000>; 3913 reg-names = "membase"; 3914 clock-names = "cxo_ref_clk_pin"; 3915 clocks = <&rpmhcc RPMH_RF_CLK2>; 3916 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3917 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3918 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3919 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3920 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3921 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3922 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3923 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3924 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3925 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3926 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3927 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3928 iommus = <&apps_smmu 0x0640 0x1>; 3929 qcom,msa-fixed-perm; 3930 status = "disabled"; 3931 }; 3932 }; 3933 3934 thermal-zones { 3935 cpu0-thermal { 3936 polling-delay-passive = <250>; 3937 3938 thermal-sensors = <&tsens0 1>; 3939 3940 trips { 3941 cpu-crit { 3942 temperature = <110000>; 3943 hysteresis = <1000>; 3944 type = "critical"; 3945 }; 3946 }; 3947 }; 3948 3949 cpu1-thermal { 3950 polling-delay-passive = <250>; 3951 3952 thermal-sensors = <&tsens0 2>; 3953 3954 trips { 3955 cpu-crit { 3956 temperature = <110000>; 3957 hysteresis = <1000>; 3958 type = "critical"; 3959 }; 3960 }; 3961 }; 3962 3963 cpu2-thermal { 3964 polling-delay-passive = <250>; 3965 3966 thermal-sensors = <&tsens0 3>; 3967 3968 trips { 3969 cpu-crit { 3970 temperature = <110000>; 3971 hysteresis = <1000>; 3972 type = "critical"; 3973 }; 3974 }; 3975 }; 3976 3977 cpu3-thermal { 3978 polling-delay-passive = <250>; 3979 3980 thermal-sensors = <&tsens0 4>; 3981 3982 trips { 3983 cpu-crit { 3984 temperature = <110000>; 3985 hysteresis = <1000>; 3986 type = "critical"; 3987 }; 3988 }; 3989 }; 3990 3991 cpu4-top-thermal { 3992 polling-delay-passive = <250>; 3993 3994 thermal-sensors = <&tsens0 7>; 3995 3996 trips { 3997 cpu-crit { 3998 temperature = <110000>; 3999 hysteresis = <1000>; 4000 type = "critical"; 4001 }; 4002 }; 4003 }; 4004 4005 cpu5-top-thermal { 4006 polling-delay-passive = <250>; 4007 4008 thermal-sensors = <&tsens0 8>; 4009 4010 trips { 4011 cpu-crit { 4012 temperature = <110000>; 4013 hysteresis = <1000>; 4014 type = "critical"; 4015 }; 4016 }; 4017 }; 4018 4019 cpu6-top-thermal { 4020 polling-delay-passive = <250>; 4021 4022 thermal-sensors = <&tsens0 9>; 4023 4024 trips { 4025 cpu-crit { 4026 temperature = <110000>; 4027 hysteresis = <1000>; 4028 type = "critical"; 4029 }; 4030 }; 4031 }; 4032 4033 cpu7-top-thermal { 4034 polling-delay-passive = <250>; 4035 4036 thermal-sensors = <&tsens0 10>; 4037 4038 trips { 4039 cpu-crit { 4040 temperature = <110000>; 4041 hysteresis = <1000>; 4042 type = "critical"; 4043 }; 4044 }; 4045 }; 4046 4047 cpu4-bottom-thermal { 4048 polling-delay-passive = <250>; 4049 4050 thermal-sensors = <&tsens0 11>; 4051 4052 trips { 4053 cpu-crit { 4054 temperature = <110000>; 4055 hysteresis = <1000>; 4056 type = "critical"; 4057 }; 4058 }; 4059 }; 4060 4061 cpu5-bottom-thermal { 4062 polling-delay-passive = <250>; 4063 4064 thermal-sensors = <&tsens0 12>; 4065 4066 trips { 4067 cpu-crit { 4068 temperature = <110000>; 4069 hysteresis = <1000>; 4070 type = "critical"; 4071 }; 4072 }; 4073 }; 4074 4075 cpu6-bottom-thermal { 4076 polling-delay-passive = <250>; 4077 4078 thermal-sensors = <&tsens0 13>; 4079 4080 trips { 4081 cpu-crit { 4082 temperature = <110000>; 4083 hysteresis = <1000>; 4084 type = "critical"; 4085 }; 4086 }; 4087 }; 4088 4089 cpu7-bottom-thermal { 4090 polling-delay-passive = <250>; 4091 4092 thermal-sensors = <&tsens0 14>; 4093 4094 trips { 4095 cpu-crit { 4096 temperature = <110000>; 4097 hysteresis = <1000>; 4098 type = "critical"; 4099 }; 4100 }; 4101 }; 4102 4103 aoss0-thermal { 4104 polling-delay-passive = <250>; 4105 4106 thermal-sensors = <&tsens0 0>; 4107 4108 trips { 4109 trip-point0 { 4110 temperature = <90000>; 4111 hysteresis = <2000>; 4112 type = "hot"; 4113 }; 4114 }; 4115 }; 4116 4117 cluster0-thermal { 4118 polling-delay-passive = <250>; 4119 4120 thermal-sensors = <&tsens0 5>; 4121 4122 trips { 4123 cluster-crit { 4124 temperature = <110000>; 4125 hysteresis = <2000>; 4126 type = "critical"; 4127 }; 4128 }; 4129 }; 4130 4131 cluster1-thermal { 4132 polling-delay-passive = <250>; 4133 4134 thermal-sensors = <&tsens0 6>; 4135 4136 trips { 4137 cluster-crit { 4138 temperature = <110000>; 4139 hysteresis = <2000>; 4140 type = "critical"; 4141 }; 4142 }; 4143 }; 4144 4145 gpu-top-thermal { 4146 polling-delay-passive = <250>; 4147 4148 thermal-sensors = <&tsens0 15>; 4149 4150 cooling-maps { 4151 map0 { 4152 trip = <&gpu_top_alert0>; 4153 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4154 }; 4155 }; 4156 4157 trips { 4158 gpu_top_alert0: trip-point0 { 4159 temperature = <85000>; 4160 hysteresis = <1000>; 4161 type = "passive"; 4162 }; 4163 4164 trip-point1 { 4165 temperature = <90000>; 4166 hysteresis = <1000>; 4167 type = "hot"; 4168 }; 4169 4170 trip-point2 { 4171 temperature = <110000>; 4172 hysteresis = <1000>; 4173 type = "critical"; 4174 }; 4175 }; 4176 }; 4177 4178 aoss1-thermal { 4179 polling-delay-passive = <250>; 4180 4181 thermal-sensors = <&tsens1 0>; 4182 4183 trips { 4184 trip-point0 { 4185 temperature = <90000>; 4186 hysteresis = <2000>; 4187 type = "hot"; 4188 }; 4189 }; 4190 }; 4191 4192 wlan-thermal { 4193 polling-delay-passive = <250>; 4194 4195 thermal-sensors = <&tsens1 1>; 4196 4197 trips { 4198 trip-point0 { 4199 temperature = <90000>; 4200 hysteresis = <2000>; 4201 type = "hot"; 4202 }; 4203 }; 4204 }; 4205 4206 video-thermal { 4207 polling-delay-passive = <250>; 4208 4209 thermal-sensors = <&tsens1 2>; 4210 4211 trips { 4212 trip-point0 { 4213 temperature = <90000>; 4214 hysteresis = <2000>; 4215 type = "hot"; 4216 }; 4217 }; 4218 }; 4219 4220 mem-thermal { 4221 polling-delay-passive = <250>; 4222 4223 thermal-sensors = <&tsens1 3>; 4224 4225 trips { 4226 trip-point0 { 4227 temperature = <90000>; 4228 hysteresis = <2000>; 4229 type = "hot"; 4230 }; 4231 }; 4232 }; 4233 4234 q6-hvx-thermal { 4235 polling-delay-passive = <250>; 4236 4237 thermal-sensors = <&tsens1 4>; 4238 4239 trips { 4240 trip-point0 { 4241 temperature = <90000>; 4242 hysteresis = <2000>; 4243 type = "hot"; 4244 }; 4245 }; 4246 }; 4247 4248 camera-thermal { 4249 polling-delay-passive = <250>; 4250 4251 thermal-sensors = <&tsens1 5>; 4252 4253 trips { 4254 trip-point0 { 4255 temperature = <90000>; 4256 hysteresis = <2000>; 4257 type = "hot"; 4258 }; 4259 }; 4260 }; 4261 4262 compute-thermal { 4263 polling-delay-passive = <250>; 4264 4265 thermal-sensors = <&tsens1 6>; 4266 4267 trips { 4268 trip-point0 { 4269 temperature = <90000>; 4270 hysteresis = <2000>; 4271 type = "hot"; 4272 }; 4273 }; 4274 }; 4275 4276 mdm-dsp-thermal { 4277 polling-delay-passive = <250>; 4278 4279 thermal-sensors = <&tsens1 7>; 4280 4281 trips { 4282 trip-point0 { 4283 temperature = <90000>; 4284 hysteresis = <2000>; 4285 type = "hot"; 4286 }; 4287 }; 4288 }; 4289 4290 npu-thermal { 4291 polling-delay-passive = <250>; 4292 4293 thermal-sensors = <&tsens1 8>; 4294 4295 trips { 4296 trip-point0 { 4297 temperature = <90000>; 4298 hysteresis = <2000>; 4299 type = "hot"; 4300 }; 4301 }; 4302 }; 4303 4304 gpu-bottom-thermal { 4305 polling-delay-passive = <250>; 4306 4307 thermal-sensors = <&tsens1 11>; 4308 4309 cooling-maps { 4310 map0 { 4311 trip = <&gpu_bottom_alert0>; 4312 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4313 }; 4314 }; 4315 4316 trips { 4317 gpu_bottom_alert0: trip-point0 { 4318 temperature = <85000>; 4319 hysteresis = <1000>; 4320 type = "passive"; 4321 }; 4322 4323 trip-point1 { 4324 temperature = <90000>; 4325 hysteresis = <1000>; 4326 type = "hot"; 4327 }; 4328 4329 trip-point2 { 4330 temperature = <110000>; 4331 hysteresis = <1000>; 4332 type = "critical"; 4333 }; 4334 }; 4335 }; 4336 }; 4337 4338 timer { 4339 compatible = "arm,armv8-timer"; 4340 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4341 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4342 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4343 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4344 }; 4345}; 4346