1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * SC7180 SoC device tree source 4 * 5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sc7180.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-sc7180.h> 11#include <dt-bindings/clock/qcom,gpucc-sc7180.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7180.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/interconnect/qcom,icc.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sc7180.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/phy/phy-qcom-qmp.h> 21#include <dt-bindings/phy/phy-qcom-qusb2.h> 22#include <dt-bindings/power/qcom-rpmpd.h> 23#include <dt-bindings/reset/qcom,sdm845-aoss.h> 24#include <dt-bindings/reset/qcom,sdm845-pdc.h> 25#include <dt-bindings/soc/qcom,rpmh-rsc.h> 26#include <dt-bindings/soc/qcom,apr.h> 27#include <dt-bindings/sound/qcom,q6afe.h> 28#include <dt-bindings/thermal/thermal.h> 29 30/ { 31 interrupt-parent = <&intc>; 32 33 #address-cells = <2>; 34 #size-cells = <2>; 35 36 aliases { 37 mmc1 = &sdhc_1; 38 mmc2 = &sdhc_2; 39 i2c0 = &i2c0; 40 i2c1 = &i2c1; 41 i2c2 = &i2c2; 42 i2c3 = &i2c3; 43 i2c4 = &i2c4; 44 i2c5 = &i2c5; 45 i2c6 = &i2c6; 46 i2c7 = &i2c7; 47 i2c8 = &i2c8; 48 i2c9 = &i2c9; 49 i2c10 = &i2c10; 50 i2c11 = &i2c11; 51 spi0 = &spi0; 52 spi1 = &spi1; 53 spi3 = &spi3; 54 spi5 = &spi5; 55 spi6 = &spi6; 56 spi8 = &spi8; 57 spi10 = &spi10; 58 spi11 = &spi11; 59 }; 60 61 chosen { }; 62 63 clocks { 64 xo_board: xo-board { 65 compatible = "fixed-clock"; 66 clock-frequency = <38400000>; 67 #clock-cells = <0>; 68 }; 69 70 sleep_clk: sleep-clk { 71 compatible = "fixed-clock"; 72 clock-frequency = <32764>; 73 #clock-cells = <0>; 74 }; 75 }; 76 77 cpus { 78 #address-cells = <2>; 79 #size-cells = <0>; 80 81 cpu0: cpu@0 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo468"; 84 reg = <0x0 0x0>; 85 clocks = <&cpufreq_hw 0>; 86 enable-method = "psci"; 87 power-domains = <&cpu_pd0>; 88 power-domain-names = "psci"; 89 capacity-dmips-mhz = <415>; 90 dynamic-power-coefficient = <137>; 91 operating-points-v2 = <&cpu0_opp_table>; 92 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 93 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 94 next-level-cache = <&l2_0>; 95 #cooling-cells = <2>; 96 qcom,freq-domain = <&cpufreq_hw 0>; 97 l2_0: l2-cache { 98 compatible = "cache"; 99 cache-level = <2>; 100 cache-unified; 101 next-level-cache = <&l3_0>; 102 l3_0: l3-cache { 103 compatible = "cache"; 104 cache-level = <3>; 105 cache-unified; 106 }; 107 }; 108 }; 109 110 cpu1: cpu@100 { 111 device_type = "cpu"; 112 compatible = "qcom,kryo468"; 113 reg = <0x0 0x100>; 114 clocks = <&cpufreq_hw 0>; 115 enable-method = "psci"; 116 power-domains = <&cpu_pd1>; 117 power-domain-names = "psci"; 118 capacity-dmips-mhz = <415>; 119 dynamic-power-coefficient = <137>; 120 next-level-cache = <&l2_100>; 121 operating-points-v2 = <&cpu0_opp_table>; 122 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 123 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 124 #cooling-cells = <2>; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 l2_100: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 cache-unified; 130 next-level-cache = <&l3_0>; 131 }; 132 }; 133 134 cpu2: cpu@200 { 135 device_type = "cpu"; 136 compatible = "qcom,kryo468"; 137 reg = <0x0 0x200>; 138 clocks = <&cpufreq_hw 0>; 139 enable-method = "psci"; 140 power-domains = <&cpu_pd2>; 141 power-domain-names = "psci"; 142 capacity-dmips-mhz = <415>; 143 dynamic-power-coefficient = <137>; 144 next-level-cache = <&l2_200>; 145 operating-points-v2 = <&cpu0_opp_table>; 146 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 147 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 148 #cooling-cells = <2>; 149 qcom,freq-domain = <&cpufreq_hw 0>; 150 l2_200: l2-cache { 151 compatible = "cache"; 152 cache-level = <2>; 153 cache-unified; 154 next-level-cache = <&l3_0>; 155 }; 156 }; 157 158 cpu3: cpu@300 { 159 device_type = "cpu"; 160 compatible = "qcom,kryo468"; 161 reg = <0x0 0x300>; 162 clocks = <&cpufreq_hw 0>; 163 enable-method = "psci"; 164 power-domains = <&cpu_pd3>; 165 power-domain-names = "psci"; 166 capacity-dmips-mhz = <415>; 167 dynamic-power-coefficient = <137>; 168 next-level-cache = <&l2_300>; 169 operating-points-v2 = <&cpu0_opp_table>; 170 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 171 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 172 #cooling-cells = <2>; 173 qcom,freq-domain = <&cpufreq_hw 0>; 174 l2_300: l2-cache { 175 compatible = "cache"; 176 cache-level = <2>; 177 cache-unified; 178 next-level-cache = <&l3_0>; 179 }; 180 }; 181 182 cpu4: cpu@400 { 183 device_type = "cpu"; 184 compatible = "qcom,kryo468"; 185 reg = <0x0 0x400>; 186 clocks = <&cpufreq_hw 0>; 187 enable-method = "psci"; 188 power-domains = <&cpu_pd4>; 189 power-domain-names = "psci"; 190 capacity-dmips-mhz = <415>; 191 dynamic-power-coefficient = <137>; 192 next-level-cache = <&l2_400>; 193 operating-points-v2 = <&cpu0_opp_table>; 194 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 195 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 196 #cooling-cells = <2>; 197 qcom,freq-domain = <&cpufreq_hw 0>; 198 l2_400: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&l3_0>; 203 }; 204 }; 205 206 cpu5: cpu@500 { 207 device_type = "cpu"; 208 compatible = "qcom,kryo468"; 209 reg = <0x0 0x500>; 210 clocks = <&cpufreq_hw 0>; 211 enable-method = "psci"; 212 power-domains = <&cpu_pd5>; 213 power-domain-names = "psci"; 214 capacity-dmips-mhz = <415>; 215 dynamic-power-coefficient = <137>; 216 next-level-cache = <&l2_500>; 217 operating-points-v2 = <&cpu0_opp_table>; 218 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 219 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 220 #cooling-cells = <2>; 221 qcom,freq-domain = <&cpufreq_hw 0>; 222 l2_500: l2-cache { 223 compatible = "cache"; 224 cache-level = <2>; 225 cache-unified; 226 next-level-cache = <&l3_0>; 227 }; 228 }; 229 230 cpu6: cpu@600 { 231 device_type = "cpu"; 232 compatible = "qcom,kryo468"; 233 reg = <0x0 0x600>; 234 clocks = <&cpufreq_hw 1>; 235 enable-method = "psci"; 236 power-domains = <&cpu_pd6>; 237 power-domain-names = "psci"; 238 capacity-dmips-mhz = <1024>; 239 dynamic-power-coefficient = <480>; 240 next-level-cache = <&l2_600>; 241 operating-points-v2 = <&cpu6_opp_table>; 242 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 243 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 244 #cooling-cells = <2>; 245 qcom,freq-domain = <&cpufreq_hw 1>; 246 l2_600: l2-cache { 247 compatible = "cache"; 248 cache-level = <2>; 249 cache-unified; 250 next-level-cache = <&l3_0>; 251 }; 252 }; 253 254 cpu7: cpu@700 { 255 device_type = "cpu"; 256 compatible = "qcom,kryo468"; 257 reg = <0x0 0x700>; 258 clocks = <&cpufreq_hw 1>; 259 enable-method = "psci"; 260 power-domains = <&cpu_pd7>; 261 power-domain-names = "psci"; 262 capacity-dmips-mhz = <1024>; 263 dynamic-power-coefficient = <480>; 264 next-level-cache = <&l2_700>; 265 operating-points-v2 = <&cpu6_opp_table>; 266 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 267 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 268 #cooling-cells = <2>; 269 qcom,freq-domain = <&cpufreq_hw 1>; 270 l2_700: l2-cache { 271 compatible = "cache"; 272 cache-level = <2>; 273 cache-unified; 274 next-level-cache = <&l3_0>; 275 }; 276 }; 277 278 cpu-map { 279 cluster0 { 280 core0 { 281 cpu = <&cpu0>; 282 }; 283 284 core1 { 285 cpu = <&cpu1>; 286 }; 287 288 core2 { 289 cpu = <&cpu2>; 290 }; 291 292 core3 { 293 cpu = <&cpu3>; 294 }; 295 296 core4 { 297 cpu = <&cpu4>; 298 }; 299 300 core5 { 301 cpu = <&cpu5>; 302 }; 303 304 core6 { 305 cpu = <&cpu6>; 306 }; 307 308 core7 { 309 cpu = <&cpu7>; 310 }; 311 }; 312 }; 313 314 idle_states: idle-states { 315 entry-method = "psci"; 316 317 little_cpu_sleep_0: cpu-sleep-0-0 { 318 compatible = "arm,idle-state"; 319 idle-state-name = "little-power-down"; 320 arm,psci-suspend-param = <0x40000003>; 321 entry-latency-us = <549>; 322 exit-latency-us = <901>; 323 min-residency-us = <1774>; 324 local-timer-stop; 325 }; 326 327 little_cpu_sleep_1: cpu-sleep-0-1 { 328 compatible = "arm,idle-state"; 329 idle-state-name = "little-rail-power-down"; 330 arm,psci-suspend-param = <0x40000004>; 331 entry-latency-us = <702>; 332 exit-latency-us = <915>; 333 min-residency-us = <4001>; 334 local-timer-stop; 335 }; 336 337 big_cpu_sleep_0: cpu-sleep-1-0 { 338 compatible = "arm,idle-state"; 339 idle-state-name = "big-power-down"; 340 arm,psci-suspend-param = <0x40000003>; 341 entry-latency-us = <523>; 342 exit-latency-us = <1244>; 343 min-residency-us = <2207>; 344 local-timer-stop; 345 }; 346 347 big_cpu_sleep_1: cpu-sleep-1-1 { 348 compatible = "arm,idle-state"; 349 idle-state-name = "big-rail-power-down"; 350 arm,psci-suspend-param = <0x40000004>; 351 entry-latency-us = <526>; 352 exit-latency-us = <1854>; 353 min-residency-us = <5555>; 354 local-timer-stop; 355 }; 356 }; 357 358 domain_idle_states: domain-idle-states { 359 cluster_sleep_pc: cluster-sleep-0 { 360 compatible = "domain-idle-state"; 361 arm,psci-suspend-param = <0x41000044>; 362 entry-latency-us = <2752>; 363 exit-latency-us = <3048>; 364 min-residency-us = <6118>; 365 }; 366 367 cluster_sleep_cx_ret: cluster-sleep-1 { 368 compatible = "domain-idle-state"; 369 arm,psci-suspend-param = <0x41001244>; 370 entry-latency-us = <3638>; 371 exit-latency-us = <4562>; 372 min-residency-us = <8467>; 373 }; 374 375 cluster_aoss_sleep: cluster-sleep-2 { 376 compatible = "domain-idle-state"; 377 arm,psci-suspend-param = <0x4100b244>; 378 entry-latency-us = <3263>; 379 exit-latency-us = <6562>; 380 min-residency-us = <9826>; 381 }; 382 }; 383 }; 384 385 firmware { 386 scm: scm { 387 compatible = "qcom,scm-sc7180", "qcom,scm"; 388 }; 389 }; 390 391 memory@80000000 { 392 device_type = "memory"; 393 /* We expect the bootloader to fill in the size */ 394 reg = <0 0x80000000 0 0>; 395 }; 396 397 cpu0_opp_table: opp-table-cpu0 { 398 compatible = "operating-points-v2"; 399 opp-shared; 400 401 cpu0_opp1: opp-300000000 { 402 opp-hz = /bits/ 64 <300000000>; 403 opp-peak-kBps = <1200000 4800000>; 404 }; 405 406 cpu0_opp2: opp-576000000 { 407 opp-hz = /bits/ 64 <576000000>; 408 opp-peak-kBps = <1200000 4800000>; 409 }; 410 411 cpu0_opp3: opp-768000000 { 412 opp-hz = /bits/ 64 <768000000>; 413 opp-peak-kBps = <1200000 4800000>; 414 }; 415 416 cpu0_opp4: opp-1017600000 { 417 opp-hz = /bits/ 64 <1017600000>; 418 opp-peak-kBps = <1804000 8908800>; 419 }; 420 421 cpu0_opp5: opp-1248000000 { 422 opp-hz = /bits/ 64 <1248000000>; 423 opp-peak-kBps = <2188000 12902400>; 424 }; 425 426 cpu0_opp6: opp-1324800000 { 427 opp-hz = /bits/ 64 <1324800000>; 428 opp-peak-kBps = <2188000 12902400>; 429 }; 430 431 cpu0_opp7: opp-1516800000 { 432 opp-hz = /bits/ 64 <1516800000>; 433 opp-peak-kBps = <3072000 15052800>; 434 }; 435 436 cpu0_opp8: opp-1612800000 { 437 opp-hz = /bits/ 64 <1612800000>; 438 opp-peak-kBps = <3072000 15052800>; 439 }; 440 441 cpu0_opp9: opp-1708800000 { 442 opp-hz = /bits/ 64 <1708800000>; 443 opp-peak-kBps = <3072000 15052800>; 444 }; 445 446 cpu0_opp10: opp-1804800000 { 447 opp-hz = /bits/ 64 <1804800000>; 448 opp-peak-kBps = <4068000 22425600>; 449 }; 450 }; 451 452 cpu6_opp_table: opp-table-cpu6 { 453 compatible = "operating-points-v2"; 454 opp-shared; 455 456 cpu6_opp1: opp-300000000 { 457 opp-hz = /bits/ 64 <300000000>; 458 opp-peak-kBps = <2188000 8908800>; 459 }; 460 461 cpu6_opp2: opp-652800000 { 462 opp-hz = /bits/ 64 <652800000>; 463 opp-peak-kBps = <2188000 8908800>; 464 }; 465 466 cpu6_opp3: opp-825600000 { 467 opp-hz = /bits/ 64 <825600000>; 468 opp-peak-kBps = <2188000 8908800>; 469 }; 470 471 cpu6_opp4: opp-979200000 { 472 opp-hz = /bits/ 64 <979200000>; 473 opp-peak-kBps = <2188000 8908800>; 474 }; 475 476 cpu6_opp5: opp-1113600000 { 477 opp-hz = /bits/ 64 <1113600000>; 478 opp-peak-kBps = <2188000 8908800>; 479 }; 480 481 cpu6_opp6: opp-1267200000 { 482 opp-hz = /bits/ 64 <1267200000>; 483 opp-peak-kBps = <4068000 12902400>; 484 }; 485 486 cpu6_opp7: opp-1555200000 { 487 opp-hz = /bits/ 64 <1555200000>; 488 opp-peak-kBps = <4068000 15052800>; 489 }; 490 491 cpu6_opp8: opp-1708800000 { 492 opp-hz = /bits/ 64 <1708800000>; 493 opp-peak-kBps = <6220000 19353600>; 494 }; 495 496 cpu6_opp9: opp-1843200000 { 497 opp-hz = /bits/ 64 <1843200000>; 498 opp-peak-kBps = <6220000 19353600>; 499 }; 500 501 cpu6_opp10: opp-1900800000 { 502 opp-hz = /bits/ 64 <1900800000>; 503 opp-peak-kBps = <6220000 22425600>; 504 }; 505 506 cpu6_opp11: opp-1996800000 { 507 opp-hz = /bits/ 64 <1996800000>; 508 opp-peak-kBps = <6220000 22425600>; 509 }; 510 511 cpu6_opp12: opp-2112000000 { 512 opp-hz = /bits/ 64 <2112000000>; 513 opp-peak-kBps = <6220000 22425600>; 514 }; 515 516 cpu6_opp13: opp-2208000000 { 517 opp-hz = /bits/ 64 <2208000000>; 518 opp-peak-kBps = <7216000 22425600>; 519 }; 520 521 cpu6_opp14: opp-2323200000 { 522 opp-hz = /bits/ 64 <2323200000>; 523 opp-peak-kBps = <7216000 22425600>; 524 }; 525 526 cpu6_opp15: opp-2400000000 { 527 opp-hz = /bits/ 64 <2400000000>; 528 opp-peak-kBps = <8532000 23347200>; 529 }; 530 531 cpu6_opp16: opp-2553600000 { 532 opp-hz = /bits/ 64 <2553600000>; 533 opp-peak-kBps = <8532000 23347200>; 534 }; 535 }; 536 537 qspi_opp_table: opp-table-qspi { 538 compatible = "operating-points-v2"; 539 540 opp-75000000 { 541 opp-hz = /bits/ 64 <75000000>; 542 required-opps = <&rpmhpd_opp_low_svs>; 543 }; 544 545 opp-150000000 { 546 opp-hz = /bits/ 64 <150000000>; 547 required-opps = <&rpmhpd_opp_svs>; 548 }; 549 550 opp-300000000 { 551 opp-hz = /bits/ 64 <300000000>; 552 required-opps = <&rpmhpd_opp_nom>; 553 }; 554 }; 555 556 qup_opp_table: opp-table-qup { 557 compatible = "operating-points-v2"; 558 559 opp-75000000 { 560 opp-hz = /bits/ 64 <75000000>; 561 required-opps = <&rpmhpd_opp_low_svs>; 562 }; 563 564 opp-100000000 { 565 opp-hz = /bits/ 64 <100000000>; 566 required-opps = <&rpmhpd_opp_svs>; 567 }; 568 569 opp-128000000 { 570 opp-hz = /bits/ 64 <128000000>; 571 required-opps = <&rpmhpd_opp_nom>; 572 }; 573 }; 574 575 pmu { 576 compatible = "arm,armv8-pmuv3"; 577 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 578 }; 579 580 psci { 581 compatible = "arm,psci-1.0"; 582 method = "smc"; 583 584 cpu_pd0: power-domain-cpu0 { 585 #power-domain-cells = <0>; 586 power-domains = <&cluster_pd>; 587 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 588 }; 589 590 cpu_pd1: power-domain-cpu1 { 591 #power-domain-cells = <0>; 592 power-domains = <&cluster_pd>; 593 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 594 }; 595 596 cpu_pd2: power-domain-cpu2 { 597 #power-domain-cells = <0>; 598 power-domains = <&cluster_pd>; 599 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 600 }; 601 602 cpu_pd3: power-domain-cpu3 { 603 #power-domain-cells = <0>; 604 power-domains = <&cluster_pd>; 605 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 606 }; 607 608 cpu_pd4: power-domain-cpu4 { 609 #power-domain-cells = <0>; 610 power-domains = <&cluster_pd>; 611 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 612 }; 613 614 cpu_pd5: power-domain-cpu5 { 615 #power-domain-cells = <0>; 616 power-domains = <&cluster_pd>; 617 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 618 }; 619 620 cpu_pd6: power-domain-cpu6 { 621 #power-domain-cells = <0>; 622 power-domains = <&cluster_pd>; 623 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 624 }; 625 626 cpu_pd7: power-domain-cpu7 { 627 #power-domain-cells = <0>; 628 power-domains = <&cluster_pd>; 629 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 630 }; 631 632 cluster_pd: power-domain-cluster { 633 #power-domain-cells = <0>; 634 domain-idle-states = <&cluster_sleep_pc 635 &cluster_sleep_cx_ret 636 &cluster_aoss_sleep>; 637 }; 638 }; 639 640 reserved_memory: reserved-memory { 641 #address-cells = <2>; 642 #size-cells = <2>; 643 ranges; 644 645 hyp_mem: memory@80000000 { 646 reg = <0x0 0x80000000 0x0 0x600000>; 647 no-map; 648 }; 649 650 xbl_mem: memory@80600000 { 651 reg = <0x0 0x80600000 0x0 0x200000>; 652 no-map; 653 }; 654 655 aop_mem: memory@80800000 { 656 reg = <0x0 0x80800000 0x0 0x20000>; 657 no-map; 658 }; 659 660 aop_cmd_db_mem: memory@80820000 { 661 reg = <0x0 0x80820000 0x0 0x20000>; 662 compatible = "qcom,cmd-db"; 663 no-map; 664 }; 665 666 sec_apps_mem: memory@808ff000 { 667 reg = <0x0 0x808ff000 0x0 0x1000>; 668 no-map; 669 }; 670 671 smem_mem: memory@80900000 { 672 reg = <0x0 0x80900000 0x0 0x200000>; 673 no-map; 674 }; 675 676 tz_mem: memory@80b00000 { 677 reg = <0x0 0x80b00000 0x0 0x3900000>; 678 no-map; 679 }; 680 681 ipa_fw_mem: memory@8b700000 { 682 reg = <0 0x8b700000 0 0x10000>; 683 no-map; 684 }; 685 686 rmtfs_mem: memory@94600000 { 687 compatible = "qcom,rmtfs-mem"; 688 reg = <0x0 0x94600000 0x0 0x200000>; 689 no-map; 690 691 qcom,client-id = <1>; 692 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 693 }; 694 }; 695 696 smem { 697 compatible = "qcom,smem"; 698 memory-region = <&smem_mem>; 699 hwlocks = <&tcsr_mutex 3>; 700 }; 701 702 smp2p-cdsp { 703 compatible = "qcom,smp2p"; 704 qcom,smem = <94>, <432>; 705 706 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 707 708 mboxes = <&apss_shared 6>; 709 710 qcom,local-pid = <0>; 711 qcom,remote-pid = <5>; 712 713 cdsp_smp2p_out: master-kernel { 714 qcom,entry-name = "master-kernel"; 715 #qcom,smem-state-cells = <1>; 716 }; 717 718 cdsp_smp2p_in: slave-kernel { 719 qcom,entry-name = "slave-kernel"; 720 721 interrupt-controller; 722 #interrupt-cells = <2>; 723 }; 724 }; 725 726 smp2p-lpass { 727 compatible = "qcom,smp2p"; 728 qcom,smem = <443>, <429>; 729 730 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 731 732 mboxes = <&apss_shared 10>; 733 734 qcom,local-pid = <0>; 735 qcom,remote-pid = <2>; 736 737 adsp_smp2p_out: master-kernel { 738 qcom,entry-name = "master-kernel"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 adsp_smp2p_in: slave-kernel { 743 qcom,entry-name = "slave-kernel"; 744 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 smp2p-mpss { 751 compatible = "qcom,smp2p"; 752 qcom,smem = <435>, <428>; 753 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 754 mboxes = <&apss_shared 14>; 755 qcom,local-pid = <0>; 756 qcom,remote-pid = <1>; 757 758 modem_smp2p_out: master-kernel { 759 qcom,entry-name = "master-kernel"; 760 #qcom,smem-state-cells = <1>; 761 }; 762 763 modem_smp2p_in: slave-kernel { 764 qcom,entry-name = "slave-kernel"; 765 interrupt-controller; 766 #interrupt-cells = <2>; 767 }; 768 769 ipa_smp2p_out: ipa-ap-to-modem { 770 qcom,entry-name = "ipa"; 771 #qcom,smem-state-cells = <1>; 772 }; 773 774 ipa_smp2p_in: ipa-modem-to-ap { 775 qcom,entry-name = "ipa"; 776 interrupt-controller; 777 #interrupt-cells = <2>; 778 }; 779 }; 780 781 soc: soc@0 { 782 #address-cells = <2>; 783 #size-cells = <2>; 784 ranges = <0 0 0 0 0x10 0>; 785 dma-ranges = <0 0 0 0 0x10 0>; 786 compatible = "simple-bus"; 787 788 gcc: clock-controller@100000 { 789 compatible = "qcom,gcc-sc7180"; 790 reg = <0 0x00100000 0 0x1f0000>; 791 clocks = <&rpmhcc RPMH_CXO_CLK>, 792 <&rpmhcc RPMH_CXO_CLK_A>, 793 <&sleep_clk>; 794 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 795 #clock-cells = <1>; 796 #reset-cells = <1>; 797 #power-domain-cells = <1>; 798 power-domains = <&rpmhpd SC7180_CX>; 799 }; 800 801 qfprom: efuse@784000 { 802 compatible = "qcom,sc7180-qfprom", "qcom,qfprom"; 803 reg = <0 0x00784000 0 0x7a0>, 804 <0 0x00780000 0 0x7a0>, 805 <0 0x00782000 0 0x100>, 806 <0 0x00786000 0 0x1fff>; 807 808 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 809 clock-names = "core"; 810 #address-cells = <1>; 811 #size-cells = <1>; 812 813 qusb2p_hstx_trim: hstx-trim-primary@25b { 814 reg = <0x25b 0x1>; 815 bits = <1 3>; 816 }; 817 818 gpu_speed_bin: gpu-speed-bin@1d2 { 819 reg = <0x1d2 0x2>; 820 bits = <5 8>; 821 }; 822 }; 823 824 sdhc_1: mmc@7c4000 { 825 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 826 reg = <0 0x007c4000 0 0x1000>, 827 <0 0x007c5000 0 0x1000>; 828 reg-names = "hc", "cqhci"; 829 830 iommus = <&apps_smmu 0x60 0x0>; 831 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 833 interrupt-names = "hc_irq", "pwr_irq"; 834 835 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 836 <&gcc GCC_SDCC1_APPS_CLK>, 837 <&rpmhcc RPMH_CXO_CLK>; 838 clock-names = "iface", "core", "xo"; 839 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, 840 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; 841 interconnect-names = "sdhc-ddr","cpu-sdhc"; 842 power-domains = <&rpmhpd SC7180_CX>; 843 operating-points-v2 = <&sdhc1_opp_table>; 844 845 bus-width = <8>; 846 non-removable; 847 supports-cqe; 848 849 mmc-ddr-1_8v; 850 mmc-hs200-1_8v; 851 mmc-hs400-1_8v; 852 mmc-hs400-enhanced-strobe; 853 854 status = "disabled"; 855 856 sdhc1_opp_table: opp-table { 857 compatible = "operating-points-v2"; 858 859 opp-100000000 { 860 opp-hz = /bits/ 64 <100000000>; 861 required-opps = <&rpmhpd_opp_low_svs>; 862 opp-peak-kBps = <1800000 600000>; 863 opp-avg-kBps = <100000 0>; 864 }; 865 866 opp-384000000 { 867 opp-hz = /bits/ 64 <384000000>; 868 required-opps = <&rpmhpd_opp_nom>; 869 opp-peak-kBps = <5400000 1600000>; 870 opp-avg-kBps = <390000 0>; 871 }; 872 }; 873 }; 874 875 qupv3_id_0: geniqup@8c0000 { 876 compatible = "qcom,geni-se-qup"; 877 reg = <0 0x008c0000 0 0x6000>; 878 clock-names = "m-ahb", "s-ahb"; 879 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 880 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 881 #address-cells = <2>; 882 #size-cells = <2>; 883 ranges; 884 iommus = <&apps_smmu 0x43 0x0>; 885 status = "disabled"; 886 887 i2c0: i2c@880000 { 888 compatible = "qcom,geni-i2c"; 889 reg = <0 0x00880000 0 0x4000>; 890 clock-names = "se"; 891 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&qup_i2c0_default>; 894 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 895 #address-cells = <1>; 896 #size-cells = <0>; 897 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 898 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 899 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 900 interconnect-names = "qup-core", "qup-config", 901 "qup-memory"; 902 power-domains = <&rpmhpd SC7180_CX>; 903 required-opps = <&rpmhpd_opp_low_svs>; 904 status = "disabled"; 905 }; 906 907 spi0: spi@880000 { 908 compatible = "qcom,geni-spi"; 909 reg = <0 0x00880000 0 0x4000>; 910 clock-names = "se"; 911 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>; 914 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 915 #address-cells = <1>; 916 #size-cells = <0>; 917 power-domains = <&rpmhpd SC7180_CX>; 918 operating-points-v2 = <&qup_opp_table>; 919 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 920 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 921 interconnect-names = "qup-core", "qup-config"; 922 status = "disabled"; 923 }; 924 925 uart0: serial@880000 { 926 compatible = "qcom,geni-uart"; 927 reg = <0 0x00880000 0 0x4000>; 928 clock-names = "se"; 929 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 930 pinctrl-names = "default"; 931 pinctrl-0 = <&qup_uart0_default>; 932 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 933 power-domains = <&rpmhpd SC7180_CX>; 934 operating-points-v2 = <&qup_opp_table>; 935 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 936 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 937 interconnect-names = "qup-core", "qup-config"; 938 status = "disabled"; 939 }; 940 941 i2c1: i2c@884000 { 942 compatible = "qcom,geni-i2c"; 943 reg = <0 0x00884000 0 0x4000>; 944 clock-names = "se"; 945 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&qup_i2c1_default>; 948 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 952 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 953 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 954 interconnect-names = "qup-core", "qup-config", 955 "qup-memory"; 956 power-domains = <&rpmhpd SC7180_CX>; 957 required-opps = <&rpmhpd_opp_low_svs>; 958 status = "disabled"; 959 }; 960 961 spi1: spi@884000 { 962 compatible = "qcom,geni-spi"; 963 reg = <0 0x00884000 0 0x4000>; 964 clock-names = "se"; 965 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>; 968 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 power-domains = <&rpmhpd SC7180_CX>; 972 operating-points-v2 = <&qup_opp_table>; 973 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 974 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 975 interconnect-names = "qup-core", "qup-config"; 976 status = "disabled"; 977 }; 978 979 uart1: serial@884000 { 980 compatible = "qcom,geni-uart"; 981 reg = <0 0x00884000 0 0x4000>; 982 clock-names = "se"; 983 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_uart1_default>; 986 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 987 power-domains = <&rpmhpd SC7180_CX>; 988 operating-points-v2 = <&qup_opp_table>; 989 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 990 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 991 interconnect-names = "qup-core", "qup-config"; 992 status = "disabled"; 993 }; 994 995 i2c2: i2c@888000 { 996 compatible = "qcom,geni-i2c"; 997 reg = <0 0x00888000 0 0x4000>; 998 clock-names = "se"; 999 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_i2c2_default>; 1002 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1006 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1007 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1008 interconnect-names = "qup-core", "qup-config", 1009 "qup-memory"; 1010 power-domains = <&rpmhpd SC7180_CX>; 1011 required-opps = <&rpmhpd_opp_low_svs>; 1012 status = "disabled"; 1013 }; 1014 1015 uart2: serial@888000 { 1016 compatible = "qcom,geni-uart"; 1017 reg = <0 0x00888000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_uart2_default>; 1022 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1023 power-domains = <&rpmhpd SC7180_CX>; 1024 operating-points-v2 = <&qup_opp_table>; 1025 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1026 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1027 interconnect-names = "qup-core", "qup-config"; 1028 status = "disabled"; 1029 }; 1030 1031 i2c3: i2c@88c000 { 1032 compatible = "qcom,geni-i2c"; 1033 reg = <0 0x0088c000 0 0x4000>; 1034 clock-names = "se"; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1036 pinctrl-names = "default"; 1037 pinctrl-0 = <&qup_i2c3_default>; 1038 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1042 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1043 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1044 interconnect-names = "qup-core", "qup-config", 1045 "qup-memory"; 1046 power-domains = <&rpmhpd SC7180_CX>; 1047 required-opps = <&rpmhpd_opp_low_svs>; 1048 status = "disabled"; 1049 }; 1050 1051 spi3: spi@88c000 { 1052 compatible = "qcom,geni-spi"; 1053 reg = <0 0x0088c000 0 0x4000>; 1054 clock-names = "se"; 1055 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1056 pinctrl-names = "default"; 1057 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>; 1058 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 power-domains = <&rpmhpd SC7180_CX>; 1062 operating-points-v2 = <&qup_opp_table>; 1063 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1064 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1065 interconnect-names = "qup-core", "qup-config"; 1066 status = "disabled"; 1067 }; 1068 1069 uart3: serial@88c000 { 1070 compatible = "qcom,geni-uart"; 1071 reg = <0 0x0088c000 0 0x4000>; 1072 clock-names = "se"; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&qup_uart3_default>; 1076 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1077 power-domains = <&rpmhpd SC7180_CX>; 1078 operating-points-v2 = <&qup_opp_table>; 1079 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1080 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1081 interconnect-names = "qup-core", "qup-config"; 1082 status = "disabled"; 1083 }; 1084 1085 i2c4: i2c@890000 { 1086 compatible = "qcom,geni-i2c"; 1087 reg = <0 0x00890000 0 0x4000>; 1088 clock-names = "se"; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1090 pinctrl-names = "default"; 1091 pinctrl-0 = <&qup_i2c4_default>; 1092 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1096 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1097 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1098 interconnect-names = "qup-core", "qup-config", 1099 "qup-memory"; 1100 power-domains = <&rpmhpd SC7180_CX>; 1101 required-opps = <&rpmhpd_opp_low_svs>; 1102 status = "disabled"; 1103 }; 1104 1105 uart4: serial@890000 { 1106 compatible = "qcom,geni-uart"; 1107 reg = <0 0x00890000 0 0x4000>; 1108 clock-names = "se"; 1109 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&qup_uart4_default>; 1112 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1113 power-domains = <&rpmhpd SC7180_CX>; 1114 operating-points-v2 = <&qup_opp_table>; 1115 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1116 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1117 interconnect-names = "qup-core", "qup-config"; 1118 status = "disabled"; 1119 }; 1120 1121 i2c5: i2c@894000 { 1122 compatible = "qcom,geni-i2c"; 1123 reg = <0 0x00894000 0 0x4000>; 1124 clock-names = "se"; 1125 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1126 pinctrl-names = "default"; 1127 pinctrl-0 = <&qup_i2c5_default>; 1128 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1132 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1133 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1134 interconnect-names = "qup-core", "qup-config", 1135 "qup-memory"; 1136 power-domains = <&rpmhpd SC7180_CX>; 1137 required-opps = <&rpmhpd_opp_low_svs>; 1138 status = "disabled"; 1139 }; 1140 1141 spi5: spi@894000 { 1142 compatible = "qcom,geni-spi"; 1143 reg = <0 0x00894000 0 0x4000>; 1144 clock-names = "se"; 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1146 pinctrl-names = "default"; 1147 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>; 1148 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 power-domains = <&rpmhpd SC7180_CX>; 1152 operating-points-v2 = <&qup_opp_table>; 1153 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1154 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1155 interconnect-names = "qup-core", "qup-config"; 1156 status = "disabled"; 1157 }; 1158 1159 uart5: serial@894000 { 1160 compatible = "qcom,geni-uart"; 1161 reg = <0 0x00894000 0 0x4000>; 1162 clock-names = "se"; 1163 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&qup_uart5_default>; 1166 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1167 power-domains = <&rpmhpd SC7180_CX>; 1168 operating-points-v2 = <&qup_opp_table>; 1169 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1170 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1171 interconnect-names = "qup-core", "qup-config"; 1172 status = "disabled"; 1173 }; 1174 }; 1175 1176 qupv3_id_1: geniqup@ac0000 { 1177 compatible = "qcom,geni-se-qup"; 1178 reg = <0 0x00ac0000 0 0x6000>; 1179 clock-names = "m-ahb", "s-ahb"; 1180 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1181 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1182 #address-cells = <2>; 1183 #size-cells = <2>; 1184 ranges; 1185 iommus = <&apps_smmu 0x4c3 0x0>; 1186 status = "disabled"; 1187 1188 i2c6: i2c@a80000 { 1189 compatible = "qcom,geni-i2c"; 1190 reg = <0 0x00a80000 0 0x4000>; 1191 clock-names = "se"; 1192 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_i2c6_default>; 1195 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1199 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1200 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1201 interconnect-names = "qup-core", "qup-config", 1202 "qup-memory"; 1203 power-domains = <&rpmhpd SC7180_CX>; 1204 required-opps = <&rpmhpd_opp_low_svs>; 1205 status = "disabled"; 1206 }; 1207 1208 spi6: spi@a80000 { 1209 compatible = "qcom,geni-spi"; 1210 reg = <0 0x00a80000 0 0x4000>; 1211 clock-names = "se"; 1212 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1213 pinctrl-names = "default"; 1214 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>; 1215 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 power-domains = <&rpmhpd SC7180_CX>; 1219 operating-points-v2 = <&qup_opp_table>; 1220 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1221 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1222 interconnect-names = "qup-core", "qup-config"; 1223 status = "disabled"; 1224 }; 1225 1226 uart6: serial@a80000 { 1227 compatible = "qcom,geni-uart"; 1228 reg = <0 0x00a80000 0 0x4000>; 1229 clock-names = "se"; 1230 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1231 pinctrl-names = "default"; 1232 pinctrl-0 = <&qup_uart6_default>; 1233 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1234 power-domains = <&rpmhpd SC7180_CX>; 1235 operating-points-v2 = <&qup_opp_table>; 1236 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1237 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1238 interconnect-names = "qup-core", "qup-config"; 1239 status = "disabled"; 1240 }; 1241 1242 i2c7: i2c@a84000 { 1243 compatible = "qcom,geni-i2c"; 1244 reg = <0 0x00a84000 0 0x4000>; 1245 clock-names = "se"; 1246 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1247 pinctrl-names = "default"; 1248 pinctrl-0 = <&qup_i2c7_default>; 1249 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1253 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1254 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1255 interconnect-names = "qup-core", "qup-config", 1256 "qup-memory"; 1257 power-domains = <&rpmhpd SC7180_CX>; 1258 required-opps = <&rpmhpd_opp_low_svs>; 1259 status = "disabled"; 1260 }; 1261 1262 uart7: serial@a84000 { 1263 compatible = "qcom,geni-uart"; 1264 reg = <0 0x00a84000 0 0x4000>; 1265 clock-names = "se"; 1266 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&qup_uart7_default>; 1269 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1270 power-domains = <&rpmhpd SC7180_CX>; 1271 operating-points-v2 = <&qup_opp_table>; 1272 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1273 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1274 interconnect-names = "qup-core", "qup-config"; 1275 status = "disabled"; 1276 }; 1277 1278 i2c8: i2c@a88000 { 1279 compatible = "qcom,geni-i2c"; 1280 reg = <0 0x00a88000 0 0x4000>; 1281 clock-names = "se"; 1282 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_i2c8_default>; 1285 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1290 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1291 interconnect-names = "qup-core", "qup-config", 1292 "qup-memory"; 1293 power-domains = <&rpmhpd SC7180_CX>; 1294 required-opps = <&rpmhpd_opp_low_svs>; 1295 status = "disabled"; 1296 }; 1297 1298 spi8: spi@a88000 { 1299 compatible = "qcom,geni-spi"; 1300 reg = <0 0x00a88000 0 0x4000>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>; 1305 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 power-domains = <&rpmhpd SC7180_CX>; 1309 operating-points-v2 = <&qup_opp_table>; 1310 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1311 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1312 interconnect-names = "qup-core", "qup-config"; 1313 status = "disabled"; 1314 }; 1315 1316 uart8: serial@a88000 { 1317 compatible = "qcom,geni-debug-uart"; 1318 reg = <0 0x00a88000 0 0x4000>; 1319 clock-names = "se"; 1320 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_uart8_default>; 1323 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1324 power-domains = <&rpmhpd SC7180_CX>; 1325 operating-points-v2 = <&qup_opp_table>; 1326 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1327 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1328 interconnect-names = "qup-core", "qup-config"; 1329 status = "disabled"; 1330 }; 1331 1332 i2c9: i2c@a8c000 { 1333 compatible = "qcom,geni-i2c"; 1334 reg = <0 0x00a8c000 0 0x4000>; 1335 clock-names = "se"; 1336 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1337 pinctrl-names = "default"; 1338 pinctrl-0 = <&qup_i2c9_default>; 1339 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1343 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1344 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1345 interconnect-names = "qup-core", "qup-config", 1346 "qup-memory"; 1347 power-domains = <&rpmhpd SC7180_CX>; 1348 required-opps = <&rpmhpd_opp_low_svs>; 1349 status = "disabled"; 1350 }; 1351 1352 uart9: serial@a8c000 { 1353 compatible = "qcom,geni-uart"; 1354 reg = <0 0x00a8c000 0 0x4000>; 1355 clock-names = "se"; 1356 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1357 pinctrl-names = "default"; 1358 pinctrl-0 = <&qup_uart9_default>; 1359 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1360 power-domains = <&rpmhpd SC7180_CX>; 1361 operating-points-v2 = <&qup_opp_table>; 1362 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1364 interconnect-names = "qup-core", "qup-config"; 1365 status = "disabled"; 1366 }; 1367 1368 i2c10: i2c@a90000 { 1369 compatible = "qcom,geni-i2c"; 1370 reg = <0 0x00a90000 0 0x4000>; 1371 clock-names = "se"; 1372 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1373 pinctrl-names = "default"; 1374 pinctrl-0 = <&qup_i2c10_default>; 1375 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1376 #address-cells = <1>; 1377 #size-cells = <0>; 1378 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1379 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1380 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1381 interconnect-names = "qup-core", "qup-config", 1382 "qup-memory"; 1383 power-domains = <&rpmhpd SC7180_CX>; 1384 required-opps = <&rpmhpd_opp_low_svs>; 1385 status = "disabled"; 1386 }; 1387 1388 spi10: spi@a90000 { 1389 compatible = "qcom,geni-spi"; 1390 reg = <0 0x00a90000 0 0x4000>; 1391 clock-names = "se"; 1392 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1393 pinctrl-names = "default"; 1394 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>; 1395 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 power-domains = <&rpmhpd SC7180_CX>; 1399 operating-points-v2 = <&qup_opp_table>; 1400 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1401 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1402 interconnect-names = "qup-core", "qup-config"; 1403 status = "disabled"; 1404 }; 1405 1406 uart10: serial@a90000 { 1407 compatible = "qcom,geni-uart"; 1408 reg = <0 0x00a90000 0 0x4000>; 1409 clock-names = "se"; 1410 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1411 pinctrl-names = "default"; 1412 pinctrl-0 = <&qup_uart10_default>; 1413 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1414 power-domains = <&rpmhpd SC7180_CX>; 1415 operating-points-v2 = <&qup_opp_table>; 1416 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1417 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1418 interconnect-names = "qup-core", "qup-config"; 1419 status = "disabled"; 1420 }; 1421 1422 i2c11: i2c@a94000 { 1423 compatible = "qcom,geni-i2c"; 1424 reg = <0 0x00a94000 0 0x4000>; 1425 clock-names = "se"; 1426 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1427 pinctrl-names = "default"; 1428 pinctrl-0 = <&qup_i2c11_default>; 1429 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1433 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1434 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1435 interconnect-names = "qup-core", "qup-config", 1436 "qup-memory"; 1437 power-domains = <&rpmhpd SC7180_CX>; 1438 required-opps = <&rpmhpd_opp_low_svs>; 1439 status = "disabled"; 1440 }; 1441 1442 spi11: spi@a94000 { 1443 compatible = "qcom,geni-spi"; 1444 reg = <0 0x00a94000 0 0x4000>; 1445 clock-names = "se"; 1446 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>; 1449 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1450 #address-cells = <1>; 1451 #size-cells = <0>; 1452 power-domains = <&rpmhpd SC7180_CX>; 1453 operating-points-v2 = <&qup_opp_table>; 1454 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1455 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1456 interconnect-names = "qup-core", "qup-config"; 1457 status = "disabled"; 1458 }; 1459 1460 uart11: serial@a94000 { 1461 compatible = "qcom,geni-uart"; 1462 reg = <0 0x00a94000 0 0x4000>; 1463 clock-names = "se"; 1464 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1465 pinctrl-names = "default"; 1466 pinctrl-0 = <&qup_uart11_default>; 1467 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1468 power-domains = <&rpmhpd SC7180_CX>; 1469 operating-points-v2 = <&qup_opp_table>; 1470 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1471 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; 1472 interconnect-names = "qup-core", "qup-config"; 1473 status = "disabled"; 1474 }; 1475 }; 1476 1477 refgen: regulator@ff1000 { 1478 compatible = "qcom,sc7180-refgen-regulator", 1479 "qcom,sdm845-refgen-regulator"; 1480 reg = <0x0 0x00ff1000 0x0 0x60>; 1481 }; 1482 1483 config_noc: interconnect@1500000 { 1484 compatible = "qcom,sc7180-config-noc"; 1485 reg = <0 0x01500000 0 0x28000>; 1486 #interconnect-cells = <2>; 1487 qcom,bcm-voters = <&apps_bcm_voter>; 1488 }; 1489 1490 system_noc: interconnect@1620000 { 1491 compatible = "qcom,sc7180-system-noc"; 1492 reg = <0 0x01620000 0 0x17080>; 1493 #interconnect-cells = <2>; 1494 qcom,bcm-voters = <&apps_bcm_voter>; 1495 }; 1496 1497 mc_virt: interconnect@1638000 { 1498 compatible = "qcom,sc7180-mc-virt"; 1499 reg = <0 0x01638000 0 0x1000>; 1500 #interconnect-cells = <2>; 1501 qcom,bcm-voters = <&apps_bcm_voter>; 1502 }; 1503 1504 qup_virt: interconnect@1650000 { 1505 compatible = "qcom,sc7180-qup-virt"; 1506 reg = <0 0x01650000 0 0x1000>; 1507 #interconnect-cells = <2>; 1508 qcom,bcm-voters = <&apps_bcm_voter>; 1509 }; 1510 1511 aggre1_noc: interconnect@16e0000 { 1512 compatible = "qcom,sc7180-aggre1-noc"; 1513 reg = <0 0x016e0000 0 0x15080>; 1514 #interconnect-cells = <2>; 1515 qcom,bcm-voters = <&apps_bcm_voter>; 1516 }; 1517 1518 aggre2_noc: interconnect@1705000 { 1519 compatible = "qcom,sc7180-aggre2-noc"; 1520 reg = <0 0x01705000 0 0x9000>; 1521 #interconnect-cells = <2>; 1522 qcom,bcm-voters = <&apps_bcm_voter>; 1523 }; 1524 1525 compute_noc: interconnect@170e000 { 1526 compatible = "qcom,sc7180-compute-noc"; 1527 reg = <0 0x0170e000 0 0x6000>; 1528 #interconnect-cells = <2>; 1529 qcom,bcm-voters = <&apps_bcm_voter>; 1530 }; 1531 1532 mmss_noc: interconnect@1740000 { 1533 compatible = "qcom,sc7180-mmss-noc"; 1534 reg = <0 0x01740000 0 0x1c100>; 1535 #interconnect-cells = <2>; 1536 qcom,bcm-voters = <&apps_bcm_voter>; 1537 }; 1538 1539 ufs_mem_hc: ufshc@1d84000 { 1540 compatible = "qcom,sc7180-ufshc", "qcom,ufshc", 1541 "jedec,ufs-2.0"; 1542 reg = <0 0x01d84000 0 0x3000>; 1543 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1544 phys = <&ufs_mem_phy>; 1545 phy-names = "ufsphy"; 1546 lanes-per-direction = <1>; 1547 #reset-cells = <1>; 1548 resets = <&gcc GCC_UFS_PHY_BCR>; 1549 reset-names = "rst"; 1550 1551 power-domains = <&gcc UFS_PHY_GDSC>; 1552 1553 iommus = <&apps_smmu 0xa0 0x0>; 1554 1555 clock-names = "core_clk", 1556 "bus_aggr_clk", 1557 "iface_clk", 1558 "core_clk_unipro", 1559 "ref_clk", 1560 "tx_lane0_sync_clk", 1561 "rx_lane0_sync_clk"; 1562 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1563 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1564 <&gcc GCC_UFS_PHY_AHB_CLK>, 1565 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1566 <&rpmhcc RPMH_CXO_CLK>, 1567 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1568 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; 1569 freq-table-hz = <50000000 200000000>, 1570 <0 0>, 1571 <0 0>, 1572 <37500000 150000000>, 1573 <0 0>, 1574 <0 0>, 1575 <0 0>; 1576 1577 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1578 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1579 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1580 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 1581 interconnect-names = "ufs-ddr", "cpu-ufs"; 1582 1583 qcom,ice = <&ice>; 1584 1585 status = "disabled"; 1586 }; 1587 1588 ufs_mem_phy: phy@1d87000 { 1589 compatible = "qcom,sc7180-qmp-ufs-phy"; 1590 reg = <0 0x01d87000 0 0x1000>; 1591 clocks = <&rpmhcc RPMH_CXO_CLK>, 1592 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1593 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1594 clock-names = "ref", 1595 "ref_aux", 1596 "qref"; 1597 power-domains = <&gcc UFS_PHY_GDSC>; 1598 resets = <&ufs_mem_hc 0>; 1599 reset-names = "ufsphy"; 1600 #phy-cells = <0>; 1601 status = "disabled"; 1602 }; 1603 1604 ice: crypto@1d90000 { 1605 compatible = "qcom,sc7180-inline-crypto-engine", 1606 "qcom,inline-crypto-engine"; 1607 reg = <0 0x01d90000 0 0x8000>; 1608 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1609 }; 1610 1611 ipa: ipa@1e40000 { 1612 compatible = "qcom,sc7180-ipa"; 1613 1614 iommus = <&apps_smmu 0x440 0x0>, 1615 <&apps_smmu 0x442 0x0>; 1616 reg = <0 0x01e40000 0 0x7000>, 1617 <0 0x01e47000 0 0x2000>, 1618 <0 0x01e04000 0 0x2c000>; 1619 reg-names = "ipa-reg", 1620 "ipa-shared", 1621 "gsi"; 1622 1623 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1624 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1625 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1626 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1627 interrupt-names = "ipa", 1628 "gsi", 1629 "ipa-clock-query", 1630 "ipa-setup-ready"; 1631 1632 clocks = <&rpmhcc RPMH_IPA_CLK>; 1633 clock-names = "core"; 1634 1635 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1636 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 1637 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1638 interconnect-names = "memory", 1639 "imem", 1640 "config"; 1641 1642 qcom,qmp = <&aoss_qmp>; 1643 1644 qcom,smem-states = <&ipa_smp2p_out 0>, 1645 <&ipa_smp2p_out 1>; 1646 qcom,smem-state-names = "ipa-clock-enabled-valid", 1647 "ipa-clock-enabled"; 1648 1649 status = "disabled"; 1650 }; 1651 1652 tcsr_mutex: hwlock@1f40000 { 1653 compatible = "qcom,tcsr-mutex"; 1654 reg = <0 0x01f40000 0 0x20000>; 1655 #hwlock-cells = <1>; 1656 }; 1657 1658 tcsr_regs_1: syscon@1f60000 { 1659 compatible = "qcom,sc7180-tcsr", "syscon"; 1660 reg = <0 0x01f60000 0 0x20000>; 1661 }; 1662 1663 tcsr_regs_2: syscon@1fc0000 { 1664 compatible = "qcom,sc7180-tcsr", "syscon"; 1665 reg = <0 0x01fc0000 0 0x40000>; 1666 }; 1667 1668 tlmm: pinctrl@3500000 { 1669 compatible = "qcom,sc7180-pinctrl"; 1670 reg = <0 0x03500000 0 0x300000>, 1671 <0 0x03900000 0 0x300000>, 1672 <0 0x03d00000 0 0x300000>; 1673 reg-names = "west", "north", "south"; 1674 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1675 gpio-controller; 1676 #gpio-cells = <2>; 1677 interrupt-controller; 1678 #interrupt-cells = <2>; 1679 gpio-ranges = <&tlmm 0 0 120>; 1680 wakeup-parent = <&pdc>; 1681 1682 dp_hot_plug_det: dp-hot-plug-det-state { 1683 pins = "gpio117"; 1684 function = "dp_hot"; 1685 }; 1686 1687 qspi_clk: qspi-clk-state { 1688 pins = "gpio63"; 1689 function = "qspi_clk"; 1690 }; 1691 1692 qspi_cs0: qspi-cs0-state { 1693 pins = "gpio68"; 1694 function = "qspi_cs"; 1695 }; 1696 1697 qspi_cs1: qspi-cs1-state { 1698 pins = "gpio72"; 1699 function = "qspi_cs"; 1700 }; 1701 1702 qspi_data0: qspi-data0-state { 1703 pins = "gpio64"; 1704 function = "qspi_data"; 1705 }; 1706 1707 qspi_data1: qspi-data1-state { 1708 pins = "gpio65"; 1709 function = "qspi_data"; 1710 }; 1711 1712 qspi_data23: qspi-data23-state { 1713 pins = "gpio66", "gpio67"; 1714 function = "qspi_data"; 1715 }; 1716 1717 qup_i2c0_default: qup-i2c0-default-state { 1718 pins = "gpio34", "gpio35"; 1719 function = "qup00"; 1720 }; 1721 1722 qup_i2c1_default: qup-i2c1-default-state { 1723 pins = "gpio0", "gpio1"; 1724 function = "qup01"; 1725 }; 1726 1727 qup_i2c2_default: qup-i2c2-default-state { 1728 pins = "gpio15", "gpio16"; 1729 function = "qup02_i2c"; 1730 }; 1731 1732 qup_i2c3_default: qup-i2c3-default-state { 1733 pins = "gpio38", "gpio39"; 1734 function = "qup03"; 1735 }; 1736 1737 qup_i2c4_default: qup-i2c4-default-state { 1738 pins = "gpio115", "gpio116"; 1739 function = "qup04_i2c"; 1740 }; 1741 1742 qup_i2c5_default: qup-i2c5-default-state { 1743 pins = "gpio25", "gpio26"; 1744 function = "qup05"; 1745 }; 1746 1747 qup_i2c6_default: qup-i2c6-default-state { 1748 pins = "gpio59", "gpio60"; 1749 function = "qup10"; 1750 }; 1751 1752 qup_i2c7_default: qup-i2c7-default-state { 1753 pins = "gpio6", "gpio7"; 1754 function = "qup11_i2c"; 1755 }; 1756 1757 qup_i2c8_default: qup-i2c8-default-state { 1758 pins = "gpio42", "gpio43"; 1759 function = "qup12"; 1760 }; 1761 1762 qup_i2c9_default: qup-i2c9-default-state { 1763 pins = "gpio46", "gpio47"; 1764 function = "qup13_i2c"; 1765 }; 1766 1767 qup_i2c10_default: qup-i2c10-default-state { 1768 pins = "gpio86", "gpio87"; 1769 function = "qup14"; 1770 }; 1771 1772 qup_i2c11_default: qup-i2c11-default-state { 1773 pins = "gpio53", "gpio54"; 1774 function = "qup15"; 1775 }; 1776 1777 qup_spi0_spi: qup-spi0-spi-state { 1778 pins = "gpio34", "gpio35", "gpio36"; 1779 function = "qup00"; 1780 }; 1781 1782 qup_spi0_cs: qup-spi0-cs-state { 1783 pins = "gpio37"; 1784 function = "qup00"; 1785 }; 1786 1787 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 1788 pins = "gpio37"; 1789 function = "gpio"; 1790 }; 1791 1792 qup_spi1_spi: qup-spi1-spi-state { 1793 pins = "gpio0", "gpio1", "gpio2"; 1794 function = "qup01"; 1795 }; 1796 1797 qup_spi1_cs: qup-spi1-cs-state { 1798 pins = "gpio3"; 1799 function = "qup01"; 1800 }; 1801 1802 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 1803 pins = "gpio3"; 1804 function = "gpio"; 1805 }; 1806 1807 qup_spi3_spi: qup-spi3-spi-state { 1808 pins = "gpio38", "gpio39", "gpio40"; 1809 function = "qup03"; 1810 }; 1811 1812 qup_spi3_cs: qup-spi3-cs-state { 1813 pins = "gpio41"; 1814 function = "qup03"; 1815 }; 1816 1817 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 1818 pins = "gpio41"; 1819 function = "gpio"; 1820 }; 1821 1822 qup_spi5_spi: qup-spi5-spi-state { 1823 pins = "gpio25", "gpio26", "gpio27"; 1824 function = "qup05"; 1825 }; 1826 1827 qup_spi5_cs: qup-spi5-cs-state { 1828 pins = "gpio28"; 1829 function = "qup05"; 1830 }; 1831 1832 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 1833 pins = "gpio28"; 1834 function = "gpio"; 1835 }; 1836 1837 qup_spi6_spi: qup-spi6-spi-state { 1838 pins = "gpio59", "gpio60", "gpio61"; 1839 function = "qup10"; 1840 }; 1841 1842 qup_spi6_cs: qup-spi6-cs-state { 1843 pins = "gpio62"; 1844 function = "qup10"; 1845 }; 1846 1847 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1848 pins = "gpio62"; 1849 function = "gpio"; 1850 }; 1851 1852 qup_spi8_spi: qup-spi8-spi-state { 1853 pins = "gpio42", "gpio43", "gpio44"; 1854 function = "qup12"; 1855 }; 1856 1857 qup_spi8_cs: qup-spi8-cs-state { 1858 pins = "gpio45"; 1859 function = "qup12"; 1860 }; 1861 1862 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 1863 pins = "gpio45"; 1864 function = "gpio"; 1865 }; 1866 1867 qup_spi10_spi: qup-spi10-spi-state { 1868 pins = "gpio86", "gpio87", "gpio88"; 1869 function = "qup14"; 1870 }; 1871 1872 qup_spi10_cs: qup-spi10-cs-state { 1873 pins = "gpio89"; 1874 function = "qup14"; 1875 }; 1876 1877 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 1878 pins = "gpio89"; 1879 function = "gpio"; 1880 }; 1881 1882 qup_spi11_spi: qup-spi11-spi-state { 1883 pins = "gpio53", "gpio54", "gpio55"; 1884 function = "qup15"; 1885 }; 1886 1887 qup_spi11_cs: qup-spi11-cs-state { 1888 pins = "gpio56"; 1889 function = "qup15"; 1890 }; 1891 1892 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 1893 pins = "gpio56"; 1894 function = "gpio"; 1895 }; 1896 1897 qup_uart0_default: qup-uart0-default-state { 1898 qup_uart0_cts: cts-pins { 1899 pins = "gpio34"; 1900 function = "qup00"; 1901 }; 1902 1903 qup_uart0_rts: rts-pins { 1904 pins = "gpio35"; 1905 function = "qup00"; 1906 }; 1907 1908 qup_uart0_tx: tx-pins { 1909 pins = "gpio36"; 1910 function = "qup00"; 1911 }; 1912 1913 qup_uart0_rx: rx-pins { 1914 pins = "gpio37"; 1915 function = "qup00"; 1916 }; 1917 }; 1918 1919 qup_uart1_default: qup-uart1-default-state { 1920 qup_uart1_cts: cts-pins { 1921 pins = "gpio0"; 1922 function = "qup01"; 1923 }; 1924 1925 qup_uart1_rts: rts-pins { 1926 pins = "gpio1"; 1927 function = "qup01"; 1928 }; 1929 1930 qup_uart1_tx: tx-pins { 1931 pins = "gpio2"; 1932 function = "qup01"; 1933 }; 1934 1935 qup_uart1_rx: rx-pins { 1936 pins = "gpio3"; 1937 function = "qup01"; 1938 }; 1939 }; 1940 1941 qup_uart2_default: qup-uart2-default-state { 1942 qup_uart2_tx: tx-pins { 1943 pins = "gpio15"; 1944 function = "qup02_uart"; 1945 }; 1946 1947 qup_uart2_rx: rx-pins { 1948 pins = "gpio16"; 1949 function = "qup02_uart"; 1950 }; 1951 }; 1952 1953 qup_uart3_default: qup-uart3-default-state { 1954 qup_uart3_cts: cts-pins { 1955 pins = "gpio38"; 1956 function = "qup03"; 1957 }; 1958 1959 qup_uart3_rts: rts-pins { 1960 pins = "gpio39"; 1961 function = "qup03"; 1962 }; 1963 1964 qup_uart3_tx: tx-pins { 1965 pins = "gpio40"; 1966 function = "qup03"; 1967 }; 1968 1969 qup_uart3_rx: rx-pins { 1970 pins = "gpio41"; 1971 function = "qup03"; 1972 }; 1973 }; 1974 1975 qup_uart4_default: qup-uart4-default-state { 1976 qup_uart4_tx: tx-pins { 1977 pins = "gpio115"; 1978 function = "qup04_uart"; 1979 }; 1980 1981 qup_uart4_rx: rx-pins { 1982 pins = "gpio116"; 1983 function = "qup04_uart"; 1984 }; 1985 }; 1986 1987 qup_uart5_default: qup-uart5-default-state { 1988 qup_uart5_cts: cts-pins { 1989 pins = "gpio25"; 1990 function = "qup05"; 1991 }; 1992 1993 qup_uart5_rts: rts-pins { 1994 pins = "gpio26"; 1995 function = "qup05"; 1996 }; 1997 1998 qup_uart5_tx: tx-pins { 1999 pins = "gpio27"; 2000 function = "qup05"; 2001 }; 2002 2003 qup_uart5_rx: rx-pins { 2004 pins = "gpio28"; 2005 function = "qup05"; 2006 }; 2007 }; 2008 2009 qup_uart6_default: qup-uart6-default-state { 2010 qup_uart6_cts: cts-pins { 2011 pins = "gpio59"; 2012 function = "qup10"; 2013 }; 2014 2015 qup_uart6_rts: rts-pins { 2016 pins = "gpio60"; 2017 function = "qup10"; 2018 }; 2019 2020 qup_uart6_tx: tx-pins { 2021 pins = "gpio61"; 2022 function = "qup10"; 2023 }; 2024 2025 qup_uart6_rx: rx-pins { 2026 pins = "gpio62"; 2027 function = "qup10"; 2028 }; 2029 }; 2030 2031 qup_uart7_default: qup-uart7-default-state { 2032 qup_uart7_tx: tx-pins { 2033 pins = "gpio6"; 2034 function = "qup11_uart"; 2035 }; 2036 2037 qup_uart7_rx: rx-pins { 2038 pins = "gpio7"; 2039 function = "qup11_uart"; 2040 }; 2041 }; 2042 2043 qup_uart8_default: qup-uart8-default-state { 2044 qup_uart8_tx: tx-pins { 2045 pins = "gpio44"; 2046 function = "qup12"; 2047 }; 2048 2049 qup_uart8_rx: rx-pins { 2050 pins = "gpio45"; 2051 function = "qup12"; 2052 }; 2053 }; 2054 2055 qup_uart9_default: qup-uart9-default-state { 2056 qup_uart9_tx: tx-pins { 2057 pins = "gpio46"; 2058 function = "qup13_uart"; 2059 }; 2060 2061 qup_uart9_rx: rx-pins { 2062 pins = "gpio47"; 2063 function = "qup13_uart"; 2064 }; 2065 }; 2066 2067 qup_uart10_default: qup-uart10-default-state { 2068 qup_uart10_cts: cts-pins { 2069 pins = "gpio86"; 2070 function = "qup14"; 2071 }; 2072 2073 qup_uart10_rts: rts-pins { 2074 pins = "gpio87"; 2075 function = "qup14"; 2076 }; 2077 2078 qup_uart10_tx: tx-pins { 2079 pins = "gpio88"; 2080 function = "qup14"; 2081 }; 2082 2083 qup_uart10_rx: rx-pins { 2084 pins = "gpio89"; 2085 function = "qup14"; 2086 }; 2087 }; 2088 2089 qup_uart11_default: qup-uart11-default-state { 2090 qup_uart11_cts: cts-pins { 2091 pins = "gpio53"; 2092 function = "qup15"; 2093 }; 2094 2095 qup_uart11_rts: rts-pins { 2096 pins = "gpio54"; 2097 function = "qup15"; 2098 }; 2099 2100 qup_uart11_tx: tx-pins { 2101 pins = "gpio55"; 2102 function = "qup15"; 2103 }; 2104 2105 qup_uart11_rx: rx-pins { 2106 pins = "gpio56"; 2107 function = "qup15"; 2108 }; 2109 }; 2110 2111 sec_mi2s_active: sec-mi2s-active-state { 2112 pins = "gpio49", "gpio50", "gpio51"; 2113 function = "mi2s_1"; 2114 }; 2115 2116 pri_mi2s_active: pri-mi2s-active-state { 2117 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 2118 function = "mi2s_0"; 2119 }; 2120 2121 pri_mi2s_mclk_active: pri-mi2s-mclk-active-state { 2122 pins = "gpio57"; 2123 function = "lpass_ext"; 2124 }; 2125 2126 ter_mi2s_active: ter-mi2s-active-state { 2127 pins = "gpio63", "gpio64", "gpio65", "gpio66"; 2128 function = "mi2s_2"; 2129 }; 2130 }; 2131 2132 remoteproc_mpss: remoteproc@4080000 { 2133 compatible = "qcom,sc7180-mpss-pas"; 2134 reg = <0 0x04080000 0 0x4040>; 2135 2136 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2137 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2138 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2139 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2140 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2141 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2142 interrupt-names = "wdog", "fatal", "ready", "handover", 2143 "stop-ack", "shutdown-ack"; 2144 2145 clocks = <&rpmhcc RPMH_CXO_CLK>; 2146 clock-names = "xo"; 2147 2148 power-domains = <&rpmhpd SC7180_CX>, 2149 <&rpmhpd SC7180_MX>, 2150 <&rpmhpd SC7180_MSS>; 2151 power-domain-names = "cx", "mx", "mss"; 2152 2153 memory-region = <&mpss_mem>; 2154 2155 qcom,qmp = <&aoss_qmp>; 2156 2157 qcom,smem-states = <&modem_smp2p_out 0>; 2158 qcom,smem-state-names = "stop"; 2159 2160 status = "disabled"; 2161 2162 glink-edge { 2163 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2164 label = "modem"; 2165 qcom,remote-pid = <1>; 2166 mboxes = <&apss_shared 12>; 2167 }; 2168 }; 2169 2170 gpu: gpu@5000000 { 2171 compatible = "qcom,adreno-618.0", "qcom,adreno"; 2172 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>, 2173 <0 0x05061000 0 0x800>; 2174 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc"; 2175 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2176 iommus = <&adreno_smmu 0>; 2177 operating-points-v2 = <&gpu_opp_table>; 2178 qcom,gmu = <&gmu>; 2179 2180 #cooling-cells = <2>; 2181 2182 nvmem-cells = <&gpu_speed_bin>; 2183 nvmem-cell-names = "speed_bin"; 2184 2185 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2186 interconnect-names = "gfx-mem"; 2187 2188 gpu_zap_shader: zap-shader { 2189 memory-region = <&gpu_mem>; 2190 }; 2191 2192 gpu_opp_table: opp-table { 2193 compatible = "operating-points-v2"; 2194 2195 opp-825000000 { 2196 opp-hz = /bits/ 64 <825000000>; 2197 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2198 opp-peak-kBps = <8532000>; 2199 opp-supported-hw = <0x04>; 2200 }; 2201 2202 opp-800000000 { 2203 opp-hz = /bits/ 64 <800000000>; 2204 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2205 opp-peak-kBps = <8532000>; 2206 opp-supported-hw = <0x07>; 2207 }; 2208 2209 opp-650000000 { 2210 opp-hz = /bits/ 64 <650000000>; 2211 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2212 opp-peak-kBps = <7216000>; 2213 opp-supported-hw = <0x07>; 2214 }; 2215 2216 opp-565000000 { 2217 opp-hz = /bits/ 64 <565000000>; 2218 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2219 opp-peak-kBps = <5412000>; 2220 opp-supported-hw = <0x07>; 2221 }; 2222 2223 opp-430000000 { 2224 opp-hz = /bits/ 64 <430000000>; 2225 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2226 opp-peak-kBps = <5412000>; 2227 opp-supported-hw = <0x07>; 2228 }; 2229 2230 opp-355000000 { 2231 opp-hz = /bits/ 64 <355000000>; 2232 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2233 opp-peak-kBps = <3072000>; 2234 opp-supported-hw = <0x07>; 2235 }; 2236 2237 opp-267000000 { 2238 opp-hz = /bits/ 64 <267000000>; 2239 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2240 opp-peak-kBps = <3072000>; 2241 opp-supported-hw = <0x07>; 2242 }; 2243 2244 opp-180000000 { 2245 opp-hz = /bits/ 64 <180000000>; 2246 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2247 opp-peak-kBps = <1804000>; 2248 opp-supported-hw = <0x07>; 2249 }; 2250 }; 2251 }; 2252 2253 adreno_smmu: iommu@5040000 { 2254 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 2255 reg = <0 0x05040000 0 0x10000>; 2256 #iommu-cells = <1>; 2257 #global-interrupts = <2>; 2258 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2259 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2260 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2261 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2262 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2263 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2264 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2265 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2266 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2267 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2268 2269 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2270 <&gcc GCC_GPU_CFG_AHB_CLK>; 2271 clock-names = "bus", "iface"; 2272 2273 power-domains = <&gpucc CX_GDSC>; 2274 }; 2275 2276 gmu: gmu@506a000 { 2277 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu"; 2278 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>, 2279 <0 0x0b490000 0 0x10000>; 2280 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2281 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2282 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2283 interrupt-names = "hfi", "gmu"; 2284 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2285 <&gpucc GPU_CC_CXO_CLK>, 2286 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2287 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2288 clock-names = "gmu", "cxo", "axi", "memnoc"; 2289 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>; 2290 power-domain-names = "cx", "gx"; 2291 iommus = <&adreno_smmu 5>; 2292 operating-points-v2 = <&gmu_opp_table>; 2293 2294 gmu_opp_table: opp-table { 2295 compatible = "operating-points-v2"; 2296 2297 opp-200000000 { 2298 opp-hz = /bits/ 64 <200000000>; 2299 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2300 }; 2301 }; 2302 }; 2303 2304 gpucc: clock-controller@5090000 { 2305 compatible = "qcom,sc7180-gpucc"; 2306 reg = <0 0x05090000 0 0x9000>; 2307 clocks = <&rpmhcc RPMH_CXO_CLK>, 2308 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2309 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2310 clock-names = "bi_tcxo", 2311 "gcc_gpu_gpll0_clk_src", 2312 "gcc_gpu_gpll0_div_clk_src"; 2313 #clock-cells = <1>; 2314 #reset-cells = <1>; 2315 #power-domain-cells = <1>; 2316 }; 2317 2318 dma@10a2000 { 2319 compatible = "qcom,sc7180-dcc", "qcom,dcc"; 2320 reg = <0x0 0x010a2000 0x0 0x1000>, 2321 <0x0 0x010ae000 0x0 0x2000>; 2322 status = "disabled"; 2323 }; 2324 2325 stm@6002000 { 2326 compatible = "arm,coresight-stm", "arm,primecell"; 2327 reg = <0 0x06002000 0 0x1000>, 2328 <0 0x16280000 0 0x180000>; 2329 reg-names = "stm-base", "stm-stimulus-base"; 2330 2331 clocks = <&aoss_qmp>; 2332 clock-names = "apb_pclk"; 2333 2334 out-ports { 2335 port { 2336 stm_out: endpoint { 2337 remote-endpoint = <&funnel0_in7>; 2338 }; 2339 }; 2340 }; 2341 }; 2342 2343 funnel@6041000 { 2344 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2345 reg = <0 0x06041000 0 0x1000>; 2346 2347 clocks = <&aoss_qmp>; 2348 clock-names = "apb_pclk"; 2349 2350 out-ports { 2351 port { 2352 funnel0_out: endpoint { 2353 remote-endpoint = <&merge_funnel_in0>; 2354 }; 2355 }; 2356 }; 2357 2358 in-ports { 2359 #address-cells = <1>; 2360 #size-cells = <0>; 2361 2362 port@7 { 2363 reg = <7>; 2364 funnel0_in7: endpoint { 2365 remote-endpoint = <&stm_out>; 2366 }; 2367 }; 2368 }; 2369 }; 2370 2371 funnel@6042000 { 2372 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2373 reg = <0 0x06042000 0 0x1000>; 2374 2375 clocks = <&aoss_qmp>; 2376 clock-names = "apb_pclk"; 2377 2378 out-ports { 2379 port { 2380 funnel1_out: endpoint { 2381 remote-endpoint = <&merge_funnel_in1>; 2382 }; 2383 }; 2384 }; 2385 2386 in-ports { 2387 #address-cells = <1>; 2388 #size-cells = <0>; 2389 2390 port@4 { 2391 reg = <4>; 2392 funnel1_in4: endpoint { 2393 remote-endpoint = <&apss_merge_funnel_out>; 2394 }; 2395 }; 2396 }; 2397 }; 2398 2399 funnel@6045000 { 2400 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2401 reg = <0 0x06045000 0 0x1000>; 2402 2403 clocks = <&aoss_qmp>; 2404 clock-names = "apb_pclk"; 2405 2406 out-ports { 2407 port { 2408 merge_funnel_out: endpoint { 2409 remote-endpoint = <&swao_funnel_in>; 2410 }; 2411 }; 2412 }; 2413 2414 in-ports { 2415 #address-cells = <1>; 2416 #size-cells = <0>; 2417 2418 port@0 { 2419 reg = <0>; 2420 merge_funnel_in0: endpoint { 2421 remote-endpoint = <&funnel0_out>; 2422 }; 2423 }; 2424 2425 port@1 { 2426 reg = <1>; 2427 merge_funnel_in1: endpoint { 2428 remote-endpoint = <&funnel1_out>; 2429 }; 2430 }; 2431 }; 2432 }; 2433 2434 replicator@6046000 { 2435 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2436 reg = <0 0x06046000 0 0x1000>; 2437 2438 clocks = <&aoss_qmp>; 2439 clock-names = "apb_pclk"; 2440 2441 out-ports { 2442 port { 2443 replicator_out: endpoint { 2444 remote-endpoint = <&etr_in>; 2445 }; 2446 }; 2447 }; 2448 2449 in-ports { 2450 port { 2451 replicator_in: endpoint { 2452 remote-endpoint = <&swao_replicator_out>; 2453 }; 2454 }; 2455 }; 2456 }; 2457 2458 etr@6048000 { 2459 compatible = "arm,coresight-tmc", "arm,primecell"; 2460 reg = <0 0x06048000 0 0x1000>; 2461 iommus = <&apps_smmu 0x04a0 0x20>; 2462 2463 clocks = <&aoss_qmp>; 2464 clock-names = "apb_pclk"; 2465 arm,scatter-gather; 2466 2467 in-ports { 2468 port { 2469 etr_in: endpoint { 2470 remote-endpoint = <&replicator_out>; 2471 }; 2472 }; 2473 }; 2474 }; 2475 2476 funnel@6b04000 { 2477 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2478 reg = <0 0x06b04000 0 0x1000>; 2479 2480 clocks = <&aoss_qmp>; 2481 clock-names = "apb_pclk"; 2482 2483 out-ports { 2484 port { 2485 swao_funnel_out: endpoint { 2486 remote-endpoint = <&etf_in>; 2487 }; 2488 }; 2489 }; 2490 2491 in-ports { 2492 #address-cells = <1>; 2493 #size-cells = <0>; 2494 2495 port@7 { 2496 reg = <7>; 2497 swao_funnel_in: endpoint { 2498 remote-endpoint = <&merge_funnel_out>; 2499 }; 2500 }; 2501 }; 2502 }; 2503 2504 etf@6b05000 { 2505 compatible = "arm,coresight-tmc", "arm,primecell"; 2506 reg = <0 0x06b05000 0 0x1000>; 2507 2508 clocks = <&aoss_qmp>; 2509 clock-names = "apb_pclk"; 2510 2511 out-ports { 2512 port { 2513 etf_out: endpoint { 2514 remote-endpoint = <&swao_replicator_in>; 2515 }; 2516 }; 2517 }; 2518 2519 in-ports { 2520 port { 2521 etf_in: endpoint { 2522 remote-endpoint = <&swao_funnel_out>; 2523 }; 2524 }; 2525 }; 2526 }; 2527 2528 replicator@6b06000 { 2529 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2530 reg = <0 0x06b06000 0 0x1000>; 2531 2532 clocks = <&aoss_qmp>; 2533 clock-names = "apb_pclk"; 2534 qcom,replicator-loses-context; 2535 2536 out-ports { 2537 port { 2538 swao_replicator_out: endpoint { 2539 remote-endpoint = <&replicator_in>; 2540 }; 2541 }; 2542 }; 2543 2544 in-ports { 2545 port { 2546 swao_replicator_in: endpoint { 2547 remote-endpoint = <&etf_out>; 2548 }; 2549 }; 2550 }; 2551 }; 2552 2553 etm@7040000 { 2554 compatible = "arm,coresight-etm4x", "arm,primecell"; 2555 reg = <0 0x07040000 0 0x1000>; 2556 2557 cpu = <&cpu0>; 2558 2559 clocks = <&aoss_qmp>; 2560 clock-names = "apb_pclk"; 2561 arm,coresight-loses-context-with-cpu; 2562 qcom,skip-power-up; 2563 2564 out-ports { 2565 port { 2566 etm0_out: endpoint { 2567 remote-endpoint = <&apss_funnel_in0>; 2568 }; 2569 }; 2570 }; 2571 }; 2572 2573 etm@7140000 { 2574 compatible = "arm,coresight-etm4x", "arm,primecell"; 2575 reg = <0 0x07140000 0 0x1000>; 2576 2577 cpu = <&cpu1>; 2578 2579 clocks = <&aoss_qmp>; 2580 clock-names = "apb_pclk"; 2581 arm,coresight-loses-context-with-cpu; 2582 qcom,skip-power-up; 2583 2584 out-ports { 2585 port { 2586 etm1_out: endpoint { 2587 remote-endpoint = <&apss_funnel_in1>; 2588 }; 2589 }; 2590 }; 2591 }; 2592 2593 etm@7240000 { 2594 compatible = "arm,coresight-etm4x", "arm,primecell"; 2595 reg = <0 0x07240000 0 0x1000>; 2596 2597 cpu = <&cpu2>; 2598 2599 clocks = <&aoss_qmp>; 2600 clock-names = "apb_pclk"; 2601 arm,coresight-loses-context-with-cpu; 2602 qcom,skip-power-up; 2603 2604 out-ports { 2605 port { 2606 etm2_out: endpoint { 2607 remote-endpoint = <&apss_funnel_in2>; 2608 }; 2609 }; 2610 }; 2611 }; 2612 2613 etm@7340000 { 2614 compatible = "arm,coresight-etm4x", "arm,primecell"; 2615 reg = <0 0x07340000 0 0x1000>; 2616 2617 cpu = <&cpu3>; 2618 2619 clocks = <&aoss_qmp>; 2620 clock-names = "apb_pclk"; 2621 arm,coresight-loses-context-with-cpu; 2622 qcom,skip-power-up; 2623 2624 out-ports { 2625 port { 2626 etm3_out: endpoint { 2627 remote-endpoint = <&apss_funnel_in3>; 2628 }; 2629 }; 2630 }; 2631 }; 2632 2633 etm@7440000 { 2634 compatible = "arm,coresight-etm4x", "arm,primecell"; 2635 reg = <0 0x07440000 0 0x1000>; 2636 2637 cpu = <&cpu4>; 2638 2639 clocks = <&aoss_qmp>; 2640 clock-names = "apb_pclk"; 2641 arm,coresight-loses-context-with-cpu; 2642 qcom,skip-power-up; 2643 2644 out-ports { 2645 port { 2646 etm4_out: endpoint { 2647 remote-endpoint = <&apss_funnel_in4>; 2648 }; 2649 }; 2650 }; 2651 }; 2652 2653 etm@7540000 { 2654 compatible = "arm,coresight-etm4x", "arm,primecell"; 2655 reg = <0 0x07540000 0 0x1000>; 2656 2657 cpu = <&cpu5>; 2658 2659 clocks = <&aoss_qmp>; 2660 clock-names = "apb_pclk"; 2661 arm,coresight-loses-context-with-cpu; 2662 qcom,skip-power-up; 2663 2664 out-ports { 2665 port { 2666 etm5_out: endpoint { 2667 remote-endpoint = <&apss_funnel_in5>; 2668 }; 2669 }; 2670 }; 2671 }; 2672 2673 etm@7640000 { 2674 compatible = "arm,coresight-etm4x", "arm,primecell"; 2675 reg = <0 0x07640000 0 0x1000>; 2676 2677 cpu = <&cpu6>; 2678 2679 clocks = <&aoss_qmp>; 2680 clock-names = "apb_pclk"; 2681 arm,coresight-loses-context-with-cpu; 2682 qcom,skip-power-up; 2683 2684 out-ports { 2685 port { 2686 etm6_out: endpoint { 2687 remote-endpoint = <&apss_funnel_in6>; 2688 }; 2689 }; 2690 }; 2691 }; 2692 2693 etm@7740000 { 2694 compatible = "arm,coresight-etm4x", "arm,primecell"; 2695 reg = <0 0x07740000 0 0x1000>; 2696 2697 cpu = <&cpu7>; 2698 2699 clocks = <&aoss_qmp>; 2700 clock-names = "apb_pclk"; 2701 arm,coresight-loses-context-with-cpu; 2702 qcom,skip-power-up; 2703 2704 out-ports { 2705 port { 2706 etm7_out: endpoint { 2707 remote-endpoint = <&apss_funnel_in7>; 2708 }; 2709 }; 2710 }; 2711 }; 2712 2713 funnel@7800000 { /* APSS Funnel */ 2714 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2715 reg = <0 0x07800000 0 0x1000>; 2716 2717 clocks = <&aoss_qmp>; 2718 clock-names = "apb_pclk"; 2719 2720 out-ports { 2721 port { 2722 apss_funnel_out: endpoint { 2723 remote-endpoint = <&apss_merge_funnel_in>; 2724 }; 2725 }; 2726 }; 2727 2728 in-ports { 2729 #address-cells = <1>; 2730 #size-cells = <0>; 2731 2732 port@0 { 2733 reg = <0>; 2734 apss_funnel_in0: endpoint { 2735 remote-endpoint = <&etm0_out>; 2736 }; 2737 }; 2738 2739 port@1 { 2740 reg = <1>; 2741 apss_funnel_in1: endpoint { 2742 remote-endpoint = <&etm1_out>; 2743 }; 2744 }; 2745 2746 port@2 { 2747 reg = <2>; 2748 apss_funnel_in2: endpoint { 2749 remote-endpoint = <&etm2_out>; 2750 }; 2751 }; 2752 2753 port@3 { 2754 reg = <3>; 2755 apss_funnel_in3: endpoint { 2756 remote-endpoint = <&etm3_out>; 2757 }; 2758 }; 2759 2760 port@4 { 2761 reg = <4>; 2762 apss_funnel_in4: endpoint { 2763 remote-endpoint = <&etm4_out>; 2764 }; 2765 }; 2766 2767 port@5 { 2768 reg = <5>; 2769 apss_funnel_in5: endpoint { 2770 remote-endpoint = <&etm5_out>; 2771 }; 2772 }; 2773 2774 port@6 { 2775 reg = <6>; 2776 apss_funnel_in6: endpoint { 2777 remote-endpoint = <&etm6_out>; 2778 }; 2779 }; 2780 2781 port@7 { 2782 reg = <7>; 2783 apss_funnel_in7: endpoint { 2784 remote-endpoint = <&etm7_out>; 2785 }; 2786 }; 2787 }; 2788 }; 2789 2790 funnel@7810000 { 2791 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2792 reg = <0 0x07810000 0 0x1000>; 2793 2794 clocks = <&aoss_qmp>; 2795 clock-names = "apb_pclk"; 2796 2797 out-ports { 2798 port { 2799 apss_merge_funnel_out: endpoint { 2800 remote-endpoint = <&funnel1_in4>; 2801 }; 2802 }; 2803 }; 2804 2805 in-ports { 2806 port { 2807 apss_merge_funnel_in: endpoint { 2808 remote-endpoint = <&apss_funnel_out>; 2809 }; 2810 }; 2811 }; 2812 }; 2813 2814 sdhc_2: mmc@8804000 { 2815 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5"; 2816 reg = <0 0x08804000 0 0x1000>; 2817 2818 iommus = <&apps_smmu 0x80 0>; 2819 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2820 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2821 interrupt-names = "hc_irq", "pwr_irq"; 2822 2823 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2824 <&gcc GCC_SDCC2_APPS_CLK>, 2825 <&rpmhcc RPMH_CXO_CLK>; 2826 clock-names = "iface", "core", "xo"; 2827 2828 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2829 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2830 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2831 power-domains = <&rpmhpd SC7180_CX>; 2832 operating-points-v2 = <&sdhc2_opp_table>; 2833 2834 bus-width = <4>; 2835 2836 status = "disabled"; 2837 2838 sdhc2_opp_table: opp-table { 2839 compatible = "operating-points-v2"; 2840 2841 opp-100000000 { 2842 opp-hz = /bits/ 64 <100000000>; 2843 required-opps = <&rpmhpd_opp_low_svs>; 2844 opp-peak-kBps = <1800000 600000>; 2845 opp-avg-kBps = <100000 0>; 2846 }; 2847 2848 opp-202000000 { 2849 opp-hz = /bits/ 64 <202000000>; 2850 required-opps = <&rpmhpd_opp_nom>; 2851 opp-peak-kBps = <5400000 1600000>; 2852 opp-avg-kBps = <200000 0>; 2853 }; 2854 }; 2855 }; 2856 2857 qspi: spi@88dc000 { 2858 compatible = "qcom,sc7180-qspi", "qcom,qspi-v1"; 2859 reg = <0 0x088dc000 0 0x600>; 2860 iommus = <&apps_smmu 0x20 0x0>; 2861 #address-cells = <1>; 2862 #size-cells = <0>; 2863 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 2864 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2865 <&gcc GCC_QSPI_CORE_CLK>; 2866 clock-names = "iface", "core"; 2867 interconnects = <&gem_noc MASTER_APPSS_PROC 0 2868 &config_noc SLAVE_QSPI_0 0>; 2869 interconnect-names = "qspi-config"; 2870 power-domains = <&rpmhpd SC7180_CX>; 2871 operating-points-v2 = <&qspi_opp_table>; 2872 status = "disabled"; 2873 }; 2874 2875 usb_1_hsphy: phy@88e3000 { 2876 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy"; 2877 reg = <0 0x088e3000 0 0x400>; 2878 status = "disabled"; 2879 #phy-cells = <0>; 2880 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2881 <&rpmhcc RPMH_CXO_CLK>; 2882 clock-names = "cfg_ahb", "ref"; 2883 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2884 2885 nvmem-cells = <&qusb2p_hstx_trim>; 2886 }; 2887 2888 usb_1_qmpphy: phy@88e8000 { 2889 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 2890 reg = <0 0x088e8000 0 0x3000>; 2891 status = "disabled"; 2892 2893 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2894 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2895 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2896 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, 2897 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; 2898 clock-names = "aux", 2899 "ref", 2900 "com_aux", 2901 "usb3_pipe", 2902 "cfg_ahb"; 2903 2904 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2905 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2906 reset-names = "phy", "common"; 2907 2908 #clock-cells = <1>; 2909 #phy-cells = <1>; 2910 2911 ports { 2912 #address-cells = <1>; 2913 #size-cells = <0>; 2914 2915 port@0 { 2916 reg = <0>; 2917 2918 usb_1_qmpphy_out: endpoint { }; 2919 }; 2920 2921 port@1 { 2922 reg = <1>; 2923 2924 usb_1_qmpphy_usb_ss_in: endpoint { 2925 remote-endpoint = <&usb_1_dwc3_ss>; 2926 }; 2927 }; 2928 2929 port@2 { 2930 reg = <2>; 2931 2932 usb_1_qmpphy_dp_in: endpoint { }; 2933 }; 2934 }; 2935 }; 2936 2937 pmu@90b6300 { 2938 compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon"; 2939 reg = <0 0x090b6300 0 0x600>; 2940 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 2941 2942 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2943 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 2944 operating-points-v2 = <&cpu_bwmon_opp_table>; 2945 2946 cpu_bwmon_opp_table: opp-table { 2947 compatible = "operating-points-v2"; 2948 2949 opp-0 { 2950 opp-peak-kBps = <2288000>; 2951 }; 2952 2953 opp-1 { 2954 opp-peak-kBps = <4577000>; 2955 }; 2956 2957 opp-2 { 2958 opp-peak-kBps = <7110000>; 2959 }; 2960 2961 opp-3 { 2962 opp-peak-kBps = <9155000>; 2963 }; 2964 2965 opp-4 { 2966 opp-peak-kBps = <12298000>; 2967 }; 2968 2969 opp-5 { 2970 opp-peak-kBps = <14236000>; 2971 }; 2972 }; 2973 }; 2974 2975 pmu@90cd000 { 2976 compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 2977 reg = <0 0x090cd000 0 0x1000>; 2978 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 2979 2980 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 2981 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2982 operating-points-v2 = <&llcc_bwmon_opp_table>; 2983 2984 llcc_bwmon_opp_table: opp-table { 2985 compatible = "operating-points-v2"; 2986 2987 opp-0 { 2988 opp-peak-kBps = <1144000>; 2989 }; 2990 2991 opp-1 { 2992 opp-peak-kBps = <1720000>; 2993 }; 2994 2995 opp-2 { 2996 opp-peak-kBps = <2086000>; 2997 }; 2998 2999 opp-3 { 3000 opp-peak-kBps = <2929000>; 3001 }; 3002 3003 opp-4 { 3004 opp-peak-kBps = <3879000>; 3005 }; 3006 3007 opp-5 { 3008 opp-peak-kBps = <5931000>; 3009 }; 3010 3011 opp-6 { 3012 opp-peak-kBps = <6881000>; 3013 }; 3014 3015 opp-7 { 3016 opp-peak-kBps = <8137000>; 3017 }; 3018 }; 3019 }; 3020 3021 dc_noc: interconnect@9160000 { 3022 compatible = "qcom,sc7180-dc-noc"; 3023 reg = <0 0x09160000 0 0x03200>; 3024 #interconnect-cells = <2>; 3025 qcom,bcm-voters = <&apps_bcm_voter>; 3026 }; 3027 3028 system-cache-controller@9200000 { 3029 compatible = "qcom,sc7180-llcc"; 3030 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 3031 reg-names = "llcc0_base", "llcc_broadcast_base"; 3032 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3033 }; 3034 3035 gem_noc: interconnect@9680000 { 3036 compatible = "qcom,sc7180-gem-noc"; 3037 reg = <0 0x09680000 0 0x3e200>; 3038 #interconnect-cells = <2>; 3039 qcom,bcm-voters = <&apps_bcm_voter>; 3040 }; 3041 3042 npu_noc: interconnect@9990000 { 3043 compatible = "qcom,sc7180-npu-noc"; 3044 reg = <0 0x09990000 0 0x1600>; 3045 #interconnect-cells = <2>; 3046 qcom,bcm-voters = <&apps_bcm_voter>; 3047 }; 3048 3049 usb_1: usb@a6f8800 { 3050 compatible = "qcom,sc7180-dwc3", "qcom,dwc3"; 3051 reg = <0 0x0a6f8800 0 0x400>; 3052 status = "disabled"; 3053 #address-cells = <2>; 3054 #size-cells = <2>; 3055 ranges; 3056 dma-ranges; 3057 3058 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3059 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3060 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3061 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3062 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3063 clock-names = "cfg_noc", 3064 "core", 3065 "iface", 3066 "sleep", 3067 "mock_utmi"; 3068 3069 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3070 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3071 assigned-clock-rates = <19200000>, <150000000>; 3072 3073 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3074 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3075 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 3076 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3077 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 3078 interrupt-names = "pwr_event", 3079 "hs_phy_irq", 3080 "dp_hs_phy_irq", 3081 "dm_hs_phy_irq", 3082 "ss_phy_irq"; 3083 3084 power-domains = <&gcc USB30_PRIM_GDSC>; 3085 required-opps = <&rpmhpd_opp_nom>; 3086 3087 resets = <&gcc GCC_USB30_PRIM_BCR>; 3088 3089 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>, 3090 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>; 3091 interconnect-names = "usb-ddr", "apps-usb"; 3092 3093 wakeup-source; 3094 3095 usb_1_dwc3: usb@a600000 { 3096 compatible = "snps,dwc3"; 3097 reg = <0 0x0a600000 0 0xe000>; 3098 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3099 iommus = <&apps_smmu 0x540 0>; 3100 snps,dis_u2_susphy_quirk; 3101 snps,dis_enblslpm_quirk; 3102 snps,parkmode-disable-ss-quirk; 3103 snps,dis-u1-entry-quirk; 3104 snps,dis-u2-entry-quirk; 3105 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3106 phy-names = "usb2-phy", "usb3-phy"; 3107 maximum-speed = "super-speed"; 3108 3109 ports { 3110 #address-cells = <1>; 3111 #size-cells = <0>; 3112 3113 port@0 { 3114 reg = <0>; 3115 3116 usb_1_dwc3_hs: endpoint { 3117 }; 3118 }; 3119 3120 port@1 { 3121 reg = <1>; 3122 3123 usb_1_dwc3_ss: endpoint { 3124 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 3125 }; 3126 }; 3127 }; 3128 }; 3129 }; 3130 3131 venus: video-codec@aa00000 { 3132 compatible = "qcom,sc7180-venus"; 3133 reg = <0 0x0aa00000 0 0xff000>; 3134 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3135 power-domains = <&videocc VENUS_GDSC>, 3136 <&videocc VCODEC0_GDSC>, 3137 <&rpmhpd SC7180_CX>; 3138 power-domain-names = "venus", "vcodec0", "cx"; 3139 operating-points-v2 = <&venus_opp_table>; 3140 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3141 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3142 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3143 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3144 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 3145 clock-names = "core", "iface", "bus", 3146 "vcodec0_core", "vcodec0_bus"; 3147 iommus = <&apps_smmu 0x0c00 0x60>; 3148 memory-region = <&venus_mem>; 3149 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>, 3150 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; 3151 interconnect-names = "video-mem", "cpu-cfg"; 3152 3153 venus_opp_table: opp-table { 3154 compatible = "operating-points-v2"; 3155 3156 opp-150000000 { 3157 opp-hz = /bits/ 64 <150000000>; 3158 required-opps = <&rpmhpd_opp_low_svs>; 3159 }; 3160 3161 opp-270000000 { 3162 opp-hz = /bits/ 64 <270000000>; 3163 required-opps = <&rpmhpd_opp_svs>; 3164 }; 3165 3166 opp-340000000 { 3167 opp-hz = /bits/ 64 <340000000>; 3168 required-opps = <&rpmhpd_opp_svs_l1>; 3169 }; 3170 3171 opp-434000000 { 3172 opp-hz = /bits/ 64 <434000000>; 3173 required-opps = <&rpmhpd_opp_nom>; 3174 }; 3175 3176 opp-500000097 { 3177 opp-hz = /bits/ 64 <500000097>; 3178 required-opps = <&rpmhpd_opp_turbo>; 3179 }; 3180 }; 3181 }; 3182 3183 videocc: clock-controller@ab00000 { 3184 compatible = "qcom,sc7180-videocc"; 3185 reg = <0 0x0ab00000 0 0x10000>; 3186 clocks = <&rpmhcc RPMH_CXO_CLK>; 3187 clock-names = "bi_tcxo"; 3188 #clock-cells = <1>; 3189 #reset-cells = <1>; 3190 #power-domain-cells = <1>; 3191 }; 3192 3193 camnoc_virt: interconnect@ac00000 { 3194 compatible = "qcom,sc7180-camnoc-virt"; 3195 reg = <0 0x0ac00000 0 0x1000>; 3196 #interconnect-cells = <2>; 3197 qcom,bcm-voters = <&apps_bcm_voter>; 3198 }; 3199 3200 camcc: clock-controller@ad00000 { 3201 compatible = "qcom,sc7180-camcc"; 3202 reg = <0 0x0ad00000 0 0x10000>; 3203 clocks = <&rpmhcc RPMH_CXO_CLK>, 3204 <&gcc GCC_CAMERA_AHB_CLK>, 3205 <&gcc GCC_CAMERA_XO_CLK>; 3206 clock-names = "bi_tcxo", "iface", "xo"; 3207 #clock-cells = <1>; 3208 #reset-cells = <1>; 3209 #power-domain-cells = <1>; 3210 }; 3211 3212 mdss: display-subsystem@ae00000 { 3213 compatible = "qcom,sc7180-mdss"; 3214 reg = <0 0x0ae00000 0 0x1000>; 3215 reg-names = "mdss"; 3216 3217 power-domains = <&dispcc MDSS_GDSC>; 3218 3219 clocks = <&gcc GCC_DISP_AHB_CLK>, 3220 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3221 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3222 clock-names = "iface", "ahb", "core"; 3223 3224 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3225 interrupt-controller; 3226 #interrupt-cells = <1>; 3227 3228 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 3229 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3230 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3231 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 3232 interconnect-names = "mdp0-mem", 3233 "cpu-cfg"; 3234 3235 iommus = <&apps_smmu 0x800 0x2>; 3236 3237 #address-cells = <2>; 3238 #size-cells = <2>; 3239 ranges; 3240 3241 status = "disabled"; 3242 3243 mdp: display-controller@ae01000 { 3244 compatible = "qcom,sc7180-dpu"; 3245 reg = <0 0x0ae01000 0 0x8f000>, 3246 <0 0x0aeb0000 0 0x3000>; 3247 reg-names = "mdp", "vbif"; 3248 3249 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3250 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3251 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3252 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3253 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3254 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3255 clock-names = "bus", "iface", "rot", "lut", "core", 3256 "vsync"; 3257 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3258 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3259 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3260 assigned-clock-rates = <19200000>, 3261 <19200000>, 3262 <19200000>; 3263 operating-points-v2 = <&mdp_opp_table>; 3264 power-domains = <&rpmhpd SC7180_CX>; 3265 3266 interrupt-parent = <&mdss>; 3267 interrupts = <0>; 3268 3269 ports { 3270 #address-cells = <1>; 3271 #size-cells = <0>; 3272 3273 port@0 { 3274 reg = <0>; 3275 dpu_intf1_out: endpoint { 3276 remote-endpoint = <&mdss_dsi0_in>; 3277 }; 3278 }; 3279 3280 port@2 { 3281 reg = <2>; 3282 dpu_intf0_out: endpoint { 3283 remote-endpoint = <&dp_in>; 3284 }; 3285 }; 3286 }; 3287 3288 mdp_opp_table: opp-table { 3289 compatible = "operating-points-v2"; 3290 3291 opp-200000000 { 3292 opp-hz = /bits/ 64 <200000000>; 3293 required-opps = <&rpmhpd_opp_low_svs>; 3294 }; 3295 3296 opp-300000000 { 3297 opp-hz = /bits/ 64 <300000000>; 3298 required-opps = <&rpmhpd_opp_svs>; 3299 }; 3300 3301 opp-345000000 { 3302 opp-hz = /bits/ 64 <345000000>; 3303 required-opps = <&rpmhpd_opp_svs_l1>; 3304 }; 3305 3306 opp-460000000 { 3307 opp-hz = /bits/ 64 <460000000>; 3308 required-opps = <&rpmhpd_opp_nom>; 3309 }; 3310 }; 3311 }; 3312 3313 mdss_dsi0: dsi@ae94000 { 3314 compatible = "qcom,sc7180-dsi-ctrl", 3315 "qcom,mdss-dsi-ctrl"; 3316 reg = <0 0x0ae94000 0 0x400>; 3317 reg-names = "dsi_ctrl"; 3318 3319 interrupt-parent = <&mdss>; 3320 interrupts = <4>; 3321 3322 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3323 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3324 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3325 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3326 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3327 <&gcc GCC_DISP_HF_AXI_CLK>; 3328 clock-names = "byte", 3329 "byte_intf", 3330 "pixel", 3331 "core", 3332 "iface", 3333 "bus"; 3334 3335 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3336 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3337 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3338 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3339 3340 operating-points-v2 = <&dsi_opp_table>; 3341 power-domains = <&rpmhpd SC7180_CX>; 3342 3343 phys = <&mdss_dsi0_phy>; 3344 3345 refgen-supply = <&refgen>; 3346 3347 #address-cells = <1>; 3348 #size-cells = <0>; 3349 3350 status = "disabled"; 3351 3352 ports { 3353 #address-cells = <1>; 3354 #size-cells = <0>; 3355 3356 port@0 { 3357 reg = <0>; 3358 mdss_dsi0_in: endpoint { 3359 remote-endpoint = <&dpu_intf1_out>; 3360 }; 3361 }; 3362 3363 port@1 { 3364 reg = <1>; 3365 mdss_dsi0_out: endpoint { 3366 }; 3367 }; 3368 }; 3369 3370 dsi_opp_table: opp-table { 3371 compatible = "operating-points-v2"; 3372 3373 opp-187500000 { 3374 opp-hz = /bits/ 64 <187500000>; 3375 required-opps = <&rpmhpd_opp_low_svs>; 3376 }; 3377 3378 opp-300000000 { 3379 opp-hz = /bits/ 64 <300000000>; 3380 required-opps = <&rpmhpd_opp_svs>; 3381 }; 3382 3383 opp-358000000 { 3384 opp-hz = /bits/ 64 <358000000>; 3385 required-opps = <&rpmhpd_opp_svs_l1>; 3386 }; 3387 }; 3388 }; 3389 3390 mdss_dsi0_phy: phy@ae94400 { 3391 compatible = "qcom,dsi-phy-10nm"; 3392 reg = <0 0x0ae94400 0 0x200>, 3393 <0 0x0ae94600 0 0x280>, 3394 <0 0x0ae94a00 0 0x1e0>; 3395 reg-names = "dsi_phy", 3396 "dsi_phy_lane", 3397 "dsi_pll"; 3398 3399 #clock-cells = <1>; 3400 #phy-cells = <0>; 3401 3402 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3403 <&rpmhcc RPMH_CXO_CLK>; 3404 clock-names = "iface", "ref"; 3405 3406 status = "disabled"; 3407 }; 3408 3409 mdss_dp: displayport-controller@ae90000 { 3410 compatible = "qcom,sc7180-dp"; 3411 status = "disabled"; 3412 3413 reg = <0 0x0ae90000 0 0x200>, 3414 <0 0x0ae90200 0 0x200>, 3415 <0 0x0ae90400 0 0xc00>, 3416 <0 0x0ae91000 0 0x400>, 3417 <0 0x0ae91400 0 0x400>; 3418 3419 interrupt-parent = <&mdss>; 3420 interrupts = <12>; 3421 3422 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3423 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3424 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3425 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3426 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3427 clock-names = "core_iface", "core_aux", "ctrl_link", 3428 "ctrl_link_iface", "stream_pixel"; 3429 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3430 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3431 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3432 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3433 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3434 phy-names = "dp"; 3435 3436 operating-points-v2 = <&dp_opp_table>; 3437 power-domains = <&rpmhpd SC7180_CX>; 3438 3439 #sound-dai-cells = <0>; 3440 3441 ports { 3442 #address-cells = <1>; 3443 #size-cells = <0>; 3444 3445 port@0 { 3446 reg = <0>; 3447 3448 dp_in: endpoint { 3449 remote-endpoint = <&dpu_intf0_out>; 3450 }; 3451 }; 3452 3453 port@1 { 3454 reg = <1>; 3455 3456 mdss_dp_out: endpoint { }; 3457 }; 3458 }; 3459 3460 dp_opp_table: opp-table { 3461 compatible = "operating-points-v2"; 3462 3463 opp-160000000 { 3464 opp-hz = /bits/ 64 <160000000>; 3465 required-opps = <&rpmhpd_opp_low_svs>; 3466 }; 3467 3468 opp-270000000 { 3469 opp-hz = /bits/ 64 <270000000>; 3470 required-opps = <&rpmhpd_opp_svs>; 3471 }; 3472 3473 opp-540000000 { 3474 opp-hz = /bits/ 64 <540000000>; 3475 required-opps = <&rpmhpd_opp_svs_l1>; 3476 }; 3477 3478 opp-810000000 { 3479 opp-hz = /bits/ 64 <810000000>; 3480 required-opps = <&rpmhpd_opp_nom>; 3481 }; 3482 }; 3483 }; 3484 }; 3485 3486 dispcc: clock-controller@af00000 { 3487 compatible = "qcom,sc7180-dispcc"; 3488 reg = <0 0x0af00000 0 0x200000>; 3489 clocks = <&rpmhcc RPMH_CXO_CLK>, 3490 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3491 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3492 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3493 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3494 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3495 clock-names = "bi_tcxo", 3496 "gcc_disp_gpll0_clk_src", 3497 "dsi0_phy_pll_out_byteclk", 3498 "dsi0_phy_pll_out_dsiclk", 3499 "dp_phy_pll_link_clk", 3500 "dp_phy_pll_vco_div_clk"; 3501 #clock-cells = <1>; 3502 #reset-cells = <1>; 3503 #power-domain-cells = <1>; 3504 }; 3505 3506 pdc: interrupt-controller@b220000 { 3507 compatible = "qcom,sc7180-pdc", "qcom,pdc"; 3508 reg = <0 0x0b220000 0 0x30000>; 3509 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3510 #interrupt-cells = <2>; 3511 interrupt-parent = <&intc>; 3512 interrupt-controller; 3513 }; 3514 3515 pdc_reset: reset-controller@b2e0000 { 3516 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global"; 3517 reg = <0 0x0b2e0000 0 0x20000>; 3518 #reset-cells = <1>; 3519 }; 3520 3521 tsens0: thermal-sensor@c263000 { 3522 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3523 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3524 <0 0x0c222000 0 0x1ff>; /* SROT */ 3525 #qcom,sensors = <15>; 3526 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3527 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3528 interrupt-names = "uplow","critical"; 3529 #thermal-sensor-cells = <1>; 3530 }; 3531 3532 tsens1: thermal-sensor@c265000 { 3533 compatible = "qcom,sc7180-tsens","qcom,tsens-v2"; 3534 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3535 <0 0x0c223000 0 0x1ff>; /* SROT */ 3536 #qcom,sensors = <10>; 3537 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3539 interrupt-names = "uplow","critical"; 3540 #thermal-sensor-cells = <1>; 3541 }; 3542 3543 aoss_reset: reset-controller@c2a0000 { 3544 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc"; 3545 reg = <0 0x0c2a0000 0 0x31000>; 3546 #reset-cells = <1>; 3547 }; 3548 3549 aoss_qmp: power-management@c300000 { 3550 compatible = "qcom,sc7180-aoss-qmp", "qcom,aoss-qmp"; 3551 reg = <0 0x0c300000 0 0x400>; 3552 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3553 mboxes = <&apss_shared 0>; 3554 3555 #clock-cells = <0>; 3556 }; 3557 3558 sram@c3f0000 { 3559 compatible = "qcom,rpmh-stats"; 3560 reg = <0 0x0c3f0000 0 0x400>; 3561 }; 3562 3563 spmi_bus: spmi@c440000 { 3564 compatible = "qcom,spmi-pmic-arb"; 3565 reg = <0 0x0c440000 0 0x1100>, 3566 <0 0x0c600000 0 0x2000000>, 3567 <0 0x0e600000 0 0x100000>, 3568 <0 0x0e700000 0 0xa0000>, 3569 <0 0x0c40a000 0 0x26000>; 3570 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3571 interrupt-names = "periph_irq"; 3572 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3573 qcom,ee = <0>; 3574 qcom,channel = <0>; 3575 #address-cells = <2>; 3576 #size-cells = <0>; 3577 interrupt-controller; 3578 #interrupt-cells = <4>; 3579 }; 3580 3581 sram@14680000 { 3582 compatible = "qcom,sc7180-imem", "syscon", "simple-mfd"; 3583 reg = <0 0x14680000 0 0x2e000>; 3584 3585 #address-cells = <1>; 3586 #size-cells = <1>; 3587 3588 ranges = <0 0 0x14680000 0x2e000>; 3589 3590 pil-reloc@2a94c { 3591 compatible = "qcom,pil-reloc-info"; 3592 reg = <0x2a94c 0xc8>; 3593 }; 3594 }; 3595 3596 apps_smmu: iommu@15000000 { 3597 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; 3598 reg = <0 0x15000000 0 0x100000>; 3599 #iommu-cells = <2>; 3600 #global-interrupts = <1>; 3601 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3602 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3603 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3604 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3605 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3631 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3632 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3654 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3660 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3670 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3671 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3672 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3673 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3674 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3675 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3676 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3677 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3678 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3680 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3681 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 3682 dma-coherent; 3683 }; 3684 3685 intc: interrupt-controller@17a00000 { 3686 compatible = "arm,gic-v3"; 3687 #address-cells = <2>; 3688 #size-cells = <2>; 3689 ranges; 3690 #interrupt-cells = <3>; 3691 interrupt-controller; 3692 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3693 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3694 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3695 3696 msi-controller@17a40000 { 3697 compatible = "arm,gic-v3-its"; 3698 msi-controller; 3699 #msi-cells = <1>; 3700 reg = <0 0x17a40000 0 0x20000>; 3701 status = "disabled"; 3702 }; 3703 }; 3704 3705 apss_shared: mailbox@17c00000 { 3706 compatible = "qcom,sc7180-apss-shared", 3707 "qcom,sdm845-apss-shared"; 3708 reg = <0 0x17c00000 0 0x10000>; 3709 #mbox-cells = <1>; 3710 }; 3711 3712 watchdog@17c10000 { 3713 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt"; 3714 reg = <0 0x17c10000 0 0x1000>; 3715 clocks = <&sleep_clk>; 3716 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 3717 }; 3718 3719 timer@17c20000 { 3720 #address-cells = <1>; 3721 #size-cells = <1>; 3722 ranges = <0 0 0 0x20000000>; 3723 compatible = "arm,armv7-timer-mem"; 3724 reg = <0 0x17c20000 0 0x1000>; 3725 3726 frame@17c21000 { 3727 frame-number = <0>; 3728 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3730 reg = <0x17c21000 0x1000>, 3731 <0x17c22000 0x1000>; 3732 }; 3733 3734 frame@17c23000 { 3735 frame-number = <1>; 3736 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3737 reg = <0x17c23000 0x1000>; 3738 status = "disabled"; 3739 }; 3740 3741 frame@17c25000 { 3742 frame-number = <2>; 3743 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3744 reg = <0x17c25000 0x1000>; 3745 status = "disabled"; 3746 }; 3747 3748 frame@17c27000 { 3749 frame-number = <3>; 3750 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3751 reg = <0x17c27000 0x1000>; 3752 status = "disabled"; 3753 }; 3754 3755 frame@17c29000 { 3756 frame-number = <4>; 3757 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3758 reg = <0x17c29000 0x1000>; 3759 status = "disabled"; 3760 }; 3761 3762 frame@17c2b000 { 3763 frame-number = <5>; 3764 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3765 reg = <0x17c2b000 0x1000>; 3766 status = "disabled"; 3767 }; 3768 3769 frame@17c2d000 { 3770 frame-number = <6>; 3771 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3772 reg = <0x17c2d000 0x1000>; 3773 status = "disabled"; 3774 }; 3775 }; 3776 3777 apps_rsc: rsc@18200000 { 3778 compatible = "qcom,sc7180-rpmh-apps-rsc", "qcom,rpmh-rsc"; 3779 reg = <0 0x18200000 0 0x10000>, 3780 <0 0x18210000 0 0x10000>, 3781 <0 0x18220000 0 0x10000>; 3782 reg-names = "drv-0", "drv-1", "drv-2"; 3783 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3786 qcom,tcs-offset = <0xd00>; 3787 qcom,drv-id = <2>; 3788 qcom,tcs-config = <ACTIVE_TCS 2>, 3789 <SLEEP_TCS 3>, 3790 <WAKE_TCS 3>, 3791 <CONTROL_TCS 1>; 3792 power-domains = <&cluster_pd>; 3793 3794 rpmhcc: clock-controller { 3795 compatible = "qcom,sc7180-rpmh-clk"; 3796 clocks = <&xo_board>; 3797 clock-names = "xo"; 3798 #clock-cells = <1>; 3799 }; 3800 3801 rpmhpd: power-controller { 3802 compatible = "qcom,sc7180-rpmhpd"; 3803 #power-domain-cells = <1>; 3804 operating-points-v2 = <&rpmhpd_opp_table>; 3805 3806 rpmhpd_opp_table: opp-table { 3807 compatible = "operating-points-v2"; 3808 3809 rpmhpd_opp_ret: opp1 { 3810 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3811 }; 3812 3813 rpmhpd_opp_min_svs: opp2 { 3814 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3815 }; 3816 3817 rpmhpd_opp_low_svs: opp3 { 3818 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3819 }; 3820 3821 rpmhpd_opp_svs: opp4 { 3822 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3823 }; 3824 3825 rpmhpd_opp_svs_l1: opp5 { 3826 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3827 }; 3828 3829 rpmhpd_opp_svs_l2: opp6 { 3830 opp-level = <224>; 3831 }; 3832 3833 rpmhpd_opp_nom: opp7 { 3834 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3835 }; 3836 3837 rpmhpd_opp_nom_l1: opp8 { 3838 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3839 }; 3840 3841 rpmhpd_opp_nom_l2: opp9 { 3842 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3843 }; 3844 3845 rpmhpd_opp_turbo: opp10 { 3846 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3847 }; 3848 3849 rpmhpd_opp_turbo_l1: opp11 { 3850 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3851 }; 3852 }; 3853 }; 3854 3855 apps_bcm_voter: bcm-voter { 3856 compatible = "qcom,bcm-voter"; 3857 }; 3858 }; 3859 3860 osm_l3: interconnect@18321000 { 3861 compatible = "qcom,sc7180-osm-l3", "qcom,osm-l3"; 3862 reg = <0 0x18321000 0 0x1400>; 3863 3864 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3865 clock-names = "xo", "alternate"; 3866 3867 #interconnect-cells = <1>; 3868 }; 3869 3870 cpufreq_hw: cpufreq@18323000 { 3871 compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw"; 3872 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3873 reg-names = "freq-domain0", "freq-domain1"; 3874 3875 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3876 clock-names = "xo", "alternate"; 3877 3878 #freq-domain-cells = <1>; 3879 #clock-cells = <1>; 3880 }; 3881 3882 wifi: wifi@18800000 { 3883 compatible = "qcom,wcn3990-wifi"; 3884 reg = <0 0x18800000 0 0x800000>; 3885 reg-names = "membase"; 3886 iommus = <&apps_smmu 0xc0 0x1>; 3887 interrupts = 3888 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >, 3889 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >, 3890 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >, 3891 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >, 3892 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >, 3893 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >, 3894 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >, 3895 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >, 3896 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >, 3897 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >, 3898 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>, 3899 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>; 3900 memory-region = <&wlan_mem>; 3901 qcom,msa-fixed-perm; 3902 status = "disabled"; 3903 }; 3904 3905 remoteproc_adsp: remoteproc@62400000 { 3906 compatible = "qcom,sc7180-adsp-pas"; 3907 reg = <0 0x62400000 0 0x100>; 3908 3909 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3910 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3911 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3912 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3913 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3914 interrupt-names = "wdog", 3915 "fatal", 3916 "ready", 3917 "handover", 3918 "stop-ack"; 3919 3920 clocks = <&rpmhcc RPMH_CXO_CLK>; 3921 clock-names = "xo"; 3922 3923 power-domains = <&rpmhpd SC7180_LCX>, 3924 <&rpmhpd SC7180_LMX>; 3925 power-domain-names = "lcx", "lmx"; 3926 3927 qcom,qmp = <&aoss_qmp>; 3928 qcom,smem-states = <&adsp_smp2p_out 0>; 3929 qcom,smem-state-names = "stop"; 3930 3931 status = "disabled"; 3932 3933 glink-edge { 3934 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3935 label = "lpass"; 3936 qcom,remote-pid = <2>; 3937 mboxes = <&apss_shared 8>; 3938 3939 apr { 3940 compatible = "qcom,apr-v2"; 3941 qcom,glink-channels = "apr_audio_svc"; 3942 qcom,domain = <APR_DOMAIN_ADSP>; 3943 #address-cells = <1>; 3944 #size-cells = <0>; 3945 3946 service@3 { 3947 compatible = "qcom,q6core"; 3948 reg = <APR_SVC_ADSP_CORE>; 3949 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3950 }; 3951 3952 q6afe: service@4 { 3953 compatible = "qcom,q6afe"; 3954 reg = <APR_SVC_AFE>; 3955 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3956 3957 q6afedai: dais { 3958 compatible = "qcom,q6afe-dais"; 3959 #address-cells = <1>; 3960 #size-cells = <0>; 3961 #sound-dai-cells = <1>; 3962 }; 3963 3964 q6afecc: clock-controller { 3965 compatible = "qcom,q6afe-clocks"; 3966 #clock-cells = <2>; 3967 }; 3968 }; 3969 3970 q6asm: service@7 { 3971 compatible = "qcom,q6asm"; 3972 reg = <APR_SVC_ASM>; 3973 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3974 3975 q6asmdai: dais { 3976 compatible = "qcom,q6asm-dais"; 3977 #address-cells = <1>; 3978 #size-cells = <0>; 3979 #sound-dai-cells = <1>; 3980 iommus = <&apps_smmu 0x1001 0x0>; 3981 }; 3982 }; 3983 3984 q6adm: service@8 { 3985 compatible = "qcom,q6adm"; 3986 reg = <APR_SVC_ADM>; 3987 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3988 3989 q6routing: routing { 3990 compatible = "qcom,q6adm-routing"; 3991 #sound-dai-cells = <0>; 3992 }; 3993 }; 3994 }; 3995 3996 fastrpc { 3997 compatible = "qcom,fastrpc"; 3998 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3999 label = "adsp"; 4000 #address-cells = <1>; 4001 #size-cells = <0>; 4002 4003 compute-cb@3 { 4004 compatible = "qcom,fastrpc-compute-cb"; 4005 reg = <3>; 4006 iommus = <&apps_smmu 0x1003 0x0>; 4007 }; 4008 4009 compute-cb@4 { 4010 compatible = "qcom,fastrpc-compute-cb"; 4011 reg = <4>; 4012 iommus = <&apps_smmu 0x1004 0x0>; 4013 }; 4014 4015 compute-cb@5 { 4016 compatible = "qcom,fastrpc-compute-cb"; 4017 reg = <5>; 4018 iommus = <&apps_smmu 0x1005 0x0>; 4019 qcom,nsessions = <5>; 4020 }; 4021 }; 4022 }; 4023 }; 4024 4025 lpasscc: clock-controller@62d00000 { 4026 compatible = "qcom,sc7180-lpasscorecc"; 4027 reg = <0 0x62d00000 0 0x50000>, 4028 <0 0x62780000 0 0x30000>; 4029 reg-names = "lpass_core_cc", "lpass_audio_cc"; 4030 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 4031 <&rpmhcc RPMH_CXO_CLK>; 4032 clock-names = "iface", "bi_tcxo"; 4033 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 4034 #clock-cells = <1>; 4035 #power-domain-cells = <1>; 4036 4037 status = "reserved"; /* Controlled by ADSP */ 4038 }; 4039 4040 lpass_cpu: lpass@62d87000 { 4041 compatible = "qcom,sc7180-lpass-cpu"; 4042 4043 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>; 4044 reg-names = "lpass-hdmiif", "lpass-lpaif"; 4045 4046 iommus = <&apps_smmu 0x1020 0>, 4047 <&apps_smmu 0x1021 0>, 4048 <&apps_smmu 0x1032 0>; 4049 4050 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>; 4051 required-opps = <&rpmhpd_opp_nom>; 4052 4053 status = "disabled"; 4054 4055 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 4056 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>, 4057 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>, 4058 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>, 4059 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>, 4060 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>; 4061 4062 clock-names = "pcnoc-sway-clk", "audio-core", 4063 "mclk0", "pcnoc-mport-clk", 4064 "mi2s-bit-clk0", "mi2s-bit-clk1"; 4065 4066 4067 #sound-dai-cells = <1>; 4068 #address-cells = <1>; 4069 #size-cells = <0>; 4070 4071 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 4073 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi"; 4074 }; 4075 4076 lpass_hm: clock-controller@63000000 { 4077 compatible = "qcom,sc7180-lpasshm"; 4078 reg = <0 0x63000000 0 0x28>; 4079 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>, 4080 <&rpmhcc RPMH_CXO_CLK>; 4081 clock-names = "iface", "bi_tcxo"; 4082 power-domains = <&rpmhpd SC7180_CX>; 4083 4084 #clock-cells = <1>; 4085 #power-domain-cells = <1>; 4086 4087 status = "reserved"; /* Controlled by ADSP */ 4088 }; 4089 }; 4090 4091 thermal-zones { 4092 cpu0_thermal: cpu0-thermal { 4093 polling-delay-passive = <250>; 4094 4095 thermal-sensors = <&tsens0 1>; 4096 sustainable-power = <1052>; 4097 4098 trips { 4099 cpu0_alert0: trip-point0 { 4100 temperature = <90000>; 4101 hysteresis = <2000>; 4102 type = "passive"; 4103 }; 4104 4105 cpu0_alert1: trip-point1 { 4106 temperature = <95000>; 4107 hysteresis = <2000>; 4108 type = "passive"; 4109 }; 4110 4111 cpu0_crit: cpu-crit { 4112 temperature = <110000>; 4113 hysteresis = <1000>; 4114 type = "critical"; 4115 }; 4116 }; 4117 4118 cooling-maps { 4119 map0 { 4120 trip = <&cpu0_alert0>; 4121 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4122 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4123 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4124 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4125 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4126 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4127 }; 4128 map1 { 4129 trip = <&cpu0_alert1>; 4130 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4131 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4132 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4133 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4134 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4135 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4136 }; 4137 }; 4138 }; 4139 4140 cpu1_thermal: cpu1-thermal { 4141 polling-delay-passive = <250>; 4142 4143 thermal-sensors = <&tsens0 2>; 4144 sustainable-power = <1052>; 4145 4146 trips { 4147 cpu1_alert0: trip-point0 { 4148 temperature = <90000>; 4149 hysteresis = <2000>; 4150 type = "passive"; 4151 }; 4152 4153 cpu1_alert1: trip-point1 { 4154 temperature = <95000>; 4155 hysteresis = <2000>; 4156 type = "passive"; 4157 }; 4158 4159 cpu1_crit: cpu-crit { 4160 temperature = <110000>; 4161 hysteresis = <1000>; 4162 type = "critical"; 4163 }; 4164 }; 4165 4166 cooling-maps { 4167 map0 { 4168 trip = <&cpu1_alert0>; 4169 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4170 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4171 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4172 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4173 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4174 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4175 }; 4176 map1 { 4177 trip = <&cpu1_alert1>; 4178 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4179 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4180 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4181 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4182 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4183 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4184 }; 4185 }; 4186 }; 4187 4188 cpu2_thermal: cpu2-thermal { 4189 polling-delay-passive = <250>; 4190 4191 thermal-sensors = <&tsens0 3>; 4192 sustainable-power = <1052>; 4193 4194 trips { 4195 cpu2_alert0: trip-point0 { 4196 temperature = <90000>; 4197 hysteresis = <2000>; 4198 type = "passive"; 4199 }; 4200 4201 cpu2_alert1: trip-point1 { 4202 temperature = <95000>; 4203 hysteresis = <2000>; 4204 type = "passive"; 4205 }; 4206 4207 cpu2_crit: cpu-crit { 4208 temperature = <110000>; 4209 hysteresis = <1000>; 4210 type = "critical"; 4211 }; 4212 }; 4213 4214 cooling-maps { 4215 map0 { 4216 trip = <&cpu2_alert0>; 4217 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4218 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4219 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4220 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4221 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4222 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4223 }; 4224 map1 { 4225 trip = <&cpu2_alert1>; 4226 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4227 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4228 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4229 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4230 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4231 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4232 }; 4233 }; 4234 }; 4235 4236 cpu3_thermal: cpu3-thermal { 4237 polling-delay-passive = <250>; 4238 4239 thermal-sensors = <&tsens0 4>; 4240 sustainable-power = <1052>; 4241 4242 trips { 4243 cpu3_alert0: trip-point0 { 4244 temperature = <90000>; 4245 hysteresis = <2000>; 4246 type = "passive"; 4247 }; 4248 4249 cpu3_alert1: trip-point1 { 4250 temperature = <95000>; 4251 hysteresis = <2000>; 4252 type = "passive"; 4253 }; 4254 4255 cpu3_crit: cpu-crit { 4256 temperature = <110000>; 4257 hysteresis = <1000>; 4258 type = "critical"; 4259 }; 4260 }; 4261 4262 cooling-maps { 4263 map0 { 4264 trip = <&cpu3_alert0>; 4265 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4266 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4267 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4268 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4269 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4270 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4271 }; 4272 map1 { 4273 trip = <&cpu3_alert1>; 4274 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4275 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4276 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4277 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4278 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4279 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4280 }; 4281 }; 4282 }; 4283 4284 cpu4_thermal: cpu4-thermal { 4285 polling-delay-passive = <250>; 4286 4287 thermal-sensors = <&tsens0 5>; 4288 sustainable-power = <1052>; 4289 4290 trips { 4291 cpu4_alert0: trip-point0 { 4292 temperature = <90000>; 4293 hysteresis = <2000>; 4294 type = "passive"; 4295 }; 4296 4297 cpu4_alert1: trip-point1 { 4298 temperature = <95000>; 4299 hysteresis = <2000>; 4300 type = "passive"; 4301 }; 4302 4303 cpu4_crit: cpu-crit { 4304 temperature = <110000>; 4305 hysteresis = <1000>; 4306 type = "critical"; 4307 }; 4308 }; 4309 4310 cooling-maps { 4311 map0 { 4312 trip = <&cpu4_alert0>; 4313 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4314 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4315 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4316 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4317 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4318 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4319 }; 4320 map1 { 4321 trip = <&cpu4_alert1>; 4322 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4323 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4324 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4325 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4326 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4327 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4328 }; 4329 }; 4330 }; 4331 4332 cpu5_thermal: cpu5-thermal { 4333 polling-delay-passive = <250>; 4334 4335 thermal-sensors = <&tsens0 6>; 4336 sustainable-power = <1052>; 4337 4338 trips { 4339 cpu5_alert0: trip-point0 { 4340 temperature = <90000>; 4341 hysteresis = <2000>; 4342 type = "passive"; 4343 }; 4344 4345 cpu5_alert1: trip-point1 { 4346 temperature = <95000>; 4347 hysteresis = <2000>; 4348 type = "passive"; 4349 }; 4350 4351 cpu5_crit: cpu-crit { 4352 temperature = <110000>; 4353 hysteresis = <1000>; 4354 type = "critical"; 4355 }; 4356 }; 4357 4358 cooling-maps { 4359 map0 { 4360 trip = <&cpu5_alert0>; 4361 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4362 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4363 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4364 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4365 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4366 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4367 }; 4368 map1 { 4369 trip = <&cpu5_alert1>; 4370 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4371 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4372 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4373 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4374 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4375 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4376 }; 4377 }; 4378 }; 4379 4380 cpu6_thermal: cpu6-thermal { 4381 polling-delay-passive = <250>; 4382 4383 thermal-sensors = <&tsens0 9>; 4384 sustainable-power = <1425>; 4385 4386 trips { 4387 cpu6_alert0: trip-point0 { 4388 temperature = <90000>; 4389 hysteresis = <2000>; 4390 type = "passive"; 4391 }; 4392 4393 cpu6_alert1: trip-point1 { 4394 temperature = <95000>; 4395 hysteresis = <2000>; 4396 type = "passive"; 4397 }; 4398 4399 cpu6_crit: cpu-crit { 4400 temperature = <110000>; 4401 hysteresis = <1000>; 4402 type = "critical"; 4403 }; 4404 }; 4405 4406 cooling-maps { 4407 map0 { 4408 trip = <&cpu6_alert0>; 4409 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4410 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4411 }; 4412 map1 { 4413 trip = <&cpu6_alert1>; 4414 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4415 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4416 }; 4417 }; 4418 }; 4419 4420 cpu7_thermal: cpu7-thermal { 4421 polling-delay-passive = <250>; 4422 4423 thermal-sensors = <&tsens0 10>; 4424 sustainable-power = <1425>; 4425 4426 trips { 4427 cpu7_alert0: trip-point0 { 4428 temperature = <90000>; 4429 hysteresis = <2000>; 4430 type = "passive"; 4431 }; 4432 4433 cpu7_alert1: trip-point1 { 4434 temperature = <95000>; 4435 hysteresis = <2000>; 4436 type = "passive"; 4437 }; 4438 4439 cpu7_crit: cpu-crit { 4440 temperature = <110000>; 4441 hysteresis = <1000>; 4442 type = "critical"; 4443 }; 4444 }; 4445 4446 cooling-maps { 4447 map0 { 4448 trip = <&cpu7_alert0>; 4449 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4450 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4451 }; 4452 map1 { 4453 trip = <&cpu7_alert1>; 4454 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4455 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4456 }; 4457 }; 4458 }; 4459 4460 cpu8_thermal: cpu8-thermal { 4461 polling-delay-passive = <250>; 4462 4463 thermal-sensors = <&tsens0 11>; 4464 sustainable-power = <1425>; 4465 4466 trips { 4467 cpu8_alert0: trip-point0 { 4468 temperature = <90000>; 4469 hysteresis = <2000>; 4470 type = "passive"; 4471 }; 4472 4473 cpu8_alert1: trip-point1 { 4474 temperature = <95000>; 4475 hysteresis = <2000>; 4476 type = "passive"; 4477 }; 4478 4479 cpu8_crit: cpu-crit { 4480 temperature = <110000>; 4481 hysteresis = <1000>; 4482 type = "critical"; 4483 }; 4484 }; 4485 4486 cooling-maps { 4487 map0 { 4488 trip = <&cpu8_alert0>; 4489 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4490 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4491 }; 4492 map1 { 4493 trip = <&cpu8_alert1>; 4494 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4495 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4496 }; 4497 }; 4498 }; 4499 4500 cpu9_thermal: cpu9-thermal { 4501 polling-delay-passive = <250>; 4502 4503 thermal-sensors = <&tsens0 12>; 4504 sustainable-power = <1425>; 4505 4506 trips { 4507 cpu9_alert0: trip-point0 { 4508 temperature = <90000>; 4509 hysteresis = <2000>; 4510 type = "passive"; 4511 }; 4512 4513 cpu9_alert1: trip-point1 { 4514 temperature = <95000>; 4515 hysteresis = <2000>; 4516 type = "passive"; 4517 }; 4518 4519 cpu9_crit: cpu-crit { 4520 temperature = <110000>; 4521 hysteresis = <1000>; 4522 type = "critical"; 4523 }; 4524 }; 4525 4526 cooling-maps { 4527 map0 { 4528 trip = <&cpu9_alert0>; 4529 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4530 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4531 }; 4532 map1 { 4533 trip = <&cpu9_alert1>; 4534 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4535 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4536 }; 4537 }; 4538 }; 4539 4540 aoss0-thermal { 4541 polling-delay-passive = <250>; 4542 4543 thermal-sensors = <&tsens0 0>; 4544 4545 trips { 4546 aoss0_alert0: trip-point0 { 4547 temperature = <90000>; 4548 hysteresis = <2000>; 4549 type = "hot"; 4550 }; 4551 4552 aoss0_crit: aoss0-crit { 4553 temperature = <110000>; 4554 hysteresis = <2000>; 4555 type = "critical"; 4556 }; 4557 }; 4558 }; 4559 4560 cpuss0-thermal { 4561 polling-delay-passive = <250>; 4562 4563 thermal-sensors = <&tsens0 7>; 4564 4565 trips { 4566 cpuss0_alert0: trip-point0 { 4567 temperature = <90000>; 4568 hysteresis = <2000>; 4569 type = "hot"; 4570 }; 4571 cpuss0_crit: cluster0-crit { 4572 temperature = <110000>; 4573 hysteresis = <2000>; 4574 type = "critical"; 4575 }; 4576 }; 4577 }; 4578 4579 cpuss1-thermal { 4580 polling-delay-passive = <250>; 4581 4582 thermal-sensors = <&tsens0 8>; 4583 4584 trips { 4585 cpuss1_alert0: trip-point0 { 4586 temperature = <90000>; 4587 hysteresis = <2000>; 4588 type = "hot"; 4589 }; 4590 cpuss1_crit: cluster0-crit { 4591 temperature = <110000>; 4592 hysteresis = <2000>; 4593 type = "critical"; 4594 }; 4595 }; 4596 }; 4597 4598 gpuss0-thermal { 4599 polling-delay-passive = <250>; 4600 4601 thermal-sensors = <&tsens0 13>; 4602 4603 trips { 4604 gpuss0_alert0: trip-point0 { 4605 temperature = <95000>; 4606 hysteresis = <2000>; 4607 type = "passive"; 4608 }; 4609 4610 gpuss0_crit: gpuss0-crit { 4611 temperature = <110000>; 4612 hysteresis = <2000>; 4613 type = "critical"; 4614 }; 4615 }; 4616 4617 cooling-maps { 4618 map0 { 4619 trip = <&gpuss0_alert0>; 4620 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4621 }; 4622 }; 4623 }; 4624 4625 gpuss1-thermal { 4626 polling-delay-passive = <250>; 4627 4628 thermal-sensors = <&tsens0 14>; 4629 4630 trips { 4631 gpuss1_alert0: trip-point0 { 4632 temperature = <95000>; 4633 hysteresis = <2000>; 4634 type = "passive"; 4635 }; 4636 4637 gpuss1_crit: gpuss1-crit { 4638 temperature = <110000>; 4639 hysteresis = <2000>; 4640 type = "critical"; 4641 }; 4642 }; 4643 4644 cooling-maps { 4645 map0 { 4646 trip = <&gpuss1_alert0>; 4647 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4648 }; 4649 }; 4650 }; 4651 4652 aoss1-thermal { 4653 polling-delay-passive = <250>; 4654 4655 thermal-sensors = <&tsens1 0>; 4656 4657 trips { 4658 aoss1_alert0: trip-point0 { 4659 temperature = <90000>; 4660 hysteresis = <2000>; 4661 type = "hot"; 4662 }; 4663 4664 aoss1_crit: aoss1-crit { 4665 temperature = <110000>; 4666 hysteresis = <2000>; 4667 type = "critical"; 4668 }; 4669 }; 4670 }; 4671 4672 cwlan-thermal { 4673 polling-delay-passive = <250>; 4674 4675 thermal-sensors = <&tsens1 1>; 4676 4677 trips { 4678 cwlan_alert0: trip-point0 { 4679 temperature = <90000>; 4680 hysteresis = <2000>; 4681 type = "hot"; 4682 }; 4683 4684 cwlan_crit: cwlan-crit { 4685 temperature = <110000>; 4686 hysteresis = <2000>; 4687 type = "critical"; 4688 }; 4689 }; 4690 }; 4691 4692 audio-thermal { 4693 polling-delay-passive = <250>; 4694 4695 thermal-sensors = <&tsens1 2>; 4696 4697 trips { 4698 audio_alert0: trip-point0 { 4699 temperature = <90000>; 4700 hysteresis = <2000>; 4701 type = "hot"; 4702 }; 4703 4704 audio_crit: audio-crit { 4705 temperature = <110000>; 4706 hysteresis = <2000>; 4707 type = "critical"; 4708 }; 4709 }; 4710 }; 4711 4712 ddr-thermal { 4713 polling-delay-passive = <250>; 4714 4715 thermal-sensors = <&tsens1 3>; 4716 4717 trips { 4718 ddr_alert0: trip-point0 { 4719 temperature = <90000>; 4720 hysteresis = <2000>; 4721 type = "hot"; 4722 }; 4723 4724 ddr_crit: ddr-crit { 4725 temperature = <110000>; 4726 hysteresis = <2000>; 4727 type = "critical"; 4728 }; 4729 }; 4730 }; 4731 4732 q6-hvx-thermal { 4733 polling-delay-passive = <250>; 4734 4735 thermal-sensors = <&tsens1 4>; 4736 4737 trips { 4738 q6_hvx_alert0: trip-point0 { 4739 temperature = <90000>; 4740 hysteresis = <2000>; 4741 type = "hot"; 4742 }; 4743 4744 q6_hvx_crit: q6-hvx-crit { 4745 temperature = <110000>; 4746 hysteresis = <2000>; 4747 type = "critical"; 4748 }; 4749 }; 4750 }; 4751 4752 camera-thermal { 4753 polling-delay-passive = <250>; 4754 4755 thermal-sensors = <&tsens1 5>; 4756 4757 trips { 4758 camera_alert0: trip-point0 { 4759 temperature = <90000>; 4760 hysteresis = <2000>; 4761 type = "hot"; 4762 }; 4763 4764 camera_crit: camera-crit { 4765 temperature = <110000>; 4766 hysteresis = <2000>; 4767 type = "critical"; 4768 }; 4769 }; 4770 }; 4771 4772 mdm-core-thermal { 4773 polling-delay-passive = <250>; 4774 4775 thermal-sensors = <&tsens1 6>; 4776 4777 trips { 4778 mdm_alert0: trip-point0 { 4779 temperature = <90000>; 4780 hysteresis = <2000>; 4781 type = "hot"; 4782 }; 4783 4784 mdm_crit: mdm-crit { 4785 temperature = <110000>; 4786 hysteresis = <2000>; 4787 type = "critical"; 4788 }; 4789 }; 4790 }; 4791 4792 mdm-dsp-thermal { 4793 polling-delay-passive = <250>; 4794 4795 thermal-sensors = <&tsens1 7>; 4796 4797 trips { 4798 mdm_dsp_alert0: trip-point0 { 4799 temperature = <90000>; 4800 hysteresis = <2000>; 4801 type = "hot"; 4802 }; 4803 4804 mdm_dsp_crit: mdm-dsp-crit { 4805 temperature = <110000>; 4806 hysteresis = <2000>; 4807 type = "critical"; 4808 }; 4809 }; 4810 }; 4811 4812 npu-thermal { 4813 polling-delay-passive = <250>; 4814 4815 thermal-sensors = <&tsens1 8>; 4816 4817 trips { 4818 npu_alert0: trip-point0 { 4819 temperature = <90000>; 4820 hysteresis = <2000>; 4821 type = "hot"; 4822 }; 4823 4824 npu_crit: npu-crit { 4825 temperature = <110000>; 4826 hysteresis = <2000>; 4827 type = "critical"; 4828 }; 4829 }; 4830 }; 4831 4832 video-thermal { 4833 polling-delay-passive = <250>; 4834 4835 thermal-sensors = <&tsens1 9>; 4836 4837 trips { 4838 video_alert0: trip-point0 { 4839 temperature = <90000>; 4840 hysteresis = <2000>; 4841 type = "hot"; 4842 }; 4843 4844 video_crit: video-crit { 4845 temperature = <110000>; 4846 hysteresis = <2000>; 4847 type = "critical"; 4848 }; 4849 }; 4850 }; 4851 }; 4852 4853 timer { 4854 compatible = "arm,armv8-timer"; 4855 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4856 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4857 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4858 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4859 }; 4860}; 4861