1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Linaro Limited 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#include <dt-bindings/interconnect/qcom,icc.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 11#include <dt-bindings/clock/qcom,sa8775p-gcc.h> 12#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/firmware/qcom,scm.h> 17#include <dt-bindings/power/qcom,rpmhpd.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 clocks { 28 xo_board_clk: xo-board-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,kryo"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 power-domains = <&cpu_pd0>; 49 power-domain-names = "psci"; 50 qcom,freq-domain = <&cpufreq_hw 0>; 51 next-level-cache = <&l2_0>; 52 capacity-dmips-mhz = <1024>; 53 dynamic-power-coefficient = <100>; 54 l2_0: l2-cache { 55 compatible = "cache"; 56 cache-level = <2>; 57 cache-unified; 58 next-level-cache = <&l3_0>; 59 l3_0: l3-cache { 60 compatible = "cache"; 61 cache-level = <3>; 62 cache-unified; 63 }; 64 }; 65 }; 66 67 cpu1: cpu@100 { 68 device_type = "cpu"; 69 compatible = "qcom,kryo"; 70 reg = <0x0 0x100>; 71 enable-method = "psci"; 72 power-domains = <&cpu_pd1>; 73 power-domain-names = "psci"; 74 qcom,freq-domain = <&cpufreq_hw 0>; 75 next-level-cache = <&l2_1>; 76 capacity-dmips-mhz = <1024>; 77 dynamic-power-coefficient = <100>; 78 l2_1: l2-cache { 79 compatible = "cache"; 80 cache-level = <2>; 81 cache-unified; 82 next-level-cache = <&l3_0>; 83 }; 84 }; 85 86 cpu2: cpu@200 { 87 device_type = "cpu"; 88 compatible = "qcom,kryo"; 89 reg = <0x0 0x200>; 90 enable-method = "psci"; 91 power-domains = <&cpu_pd2>; 92 power-domain-names = "psci"; 93 qcom,freq-domain = <&cpufreq_hw 0>; 94 next-level-cache = <&l2_2>; 95 capacity-dmips-mhz = <1024>; 96 dynamic-power-coefficient = <100>; 97 l2_2: l2-cache { 98 compatible = "cache"; 99 cache-level = <2>; 100 cache-unified; 101 next-level-cache = <&l3_0>; 102 }; 103 }; 104 105 cpu3: cpu@300 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo"; 108 reg = <0x0 0x300>; 109 enable-method = "psci"; 110 power-domains = <&cpu_pd3>; 111 power-domain-names = "psci"; 112 qcom,freq-domain = <&cpufreq_hw 0>; 113 next-level-cache = <&l2_3>; 114 capacity-dmips-mhz = <1024>; 115 dynamic-power-coefficient = <100>; 116 l2_3: l2-cache { 117 compatible = "cache"; 118 cache-level = <2>; 119 cache-unified; 120 next-level-cache = <&l3_0>; 121 }; 122 }; 123 124 cpu4: cpu@10000 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo"; 127 reg = <0x0 0x10000>; 128 enable-method = "psci"; 129 power-domains = <&cpu_pd4>; 130 power-domain-names = "psci"; 131 qcom,freq-domain = <&cpufreq_hw 1>; 132 next-level-cache = <&l2_4>; 133 capacity-dmips-mhz = <1024>; 134 dynamic-power-coefficient = <100>; 135 l2_4: l2-cache { 136 compatible = "cache"; 137 cache-level = <2>; 138 cache-unified; 139 next-level-cache = <&l3_1>; 140 l3_1: l3-cache { 141 compatible = "cache"; 142 cache-level = <3>; 143 cache-unified; 144 }; 145 146 }; 147 }; 148 149 cpu5: cpu@10100 { 150 device_type = "cpu"; 151 compatible = "qcom,kryo"; 152 reg = <0x0 0x10100>; 153 enable-method = "psci"; 154 power-domains = <&cpu_pd5>; 155 power-domain-names = "psci"; 156 qcom,freq-domain = <&cpufreq_hw 1>; 157 next-level-cache = <&l2_5>; 158 capacity-dmips-mhz = <1024>; 159 dynamic-power-coefficient = <100>; 160 l2_5: l2-cache { 161 compatible = "cache"; 162 cache-level = <2>; 163 cache-unified; 164 next-level-cache = <&l3_1>; 165 }; 166 }; 167 168 cpu6: cpu@10200 { 169 device_type = "cpu"; 170 compatible = "qcom,kryo"; 171 reg = <0x0 0x10200>; 172 enable-method = "psci"; 173 power-domains = <&cpu_pd6>; 174 power-domain-names = "psci"; 175 qcom,freq-domain = <&cpufreq_hw 1>; 176 next-level-cache = <&l2_6>; 177 capacity-dmips-mhz = <1024>; 178 dynamic-power-coefficient = <100>; 179 l2_6: l2-cache { 180 compatible = "cache"; 181 cache-level = <2>; 182 cache-unified; 183 next-level-cache = <&l3_1>; 184 }; 185 }; 186 187 cpu7: cpu@10300 { 188 device_type = "cpu"; 189 compatible = "qcom,kryo"; 190 reg = <0x0 0x10300>; 191 enable-method = "psci"; 192 power-domains = <&cpu_pd7>; 193 power-domain-names = "psci"; 194 qcom,freq-domain = <&cpufreq_hw 1>; 195 next-level-cache = <&l2_7>; 196 capacity-dmips-mhz = <1024>; 197 dynamic-power-coefficient = <100>; 198 l2_7: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&l3_1>; 203 }; 204 }; 205 206 cpu-map { 207 cluster0 { 208 core0 { 209 cpu = <&cpu0>; 210 }; 211 212 core1 { 213 cpu = <&cpu1>; 214 }; 215 216 core2 { 217 cpu = <&cpu2>; 218 }; 219 220 core3 { 221 cpu = <&cpu3>; 222 }; 223 }; 224 225 cluster1 { 226 core0 { 227 cpu = <&cpu4>; 228 }; 229 230 core1 { 231 cpu = <&cpu5>; 232 }; 233 234 core2 { 235 cpu = <&cpu6>; 236 }; 237 238 core3 { 239 cpu = <&cpu7>; 240 }; 241 }; 242 }; 243 244 idle-states { 245 entry-method = "psci"; 246 247 gold_cpu_sleep_0: cpu-sleep-0 { 248 compatible = "arm,idle-state"; 249 idle-state-name = "gold-power-collapse"; 250 arm,psci-suspend-param = <0x40000003>; 251 entry-latency-us = <549>; 252 exit-latency-us = <901>; 253 min-residency-us = <1774>; 254 local-timer-stop; 255 }; 256 257 gold_rail_cpu_sleep_0: cpu-sleep-1 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "gold-rail-power-collapse"; 260 arm,psci-suspend-param = <0x40000004>; 261 entry-latency-us = <702>; 262 exit-latency-us = <1061>; 263 min-residency-us = <4488>; 264 local-timer-stop; 265 }; 266 }; 267 268 domain-idle-states { 269 cluster_sleep_gold: cluster-sleep-0 { 270 compatible = "domain-idle-state"; 271 arm,psci-suspend-param = <0x41000044>; 272 entry-latency-us = <2752>; 273 exit-latency-us = <3048>; 274 min-residency-us = <6118>; 275 }; 276 277 cluster_sleep_apss_rsc_pc: cluster-sleep-1 { 278 compatible = "domain-idle-state"; 279 arm,psci-suspend-param = <0x42000144>; 280 entry-latency-us = <3263>; 281 exit-latency-us = <6562>; 282 min-residency-us = <9987>; 283 }; 284 }; 285 }; 286 287 dummy-sink { 288 compatible = "arm,coresight-dummy-sink"; 289 290 in-ports { 291 port { 292 eud_in: endpoint { 293 remote-endpoint = 294 <&swao_rep_out1>; 295 }; 296 }; 297 }; 298 }; 299 300 firmware { 301 scm { 302 compatible = "qcom,scm-sa8775p", "qcom,scm"; 303 qcom,dload-mode = <&tcsr 0x13000>; 304 memory-region = <&tz_ffi_mem>; 305 }; 306 }; 307 308 aggre1_noc: interconnect-aggre1-noc { 309 compatible = "qcom,sa8775p-aggre1-noc"; 310 #interconnect-cells = <2>; 311 qcom,bcm-voters = <&apps_bcm_voter>; 312 }; 313 314 aggre2_noc: interconnect-aggre2-noc { 315 compatible = "qcom,sa8775p-aggre2-noc"; 316 #interconnect-cells = <2>; 317 qcom,bcm-voters = <&apps_bcm_voter>; 318 }; 319 320 clk_virt: interconnect-clk-virt { 321 compatible = "qcom,sa8775p-clk-virt"; 322 #interconnect-cells = <2>; 323 qcom,bcm-voters = <&apps_bcm_voter>; 324 }; 325 326 config_noc: interconnect-config-noc { 327 compatible = "qcom,sa8775p-config-noc"; 328 #interconnect-cells = <2>; 329 qcom,bcm-voters = <&apps_bcm_voter>; 330 }; 331 332 dc_noc: interconnect-dc-noc { 333 compatible = "qcom,sa8775p-dc-noc"; 334 #interconnect-cells = <2>; 335 qcom,bcm-voters = <&apps_bcm_voter>; 336 }; 337 338 gem_noc: interconnect-gem-noc { 339 compatible = "qcom,sa8775p-gem-noc"; 340 #interconnect-cells = <2>; 341 qcom,bcm-voters = <&apps_bcm_voter>; 342 }; 343 344 gpdsp_anoc: interconnect-gpdsp-anoc { 345 compatible = "qcom,sa8775p-gpdsp-anoc"; 346 #interconnect-cells = <2>; 347 qcom,bcm-voters = <&apps_bcm_voter>; 348 }; 349 350 lpass_ag_noc: interconnect-lpass-ag-noc { 351 compatible = "qcom,sa8775p-lpass-ag-noc"; 352 #interconnect-cells = <2>; 353 qcom,bcm-voters = <&apps_bcm_voter>; 354 }; 355 356 mc_virt: interconnect-mc-virt { 357 compatible = "qcom,sa8775p-mc-virt"; 358 #interconnect-cells = <2>; 359 qcom,bcm-voters = <&apps_bcm_voter>; 360 }; 361 362 mmss_noc: interconnect-mmss-noc { 363 compatible = "qcom,sa8775p-mmss-noc"; 364 #interconnect-cells = <2>; 365 qcom,bcm-voters = <&apps_bcm_voter>; 366 }; 367 368 nspa_noc: interconnect-nspa-noc { 369 compatible = "qcom,sa8775p-nspa-noc"; 370 #interconnect-cells = <2>; 371 qcom,bcm-voters = <&apps_bcm_voter>; 372 }; 373 374 nspb_noc: interconnect-nspb-noc { 375 compatible = "qcom,sa8775p-nspb-noc"; 376 #interconnect-cells = <2>; 377 qcom,bcm-voters = <&apps_bcm_voter>; 378 }; 379 380 pcie_anoc: interconnect-pcie-anoc { 381 compatible = "qcom,sa8775p-pcie-anoc"; 382 #interconnect-cells = <2>; 383 qcom,bcm-voters = <&apps_bcm_voter>; 384 }; 385 386 system_noc: interconnect-system-noc { 387 compatible = "qcom,sa8775p-system-noc"; 388 #interconnect-cells = <2>; 389 qcom,bcm-voters = <&apps_bcm_voter>; 390 }; 391 392 /* Will be updated by the bootloader. */ 393 memory@80000000 { 394 device_type = "memory"; 395 reg = <0x0 0x80000000 0x0 0x0>; 396 }; 397 398 qup_opp_table_100mhz: opp-table-qup100mhz { 399 compatible = "operating-points-v2"; 400 401 opp-100000000 { 402 opp-hz = /bits/ 64 <100000000>; 403 required-opps = <&rpmhpd_opp_svs_l1>; 404 }; 405 }; 406 407 pmu { 408 compatible = "arm,armv8-pmuv3"; 409 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 410 }; 411 412 psci { 413 compatible = "arm,psci-1.0"; 414 method = "smc"; 415 416 cpu_pd0: power-domain-cpu0 { 417 #power-domain-cells = <0>; 418 power-domains = <&cluster_0_pd>; 419 domain-idle-states = <&gold_cpu_sleep_0>, 420 <&gold_rail_cpu_sleep_0>; 421 }; 422 423 cpu_pd1: power-domain-cpu1 { 424 #power-domain-cells = <0>; 425 power-domains = <&cluster_0_pd>; 426 domain-idle-states = <&gold_cpu_sleep_0>, 427 <&gold_rail_cpu_sleep_0>; 428 }; 429 430 cpu_pd2: power-domain-cpu2 { 431 #power-domain-cells = <0>; 432 power-domains = <&cluster_0_pd>; 433 domain-idle-states = <&gold_cpu_sleep_0>, 434 <&gold_rail_cpu_sleep_0>; 435 }; 436 437 cpu_pd3: power-domain-cpu3 { 438 #power-domain-cells = <0>; 439 power-domains = <&cluster_0_pd>; 440 domain-idle-states = <&gold_cpu_sleep_0>, 441 <&gold_rail_cpu_sleep_0>; 442 }; 443 444 cpu_pd4: power-domain-cpu4 { 445 #power-domain-cells = <0>; 446 power-domains = <&cluster_1_pd>; 447 domain-idle-states = <&gold_cpu_sleep_0>, 448 <&gold_rail_cpu_sleep_0>; 449 }; 450 451 cpu_pd5: power-domain-cpu5 { 452 #power-domain-cells = <0>; 453 power-domains = <&cluster_1_pd>; 454 domain-idle-states = <&gold_cpu_sleep_0>, 455 <&gold_rail_cpu_sleep_0>; 456 }; 457 458 cpu_pd6: power-domain-cpu6 { 459 #power-domain-cells = <0>; 460 power-domains = <&cluster_1_pd>; 461 domain-idle-states = <&gold_cpu_sleep_0>, 462 <&gold_rail_cpu_sleep_0>; 463 }; 464 465 cpu_pd7: power-domain-cpu7 { 466 #power-domain-cells = <0>; 467 power-domains = <&cluster_1_pd>; 468 domain-idle-states = <&gold_cpu_sleep_0>, 469 <&gold_rail_cpu_sleep_0>; 470 }; 471 472 cluster_0_pd: power-domain-cluster0 { 473 #power-domain-cells = <0>; 474 power-domains = <&cluster_2_pd>; 475 domain-idle-states = <&cluster_sleep_gold>; 476 }; 477 478 cluster_1_pd: power-domain-cluster1 { 479 #power-domain-cells = <0>; 480 power-domains = <&cluster_2_pd>; 481 domain-idle-states = <&cluster_sleep_gold>; 482 }; 483 484 cluster_2_pd: power-domain-cluster2 { 485 #power-domain-cells = <0>; 486 domain-idle-states = <&cluster_sleep_apss_rsc_pc>; 487 }; 488 }; 489 490 reserved-memory { 491 #address-cells = <2>; 492 #size-cells = <2>; 493 ranges; 494 495 sail_ss_mem: sail-ss@80000000 { 496 reg = <0x0 0x80000000 0x0 0x10000000>; 497 no-map; 498 }; 499 500 hyp_mem: hyp@90000000 { 501 reg = <0x0 0x90000000 0x0 0x600000>; 502 no-map; 503 }; 504 505 xbl_boot_mem: xbl-boot@90600000 { 506 reg = <0x0 0x90600000 0x0 0x200000>; 507 no-map; 508 }; 509 510 aop_image_mem: aop-image@90800000 { 511 reg = <0x0 0x90800000 0x0 0x60000>; 512 no-map; 513 }; 514 515 aop_cmd_db_mem: aop-cmd-db@90860000 { 516 compatible = "qcom,cmd-db"; 517 reg = <0x0 0x90860000 0x0 0x20000>; 518 no-map; 519 }; 520 521 uefi_log: uefi-log@908b0000 { 522 reg = <0x0 0x908b0000 0x0 0x10000>; 523 no-map; 524 }; 525 526 ddr_training_checksum: ddr-training-checksum@908c0000 { 527 reg = <0x0 0x908c0000 0x0 0x1000>; 528 no-map; 529 }; 530 531 reserved_mem: reserved@908f0000 { 532 reg = <0x0 0x908f0000 0x0 0xe000>; 533 no-map; 534 }; 535 536 secdata_apss_mem: secdata-apss@908fe000 { 537 reg = <0x0 0x908fe000 0x0 0x2000>; 538 no-map; 539 }; 540 541 smem_mem: smem@90900000 { 542 compatible = "qcom,smem"; 543 reg = <0x0 0x90900000 0x0 0x200000>; 544 no-map; 545 hwlocks = <&tcsr_mutex 3>; 546 }; 547 548 tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 { 549 reg = <0x0 0x90c00000 0x0 0x100000>; 550 no-map; 551 }; 552 553 sail_mailbox_mem: sail-ss@90d00000 { 554 reg = <0x0 0x90d00000 0x0 0x100000>; 555 no-map; 556 }; 557 558 sail_ota_mem: sail-ss@90e00000 { 559 reg = <0x0 0x90e00000 0x0 0x300000>; 560 no-map; 561 }; 562 563 aoss_backup_mem: aoss-backup@91b00000 { 564 reg = <0x0 0x91b00000 0x0 0x40000>; 565 no-map; 566 }; 567 568 cpucp_backup_mem: cpucp-backup@91b40000 { 569 reg = <0x0 0x91b40000 0x0 0x40000>; 570 no-map; 571 }; 572 573 tz_config_backup_mem: tz-config-backup@91b80000 { 574 reg = <0x0 0x91b80000 0x0 0x10000>; 575 no-map; 576 }; 577 578 ddr_training_data_mem: ddr-training-data@91b90000 { 579 reg = <0x0 0x91b90000 0x0 0x10000>; 580 no-map; 581 }; 582 583 cdt_data_backup_mem: cdt-data-backup@91ba0000 { 584 reg = <0x0 0x91ba0000 0x0 0x1000>; 585 no-map; 586 }; 587 588 tz_ffi_mem: tz-ffi@91c00000 { 589 compatible = "shared-dma-pool"; 590 reg = <0x0 0x91c00000 0x0 0x1400000>; 591 no-map; 592 }; 593 594 lpass_machine_learning_mem: lpass-machine-learning@93b00000 { 595 reg = <0x0 0x93b00000 0x0 0xf00000>; 596 no-map; 597 }; 598 599 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { 600 reg = <0x0 0x94a00000 0x0 0x800000>; 601 no-map; 602 }; 603 604 pil_camera_mem: pil-camera@95200000 { 605 reg = <0x0 0x95200000 0x0 0x500000>; 606 no-map; 607 }; 608 609 pil_adsp_mem: pil-adsp@95c00000 { 610 reg = <0x0 0x95c00000 0x0 0x1e00000>; 611 no-map; 612 }; 613 614 pil_gdsp0_mem: pil-gdsp0@97b00000 { 615 reg = <0x0 0x97b00000 0x0 0x1e00000>; 616 no-map; 617 }; 618 619 pil_gdsp1_mem: pil-gdsp1@99900000 { 620 reg = <0x0 0x99900000 0x0 0x1e00000>; 621 no-map; 622 }; 623 624 pil_cdsp0_mem: pil-cdsp0@9b800000 { 625 reg = <0x0 0x9b800000 0x0 0x1e00000>; 626 no-map; 627 }; 628 629 pil_gpu_mem: pil-gpu@9d600000 { 630 reg = <0x0 0x9d600000 0x0 0x2000>; 631 no-map; 632 }; 633 634 pil_cdsp1_mem: pil-cdsp1@9d700000 { 635 reg = <0x0 0x9d700000 0x0 0x1e00000>; 636 no-map; 637 }; 638 639 pil_cvp_mem: pil-cvp@9f500000 { 640 reg = <0x0 0x9f500000 0x0 0x700000>; 641 no-map; 642 }; 643 644 pil_video_mem: pil-video@9fc00000 { 645 reg = <0x0 0x9fc00000 0x0 0x700000>; 646 no-map; 647 }; 648 649 audio_mdf_mem: audio-mdf-region@ae000000 { 650 reg = <0x0 0xae000000 0x0 0x1000000>; 651 no-map; 652 }; 653 654 firmware_mem: firmware-region@b0000000 { 655 reg = <0x0 0xb0000000 0x0 0x800000>; 656 no-map; 657 }; 658 659 hyptz_reserved_mem: hyptz-reserved@beb00000 { 660 reg = <0x0 0xbeb00000 0x0 0x11500000>; 661 no-map; 662 }; 663 664 scmi_mem: scmi-region@d0000000 { 665 reg = <0x0 0xd0000000 0x0 0x40000>; 666 no-map; 667 }; 668 669 firmware_logs_mem: firmware-logs@d0040000 { 670 reg = <0x0 0xd0040000 0x0 0x10000>; 671 no-map; 672 }; 673 674 firmware_audio_mem: firmware-audio@d0050000 { 675 reg = <0x0 0xd0050000 0x0 0x4000>; 676 no-map; 677 }; 678 679 firmware_reserved_mem: firmware-reserved@d0054000 { 680 reg = <0x0 0xd0054000 0x0 0x9c000>; 681 no-map; 682 }; 683 684 firmware_quantum_test_mem: firmware-quantum-test@d00f0000 { 685 reg = <0x0 0xd00f0000 0x0 0x10000>; 686 no-map; 687 }; 688 689 tags_mem: tags@d0100000 { 690 reg = <0x0 0xd0100000 0x0 0x1200000>; 691 no-map; 692 }; 693 694 qtee_mem: qtee@d1300000 { 695 reg = <0x0 0xd1300000 0x0 0x500000>; 696 no-map; 697 }; 698 699 deepsleep_backup_mem: deepsleep-backup@d1800000 { 700 reg = <0x0 0xd1800000 0x0 0x100000>; 701 no-map; 702 }; 703 704 trusted_apps_mem: trusted-apps@d1900000 { 705 reg = <0x0 0xd1900000 0x0 0x3800000>; 706 no-map; 707 }; 708 709 tz_stat_mem: tz-stat@db100000 { 710 reg = <0x0 0xdb100000 0x0 0x100000>; 711 no-map; 712 }; 713 714 cpucp_fw_mem: cpucp-fw@db200000 { 715 reg = <0x0 0xdb200000 0x0 0x100000>; 716 no-map; 717 }; 718 }; 719 720 smp2p-adsp { 721 compatible = "qcom,smp2p"; 722 qcom,smem = <443>, <429>; 723 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 724 IPCC_MPROC_SIGNAL_SMP2P 725 IRQ_TYPE_EDGE_RISING>; 726 mboxes = <&ipcc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 727 728 qcom,local-pid = <0>; 729 qcom,remote-pid = <2>; 730 731 smp2p_adsp_out: master-kernel { 732 qcom,entry-name = "master-kernel"; 733 #qcom,smem-state-cells = <1>; 734 }; 735 736 smp2p_adsp_in: slave-kernel { 737 qcom,entry-name = "slave-kernel"; 738 interrupt-controller; 739 #interrupt-cells = <2>; 740 }; 741 }; 742 743 smp2p-cdsp0 { 744 compatible = "qcom,smp2p"; 745 qcom,smem = <94>, <432>; 746 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 747 IPCC_MPROC_SIGNAL_SMP2P 748 IRQ_TYPE_EDGE_RISING>; 749 mboxes = <&ipcc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 750 751 qcom,local-pid = <0>; 752 qcom,remote-pid = <5>; 753 754 smp2p_cdsp0_out: master-kernel { 755 qcom,entry-name = "master-kernel"; 756 #qcom,smem-state-cells = <1>; 757 }; 758 759 smp2p_cdsp0_in: slave-kernel { 760 qcom,entry-name = "slave-kernel"; 761 interrupt-controller; 762 #interrupt-cells = <2>; 763 }; 764 }; 765 766 smp2p-cdsp1 { 767 compatible = "qcom,smp2p"; 768 qcom,smem = <617>, <616>; 769 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 770 IPCC_MPROC_SIGNAL_SMP2P 771 IRQ_TYPE_EDGE_RISING>; 772 mboxes = <&ipcc IPCC_CLIENT_NSP1 IPCC_MPROC_SIGNAL_SMP2P>; 773 774 qcom,local-pid = <0>; 775 qcom,remote-pid = <12>; 776 777 smp2p_cdsp1_out: master-kernel { 778 qcom,entry-name = "master-kernel"; 779 #qcom,smem-state-cells = <1>; 780 }; 781 782 smp2p_cdsp1_in: slave-kernel { 783 qcom,entry-name = "slave-kernel"; 784 interrupt-controller; 785 #interrupt-cells = <2>; 786 }; 787 }; 788 789 smp2p-gpdsp0 { 790 compatible = "qcom,smp2p"; 791 qcom,smem = <617>, <616>; 792 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 793 IPCC_MPROC_SIGNAL_SMP2P 794 IRQ_TYPE_EDGE_RISING>; 795 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P>; 796 797 qcom,local-pid = <0>; 798 qcom,remote-pid = <17>; 799 800 smp2p_gpdsp0_out: master-kernel { 801 qcom,entry-name = "master-kernel"; 802 #qcom,smem-state-cells = <1>; 803 }; 804 805 smp2p_gpdsp0_in: slave-kernel { 806 qcom,entry-name = "slave-kernel"; 807 interrupt-controller; 808 #interrupt-cells = <2>; 809 }; 810 }; 811 812 smp2p-gpdsp1 { 813 compatible = "qcom,smp2p"; 814 qcom,smem = <617>, <616>; 815 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 816 IPCC_MPROC_SIGNAL_SMP2P 817 IRQ_TYPE_EDGE_RISING>; 818 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P>; 819 820 qcom,local-pid = <0>; 821 qcom,remote-pid = <18>; 822 823 smp2p_gpdsp1_out: master-kernel { 824 qcom,entry-name = "master-kernel"; 825 #qcom,smem-state-cells = <1>; 826 }; 827 828 smp2p_gpdsp1_in: slave-kernel { 829 qcom,entry-name = "slave-kernel"; 830 interrupt-controller; 831 #interrupt-cells = <2>; 832 }; 833 }; 834 835 soc: soc@0 { 836 compatible = "simple-bus"; 837 #address-cells = <2>; 838 #size-cells = <2>; 839 ranges = <0 0 0 0 0x10 0>; 840 841 gcc: clock-controller@100000 { 842 compatible = "qcom,sa8775p-gcc"; 843 reg = <0x0 0x00100000 0x0 0xc7018>; 844 #clock-cells = <1>; 845 #reset-cells = <1>; 846 #power-domain-cells = <1>; 847 clocks = <&rpmhcc RPMH_CXO_CLK>, 848 <&sleep_clk>, 849 <0>, 850 <0>, 851 <0>, 852 <&usb_0_qmpphy>, 853 <&usb_1_qmpphy>, 854 <0>, 855 <0>, 856 <0>, 857 <&pcie0_phy>, 858 <&pcie1_phy>, 859 <0>, 860 <0>, 861 <0>; 862 power-domains = <&rpmhpd SA8775P_CX>; 863 }; 864 865 ipcc: mailbox@408000 { 866 compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; 867 reg = <0x0 0x00408000 0x0 0x1000>; 868 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 869 interrupt-controller; 870 #interrupt-cells = <3>; 871 #mbox-cells = <2>; 872 }; 873 874 gpi_dma2: dma-controller@800000 { 875 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 876 reg = <0x0 0x00800000 0x0 0x60000>; 877 #dma-cells = <3>; 878 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 890 dma-channels = <12>; 891 dma-channel-mask = <0xfff>; 892 iommus = <&apps_smmu 0x5b6 0x0>; 893 status = "disabled"; 894 }; 895 896 qupv3_id_2: geniqup@8c0000 { 897 compatible = "qcom,geni-se-qup"; 898 reg = <0x0 0x008c0000 0x0 0x6000>; 899 ranges; 900 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 901 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 902 clock-names = "m-ahb", "s-ahb"; 903 iommus = <&apps_smmu 0x5a3 0x0>; 904 #address-cells = <2>; 905 #size-cells = <2>; 906 status = "disabled"; 907 908 i2c14: i2c@880000 { 909 compatible = "qcom,geni-i2c"; 910 reg = <0x0 0x880000 0x0 0x4000>; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 915 clock-names = "se"; 916 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 917 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 918 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 919 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 920 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 921 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 922 interconnect-names = "qup-core", 923 "qup-config", 924 "qup-memory"; 925 power-domains = <&rpmhpd SA8775P_CX>; 926 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 927 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 928 dma-names = "tx", 929 "rx"; 930 status = "disabled"; 931 }; 932 933 spi14: spi@880000 { 934 compatible = "qcom,geni-spi"; 935 reg = <0x0 0x880000 0x0 0x4000>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 939 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 940 clock-names = "se"; 941 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 942 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 943 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 944 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 945 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 946 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 947 interconnect-names = "qup-core", 948 "qup-config", 949 "qup-memory"; 950 power-domains = <&rpmhpd SA8775P_CX>; 951 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 952 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 953 dma-names = "tx", 954 "rx"; 955 status = "disabled"; 956 }; 957 958 uart14: serial@880000 { 959 compatible = "qcom,geni-uart"; 960 reg = <0x0 0x00880000 0x0 0x4000>; 961 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 963 clock-names = "se"; 964 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 965 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 966 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 967 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 968 interconnect-names = "qup-core", "qup-config"; 969 power-domains = <&rpmhpd SA8775P_CX>; 970 status = "disabled"; 971 }; 972 973 i2c15: i2c@884000 { 974 compatible = "qcom,geni-i2c"; 975 reg = <0x0 0x884000 0x0 0x4000>; 976 #address-cells = <1>; 977 #size-cells = <0>; 978 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 980 clock-names = "se"; 981 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 982 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 983 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 984 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 985 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 986 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 987 interconnect-names = "qup-core", 988 "qup-config", 989 "qup-memory"; 990 power-domains = <&rpmhpd SA8775P_CX>; 991 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 992 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 993 dma-names = "tx", 994 "rx"; 995 status = "disabled"; 996 }; 997 998 spi15: spi@884000 { 999 compatible = "qcom,geni-spi"; 1000 reg = <0x0 0x884000 0x0 0x4000>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1004 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1005 clock-names = "se"; 1006 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1007 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1008 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1009 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1010 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1011 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1012 interconnect-names = "qup-core", 1013 "qup-config", 1014 "qup-memory"; 1015 power-domains = <&rpmhpd SA8775P_CX>; 1016 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1017 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1018 dma-names = "tx", 1019 "rx"; 1020 status = "disabled"; 1021 }; 1022 1023 uart15: serial@884000 { 1024 compatible = "qcom,geni-uart"; 1025 reg = <0x0 0x00884000 0x0 0x4000>; 1026 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1028 clock-names = "se"; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1030 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1031 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1032 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1033 interconnect-names = "qup-core", "qup-config"; 1034 power-domains = <&rpmhpd SA8775P_CX>; 1035 status = "disabled"; 1036 }; 1037 1038 i2c16: i2c@888000 { 1039 compatible = "qcom,geni-i2c"; 1040 reg = <0x0 0x888000 0x0 0x4000>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1045 clock-names = "se"; 1046 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1047 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1048 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1049 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1050 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1051 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1052 interconnect-names = "qup-core", 1053 "qup-config", 1054 "qup-memory"; 1055 power-domains = <&rpmhpd SA8775P_CX>; 1056 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1057 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1058 dma-names = "tx", 1059 "rx"; 1060 status = "disabled"; 1061 }; 1062 1063 spi16: spi@888000 { 1064 compatible = "qcom,geni-spi"; 1065 reg = <0x0 0x00888000 0x0 0x4000>; 1066 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1068 clock-names = "se"; 1069 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1070 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1071 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1072 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1073 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1074 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1075 interconnect-names = "qup-core", 1076 "qup-config", 1077 "qup-memory"; 1078 power-domains = <&rpmhpd SA8775P_CX>; 1079 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1080 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1081 dma-names = "tx", 1082 "rx"; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 status = "disabled"; 1086 }; 1087 1088 uart16: serial@888000 { 1089 compatible = "qcom,geni-uart"; 1090 reg = <0x0 0x00888000 0x0 0x4000>; 1091 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1093 clock-names = "se"; 1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1095 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1096 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1097 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1098 interconnect-names = "qup-core", "qup-config"; 1099 power-domains = <&rpmhpd SA8775P_CX>; 1100 status = "disabled"; 1101 }; 1102 1103 i2c17: i2c@88c000 { 1104 compatible = "qcom,geni-i2c"; 1105 reg = <0x0 0x88c000 0x0 0x4000>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1109 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1110 clock-names = "se"; 1111 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1112 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1113 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1114 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1115 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1116 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1117 interconnect-names = "qup-core", 1118 "qup-config", 1119 "qup-memory"; 1120 power-domains = <&rpmhpd SA8775P_CX>; 1121 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1122 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1123 dma-names = "tx", 1124 "rx"; 1125 status = "disabled"; 1126 }; 1127 1128 spi17: spi@88c000 { 1129 compatible = "qcom,geni-spi"; 1130 reg = <0x0 0x88c000 0x0 0x4000>; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1134 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1135 clock-names = "se"; 1136 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1137 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1138 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1139 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1140 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1141 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1142 interconnect-names = "qup-core", 1143 "qup-config", 1144 "qup-memory"; 1145 power-domains = <&rpmhpd SA8775P_CX>; 1146 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1147 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1148 dma-names = "tx", 1149 "rx"; 1150 status = "disabled"; 1151 }; 1152 1153 uart17: serial@88c000 { 1154 compatible = "qcom,geni-uart"; 1155 reg = <0x0 0x0088c000 0x0 0x4000>; 1156 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1157 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1158 clock-names = "se"; 1159 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1160 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1161 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1162 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1163 interconnect-names = "qup-core", "qup-config"; 1164 power-domains = <&rpmhpd SA8775P_CX>; 1165 status = "disabled"; 1166 }; 1167 1168 i2c18: i2c@890000 { 1169 compatible = "qcom,geni-i2c"; 1170 reg = <0x0 0x00890000 0x0 0x4000>; 1171 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1173 clock-names = "se"; 1174 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1175 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1176 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1177 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1178 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1179 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1180 interconnect-names = "qup-core", 1181 "qup-config", 1182 "qup-memory"; 1183 power-domains = <&rpmhpd SA8775P_CX>; 1184 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1185 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1186 dma-names = "tx", 1187 "rx"; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 status = "disabled"; 1191 }; 1192 1193 spi18: spi@890000 { 1194 compatible = "qcom,geni-spi"; 1195 reg = <0x0 0x890000 0x0 0x4000>; 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1199 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1200 clock-names = "se"; 1201 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1202 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1203 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1204 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1205 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1206 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1207 interconnect-names = "qup-core", 1208 "qup-config", 1209 "qup-memory"; 1210 power-domains = <&rpmhpd SA8775P_CX>; 1211 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1212 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1213 dma-names = "tx", 1214 "rx"; 1215 status = "disabled"; 1216 }; 1217 1218 uart18: serial@890000 { 1219 compatible = "qcom,geni-uart"; 1220 reg = <0x0 0x00890000 0x0 0x4000>; 1221 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1223 clock-names = "se"; 1224 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1225 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1226 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1227 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1228 interconnect-names = "qup-core", "qup-config"; 1229 power-domains = <&rpmhpd SA8775P_CX>; 1230 status = "disabled"; 1231 }; 1232 1233 i2c19: i2c@894000 { 1234 compatible = "qcom,geni-i2c"; 1235 reg = <0x0 0x894000 0x0 0x4000>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1239 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1240 clock-names = "se"; 1241 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1242 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1243 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1244 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1245 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1246 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1247 interconnect-names = "qup-core", 1248 "qup-config", 1249 "qup-memory"; 1250 power-domains = <&rpmhpd SA8775P_CX>; 1251 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1252 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1253 dma-names = "tx", 1254 "rx"; 1255 status = "disabled"; 1256 }; 1257 1258 spi19: spi@894000 { 1259 compatible = "qcom,geni-spi"; 1260 reg = <0x0 0x894000 0x0 0x4000>; 1261 #address-cells = <1>; 1262 #size-cells = <0>; 1263 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1264 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1265 clock-names = "se"; 1266 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1267 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1268 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1269 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1270 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1271 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1272 interconnect-names = "qup-core", 1273 "qup-config", 1274 "qup-memory"; 1275 power-domains = <&rpmhpd SA8775P_CX>; 1276 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1277 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1278 dma-names = "tx", 1279 "rx"; 1280 status = "disabled"; 1281 }; 1282 1283 uart19: serial@894000 { 1284 compatible = "qcom,geni-uart"; 1285 reg = <0x0 0x00894000 0x0 0x4000>; 1286 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1288 clock-names = "se"; 1289 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1290 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1291 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1292 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1293 interconnect-names = "qup-core", "qup-config"; 1294 power-domains = <&rpmhpd SA8775P_CX>; 1295 status = "disabled"; 1296 }; 1297 1298 i2c20: i2c@898000 { 1299 compatible = "qcom,geni-i2c"; 1300 reg = <0x0 0x898000 0x0 0x4000>; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1305 clock-names = "se"; 1306 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1307 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1308 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1309 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1310 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1311 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1312 interconnect-names = "qup-core", 1313 "qup-config", 1314 "qup-memory"; 1315 power-domains = <&rpmhpd SA8775P_CX>; 1316 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1317 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1318 dma-names = "tx", 1319 "rx"; 1320 status = "disabled"; 1321 }; 1322 1323 spi20: spi@898000 { 1324 compatible = "qcom,geni-spi"; 1325 reg = <0x0 0x898000 0x0 0x4000>; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1329 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1330 clock-names = "se"; 1331 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1332 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1333 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1334 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1335 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1336 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1337 interconnect-names = "qup-core", 1338 "qup-config", 1339 "qup-memory"; 1340 power-domains = <&rpmhpd SA8775P_CX>; 1341 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1342 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1343 dma-names = "tx", 1344 "rx"; 1345 status = "disabled"; 1346 }; 1347 1348 uart20: serial@898000 { 1349 compatible = "qcom,geni-uart"; 1350 reg = <0x0 0x00898000 0x0 0x4000>; 1351 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1352 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1353 clock-names = "se"; 1354 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1355 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1356 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1357 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1358 interconnect-names = "qup-core", "qup-config"; 1359 power-domains = <&rpmhpd SA8775P_CX>; 1360 status = "disabled"; 1361 }; 1362 1363 }; 1364 1365 gpi_dma0: dma-controller@900000 { 1366 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1367 reg = <0x0 0x00900000 0x0 0x60000>; 1368 #dma-cells = <3>; 1369 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1381 dma-channels = <12>; 1382 dma-channel-mask = <0xfff>; 1383 iommus = <&apps_smmu 0x416 0x0>; 1384 status = "disabled"; 1385 }; 1386 1387 qupv3_id_0: geniqup@9c0000 { 1388 compatible = "qcom,geni-se-qup"; 1389 reg = <0x0 0x9c0000 0x0 0x6000>; 1390 #address-cells = <2>; 1391 #size-cells = <2>; 1392 ranges; 1393 clock-names = "m-ahb", "s-ahb"; 1394 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1395 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1396 iommus = <&apps_smmu 0x403 0x0>; 1397 status = "disabled"; 1398 1399 i2c0: i2c@980000 { 1400 compatible = "qcom,geni-i2c"; 1401 reg = <0x0 0x980000 0x0 0x4000>; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1406 clock-names = "se"; 1407 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1408 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1409 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1410 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1411 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1412 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1413 interconnect-names = "qup-core", 1414 "qup-config", 1415 "qup-memory"; 1416 power-domains = <&rpmhpd SA8775P_CX>; 1417 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1418 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1419 dma-names = "tx", 1420 "rx"; 1421 status = "disabled"; 1422 }; 1423 1424 spi0: spi@980000 { 1425 compatible = "qcom,geni-spi"; 1426 reg = <0x0 0x980000 0x0 0x4000>; 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1430 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1431 clock-names = "se"; 1432 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1433 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1434 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1435 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1436 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1437 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1438 interconnect-names = "qup-core", 1439 "qup-config", 1440 "qup-memory"; 1441 power-domains = <&rpmhpd SA8775P_CX>; 1442 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1443 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1444 dma-names = "tx", 1445 "rx"; 1446 status = "disabled"; 1447 }; 1448 1449 uart0: serial@980000 { 1450 compatible = "qcom,geni-uart"; 1451 reg = <0x0 0x980000 0x0 0x4000>; 1452 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1453 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1454 clock-names = "se"; 1455 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1456 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1457 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1458 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1459 interconnect-names = "qup-core", "qup-config"; 1460 power-domains = <&rpmhpd SA8775P_CX>; 1461 status = "disabled"; 1462 }; 1463 1464 i2c1: i2c@984000 { 1465 compatible = "qcom,geni-i2c"; 1466 reg = <0x0 0x984000 0x0 0x4000>; 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1470 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1471 clock-names = "se"; 1472 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1473 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1474 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1475 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1476 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1477 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1478 interconnect-names = "qup-core", 1479 "qup-config", 1480 "qup-memory"; 1481 power-domains = <&rpmhpd SA8775P_CX>; 1482 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1483 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1484 dma-names = "tx", 1485 "rx"; 1486 status = "disabled"; 1487 }; 1488 1489 spi1: spi@984000 { 1490 compatible = "qcom,geni-spi"; 1491 reg = <0x0 0x984000 0x0 0x4000>; 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1495 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1496 clock-names = "se"; 1497 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1498 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1499 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1500 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1501 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1502 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1503 interconnect-names = "qup-core", 1504 "qup-config", 1505 "qup-memory"; 1506 power-domains = <&rpmhpd SA8775P_CX>; 1507 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1508 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1509 dma-names = "tx", 1510 "rx"; 1511 status = "disabled"; 1512 }; 1513 1514 uart1: serial@984000 { 1515 compatible = "qcom,geni-uart"; 1516 reg = <0x0 0x984000 0x0 0x4000>; 1517 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1518 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1519 clock-names = "se"; 1520 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1521 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1522 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1523 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1524 interconnect-names = "qup-core", "qup-config"; 1525 power-domains = <&rpmhpd SA8775P_CX>; 1526 status = "disabled"; 1527 }; 1528 1529 i2c2: i2c@988000 { 1530 compatible = "qcom,geni-i2c"; 1531 reg = <0x0 0x988000 0x0 0x4000>; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1535 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1536 clock-names = "se"; 1537 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1538 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1539 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1540 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1541 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1542 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1543 interconnect-names = "qup-core", 1544 "qup-config", 1545 "qup-memory"; 1546 power-domains = <&rpmhpd SA8775P_CX>; 1547 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1548 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1549 dma-names = "tx", 1550 "rx"; 1551 status = "disabled"; 1552 }; 1553 1554 spi2: spi@988000 { 1555 compatible = "qcom,geni-spi"; 1556 reg = <0x0 0x988000 0x0 0x4000>; 1557 #address-cells = <1>; 1558 #size-cells = <0>; 1559 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1560 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1561 clock-names = "se"; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1563 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1564 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1565 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1566 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1567 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1568 interconnect-names = "qup-core", 1569 "qup-config", 1570 "qup-memory"; 1571 power-domains = <&rpmhpd SA8775P_CX>; 1572 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1573 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1574 dma-names = "tx", 1575 "rx"; 1576 status = "disabled"; 1577 }; 1578 1579 uart2: serial@988000 { 1580 compatible = "qcom,geni-uart"; 1581 reg = <0x0 0x988000 0x0 0x4000>; 1582 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1583 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1584 clock-names = "se"; 1585 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1586 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1587 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1588 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1589 interconnect-names = "qup-core", "qup-config"; 1590 power-domains = <&rpmhpd SA8775P_CX>; 1591 status = "disabled"; 1592 }; 1593 1594 i2c3: i2c@98c000 { 1595 compatible = "qcom,geni-i2c"; 1596 reg = <0x0 0x98c000 0x0 0x4000>; 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1600 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1601 clock-names = "se"; 1602 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1603 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1604 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1605 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1606 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1607 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1608 interconnect-names = "qup-core", 1609 "qup-config", 1610 "qup-memory"; 1611 power-domains = <&rpmhpd SA8775P_CX>; 1612 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1613 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1614 dma-names = "tx", 1615 "rx"; 1616 status = "disabled"; 1617 }; 1618 1619 spi3: spi@98c000 { 1620 compatible = "qcom,geni-spi"; 1621 reg = <0x0 0x98c000 0x0 0x4000>; 1622 #address-cells = <1>; 1623 #size-cells = <0>; 1624 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1625 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1626 clock-names = "se"; 1627 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1628 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1629 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1630 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1631 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1632 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1633 interconnect-names = "qup-core", 1634 "qup-config", 1635 "qup-memory"; 1636 power-domains = <&rpmhpd SA8775P_CX>; 1637 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1638 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1639 dma-names = "tx", 1640 "rx"; 1641 status = "disabled"; 1642 }; 1643 1644 uart3: serial@98c000 { 1645 compatible = "qcom,geni-uart"; 1646 reg = <0x0 0x98c000 0x0 0x4000>; 1647 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1648 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1649 clock-names = "se"; 1650 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1651 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1652 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1653 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1654 interconnect-names = "qup-core", "qup-config"; 1655 power-domains = <&rpmhpd SA8775P_CX>; 1656 status = "disabled"; 1657 }; 1658 1659 i2c4: i2c@990000 { 1660 compatible = "qcom,geni-i2c"; 1661 reg = <0x0 0x990000 0x0 0x4000>; 1662 #address-cells = <1>; 1663 #size-cells = <0>; 1664 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1665 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1666 clock-names = "se"; 1667 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1668 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1669 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1670 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1671 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1672 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1673 interconnect-names = "qup-core", 1674 "qup-config", 1675 "qup-memory"; 1676 power-domains = <&rpmhpd SA8775P_CX>; 1677 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1678 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1679 dma-names = "tx", 1680 "rx"; 1681 status = "disabled"; 1682 }; 1683 1684 spi4: spi@990000 { 1685 compatible = "qcom,geni-spi"; 1686 reg = <0x0 0x990000 0x0 0x4000>; 1687 #address-cells = <1>; 1688 #size-cells = <0>; 1689 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1690 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1691 clock-names = "se"; 1692 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1693 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1694 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1695 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1696 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1697 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1698 interconnect-names = "qup-core", 1699 "qup-config", 1700 "qup-memory"; 1701 power-domains = <&rpmhpd SA8775P_CX>; 1702 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1703 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1704 dma-names = "tx", 1705 "rx"; 1706 status = "disabled"; 1707 }; 1708 1709 uart4: serial@990000 { 1710 compatible = "qcom,geni-uart"; 1711 reg = <0x0 0x990000 0x0 0x4000>; 1712 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1713 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1714 clock-names = "se"; 1715 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1716 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1717 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1718 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1719 interconnect-names = "qup-core", "qup-config"; 1720 power-domains = <&rpmhpd SA8775P_CX>; 1721 status = "disabled"; 1722 }; 1723 1724 i2c5: i2c@994000 { 1725 compatible = "qcom,geni-i2c"; 1726 reg = <0x0 0x994000 0x0 0x4000>; 1727 #address-cells = <1>; 1728 #size-cells = <0>; 1729 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1730 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1731 clock-names = "se"; 1732 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1733 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1734 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1735 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1736 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1737 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1738 interconnect-names = "qup-core", 1739 "qup-config", 1740 "qup-memory"; 1741 power-domains = <&rpmhpd SA8775P_CX>; 1742 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1743 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1744 dma-names = "tx", 1745 "rx"; 1746 status = "disabled"; 1747 }; 1748 1749 spi5: spi@994000 { 1750 compatible = "qcom,geni-spi"; 1751 reg = <0x0 0x994000 0x0 0x4000>; 1752 #address-cells = <1>; 1753 #size-cells = <0>; 1754 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1755 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1756 clock-names = "se"; 1757 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1758 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1759 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1760 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1761 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1762 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1763 interconnect-names = "qup-core", 1764 "qup-config", 1765 "qup-memory"; 1766 power-domains = <&rpmhpd SA8775P_CX>; 1767 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1768 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1769 dma-names = "tx", 1770 "rx"; 1771 status = "disabled"; 1772 }; 1773 1774 uart5: serial@994000 { 1775 compatible = "qcom,geni-uart"; 1776 reg = <0x0 0x994000 0x0 0x4000>; 1777 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1778 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1779 clock-names = "se"; 1780 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1781 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1782 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1783 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1784 interconnect-names = "qup-core", "qup-config"; 1785 power-domains = <&rpmhpd SA8775P_CX>; 1786 status = "disabled"; 1787 }; 1788 }; 1789 1790 gpi_dma1: dma-controller@a00000 { 1791 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 1792 reg = <0x0 0x00a00000 0x0 0x60000>; 1793 #dma-cells = <3>; 1794 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1798 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1806 iommus = <&apps_smmu 0x456 0x0>; 1807 dma-channels = <12>; 1808 dma-channel-mask = <0xfff>; 1809 status = "disabled"; 1810 }; 1811 1812 qupv3_id_1: geniqup@ac0000 { 1813 compatible = "qcom,geni-se-qup"; 1814 reg = <0x0 0x00ac0000 0x0 0x6000>; 1815 #address-cells = <2>; 1816 #size-cells = <2>; 1817 ranges; 1818 clock-names = "m-ahb", "s-ahb"; 1819 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1820 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1821 iommus = <&apps_smmu 0x443 0x0>; 1822 status = "disabled"; 1823 1824 i2c7: i2c@a80000 { 1825 compatible = "qcom,geni-i2c"; 1826 reg = <0x0 0xa80000 0x0 0x4000>; 1827 #address-cells = <1>; 1828 #size-cells = <0>; 1829 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1830 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1831 clock-names = "se"; 1832 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1833 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1834 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1835 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1836 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1837 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1838 interconnect-names = "qup-core", 1839 "qup-config", 1840 "qup-memory"; 1841 power-domains = <&rpmhpd SA8775P_CX>; 1842 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1843 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1844 dma-names = "tx", 1845 "rx"; 1846 status = "disabled"; 1847 }; 1848 1849 spi7: spi@a80000 { 1850 compatible = "qcom,geni-spi"; 1851 reg = <0x0 0xa80000 0x0 0x4000>; 1852 #address-cells = <1>; 1853 #size-cells = <0>; 1854 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1855 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1856 clock-names = "se"; 1857 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1858 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1859 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1860 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1861 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1862 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1863 interconnect-names = "qup-core", 1864 "qup-config", 1865 "qup-memory"; 1866 power-domains = <&rpmhpd SA8775P_CX>; 1867 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1868 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1869 dma-names = "tx", 1870 "rx"; 1871 status = "disabled"; 1872 }; 1873 1874 uart7: serial@a80000 { 1875 compatible = "qcom,geni-uart"; 1876 reg = <0x0 0x00a80000 0x0 0x4000>; 1877 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1878 clock-names = "se"; 1879 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1880 interconnect-names = "qup-core", "qup-config"; 1881 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1882 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1883 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1884 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1885 power-domains = <&rpmhpd SA8775P_CX>; 1886 operating-points-v2 = <&qup_opp_table_100mhz>; 1887 status = "disabled"; 1888 }; 1889 1890 i2c8: i2c@a84000 { 1891 compatible = "qcom,geni-i2c"; 1892 reg = <0x0 0xa84000 0x0 0x4000>; 1893 #address-cells = <1>; 1894 #size-cells = <0>; 1895 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1896 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1897 clock-names = "se"; 1898 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1899 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1900 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1901 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1902 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1903 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1904 interconnect-names = "qup-core", 1905 "qup-config", 1906 "qup-memory"; 1907 power-domains = <&rpmhpd SA8775P_CX>; 1908 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1909 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1910 dma-names = "tx", 1911 "rx"; 1912 status = "disabled"; 1913 }; 1914 1915 spi8: spi@a84000 { 1916 compatible = "qcom,geni-spi"; 1917 reg = <0x0 0xa84000 0x0 0x4000>; 1918 #address-cells = <1>; 1919 #size-cells = <0>; 1920 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1921 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1922 clock-names = "se"; 1923 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1924 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1925 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1926 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1927 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1928 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1929 interconnect-names = "qup-core", 1930 "qup-config", 1931 "qup-memory"; 1932 power-domains = <&rpmhpd SA8775P_CX>; 1933 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1934 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1935 dma-names = "tx", 1936 "rx"; 1937 status = "disabled"; 1938 }; 1939 1940 uart8: serial@a84000 { 1941 compatible = "qcom,geni-uart"; 1942 reg = <0x0 0x00a84000 0x0 0x4000>; 1943 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1944 clock-names = "se"; 1945 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1946 interconnect-names = "qup-core", "qup-config"; 1947 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1948 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1949 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1950 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1951 power-domains = <&rpmhpd SA8775P_CX>; 1952 operating-points-v2 = <&qup_opp_table_100mhz>; 1953 status = "disabled"; 1954 }; 1955 1956 i2c9: i2c@a88000 { 1957 compatible = "qcom,geni-i2c"; 1958 reg = <0x0 0xa88000 0x0 0x4000>; 1959 #address-cells = <1>; 1960 #size-cells = <0>; 1961 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1962 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1963 clock-names = "se"; 1964 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1965 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1966 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1967 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1968 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1969 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1970 interconnect-names = "qup-core", 1971 "qup-config", 1972 "qup-memory"; 1973 power-domains = <&rpmhpd SA8775P_CX>; 1974 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1975 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1976 dma-names = "tx", 1977 "rx"; 1978 status = "disabled"; 1979 }; 1980 1981 spi9: spi@a88000 { 1982 compatible = "qcom,geni-spi"; 1983 reg = <0x0 0xa88000 0x0 0x4000>; 1984 #address-cells = <1>; 1985 #size-cells = <0>; 1986 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1987 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1988 clock-names = "se"; 1989 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1990 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1992 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1993 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1994 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1995 interconnect-names = "qup-core", 1996 "qup-config", 1997 "qup-memory"; 1998 power-domains = <&rpmhpd SA8775P_CX>; 1999 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 2000 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 2001 dma-names = "tx", 2002 "rx"; 2003 status = "disabled"; 2004 }; 2005 2006 uart9: serial@a88000 { 2007 compatible = "qcom,geni-uart"; 2008 reg = <0x0 0xa88000 0x0 0x4000>; 2009 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2010 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 2011 clock-names = "se"; 2012 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2013 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2014 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2015 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2016 interconnect-names = "qup-core", "qup-config"; 2017 power-domains = <&rpmhpd SA8775P_CX>; 2018 status = "disabled"; 2019 }; 2020 2021 i2c10: i2c@a8c000 { 2022 compatible = "qcom,geni-i2c"; 2023 reg = <0x0 0xa8c000 0x0 0x4000>; 2024 #address-cells = <1>; 2025 #size-cells = <0>; 2026 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2027 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2028 clock-names = "se"; 2029 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2030 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2031 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2032 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2033 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2034 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2035 interconnect-names = "qup-core", 2036 "qup-config", 2037 "qup-memory"; 2038 power-domains = <&rpmhpd SA8775P_CX>; 2039 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 2040 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 2041 dma-names = "tx", 2042 "rx"; 2043 status = "disabled"; 2044 }; 2045 2046 spi10: spi@a8c000 { 2047 compatible = "qcom,geni-spi"; 2048 reg = <0x0 0xa8c000 0x0 0x4000>; 2049 #address-cells = <1>; 2050 #size-cells = <0>; 2051 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2052 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2053 clock-names = "se"; 2054 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2055 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2056 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2057 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2058 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2059 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2060 interconnect-names = "qup-core", 2061 "qup-config", 2062 "qup-memory"; 2063 power-domains = <&rpmhpd SA8775P_CX>; 2064 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 2065 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 2066 dma-names = "tx", 2067 "rx"; 2068 status = "disabled"; 2069 }; 2070 2071 uart10: serial@a8c000 { 2072 compatible = "qcom,geni-uart"; 2073 reg = <0x0 0x00a8c000 0x0 0x4000>; 2074 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2075 clock-names = "se"; 2076 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 2077 interconnect-names = "qup-core", "qup-config"; 2078 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 2079 &clk_virt SLAVE_QUP_CORE_1 0>, 2080 <&gem_noc MASTER_APPSS_PROC 0 2081 &config_noc SLAVE_QUP_1 0>; 2082 power-domains = <&rpmhpd SA8775P_CX>; 2083 operating-points-v2 = <&qup_opp_table_100mhz>; 2084 status = "disabled"; 2085 }; 2086 2087 i2c11: i2c@a90000 { 2088 compatible = "qcom,geni-i2c"; 2089 reg = <0x0 0xa90000 0x0 0x4000>; 2090 #address-cells = <1>; 2091 #size-cells = <0>; 2092 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2093 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2094 clock-names = "se"; 2095 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2096 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2097 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2098 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2099 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2100 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2101 interconnect-names = "qup-core", 2102 "qup-config", 2103 "qup-memory"; 2104 power-domains = <&rpmhpd SA8775P_CX>; 2105 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2106 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2107 dma-names = "tx", 2108 "rx"; 2109 status = "disabled"; 2110 }; 2111 2112 spi11: spi@a90000 { 2113 compatible = "qcom,geni-spi"; 2114 reg = <0x0 0xa90000 0x0 0x4000>; 2115 #address-cells = <1>; 2116 #size-cells = <0>; 2117 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2118 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2119 clock-names = "se"; 2120 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2121 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2122 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2123 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2124 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2125 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2126 interconnect-names = "qup-core", 2127 "qup-config", 2128 "qup-memory"; 2129 power-domains = <&rpmhpd SA8775P_CX>; 2130 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2131 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2132 dma-names = "tx", 2133 "rx"; 2134 status = "disabled"; 2135 }; 2136 2137 uart11: serial@a90000 { 2138 compatible = "qcom,geni-uart"; 2139 reg = <0x0 0x00a90000 0x0 0x4000>; 2140 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2141 clock-names = "se"; 2142 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2143 interconnect-names = "qup-core", "qup-config"; 2144 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2145 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2146 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2147 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2148 power-domains = <&rpmhpd SA8775P_CX>; 2149 operating-points-v2 = <&qup_opp_table_100mhz>; 2150 status = "disabled"; 2151 }; 2152 2153 i2c12: i2c@a94000 { 2154 compatible = "qcom,geni-i2c"; 2155 reg = <0x0 0xa94000 0x0 0x4000>; 2156 #address-cells = <1>; 2157 #size-cells = <0>; 2158 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2159 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2160 clock-names = "se"; 2161 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2162 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2163 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2164 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2165 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2166 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2167 interconnect-names = "qup-core", 2168 "qup-config", 2169 "qup-memory"; 2170 power-domains = <&rpmhpd SA8775P_CX>; 2171 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2172 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2173 dma-names = "tx", 2174 "rx"; 2175 status = "disabled"; 2176 }; 2177 2178 spi12: spi@a94000 { 2179 compatible = "qcom,geni-spi"; 2180 reg = <0x0 0xa94000 0x0 0x4000>; 2181 #address-cells = <1>; 2182 #size-cells = <0>; 2183 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2184 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2185 clock-names = "se"; 2186 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2187 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2188 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2189 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2190 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2191 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2192 interconnect-names = "qup-core", 2193 "qup-config", 2194 "qup-memory"; 2195 power-domains = <&rpmhpd SA8775P_CX>; 2196 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2197 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2198 dma-names = "tx", 2199 "rx"; 2200 status = "disabled"; 2201 }; 2202 2203 uart12: serial@a94000 { 2204 compatible = "qcom,geni-uart"; 2205 reg = <0x0 0x00a94000 0x0 0x4000>; 2206 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2207 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2208 clock-names = "se"; 2209 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2210 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2211 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2212 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2213 interconnect-names = "qup-core", "qup-config"; 2214 power-domains = <&rpmhpd SA8775P_CX>; 2215 status = "disabled"; 2216 }; 2217 2218 i2c13: i2c@a98000 { 2219 compatible = "qcom,geni-i2c"; 2220 reg = <0x0 0xa98000 0x0 0x4000>; 2221 #address-cells = <1>; 2222 #size-cells = <0>; 2223 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2224 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2225 clock-names = "se"; 2226 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2227 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2228 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2229 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2230 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2231 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2232 interconnect-names = "qup-core", 2233 "qup-config", 2234 "qup-memory"; 2235 power-domains = <&rpmhpd SA8775P_CX>; 2236 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2237 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2238 dma-names = "tx", 2239 "rx"; 2240 status = "disabled"; 2241 2242 }; 2243 }; 2244 2245 gpi_dma3: dma-controller@b00000 { 2246 compatible = "qcom,sa8775p-gpi-dma", "qcom,sm6350-gpi-dma"; 2247 reg = <0x0 0x00b00000 0x0 0x58000>; 2248 #dma-cells = <3>; 2249 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2253 iommus = <&apps_smmu 0x056 0x0>; 2254 dma-channels = <4>; 2255 dma-channel-mask = <0xf>; 2256 status = "disabled"; 2257 }; 2258 2259 qupv3_id_3: geniqup@bc0000 { 2260 compatible = "qcom,geni-se-qup"; 2261 reg = <0x0 0xbc0000 0x0 0x6000>; 2262 #address-cells = <2>; 2263 #size-cells = <2>; 2264 ranges; 2265 clock-names = "m-ahb", "s-ahb"; 2266 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2267 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2268 iommus = <&apps_smmu 0x43 0x0>; 2269 status = "disabled"; 2270 2271 i2c21: i2c@b80000 { 2272 compatible = "qcom,geni-i2c"; 2273 reg = <0x0 0xb80000 0x0 0x4000>; 2274 #address-cells = <1>; 2275 #size-cells = <0>; 2276 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2277 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2278 clock-names = "se"; 2279 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2280 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2281 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2282 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2283 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2284 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2285 interconnect-names = "qup-core", 2286 "qup-config", 2287 "qup-memory"; 2288 power-domains = <&rpmhpd SA8775P_CX>; 2289 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2290 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2291 dma-names = "tx", 2292 "rx"; 2293 status = "disabled"; 2294 }; 2295 2296 spi21: spi@b80000 { 2297 compatible = "qcom,geni-spi"; 2298 reg = <0x0 0xb80000 0x0 0x4000>; 2299 #address-cells = <1>; 2300 #size-cells = <0>; 2301 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2302 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2303 clock-names = "se"; 2304 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2305 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2306 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2307 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2308 <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2309 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2310 interconnect-names = "qup-core", 2311 "qup-config", 2312 "qup-memory"; 2313 power-domains = <&rpmhpd SA8775P_CX>; 2314 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2315 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2316 dma-names = "tx", 2317 "rx"; 2318 status = "disabled"; 2319 }; 2320 2321 uart21: serial@b80000 { 2322 compatible = "qcom,geni-uart"; 2323 reg = <0x0 0x00b80000 0x0 0x4000>; 2324 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 2325 clock-names = "se"; 2326 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2327 interconnect-names = "qup-core", "qup-config"; 2328 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2329 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2330 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2331 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2332 power-domains = <&rpmhpd SA8775P_CX>; 2333 operating-points-v2 = <&qup_opp_table_100mhz>; 2334 status = "disabled"; 2335 }; 2336 }; 2337 2338 rng: rng@10d2000 { 2339 compatible = "qcom,sa8775p-trng", "qcom,trng"; 2340 reg = <0 0x010d2000 0 0x1000>; 2341 }; 2342 2343 ufs_mem_hc: ufshc@1d84000 { 2344 compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2345 reg = <0x0 0x01d84000 0x0 0x3000>; 2346 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2347 phys = <&ufs_mem_phy>; 2348 phy-names = "ufsphy"; 2349 lanes-per-direction = <2>; 2350 #reset-cells = <1>; 2351 resets = <&gcc GCC_UFS_PHY_BCR>; 2352 reset-names = "rst"; 2353 power-domains = <&gcc UFS_PHY_GDSC>; 2354 required-opps = <&rpmhpd_opp_nom>; 2355 iommus = <&apps_smmu 0x100 0x0>; 2356 dma-coherent; 2357 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2358 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2359 <&gcc GCC_UFS_PHY_AHB_CLK>, 2360 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2361 <&rpmhcc RPMH_CXO_CLK>, 2362 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2363 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2364 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2365 clock-names = "core_clk", 2366 "bus_aggr_clk", 2367 "iface_clk", 2368 "core_clk_unipro", 2369 "ref_clk", 2370 "tx_lane0_sync_clk", 2371 "rx_lane0_sync_clk", 2372 "rx_lane1_sync_clk"; 2373 freq-table-hz = <75000000 300000000>, 2374 <0 0>, 2375 <0 0>, 2376 <75000000 300000000>, 2377 <0 0>, 2378 <0 0>, 2379 <0 0>, 2380 <0 0>; 2381 qcom,ice = <&ice>; 2382 status = "disabled"; 2383 }; 2384 2385 ufs_mem_phy: phy@1d87000 { 2386 compatible = "qcom,sa8775p-qmp-ufs-phy"; 2387 reg = <0x0 0x01d87000 0x0 0xe10>; 2388 /* 2389 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2390 * enables the CXO clock to eDP *and* UFS PHY. 2391 */ 2392 clocks = <&rpmhcc RPMH_CXO_CLK>, 2393 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2394 <&gcc GCC_EDP_REF_CLKREF_EN>; 2395 clock-names = "ref", "ref_aux", "qref"; 2396 power-domains = <&gcc UFS_PHY_GDSC>; 2397 resets = <&ufs_mem_hc 0>; 2398 reset-names = "ufsphy"; 2399 #phy-cells = <0>; 2400 status = "disabled"; 2401 }; 2402 2403 ice: crypto@1d88000 { 2404 compatible = "qcom,sa8775p-inline-crypto-engine", 2405 "qcom,inline-crypto-engine"; 2406 reg = <0x0 0x01d88000 0x0 0x18000>; 2407 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2408 }; 2409 2410 cryptobam: dma-controller@1dc4000 { 2411 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2412 reg = <0x0 0x01dc4000 0x0 0x28000>; 2413 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2414 #dma-cells = <1>; 2415 qcom,ee = <0>; 2416 qcom,controlled-remotely; 2417 iommus = <&apps_smmu 0x480 0x00>, 2418 <&apps_smmu 0x481 0x00>; 2419 }; 2420 2421 crypto: crypto@1dfa000 { 2422 compatible = "qcom,sa8775p-qce", "qcom,qce"; 2423 reg = <0x0 0x01dfa000 0x0 0x6000>; 2424 dmas = <&cryptobam 4>, <&cryptobam 5>; 2425 dma-names = "rx", "tx"; 2426 iommus = <&apps_smmu 0x480 0x00>, 2427 <&apps_smmu 0x481 0x00>; 2428 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 0 &mc_virt SLAVE_EBI1 0>; 2429 interconnect-names = "memory"; 2430 }; 2431 2432 stm: stm@4002000 { 2433 compatible = "arm,coresight-stm", "arm,primecell"; 2434 reg = <0x0 0x4002000 0x0 0x1000>, 2435 <0x0 0x16280000 0x0 0x180000>; 2436 reg-names = "stm-base", "stm-stimulus-base"; 2437 2438 clocks = <&aoss_qmp>; 2439 clock-names = "apb_pclk"; 2440 2441 out-ports { 2442 port { 2443 stm_out: endpoint { 2444 remote-endpoint = 2445 <&funnel0_in7>; 2446 }; 2447 }; 2448 }; 2449 }; 2450 2451 tpdm@4003000 { 2452 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2453 reg = <0x0 0x4003000 0x0 0x1000>; 2454 2455 clocks = <&aoss_qmp>; 2456 clock-names = "apb_pclk"; 2457 2458 qcom,cmb-element-bits = <32>; 2459 qcom,cmb-msrs-num = <32>; 2460 status = "disabled"; 2461 2462 out-ports { 2463 port { 2464 qdss_tpdm0_out: endpoint { 2465 remote-endpoint = 2466 <&qdss_tpda_in0>; 2467 }; 2468 }; 2469 }; 2470 }; 2471 2472 tpda@4004000 { 2473 compatible = "qcom,coresight-tpda", "arm,primecell"; 2474 reg = <0x0 0x4004000 0x0 0x1000>; 2475 2476 clocks = <&aoss_qmp>; 2477 clock-names = "apb_pclk"; 2478 2479 out-ports { 2480 port { 2481 qdss_tpda_out: endpoint { 2482 remote-endpoint = 2483 <&funnel0_in6>; 2484 }; 2485 }; 2486 }; 2487 2488 in-ports { 2489 #address-cells = <1>; 2490 #size-cells = <0>; 2491 2492 port@0 { 2493 reg = <0>; 2494 qdss_tpda_in0: endpoint { 2495 remote-endpoint = 2496 <&qdss_tpdm0_out>; 2497 }; 2498 }; 2499 2500 port@1 { 2501 reg = <1>; 2502 qdss_tpda_in1: endpoint { 2503 remote-endpoint = 2504 <&qdss_tpdm1_out>; 2505 }; 2506 }; 2507 }; 2508 }; 2509 2510 tpdm@400f000 { 2511 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2512 reg = <0x0 0x400f000 0x0 0x1000>; 2513 2514 clocks = <&aoss_qmp>; 2515 clock-names = "apb_pclk"; 2516 2517 qcom,cmb-element-bits = <32>; 2518 qcom,cmb-msrs-num = <32>; 2519 2520 out-ports { 2521 port { 2522 qdss_tpdm1_out: endpoint { 2523 remote-endpoint = 2524 <&qdss_tpda_in1>; 2525 }; 2526 }; 2527 }; 2528 }; 2529 2530 funnel@4041000 { 2531 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2532 reg = <0x0 0x4041000 0x0 0x1000>; 2533 2534 clocks = <&aoss_qmp>; 2535 clock-names = "apb_pclk"; 2536 2537 out-ports { 2538 port { 2539 funnel0_out: endpoint { 2540 remote-endpoint = 2541 <&qdss_funnel_in0>; 2542 }; 2543 }; 2544 }; 2545 2546 in-ports { 2547 #address-cells = <1>; 2548 #size-cells = <0>; 2549 2550 port@6 { 2551 reg = <6>; 2552 funnel0_in6: endpoint { 2553 remote-endpoint = 2554 <&qdss_tpda_out>; 2555 }; 2556 }; 2557 2558 port@7 { 2559 reg = <7>; 2560 funnel0_in7: endpoint { 2561 remote-endpoint = 2562 <&stm_out>; 2563 }; 2564 }; 2565 }; 2566 }; 2567 2568 funnel@4042000 { 2569 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2570 reg = <0x0 0x4042000 0x0 0x1000>; 2571 2572 clocks = <&aoss_qmp>; 2573 clock-names = "apb_pclk"; 2574 2575 out-ports { 2576 port { 2577 funnel1_out: endpoint { 2578 remote-endpoint = 2579 <&qdss_funnel_in1>; 2580 }; 2581 }; 2582 }; 2583 2584 in-ports { 2585 #address-cells = <1>; 2586 #size-cells = <0>; 2587 2588 port@4 { 2589 reg = <4>; 2590 funnel1_in4: endpoint { 2591 remote-endpoint = 2592 <&apss_funnel1_out>; 2593 }; 2594 }; 2595 }; 2596 }; 2597 2598 funnel@4045000 { 2599 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2600 reg = <0x0 0x4045000 0x0 0x1000>; 2601 2602 clocks = <&aoss_qmp>; 2603 clock-names = "apb_pclk"; 2604 2605 out-ports { 2606 port { 2607 qdss_funnel_out: endpoint { 2608 remote-endpoint = 2609 <&aoss_funnel_in7>; 2610 }; 2611 }; 2612 }; 2613 2614 in-ports { 2615 #address-cells = <1>; 2616 #size-cells = <0>; 2617 2618 port@0 { 2619 reg = <0>; 2620 qdss_funnel_in0: endpoint { 2621 remote-endpoint = 2622 <&funnel0_out>; 2623 }; 2624 }; 2625 2626 port@1 { 2627 reg = <1>; 2628 qdss_funnel_in1: endpoint { 2629 remote-endpoint = 2630 <&funnel1_out>; 2631 }; 2632 }; 2633 }; 2634 }; 2635 2636 funnel@4b04000 { 2637 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2638 reg = <0x0 0x4b04000 0x0 0x1000>; 2639 2640 clocks = <&aoss_qmp>; 2641 clock-names = "apb_pclk"; 2642 2643 out-ports { 2644 port { 2645 aoss_funnel_out: endpoint { 2646 remote-endpoint = 2647 <&etf0_in>; 2648 }; 2649 }; 2650 }; 2651 2652 in-ports { 2653 #address-cells = <1>; 2654 #size-cells = <0>; 2655 2656 port@6 { 2657 reg = <6>; 2658 aoss_funnel_in6: endpoint { 2659 remote-endpoint = 2660 <&aoss_tpda_out>; 2661 }; 2662 }; 2663 2664 port@7 { 2665 reg = <7>; 2666 aoss_funnel_in7: endpoint { 2667 remote-endpoint = 2668 <&qdss_funnel_out>; 2669 }; 2670 }; 2671 }; 2672 }; 2673 2674 tmc_etf: tmc@4b05000 { 2675 compatible = "arm,coresight-tmc", "arm,primecell"; 2676 reg = <0x0 0x4b05000 0x0 0x1000>; 2677 2678 clocks = <&aoss_qmp>; 2679 clock-names = "apb_pclk"; 2680 2681 out-ports { 2682 port { 2683 etf0_out: endpoint { 2684 remote-endpoint = 2685 <&swao_rep_in>; 2686 }; 2687 }; 2688 }; 2689 2690 in-ports { 2691 port { 2692 etf0_in: endpoint { 2693 remote-endpoint = 2694 <&aoss_funnel_out>; 2695 }; 2696 }; 2697 }; 2698 }; 2699 2700 replicator@4b06000 { 2701 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2702 reg = <0x0 0x4b06000 0x0 0x1000>; 2703 2704 clocks = <&aoss_qmp>; 2705 clock-names = "apb_pclk"; 2706 2707 out-ports { 2708 #address-cells = <1>; 2709 #size-cells = <0>; 2710 2711 port@1 { 2712 reg = <1>; 2713 swao_rep_out1: endpoint { 2714 remote-endpoint = 2715 <&eud_in>; 2716 }; 2717 }; 2718 }; 2719 2720 in-ports { 2721 port { 2722 swao_rep_in: endpoint { 2723 remote-endpoint = 2724 <&etf0_out>; 2725 }; 2726 }; 2727 }; 2728 }; 2729 2730 tpda@4b08000 { 2731 compatible = "qcom,coresight-tpda", "arm,primecell"; 2732 reg = <0x0 0x4b08000 0x0 0x1000>; 2733 2734 clocks = <&aoss_qmp>; 2735 clock-names = "apb_pclk"; 2736 2737 out-ports { 2738 port { 2739 aoss_tpda_out: endpoint { 2740 remote-endpoint = 2741 <&aoss_funnel_in6>; 2742 }; 2743 }; 2744 }; 2745 2746 in-ports { 2747 #address-cells = <1>; 2748 #size-cells = <0>; 2749 2750 port@0 { 2751 reg = <0>; 2752 aoss_tpda_in0: endpoint { 2753 remote-endpoint = 2754 <&aoss_tpdm0_out>; 2755 }; 2756 }; 2757 2758 port@1 { 2759 reg = <1>; 2760 aoss_tpda_in1: endpoint { 2761 remote-endpoint = 2762 <&aoss_tpdm1_out>; 2763 }; 2764 }; 2765 2766 port@2 { 2767 reg = <2>; 2768 aoss_tpda_in2: endpoint { 2769 remote-endpoint = 2770 <&aoss_tpdm2_out>; 2771 }; 2772 }; 2773 2774 port@3 { 2775 reg = <3>; 2776 aoss_tpda_in3: endpoint { 2777 remote-endpoint = 2778 <&aoss_tpdm3_out>; 2779 }; 2780 }; 2781 2782 port@4 { 2783 reg = <4>; 2784 aoss_tpda_in4: endpoint { 2785 remote-endpoint = 2786 <&aoss_tpdm4_out>; 2787 }; 2788 }; 2789 }; 2790 }; 2791 2792 tpdm@4b09000 { 2793 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2794 reg = <0x0 0x4b09000 0x0 0x1000>; 2795 2796 clocks = <&aoss_qmp>; 2797 clock-names = "apb_pclk"; 2798 2799 qcom,cmb-element-bits = <64>; 2800 qcom,cmb-msrs-num = <32>; 2801 2802 out-ports { 2803 port { 2804 aoss_tpdm0_out: endpoint { 2805 remote-endpoint = 2806 <&aoss_tpda_in0>; 2807 }; 2808 }; 2809 }; 2810 }; 2811 2812 tpdm@4b0a000 { 2813 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2814 reg = <0x0 0x4b0a000 0x0 0x1000>; 2815 2816 clocks = <&aoss_qmp>; 2817 clock-names = "apb_pclk"; 2818 2819 qcom,cmb-element-bits = <64>; 2820 qcom,cmb-msrs-num = <32>; 2821 2822 out-ports { 2823 port { 2824 aoss_tpdm1_out: endpoint { 2825 remote-endpoint = 2826 <&aoss_tpda_in1>; 2827 }; 2828 }; 2829 }; 2830 }; 2831 2832 tpdm@4b0b000 { 2833 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2834 reg = <0x0 0x4b0b000 0x0 0x1000>; 2835 2836 clocks = <&aoss_qmp>; 2837 clock-names = "apb_pclk"; 2838 2839 qcom,cmb-element-bits = <64>; 2840 qcom,cmb-msrs-num = <32>; 2841 2842 out-ports { 2843 port { 2844 aoss_tpdm2_out: endpoint { 2845 remote-endpoint = 2846 <&aoss_tpda_in2>; 2847 }; 2848 }; 2849 }; 2850 }; 2851 2852 tpdm@4b0c000 { 2853 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2854 reg = <0x0 0x4b0c000 0x0 0x1000>; 2855 2856 clocks = <&aoss_qmp>; 2857 clock-names = "apb_pclk"; 2858 2859 qcom,cmb-element-bits = <64>; 2860 qcom,cmb-msrs-num = <32>; 2861 2862 out-ports { 2863 port { 2864 aoss_tpdm3_out: endpoint { 2865 remote-endpoint = 2866 <&aoss_tpda_in3>; 2867 }; 2868 }; 2869 }; 2870 }; 2871 2872 tpdm@4b0d000 { 2873 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2874 reg = <0x0 0x4b0d000 0x0 0x1000>; 2875 2876 clocks = <&aoss_qmp>; 2877 clock-names = "apb_pclk"; 2878 2879 qcom,dsb-element-bits = <32>; 2880 qcom,dsb-msrs-num = <32>; 2881 2882 out-ports { 2883 port { 2884 aoss_tpdm4_out: endpoint { 2885 remote-endpoint = 2886 <&aoss_tpda_in4>; 2887 }; 2888 }; 2889 }; 2890 }; 2891 2892 aoss_cti: cti@4b13000 { 2893 compatible = "arm,coresight-cti", "arm,primecell"; 2894 reg = <0x0 0x4b13000 0x0 0x1000>; 2895 2896 clocks = <&aoss_qmp>; 2897 clock-names = "apb_pclk"; 2898 }; 2899 2900 etm@6040000 { 2901 compatible = "arm,primecell"; 2902 reg = <0x0 0x6040000 0x0 0x1000>; 2903 cpu = <&cpu0>; 2904 2905 clocks = <&aoss_qmp>; 2906 clock-names = "apb_pclk"; 2907 arm,coresight-loses-context-with-cpu; 2908 qcom,skip-power-up; 2909 2910 out-ports { 2911 port { 2912 etm0_out: endpoint { 2913 remote-endpoint = 2914 <&apss_funnel0_in0>; 2915 }; 2916 }; 2917 }; 2918 }; 2919 2920 etm@6140000 { 2921 compatible = "arm,primecell"; 2922 reg = <0x0 0x6140000 0x0 0x1000>; 2923 cpu = <&cpu1>; 2924 2925 clocks = <&aoss_qmp>; 2926 clock-names = "apb_pclk"; 2927 arm,coresight-loses-context-with-cpu; 2928 qcom,skip-power-up; 2929 2930 out-ports { 2931 port { 2932 etm1_out: endpoint { 2933 remote-endpoint = 2934 <&apss_funnel0_in1>; 2935 }; 2936 }; 2937 }; 2938 }; 2939 2940 etm@6240000 { 2941 compatible = "arm,primecell"; 2942 reg = <0x0 0x6240000 0x0 0x1000>; 2943 cpu = <&cpu2>; 2944 2945 clocks = <&aoss_qmp>; 2946 clock-names = "apb_pclk"; 2947 arm,coresight-loses-context-with-cpu; 2948 qcom,skip-power-up; 2949 2950 out-ports { 2951 port { 2952 etm2_out: endpoint { 2953 remote-endpoint = 2954 <&apss_funnel0_in2>; 2955 }; 2956 }; 2957 }; 2958 }; 2959 2960 etm@6340000 { 2961 compatible = "arm,primecell"; 2962 reg = <0x0 0x6340000 0x0 0x1000>; 2963 cpu = <&cpu3>; 2964 2965 clocks = <&aoss_qmp>; 2966 clock-names = "apb_pclk"; 2967 arm,coresight-loses-context-with-cpu; 2968 qcom,skip-power-up; 2969 2970 out-ports { 2971 port { 2972 etm3_out: endpoint { 2973 remote-endpoint = 2974 <&apss_funnel0_in3>; 2975 }; 2976 }; 2977 }; 2978 }; 2979 2980 etm@6440000 { 2981 compatible = "arm,primecell"; 2982 reg = <0x0 0x6440000 0x0 0x1000>; 2983 cpu = <&cpu4>; 2984 2985 clocks = <&aoss_qmp>; 2986 clock-names = "apb_pclk"; 2987 arm,coresight-loses-context-with-cpu; 2988 qcom,skip-power-up; 2989 2990 out-ports { 2991 port { 2992 etm4_out: endpoint { 2993 remote-endpoint = 2994 <&apss_funnel0_in4>; 2995 }; 2996 }; 2997 }; 2998 }; 2999 3000 etm@6540000 { 3001 compatible = "arm,primecell"; 3002 reg = <0x0 0x6540000 0x0 0x1000>; 3003 cpu = <&cpu5>; 3004 3005 clocks = <&aoss_qmp>; 3006 clock-names = "apb_pclk"; 3007 arm,coresight-loses-context-with-cpu; 3008 qcom,skip-power-up; 3009 3010 out-ports { 3011 port { 3012 etm5_out: endpoint { 3013 remote-endpoint = 3014 <&apss_funnel0_in5>; 3015 }; 3016 }; 3017 }; 3018 }; 3019 3020 etm@6640000 { 3021 compatible = "arm,primecell"; 3022 reg = <0x0 0x6640000 0x0 0x1000>; 3023 cpu = <&cpu6>; 3024 3025 clocks = <&aoss_qmp>; 3026 clock-names = "apb_pclk"; 3027 arm,coresight-loses-context-with-cpu; 3028 qcom,skip-power-up; 3029 3030 out-ports { 3031 port { 3032 etm6_out: endpoint { 3033 remote-endpoint = 3034 <&apss_funnel0_in6>; 3035 }; 3036 }; 3037 }; 3038 }; 3039 3040 etm@6740000 { 3041 compatible = "arm,primecell"; 3042 reg = <0x0 0x6740000 0x0 0x1000>; 3043 cpu = <&cpu7>; 3044 3045 clocks = <&aoss_qmp>; 3046 clock-names = "apb_pclk"; 3047 arm,coresight-loses-context-with-cpu; 3048 qcom,skip-power-up; 3049 3050 out-ports { 3051 port { 3052 etm7_out: endpoint { 3053 remote-endpoint = 3054 <&apss_funnel0_in7>; 3055 }; 3056 }; 3057 }; 3058 }; 3059 3060 funnel@6800000 { 3061 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3062 reg = <0x0 0x6800000 0x0 0x1000>; 3063 3064 clocks = <&aoss_qmp>; 3065 clock-names = "apb_pclk"; 3066 3067 out-ports { 3068 port { 3069 apss_funnel0_out: endpoint { 3070 remote-endpoint = 3071 <&apss_funnel1_in0>; 3072 }; 3073 }; 3074 }; 3075 3076 in-ports { 3077 #address-cells = <1>; 3078 #size-cells = <0>; 3079 3080 port@0 { 3081 reg = <0>; 3082 apss_funnel0_in0: endpoint { 3083 remote-endpoint = 3084 <&etm0_out>; 3085 }; 3086 }; 3087 3088 port@1 { 3089 reg = <1>; 3090 apss_funnel0_in1: endpoint { 3091 remote-endpoint = 3092 <&etm1_out>; 3093 }; 3094 }; 3095 3096 port@2 { 3097 reg = <2>; 3098 apss_funnel0_in2: endpoint { 3099 remote-endpoint = 3100 <&etm2_out>; 3101 }; 3102 }; 3103 3104 port@3 { 3105 reg = <3>; 3106 apss_funnel0_in3: endpoint { 3107 remote-endpoint = 3108 <&etm3_out>; 3109 }; 3110 }; 3111 3112 port@4 { 3113 reg = <4>; 3114 apss_funnel0_in4: endpoint { 3115 remote-endpoint = 3116 <&etm4_out>; 3117 }; 3118 }; 3119 3120 port@5 { 3121 reg = <5>; 3122 apss_funnel0_in5: endpoint { 3123 remote-endpoint = 3124 <&etm5_out>; 3125 }; 3126 }; 3127 3128 port@6 { 3129 reg = <6>; 3130 apss_funnel0_in6: endpoint { 3131 remote-endpoint = 3132 <&etm6_out>; 3133 }; 3134 }; 3135 3136 port@7 { 3137 reg = <7>; 3138 apss_funnel0_in7: endpoint { 3139 remote-endpoint = 3140 <&etm7_out>; 3141 }; 3142 }; 3143 }; 3144 }; 3145 3146 funnel@6810000 { 3147 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3148 reg = <0x0 0x6810000 0x0 0x1000>; 3149 3150 clocks = <&aoss_qmp>; 3151 clock-names = "apb_pclk"; 3152 3153 out-ports { 3154 port { 3155 apss_funnel1_out: endpoint { 3156 remote-endpoint = 3157 <&funnel1_in4>; 3158 }; 3159 }; 3160 }; 3161 3162 in-ports { 3163 #address-cells = <1>; 3164 #size-cells = <0>; 3165 3166 port@0 { 3167 reg = <0>; 3168 apss_funnel1_in0: endpoint { 3169 remote-endpoint = 3170 <&apss_funnel0_out>; 3171 }; 3172 }; 3173 3174 port@3 { 3175 reg = <3>; 3176 apss_funnel1_in3: endpoint { 3177 remote-endpoint = 3178 <&apss_tpda_out>; 3179 }; 3180 }; 3181 }; 3182 }; 3183 3184 tpdm@6860000 { 3185 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3186 reg = <0x0 0x6860000 0x0 0x1000>; 3187 3188 clocks = <&aoss_qmp>; 3189 clock-names = "apb_pclk"; 3190 3191 qcom,cmb-element-bits = <64>; 3192 qcom,cmb-msrs-num = <32>; 3193 3194 out-ports { 3195 port { 3196 apss_tpdm3_out: endpoint { 3197 remote-endpoint = 3198 <&apss_tpda_in3>; 3199 }; 3200 }; 3201 }; 3202 }; 3203 3204 tpdm@6861000 { 3205 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3206 reg = <0x0 0x6861000 0x0 0x1000>; 3207 3208 clocks = <&aoss_qmp>; 3209 clock-names = "apb_pclk"; 3210 3211 qcom,dsb-element-bits = <32>; 3212 qcom,dsb-msrs-num = <32>; 3213 3214 out-ports { 3215 port { 3216 apss_tpdm4_out: endpoint { 3217 remote-endpoint = 3218 <&apss_tpda_in4>; 3219 }; 3220 }; 3221 }; 3222 }; 3223 3224 tpda@6863000 { 3225 compatible = "qcom,coresight-tpda", "arm,primecell"; 3226 reg = <0x0 0x6863000 0x0 0x1000>; 3227 3228 clocks = <&aoss_qmp>; 3229 clock-names = "apb_pclk"; 3230 3231 out-ports { 3232 port { 3233 apss_tpda_out: endpoint { 3234 remote-endpoint = 3235 <&apss_funnel1_in3>; 3236 }; 3237 }; 3238 }; 3239 3240 in-ports { 3241 #address-cells = <1>; 3242 #size-cells = <0>; 3243 3244 port@0 { 3245 reg = <0>; 3246 apss_tpda_in0: endpoint { 3247 remote-endpoint = 3248 <&apss_tpdm0_out>; 3249 }; 3250 }; 3251 3252 port@1 { 3253 reg = <1>; 3254 apss_tpda_in1: endpoint { 3255 remote-endpoint = 3256 <&apss_tpdm1_out>; 3257 }; 3258 }; 3259 3260 port@2 { 3261 reg = <2>; 3262 apss_tpda_in2: endpoint { 3263 remote-endpoint = 3264 <&apss_tpdm2_out>; 3265 }; 3266 }; 3267 3268 port@3 { 3269 reg = <3>; 3270 apss_tpda_in3: endpoint { 3271 remote-endpoint = 3272 <&apss_tpdm3_out>; 3273 }; 3274 }; 3275 3276 port@4 { 3277 reg = <4>; 3278 apss_tpda_in4: endpoint { 3279 remote-endpoint = 3280 <&apss_tpdm4_out>; 3281 }; 3282 }; 3283 }; 3284 }; 3285 3286 tpdm@68a0000 { 3287 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3288 reg = <0x0 0x68a0000 0x0 0x1000>; 3289 3290 clocks = <&aoss_qmp>; 3291 clock-names = "apb_pclk"; 3292 3293 qcom,cmb-element-bits = <32>; 3294 qcom,cmb-msrs-num = <32>; 3295 3296 out-ports { 3297 port { 3298 apss_tpdm0_out: endpoint { 3299 remote-endpoint = 3300 <&apss_tpda_in0>; 3301 }; 3302 }; 3303 }; 3304 }; 3305 3306 tpdm@68b0000 { 3307 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3308 reg = <0x0 0x68b0000 0x0 0x1000>; 3309 3310 clocks = <&aoss_qmp>; 3311 clock-names = "apb_pclk"; 3312 3313 qcom,cmb-element-bits = <32>; 3314 qcom,cmb-msrs-num = <32>; 3315 3316 out-ports { 3317 port { 3318 apss_tpdm1_out: endpoint { 3319 remote-endpoint = 3320 <&apss_tpda_in1>; 3321 }; 3322 }; 3323 }; 3324 }; 3325 3326 tpdm@68c0000 { 3327 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3328 reg = <0x0 0x68c0000 0x0 0x1000>; 3329 3330 clocks = <&aoss_qmp>; 3331 clock-names = "apb_pclk"; 3332 3333 qcom,dsb-element-bits = <32>; 3334 qcom,dsb-msrs-num = <32>; 3335 3336 out-ports { 3337 port { 3338 apss_tpdm2_out: endpoint { 3339 remote-endpoint = 3340 <&apss_tpda_in2>; 3341 }; 3342 }; 3343 }; 3344 }; 3345 3346 usb_0_hsphy: phy@88e4000 { 3347 compatible = "qcom,sa8775p-usb-hs-phy", 3348 "qcom,usb-snps-hs-5nm-phy"; 3349 reg = <0 0x088e4000 0 0x120>; 3350 clocks = <&rpmhcc RPMH_CXO_CLK>; 3351 clock-names = "ref"; 3352 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 3353 3354 #phy-cells = <0>; 3355 3356 status = "disabled"; 3357 }; 3358 3359 usb_0_qmpphy: phy@88e8000 { 3360 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 3361 reg = <0 0x088e8000 0 0x2000>; 3362 3363 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3364 <&gcc GCC_USB_CLKREF_EN>, 3365 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3366 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3367 clock-names = "aux", "ref", "com_aux", "pipe"; 3368 3369 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3370 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 3371 reset-names = "phy", "phy_phy"; 3372 3373 power-domains = <&gcc USB30_PRIM_GDSC>; 3374 3375 #clock-cells = <0>; 3376 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 3377 3378 #phy-cells = <0>; 3379 3380 status = "disabled"; 3381 }; 3382 3383 usb_0: usb@a6f8800 { 3384 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 3385 reg = <0 0x0a6f8800 0 0x400>; 3386 #address-cells = <2>; 3387 #size-cells = <2>; 3388 ranges; 3389 3390 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3391 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3392 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3393 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3394 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3395 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3396 3397 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3398 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3399 assigned-clock-rates = <19200000>, <200000000>; 3400 3401 interrupts-extended = <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 3402 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3403 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3404 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3405 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 3406 interrupt-names = "pwr_event", 3407 "hs_phy_irq", 3408 "dp_hs_phy_irq", 3409 "dm_hs_phy_irq", 3410 "ss_phy_irq"; 3411 3412 power-domains = <&gcc USB30_PRIM_GDSC>; 3413 required-opps = <&rpmhpd_opp_nom>; 3414 3415 resets = <&gcc GCC_USB30_PRIM_BCR>; 3416 3417 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3418 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3419 interconnect-names = "usb-ddr", "apps-usb"; 3420 3421 wakeup-source; 3422 3423 status = "disabled"; 3424 3425 usb_0_dwc3: usb@a600000 { 3426 compatible = "snps,dwc3"; 3427 reg = <0 0x0a600000 0 0xe000>; 3428 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>; 3429 iommus = <&apps_smmu 0x080 0x0>; 3430 phys = <&usb_0_hsphy>, <&usb_0_qmpphy>; 3431 phy-names = "usb2-phy", "usb3-phy"; 3432 snps,dis-u1-entry-quirk; 3433 snps,dis-u2-entry-quirk; 3434 }; 3435 }; 3436 3437 usb_1_hsphy: phy@88e6000 { 3438 compatible = "qcom,sa8775p-usb-hs-phy", 3439 "qcom,usb-snps-hs-5nm-phy"; 3440 reg = <0 0x088e6000 0 0x120>; 3441 clocks = <&gcc GCC_USB_CLKREF_EN>; 3442 clock-names = "ref"; 3443 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 3444 3445 #phy-cells = <0>; 3446 3447 status = "disabled"; 3448 }; 3449 3450 usb_1_qmpphy: phy@88ea000 { 3451 compatible = "qcom,sa8775p-qmp-usb3-uni-phy"; 3452 reg = <0 0x088ea000 0 0x2000>; 3453 3454 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3455 <&gcc GCC_USB_CLKREF_EN>, 3456 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3457 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3458 clock-names = "aux", "ref", "com_aux", "pipe"; 3459 3460 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3461 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3462 reset-names = "phy", "phy_phy"; 3463 3464 power-domains = <&gcc USB30_SEC_GDSC>; 3465 3466 #clock-cells = <0>; 3467 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 3468 3469 #phy-cells = <0>; 3470 3471 status = "disabled"; 3472 }; 3473 3474 usb_1: usb@a8f8800 { 3475 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 3476 reg = <0 0x0a8f8800 0 0x400>; 3477 #address-cells = <2>; 3478 #size-cells = <2>; 3479 ranges; 3480 3481 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3482 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3483 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3484 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3485 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3486 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3487 3488 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3489 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3490 assigned-clock-rates = <19200000>, <200000000>; 3491 3492 interrupts-extended = <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 3493 <&intc GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 3494 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3495 <&pdc 7 IRQ_TYPE_EDGE_BOTH>, 3496 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>; 3497 interrupt-names = "pwr_event", 3498 "hs_phy_irq", 3499 "dp_hs_phy_irq", 3500 "dm_hs_phy_irq", 3501 "ss_phy_irq"; 3502 3503 power-domains = <&gcc USB30_SEC_GDSC>; 3504 required-opps = <&rpmhpd_opp_nom>; 3505 3506 resets = <&gcc GCC_USB30_SEC_BCR>; 3507 3508 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3509 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3510 interconnect-names = "usb-ddr", "apps-usb"; 3511 3512 wakeup-source; 3513 3514 status = "disabled"; 3515 3516 usb_1_dwc3: usb@a800000 { 3517 compatible = "snps,dwc3"; 3518 reg = <0 0x0a800000 0 0xe000>; 3519 interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 3520 iommus = <&apps_smmu 0x0a0 0x0>; 3521 phys = <&usb_1_hsphy>, <&usb_1_qmpphy>; 3522 phy-names = "usb2-phy", "usb3-phy"; 3523 snps,dis-u1-entry-quirk; 3524 snps,dis-u2-entry-quirk; 3525 }; 3526 }; 3527 3528 usb_2_hsphy: phy@88e7000 { 3529 compatible = "qcom,sa8775p-usb-hs-phy", 3530 "qcom,usb-snps-hs-5nm-phy"; 3531 reg = <0 0x088e7000 0 0x120>; 3532 clocks = <&gcc GCC_USB_CLKREF_EN>; 3533 clock-names = "ref"; 3534 resets = <&gcc GCC_USB3_PHY_TERT_BCR>; 3535 3536 #phy-cells = <0>; 3537 3538 status = "disabled"; 3539 }; 3540 3541 usb_2: usb@a4f8800 { 3542 compatible = "qcom,sa8775p-dwc3", "qcom,dwc3"; 3543 reg = <0 0x0a4f8800 0 0x400>; 3544 #address-cells = <2>; 3545 #size-cells = <2>; 3546 ranges; 3547 3548 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 3549 <&gcc GCC_USB20_MASTER_CLK>, 3550 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 3551 <&gcc GCC_USB20_SLEEP_CLK>, 3552 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 3553 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi"; 3554 3555 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 3556 <&gcc GCC_USB20_MASTER_CLK>; 3557 assigned-clock-rates = <19200000>, <200000000>; 3558 3559 interrupts-extended = <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 3560 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 3561 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 3562 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 3563 interrupt-names = "pwr_event", 3564 "hs_phy_irq", 3565 "dp_hs_phy_irq", 3566 "dm_hs_phy_irq"; 3567 3568 power-domains = <&gcc USB20_PRIM_GDSC>; 3569 required-opps = <&rpmhpd_opp_nom>; 3570 3571 resets = <&gcc GCC_USB20_PRIM_BCR>; 3572 3573 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3574 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB2 0>; 3575 interconnect-names = "usb-ddr", "apps-usb"; 3576 3577 wakeup-source; 3578 3579 status = "disabled"; 3580 3581 usb_2_dwc3: usb@a400000 { 3582 compatible = "snps,dwc3"; 3583 reg = <0 0x0a400000 0 0xe000>; 3584 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>; 3585 iommus = <&apps_smmu 0x020 0x0>; 3586 phys = <&usb_2_hsphy>; 3587 phy-names = "usb2-phy"; 3588 snps,dis-u1-entry-quirk; 3589 snps,dis-u2-entry-quirk; 3590 }; 3591 }; 3592 3593 tcsr_mutex: hwlock@1f40000 { 3594 compatible = "qcom,tcsr-mutex"; 3595 reg = <0x0 0x01f40000 0x0 0x20000>; 3596 #hwlock-cells = <1>; 3597 }; 3598 3599 tcsr: syscon@1fc0000 { 3600 compatible = "qcom,sa8775p-tcsr", "syscon"; 3601 reg = <0x0 0x1fc0000 0x0 0x30000>; 3602 }; 3603 3604 gpucc: clock-controller@3d90000 { 3605 compatible = "qcom,sa8775p-gpucc"; 3606 reg = <0x0 0x03d90000 0x0 0xa000>; 3607 clocks = <&rpmhcc RPMH_CXO_CLK>, 3608 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3609 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3610 clock-names = "bi_tcxo", 3611 "gcc_gpu_gpll0_clk_src", 3612 "gcc_gpu_gpll0_div_clk_src"; 3613 #clock-cells = <1>; 3614 #reset-cells = <1>; 3615 #power-domain-cells = <1>; 3616 }; 3617 3618 adreno_smmu: iommu@3da0000 { 3619 compatible = "qcom,sa8775p-smmu-500", "qcom,adreno-smmu", 3620 "qcom,smmu-500", "arm,mmu-500"; 3621 reg = <0x0 0x03da0000 0x0 0x20000>; 3622 #iommu-cells = <2>; 3623 #global-interrupts = <2>; 3624 dma-coherent; 3625 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3626 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3627 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3628 <&gpucc GPU_CC_AHB_CLK>, 3629 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3630 <&gpucc GPU_CC_CX_GMU_CLK>, 3631 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3632 <&gpucc GPU_CC_HUB_AON_CLK>; 3633 clock-names = "gcc_gpu_memnoc_gfx_clk", 3634 "gcc_gpu_snoc_dvm_gfx_clk", 3635 "gpu_cc_ahb_clk", 3636 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3637 "gpu_cc_cx_gmu_clk", 3638 "gpu_cc_hub_cx_int_clk", 3639 "gpu_cc_hub_aon_clk"; 3640 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 3652 }; 3653 3654 serdes0: phy@8901000 { 3655 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 3656 reg = <0x0 0x08901000 0x0 0xe10>; 3657 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 3658 clock-names = "sgmi_ref"; 3659 #phy-cells = <0>; 3660 status = "disabled"; 3661 }; 3662 3663 serdes1: phy@8902000 { 3664 compatible = "qcom,sa8775p-dwmac-sgmii-phy"; 3665 reg = <0x0 0x08902000 0x0 0xe10>; 3666 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 3667 clock-names = "sgmi_ref"; 3668 #phy-cells = <0>; 3669 status = "disabled"; 3670 }; 3671 3672 pmu@9091000 { 3673 compatible = "qcom,sa8775p-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3674 reg = <0x0 0x9091000 0x0 0x1000>; 3675 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 3676 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3677 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3678 3679 operating-points-v2 = <&llcc_bwmon_opp_table>; 3680 3681 llcc_bwmon_opp_table: opp-table { 3682 compatible = "operating-points-v2"; 3683 3684 opp-0 { 3685 opp-peak-kBps = <762000>; 3686 }; 3687 3688 opp-1 { 3689 opp-peak-kBps = <1720000>; 3690 }; 3691 3692 opp-2 { 3693 opp-peak-kBps = <2086000>; 3694 }; 3695 3696 opp-3 { 3697 opp-peak-kBps = <2601000>; 3698 }; 3699 3700 opp-4 { 3701 opp-peak-kBps = <2929000>; 3702 }; 3703 3704 opp-5 { 3705 opp-peak-kBps = <5931000>; 3706 }; 3707 3708 opp-6 { 3709 opp-peak-kBps = <6515000>; 3710 }; 3711 3712 opp-7 { 3713 opp-peak-kBps = <7984000>; 3714 }; 3715 3716 opp-8 { 3717 opp-peak-kBps = <10437000>; 3718 }; 3719 3720 opp-9 { 3721 opp-peak-kBps = <12195000>; 3722 }; 3723 }; 3724 }; 3725 3726 pmu@90b5400 { 3727 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 3728 reg = <0x0 0x90b5400 0x0 0x600>; 3729 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3730 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3731 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3732 3733 operating-points-v2 = <&cpu_bwmon_opp_table>; 3734 3735 cpu_bwmon_opp_table: opp-table { 3736 compatible = "operating-points-v2"; 3737 3738 opp-0 { 3739 opp-peak-kBps = <9155000>; 3740 }; 3741 3742 opp-1 { 3743 opp-peak-kBps = <12298000>; 3744 }; 3745 3746 opp-2 { 3747 opp-peak-kBps = <14236000>; 3748 }; 3749 3750 opp-3 { 3751 opp-peak-kBps = <16265000>; 3752 }; 3753 }; 3754 3755 }; 3756 3757 pmu@90b6400 { 3758 compatible = "qcom,sa8775p-cpu-bwmon", "qcom,sdm845-bwmon"; 3759 reg = <0x0 0x90b6400 0x0 0x600>; 3760 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3761 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3762 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3763 3764 operating-points-v2 = <&cpu_bwmon_opp_table>; 3765 }; 3766 3767 llcc: system-cache-controller@9200000 { 3768 compatible = "qcom,sa8775p-llcc"; 3769 reg = <0x0 0x09200000 0x0 0x80000>, 3770 <0x0 0x09300000 0x0 0x80000>, 3771 <0x0 0x09400000 0x0 0x80000>, 3772 <0x0 0x09500000 0x0 0x80000>, 3773 <0x0 0x09600000 0x0 0x80000>, 3774 <0x0 0x09700000 0x0 0x80000>, 3775 <0x0 0x09a00000 0x0 0x80000>; 3776 reg-names = "llcc0_base", 3777 "llcc1_base", 3778 "llcc2_base", 3779 "llcc3_base", 3780 "llcc4_base", 3781 "llcc5_base", 3782 "llcc_broadcast_base"; 3783 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 3784 }; 3785 3786 videocc: clock-controller@abf0000 { 3787 compatible = "qcom,sa8775p-videocc"; 3788 reg = <0x0 0x0abf0000 0x0 0x10000>; 3789 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3790 <&rpmhcc RPMH_CXO_CLK>, 3791 <&rpmhcc RPMH_CXO_CLK_A>, 3792 <&sleep_clk>; 3793 power-domains = <&rpmhpd SA8775P_MMCX>; 3794 #clock-cells = <1>; 3795 #reset-cells = <1>; 3796 #power-domain-cells = <1>; 3797 }; 3798 3799 camcc: clock-controller@ade0000 { 3800 compatible = "qcom,sa8775p-camcc"; 3801 reg = <0x0 0x0ade0000 0x0 0x20000>; 3802 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3803 <&rpmhcc RPMH_CXO_CLK>, 3804 <&rpmhcc RPMH_CXO_CLK_A>, 3805 <&sleep_clk>; 3806 power-domains = <&rpmhpd SA8775P_MMCX>; 3807 #clock-cells = <1>; 3808 #reset-cells = <1>; 3809 #power-domain-cells = <1>; 3810 }; 3811 3812 mdss0: display-subsystem@ae00000 { 3813 compatible = "qcom,sa8775p-mdss"; 3814 reg = <0x0 0x0ae00000 0x0 0x1000>; 3815 reg-names = "mdss"; 3816 3817 /* same path used twice */ 3818 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 3819 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3820 <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ACTIVE_ONLY 3821 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 3822 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3823 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3824 interconnect-names = "mdp0-mem", 3825 "mdp1-mem", 3826 "cpu-cfg"; 3827 3828 resets = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_BCR>; 3829 3830 power-domains = <&dispcc0 MDSS_DISP_CC_MDSS_CORE_GDSC>; 3831 3832 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 3833 <&gcc GCC_DISP_HF_AXI_CLK>, 3834 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>; 3835 3836 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 3837 interrupt-controller; 3838 #interrupt-cells = <1>; 3839 3840 iommus = <&apps_smmu 0x1000 0x402>; 3841 3842 #address-cells = <2>; 3843 #size-cells = <2>; 3844 ranges; 3845 3846 status = "disabled"; 3847 3848 mdss0_mdp: display-controller@ae01000 { 3849 compatible = "qcom,sa8775p-dpu"; 3850 reg = <0x0 0x0ae01000 0x0 0x8f000>, 3851 <0x0 0x0aeb0000 0x0 0x2008>; 3852 reg-names = "mdp", "vbif"; 3853 3854 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3855 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 3856 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 3857 <&dispcc0 MDSS_DISP_CC_MDSS_MDP_CLK>, 3858 <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 3859 clock-names = "bus", 3860 "iface", 3861 "lut", 3862 "core", 3863 "vsync"; 3864 3865 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_VSYNC_CLK>; 3866 assigned-clock-rates = <19200000>; 3867 3868 operating-points-v2 = <&mdss0_mdp_opp_table>; 3869 power-domains = <&rpmhpd SA8775P_MMCX>; 3870 3871 interrupt-parent = <&mdss0>; 3872 interrupts = <0>; 3873 3874 ports { 3875 #address-cells = <1>; 3876 #size-cells = <0>; 3877 3878 port@0 { 3879 reg = <0>; 3880 3881 dpu_intf0_out: endpoint { 3882 remote-endpoint = <&mdss0_dp0_in>; 3883 }; 3884 }; 3885 3886 port@1 { 3887 reg = <1>; 3888 3889 dpu_intf4_out: endpoint { 3890 remote-endpoint = <&mdss0_dp1_in>; 3891 }; 3892 }; 3893 }; 3894 3895 mdss0_mdp_opp_table: opp-table { 3896 compatible = "operating-points-v2"; 3897 3898 opp-375000000 { 3899 opp-hz = /bits/ 64 <375000000>; 3900 required-opps = <&rpmhpd_opp_svs_l1>; 3901 }; 3902 3903 opp-500000000 { 3904 opp-hz = /bits/ 64 <500000000>; 3905 required-opps = <&rpmhpd_opp_nom>; 3906 }; 3907 3908 opp-575000000 { 3909 opp-hz = /bits/ 64 <575000000>; 3910 required-opps = <&rpmhpd_opp_turbo>; 3911 }; 3912 3913 opp-650000000 { 3914 opp-hz = /bits/ 64 <650000000>; 3915 required-opps = <&rpmhpd_opp_turbo_l1>; 3916 }; 3917 }; 3918 }; 3919 3920 mdss0_dp0_phy: phy@aec2a00 { 3921 compatible = "qcom,sa8775p-edp-phy"; 3922 3923 reg = <0x0 0x0aec2a00 0x0 0x200>, 3924 <0x0 0x0aec2200 0x0 0xd0>, 3925 <0x0 0x0aec2600 0x0 0xd0>, 3926 <0x0 0x0aec2000 0x0 0x1c8>; 3927 3928 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 3929 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; 3930 clock-names = "aux", 3931 "cfg_ahb"; 3932 3933 #clock-cells = <1>; 3934 #phy-cells = <0>; 3935 3936 status = "disabled"; 3937 }; 3938 3939 mdss0_dp1_phy: phy@aec5a00 { 3940 compatible = "qcom,sa8775p-edp-phy"; 3941 3942 reg = <0x0 0x0aec5a00 0x0 0x200>, 3943 <0x0 0x0aec5200 0x0 0xd0>, 3944 <0x0 0x0aec5600 0x0 0xd0>, 3945 <0x0 0x0aec5000 0x0 0x1c8>; 3946 3947 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 3948 <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; 3949 clock-names = "aux", 3950 "cfg_ahb"; 3951 3952 #clock-cells = <1>; 3953 #phy-cells = <0>; 3954 3955 status = "disabled"; 3956 }; 3957 3958 mdss0_dp0: displayport-controller@af54000 { 3959 compatible = "qcom,sa8775p-dp"; 3960 3961 reg = <0x0 0x0af54000 0x0 0x104>, 3962 <0x0 0x0af54200 0x0 0x0c0>, 3963 <0x0 0x0af55000 0x0 0x770>, 3964 <0x0 0x0af56000 0x0 0x09c>, 3965 <0x0 0x0af57000 0x0 0x09c>; 3966 3967 interrupt-parent = <&mdss0>; 3968 interrupts = <12>; 3969 3970 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 3971 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 3972 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 3973 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3974 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3975 clock-names = "core_iface", 3976 "core_aux", 3977 "ctrl_link", 3978 "ctrl_link_iface", 3979 "stream_pixel"; 3980 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3981 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3982 assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; 3983 phys = <&mdss0_dp0_phy>; 3984 phy-names = "dp"; 3985 3986 operating-points-v2 = <&dp_opp_table>; 3987 power-domains = <&rpmhpd SA8775P_MMCX>; 3988 3989 #sound-dai-cells = <0>; 3990 3991 status = "disabled"; 3992 3993 ports { 3994 #address-cells = <1>; 3995 #size-cells = <0>; 3996 3997 port@0 { 3998 reg = <0>; 3999 4000 mdss0_dp0_in: endpoint { 4001 remote-endpoint = <&dpu_intf0_out>; 4002 }; 4003 }; 4004 4005 port@1 { 4006 reg = <1>; 4007 4008 mdss0_dp0_out: endpoint { }; 4009 }; 4010 }; 4011 4012 dp_opp_table: opp-table { 4013 compatible = "operating-points-v2"; 4014 4015 opp-160000000 { 4016 opp-hz = /bits/ 64 <160000000>; 4017 required-opps = <&rpmhpd_opp_low_svs>; 4018 }; 4019 4020 opp-270000000 { 4021 opp-hz = /bits/ 64 <270000000>; 4022 required-opps = <&rpmhpd_opp_svs>; 4023 }; 4024 4025 opp-540000000 { 4026 opp-hz = /bits/ 64 <540000000>; 4027 required-opps = <&rpmhpd_opp_svs_l1>; 4028 }; 4029 4030 opp-810000000 { 4031 opp-hz = /bits/ 64 <810000000>; 4032 required-opps = <&rpmhpd_opp_nom>; 4033 }; 4034 }; 4035 }; 4036 4037 mdss0_dp1: displayport-controller@af5c000 { 4038 compatible = "qcom,sa8775p-dp"; 4039 4040 reg = <0x0 0x0af5c000 0x0 0x104>, 4041 <0x0 0x0af5c200 0x0 0x0c0>, 4042 <0x0 0x0af5d000 0x0 0x770>, 4043 <0x0 0x0af5e000 0x0 0x09c>, 4044 <0x0 0x0af5f000 0x0 0x09c>; 4045 4046 interrupt-parent = <&mdss0>; 4047 interrupts = <13>; 4048 4049 clocks = <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, 4050 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>, 4051 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>, 4052 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4053 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4054 clock-names = "core_iface", 4055 "core_aux", 4056 "ctrl_link", 4057 "ctrl_link_iface", 4058 "stream_pixel"; 4059 assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4060 <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4061 assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>; 4062 phys = <&mdss0_dp1_phy>; 4063 phy-names = "dp"; 4064 4065 operating-points-v2 = <&dp1_opp_table>; 4066 power-domains = <&rpmhpd SA8775P_MMCX>; 4067 4068 #sound-dai-cells = <0>; 4069 4070 status = "disabled"; 4071 4072 ports { 4073 #address-cells = <1>; 4074 #size-cells = <0>; 4075 4076 port@0 { 4077 reg = <0>; 4078 4079 mdss0_dp1_in: endpoint { 4080 remote-endpoint = <&dpu_intf4_out>; 4081 }; 4082 }; 4083 4084 port@1 { 4085 reg = <1>; 4086 4087 mdss0_dp1_out: endpoint { }; 4088 }; 4089 }; 4090 4091 dp1_opp_table: opp-table { 4092 compatible = "operating-points-v2"; 4093 4094 opp-160000000 { 4095 opp-hz = /bits/ 64 <160000000>; 4096 required-opps = <&rpmhpd_opp_low_svs>; 4097 }; 4098 4099 opp-270000000 { 4100 opp-hz = /bits/ 64 <270000000>; 4101 required-opps = <&rpmhpd_opp_svs>; 4102 }; 4103 4104 opp-540000000 { 4105 opp-hz = /bits/ 64 <540000000>; 4106 required-opps = <&rpmhpd_opp_svs_l1>; 4107 }; 4108 4109 opp-810000000 { 4110 opp-hz = /bits/ 64 <810000000>; 4111 required-opps = <&rpmhpd_opp_nom>; 4112 }; 4113 }; 4114 }; 4115 }; 4116 4117 dispcc0: clock-controller@af00000 { 4118 compatible = "qcom,sa8775p-dispcc0"; 4119 reg = <0x0 0x0af00000 0x0 0x20000>; 4120 clocks = <&gcc GCC_DISP_AHB_CLK>, 4121 <&rpmhcc RPMH_CXO_CLK>, 4122 <&rpmhcc RPMH_CXO_CLK_A>, 4123 <&sleep_clk>, 4124 <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>, 4125 <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>, 4126 <0>, <0>, <0>, <0>; 4127 power-domains = <&rpmhpd SA8775P_MMCX>; 4128 #clock-cells = <1>; 4129 #reset-cells = <1>; 4130 #power-domain-cells = <1>; 4131 }; 4132 4133 pdc: interrupt-controller@b220000 { 4134 compatible = "qcom,sa8775p-pdc", "qcom,pdc"; 4135 reg = <0x0 0x0b220000 0x0 0x30000>, 4136 <0x0 0x17c000f0 0x0 0x64>; 4137 qcom,pdc-ranges = <0 480 40>, 4138 <40 140 14>, 4139 <54 263 1>, 4140 <55 306 4>, 4141 <59 312 3>, 4142 <62 374 2>, 4143 <64 434 2>, 4144 <66 438 2>, 4145 <70 520 1>, 4146 <73 523 1>, 4147 <118 568 6>, 4148 <124 609 3>, 4149 <159 638 1>, 4150 <160 720 3>, 4151 <169 728 30>, 4152 <199 416 2>, 4153 <201 449 1>, 4154 <202 89 1>, 4155 <203 451 1>, 4156 <204 462 1>, 4157 <205 264 1>, 4158 <206 579 1>, 4159 <207 653 1>, 4160 <208 656 1>, 4161 <209 659 1>, 4162 <210 122 1>, 4163 <211 699 1>, 4164 <212 705 1>, 4165 <213 450 1>, 4166 <214 643 2>, 4167 <216 646 5>, 4168 <221 390 5>, 4169 <226 700 2>, 4170 <228 440 1>, 4171 <229 663 1>, 4172 <230 524 2>, 4173 <232 612 3>, 4174 <235 723 5>; 4175 #interrupt-cells = <2>; 4176 interrupt-parent = <&intc>; 4177 interrupt-controller; 4178 }; 4179 4180 tsens2: thermal-sensor@c251000 { 4181 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 4182 reg = <0x0 0x0c251000 0x0 0x1ff>, 4183 <0x0 0x0c224000 0x0 0x8>; 4184 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 4185 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 4186 #qcom,sensors = <13>; 4187 interrupt-names = "uplow", "critical"; 4188 #thermal-sensor-cells = <1>; 4189 }; 4190 4191 tsens3: thermal-sensor@c252000 { 4192 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 4193 reg = <0x0 0x0c252000 0x0 0x1ff>, 4194 <0x0 0x0c225000 0x0 0x8>; 4195 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 4197 #qcom,sensors = <13>; 4198 interrupt-names = "uplow", "critical"; 4199 #thermal-sensor-cells = <1>; 4200 }; 4201 4202 tsens0: thermal-sensor@c263000 { 4203 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 4204 reg = <0x0 0x0c263000 0x0 0x1ff>, 4205 <0x0 0x0c222000 0x0 0x8>; 4206 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4207 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4208 #qcom,sensors = <12>; 4209 interrupt-names = "uplow", "critical"; 4210 #thermal-sensor-cells = <1>; 4211 }; 4212 4213 tsens1: thermal-sensor@c265000 { 4214 compatible = "qcom,sa8775p-tsens", "qcom,tsens-v2"; 4215 reg = <0x0 0x0c265000 0x0 0x1ff>, 4216 <0x0 0x0c223000 0x0 0x8>; 4217 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4218 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4219 #qcom,sensors = <12>; 4220 interrupt-names = "uplow", "critical"; 4221 #thermal-sensor-cells = <1>; 4222 }; 4223 4224 aoss_qmp: power-management@c300000 { 4225 compatible = "qcom,sa8775p-aoss-qmp", "qcom,aoss-qmp"; 4226 reg = <0x0 0x0c300000 0x0 0x400>; 4227 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4228 IPCC_MPROC_SIGNAL_GLINK_QMP 4229 IRQ_TYPE_EDGE_RISING>; 4230 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4231 #clock-cells = <0>; 4232 }; 4233 4234 sram@c3f0000 { 4235 compatible = "qcom,rpmh-stats"; 4236 reg = <0x0 0x0c3f0000 0x0 0x400>; 4237 }; 4238 4239 spmi_bus: spmi@c440000 { 4240 compatible = "qcom,spmi-pmic-arb"; 4241 reg = <0x0 0x0c440000 0x0 0x1100>, 4242 <0x0 0x0c600000 0x0 0x2000000>, 4243 <0x0 0x0e600000 0x0 0x100000>, 4244 <0x0 0x0e700000 0x0 0xa0000>, 4245 <0x0 0x0c40a000 0x0 0x26000>; 4246 reg-names = "core", 4247 "chnls", 4248 "obsrvr", 4249 "intr", 4250 "cnfg"; 4251 qcom,channel = <0>; 4252 qcom,ee = <0>; 4253 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4254 interrupt-names = "periph_irq"; 4255 interrupt-controller; 4256 #interrupt-cells = <4>; 4257 #address-cells = <2>; 4258 #size-cells = <0>; 4259 }; 4260 4261 tlmm: pinctrl@f000000 { 4262 compatible = "qcom,sa8775p-tlmm"; 4263 reg = <0x0 0x0f000000 0x0 0x1000000>; 4264 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4265 gpio-controller; 4266 #gpio-cells = <2>; 4267 interrupt-controller; 4268 #interrupt-cells = <2>; 4269 gpio-ranges = <&tlmm 0 0 149>; 4270 wakeup-parent = <&pdc>; 4271 }; 4272 4273 sram: sram@146d8000 { 4274 compatible = "qcom,sa8775p-imem", "syscon", "simple-mfd"; 4275 reg = <0x0 0x146d8000 0x0 0x1000>; 4276 ranges = <0x0 0x0 0x146d8000 0x1000>; 4277 4278 #address-cells = <1>; 4279 #size-cells = <1>; 4280 4281 pil-reloc@94c { 4282 compatible = "qcom,pil-reloc-info"; 4283 reg = <0x94c 0xc8>; 4284 }; 4285 }; 4286 4287 apps_smmu: iommu@15000000 { 4288 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4289 reg = <0x0 0x15000000 0x0 0x100000>; 4290 #iommu-cells = <2>; 4291 #global-interrupts = <2>; 4292 dma-coherent; 4293 4294 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4299 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4300 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4303 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4304 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4305 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4306 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4307 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4308 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4309 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4311 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4312 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4313 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4315 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4316 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4317 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4318 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4319 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4320 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4321 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4322 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4323 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4324 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4325 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4326 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4327 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4328 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4329 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4330 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4331 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4332 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4333 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4334 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4335 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4336 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4337 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4340 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4341 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4342 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4343 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4344 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4346 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4347 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4348 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4349 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4350 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4351 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4352 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4353 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4354 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4357 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4360 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4361 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4362 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4363 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4364 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4365 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4366 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4367 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4368 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4369 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4370 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4371 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4372 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4373 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4374 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4375 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4376 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4377 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4378 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4379 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4380 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4381 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4382 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4383 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4384 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4385 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4386 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4387 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 4388 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 4389 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4390 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 4391 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4392 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4393 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 4394 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 4395 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 4396 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 4397 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4398 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 4399 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 4400 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 4401 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 4402 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 4403 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 4404 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 4405 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 4406 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 4407 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 4408 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 4409 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 4410 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 4411 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 4412 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 4413 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 4414 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 4415 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 4416 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 4417 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 4418 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 4419 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 4420 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 4421 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 4422 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 4423 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; 4424 }; 4425 4426 pcie_smmu: iommu@15200000 { 4427 compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4428 reg = <0x0 0x15200000 0x0 0x80000>; 4429 #iommu-cells = <2>; 4430 #global-interrupts = <2>; 4431 dma-coherent; 4432 4433 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 4434 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 4435 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 4436 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 4437 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 4438 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 4439 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 4440 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 4441 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 4442 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 4443 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 4444 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 4445 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 4446 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 4447 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 4448 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 4449 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 4450 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 4451 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 4452 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 4453 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 4454 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 4455 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 4456 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 4457 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 4458 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 4459 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 4460 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 4461 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 4462 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 4463 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 4464 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 4465 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 4466 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 4467 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 4468 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 4469 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 4470 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 4471 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 4472 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 4473 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 4474 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 4475 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 4476 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 4477 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 4478 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 4479 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 4480 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 4481 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 4482 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 4483 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 4484 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 4485 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 4486 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 4487 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 4488 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 4489 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 4490 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 4491 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 4492 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 4493 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 4494 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 4495 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 4496 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 4497 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 4498 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 4499 }; 4500 4501 intc: interrupt-controller@17a00000 { 4502 compatible = "arm,gic-v3"; 4503 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4504 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4505 interrupt-controller; 4506 #interrupt-cells = <3>; 4507 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4508 #redistributor-regions = <1>; 4509 redistributor-stride = <0x0 0x20000>; 4510 }; 4511 4512 watchdog@17c10000 { 4513 compatible = "qcom,apss-wdt-sa8775p", "qcom,kpss-wdt"; 4514 reg = <0x0 0x17c10000 0x0 0x1000>; 4515 clocks = <&sleep_clk>; 4516 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4517 }; 4518 4519 memtimer: timer@17c20000 { 4520 compatible = "arm,armv7-timer-mem"; 4521 reg = <0x0 0x17c20000 0x0 0x1000>; 4522 ranges = <0x0 0x0 0x0 0x20000000>; 4523 #address-cells = <1>; 4524 #size-cells = <1>; 4525 4526 frame@17c21000 { 4527 reg = <0x17c21000 0x1000>, 4528 <0x17c22000 0x1000>; 4529 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4530 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4531 frame-number = <0>; 4532 }; 4533 4534 frame@17c23000 { 4535 reg = <0x17c23000 0x1000>; 4536 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4537 frame-number = <1>; 4538 status = "disabled"; 4539 }; 4540 4541 frame@17c25000 { 4542 reg = <0x17c25000 0x1000>; 4543 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4544 frame-number = <2>; 4545 status = "disabled"; 4546 }; 4547 4548 frame@17c27000 { 4549 reg = <0x17c27000 0x1000>; 4550 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4551 frame-number = <3>; 4552 status = "disabled"; 4553 }; 4554 4555 frame@17c29000 { 4556 reg = <0x17c29000 0x1000>; 4557 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4558 frame-number = <4>; 4559 status = "disabled"; 4560 }; 4561 4562 frame@17c2b000 { 4563 reg = <0x17c2b000 0x1000>; 4564 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4565 frame-number = <5>; 4566 status = "disabled"; 4567 }; 4568 4569 frame@17c2d000 { 4570 reg = <0x17c2d000 0x1000>; 4571 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4572 frame-number = <6>; 4573 status = "disabled"; 4574 }; 4575 }; 4576 4577 apps_rsc: rsc@18200000 { 4578 compatible = "qcom,rpmh-rsc"; 4579 reg = <0x0 0x18200000 0x0 0x10000>, 4580 <0x0 0x18210000 0x0 0x10000>, 4581 <0x0 0x18220000 0x0 0x10000>; 4582 reg-names = "drv-0", "drv-1", "drv-2"; 4583 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4584 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4585 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4586 qcom,tcs-offset = <0xd00>; 4587 qcom,drv-id = <2>; 4588 qcom,tcs-config = <ACTIVE_TCS 2>, 4589 <SLEEP_TCS 3>, 4590 <WAKE_TCS 3>, 4591 <CONTROL_TCS 0>; 4592 label = "apps_rsc"; 4593 4594 apps_bcm_voter: bcm-voter { 4595 compatible = "qcom,bcm-voter"; 4596 }; 4597 4598 rpmhcc: clock-controller { 4599 compatible = "qcom,sa8775p-rpmh-clk"; 4600 #clock-cells = <1>; 4601 clock-names = "xo"; 4602 clocks = <&xo_board_clk>; 4603 }; 4604 4605 rpmhpd: power-controller { 4606 compatible = "qcom,sa8775p-rpmhpd"; 4607 #power-domain-cells = <1>; 4608 operating-points-v2 = <&rpmhpd_opp_table>; 4609 4610 rpmhpd_opp_table: opp-table { 4611 compatible = "operating-points-v2"; 4612 4613 rpmhpd_opp_ret: opp-0 { 4614 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4615 }; 4616 4617 rpmhpd_opp_min_svs: opp-1 { 4618 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4619 }; 4620 4621 rpmhpd_opp_low_svs: opp2 { 4622 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4623 }; 4624 4625 rpmhpd_opp_svs: opp3 { 4626 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4627 }; 4628 4629 rpmhpd_opp_svs_l1: opp-4 { 4630 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4631 }; 4632 4633 rpmhpd_opp_nom: opp-5 { 4634 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4635 }; 4636 4637 rpmhpd_opp_nom_l1: opp-6 { 4638 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4639 }; 4640 4641 rpmhpd_opp_nom_l2: opp-7 { 4642 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4643 }; 4644 4645 rpmhpd_opp_turbo: opp-8 { 4646 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4647 }; 4648 4649 rpmhpd_opp_turbo_l1: opp-9 { 4650 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4651 }; 4652 }; 4653 }; 4654 }; 4655 4656 cpufreq_hw: cpufreq@18591000 { 4657 compatible = "qcom,sa8775p-cpufreq-epss", 4658 "qcom,cpufreq-epss"; 4659 reg = <0x0 0x18591000 0x0 0x1000>, 4660 <0x0 0x18593000 0x0 0x1000>; 4661 reg-names = "freq-domain0", "freq-domain1"; 4662 4663 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4664 clock-names = "xo", "alternate"; 4665 4666 #freq-domain-cells = <1>; 4667 }; 4668 4669 remoteproc_gpdsp0: remoteproc@20c00000 { 4670 compatible = "qcom,sa8775p-gpdsp0-pas"; 4671 reg = <0x0 0x20c00000 0x0 0x10000>; 4672 4673 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 4674 <&smp2p_gpdsp0_in 0 0>, 4675 <&smp2p_gpdsp0_in 2 0>, 4676 <&smp2p_gpdsp0_in 1 0>, 4677 <&smp2p_gpdsp0_in 3 0>; 4678 interrupt-names = "wdog", "fatal", "ready", 4679 "handover", "stop-ack"; 4680 4681 clocks = <&rpmhcc RPMH_CXO_CLK>; 4682 clock-names = "xo"; 4683 4684 power-domains = <&rpmhpd RPMHPD_CX>, 4685 <&rpmhpd RPMHPD_MXC>; 4686 power-domain-names = "cx", "mxc"; 4687 4688 interconnects = <&gpdsp_anoc MASTER_DSP0 0 4689 &config_noc SLAVE_CLK_CTL 0>; 4690 4691 memory-region = <&pil_gdsp0_mem>; 4692 4693 qcom,qmp = <&aoss_qmp>; 4694 4695 qcom,smem-states = <&smp2p_gpdsp0_out 0>; 4696 qcom,smem-state-names = "stop"; 4697 4698 status = "disabled"; 4699 4700 glink-edge { 4701 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 4702 IPCC_MPROC_SIGNAL_GLINK_QMP 4703 IRQ_TYPE_EDGE_RISING>; 4704 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 4705 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4706 4707 label = "gpdsp0"; 4708 qcom,remote-pid = <17>; 4709 }; 4710 }; 4711 4712 remoteproc_gpdsp1: remoteproc@21c00000 { 4713 compatible = "qcom,sa8775p-gpdsp1-pas"; 4714 reg = <0x0 0x21c00000 0x0 0x10000>; 4715 4716 interrupts-extended = <&intc GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 4717 <&smp2p_gpdsp1_in 0 0>, 4718 <&smp2p_gpdsp1_in 2 0>, 4719 <&smp2p_gpdsp1_in 1 0>, 4720 <&smp2p_gpdsp1_in 3 0>; 4721 interrupt-names = "wdog", "fatal", "ready", 4722 "handover", "stop-ack"; 4723 4724 clocks = <&rpmhcc RPMH_CXO_CLK>; 4725 clock-names = "xo"; 4726 4727 power-domains = <&rpmhpd RPMHPD_CX>, 4728 <&rpmhpd RPMHPD_MXC>; 4729 power-domain-names = "cx", "mxc"; 4730 4731 interconnects = <&gpdsp_anoc MASTER_DSP1 0 4732 &config_noc SLAVE_CLK_CTL 0>; 4733 4734 memory-region = <&pil_gdsp1_mem>; 4735 4736 qcom,qmp = <&aoss_qmp>; 4737 4738 qcom,smem-states = <&smp2p_gpdsp1_out 0>; 4739 qcom,smem-state-names = "stop"; 4740 4741 status = "disabled"; 4742 4743 glink-edge { 4744 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP1 4745 IPCC_MPROC_SIGNAL_GLINK_QMP 4746 IRQ_TYPE_EDGE_RISING>; 4747 mboxes = <&ipcc IPCC_CLIENT_GPDSP1 4748 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4749 4750 label = "gpdsp1"; 4751 qcom,remote-pid = <18>; 4752 }; 4753 }; 4754 4755 dispcc1: clock-controller@22100000 { 4756 compatible = "qcom,sa8775p-dispcc1"; 4757 reg = <0x0 0x22100000 0x0 0x20000>; 4758 clocks = <&gcc GCC_DISP_AHB_CLK>, 4759 <&rpmhcc RPMH_CXO_CLK>, 4760 <&rpmhcc RPMH_CXO_CLK_A>, 4761 <&sleep_clk>, 4762 <0>, <0>, <0>, <0>, 4763 <0>, <0>, <0>, <0>; 4764 power-domains = <&rpmhpd SA8775P_MMCX>; 4765 #clock-cells = <1>; 4766 #reset-cells = <1>; 4767 #power-domain-cells = <1>; 4768 status = "disabled"; 4769 }; 4770 4771 ethernet1: ethernet@23000000 { 4772 compatible = "qcom,sa8775p-ethqos"; 4773 reg = <0x0 0x23000000 0x0 0x10000>, 4774 <0x0 0x23016000 0x0 0x100>; 4775 reg-names = "stmmaceth", "rgmii"; 4776 4777 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 4778 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>; 4779 interrupt-names = "macirq", "sfty"; 4780 4781 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 4782 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 4783 <&gcc GCC_EMAC1_PTP_CLK>, 4784 <&gcc GCC_EMAC1_PHY_AUX_CLK>; 4785 clock-names = "stmmaceth", 4786 "pclk", 4787 "ptp_ref", 4788 "phyaux"; 4789 4790 interconnects = <&aggre1_noc MASTER_EMAC_1 QCOM_ICC_TAG_ALWAYS 4791 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4792 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4793 &config_noc SLAVE_EMAC1_CFG QCOM_ICC_TAG_ALWAYS>; 4794 interconnect-names = "mac-mem", "cpu-mac"; 4795 4796 power-domains = <&gcc EMAC1_GDSC>; 4797 4798 phys = <&serdes1>; 4799 phy-names = "serdes"; 4800 4801 iommus = <&apps_smmu 0x140 0xf>; 4802 dma-coherent; 4803 4804 snps,tso; 4805 snps,pbl = <32>; 4806 rx-fifo-depth = <16384>; 4807 tx-fifo-depth = <16384>; 4808 4809 status = "disabled"; 4810 }; 4811 4812 ethernet0: ethernet@23040000 { 4813 compatible = "qcom,sa8775p-ethqos"; 4814 reg = <0x0 0x23040000 0x0 0x10000>, 4815 <0x0 0x23056000 0x0 0x100>; 4816 reg-names = "stmmaceth", "rgmii"; 4817 4818 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 4819 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>; 4820 interrupt-names = "macirq", "sfty"; 4821 4822 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 4823 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 4824 <&gcc GCC_EMAC0_PTP_CLK>, 4825 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 4826 clock-names = "stmmaceth", 4827 "pclk", 4828 "ptp_ref", 4829 "phyaux"; 4830 4831 interconnects = <&aggre1_noc MASTER_EMAC QCOM_ICC_TAG_ALWAYS 4832 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4833 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4834 &config_noc SLAVE_EMAC_CFG QCOM_ICC_TAG_ALWAYS>; 4835 interconnect-names = "mac-mem", "cpu-mac"; 4836 4837 power-domains = <&gcc EMAC0_GDSC>; 4838 4839 phys = <&serdes0>; 4840 phy-names = "serdes"; 4841 4842 iommus = <&apps_smmu 0x120 0xf>; 4843 dma-coherent; 4844 4845 snps,tso; 4846 snps,pbl = <32>; 4847 rx-fifo-depth = <16384>; 4848 tx-fifo-depth = <16384>; 4849 4850 status = "disabled"; 4851 }; 4852 4853 remoteproc_cdsp0: remoteproc@26300000 { 4854 compatible = "qcom,sa8775p-cdsp0-pas"; 4855 reg = <0x0 0x26300000 0x0 0x10000>; 4856 4857 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4858 <&smp2p_cdsp0_in 0 IRQ_TYPE_EDGE_RISING>, 4859 <&smp2p_cdsp0_in 2 IRQ_TYPE_EDGE_RISING>, 4860 <&smp2p_cdsp0_in 1 IRQ_TYPE_EDGE_RISING>, 4861 <&smp2p_cdsp0_in 3 IRQ_TYPE_EDGE_RISING>; 4862 interrupt-names = "wdog", "fatal", "ready", 4863 "handover", "stop-ack"; 4864 4865 clocks = <&rpmhcc RPMH_CXO_CLK>; 4866 clock-names = "xo"; 4867 4868 power-domains = <&rpmhpd RPMHPD_CX>, 4869 <&rpmhpd RPMHPD_MXC>, 4870 <&rpmhpd RPMHPD_NSP0>; 4871 power-domain-names = "cx", "mxc", "nsp"; 4872 4873 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 4874 &mc_virt SLAVE_EBI1 0>; 4875 4876 memory-region = <&pil_cdsp0_mem>; 4877 4878 qcom,qmp = <&aoss_qmp>; 4879 4880 qcom,smem-states = <&smp2p_cdsp0_out 0>; 4881 qcom,smem-state-names = "stop"; 4882 4883 status = "disabled"; 4884 4885 glink-edge { 4886 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4887 IPCC_MPROC_SIGNAL_GLINK_QMP 4888 IRQ_TYPE_EDGE_RISING>; 4889 mboxes = <&ipcc IPCC_CLIENT_CDSP 4890 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4891 4892 label = "cdsp"; 4893 qcom,remote-pid = <5>; 4894 4895 fastrpc { 4896 compatible = "qcom,fastrpc"; 4897 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4898 label = "cdsp"; 4899 #address-cells = <1>; 4900 #size-cells = <0>; 4901 4902 compute-cb@1 { 4903 compatible = "qcom,fastrpc-compute-cb"; 4904 reg = <1>; 4905 iommus = <&apps_smmu 0x2141 0x04a0>, 4906 <&apps_smmu 0x2161 0x04a0>, 4907 <&apps_smmu 0x2181 0x0400>, 4908 <&apps_smmu 0x21c1 0x04a0>, 4909 <&apps_smmu 0x21e1 0x04a0>, 4910 <&apps_smmu 0x2541 0x04a0>, 4911 <&apps_smmu 0x2561 0x04a0>, 4912 <&apps_smmu 0x2581 0x0400>, 4913 <&apps_smmu 0x25c1 0x04a0>, 4914 <&apps_smmu 0x25e1 0x04a0>; 4915 dma-coherent; 4916 }; 4917 4918 compute-cb@2 { 4919 compatible = "qcom,fastrpc-compute-cb"; 4920 reg = <2>; 4921 iommus = <&apps_smmu 0x2142 0x04a0>, 4922 <&apps_smmu 0x2162 0x04a0>, 4923 <&apps_smmu 0x2182 0x0400>, 4924 <&apps_smmu 0x21c2 0x04a0>, 4925 <&apps_smmu 0x21e2 0x04a0>, 4926 <&apps_smmu 0x2542 0x04a0>, 4927 <&apps_smmu 0x2562 0x04a0>, 4928 <&apps_smmu 0x2582 0x0400>, 4929 <&apps_smmu 0x25c2 0x04a0>, 4930 <&apps_smmu 0x25e2 0x04a0>; 4931 dma-coherent; 4932 }; 4933 4934 compute-cb@3 { 4935 compatible = "qcom,fastrpc-compute-cb"; 4936 reg = <3>; 4937 iommus = <&apps_smmu 0x2143 0x04a0>, 4938 <&apps_smmu 0x2163 0x04a0>, 4939 <&apps_smmu 0x2183 0x0400>, 4940 <&apps_smmu 0x21c3 0x04a0>, 4941 <&apps_smmu 0x21e3 0x04a0>, 4942 <&apps_smmu 0x2543 0x04a0>, 4943 <&apps_smmu 0x2563 0x04a0>, 4944 <&apps_smmu 0x2583 0x0400>, 4945 <&apps_smmu 0x25c3 0x04a0>, 4946 <&apps_smmu 0x25e3 0x04a0>; 4947 dma-coherent; 4948 }; 4949 4950 compute-cb@4 { 4951 compatible = "qcom,fastrpc-compute-cb"; 4952 reg = <4>; 4953 iommus = <&apps_smmu 0x2144 0x04a0>, 4954 <&apps_smmu 0x2164 0x04a0>, 4955 <&apps_smmu 0x2184 0x0400>, 4956 <&apps_smmu 0x21c4 0x04a0>, 4957 <&apps_smmu 0x21e4 0x04a0>, 4958 <&apps_smmu 0x2544 0x04a0>, 4959 <&apps_smmu 0x2564 0x04a0>, 4960 <&apps_smmu 0x2584 0x0400>, 4961 <&apps_smmu 0x25c4 0x04a0>, 4962 <&apps_smmu 0x25e4 0x04a0>; 4963 dma-coherent; 4964 }; 4965 4966 compute-cb@5 { 4967 compatible = "qcom,fastrpc-compute-cb"; 4968 reg = <5>; 4969 iommus = <&apps_smmu 0x2145 0x04a0>, 4970 <&apps_smmu 0x2165 0x04a0>, 4971 <&apps_smmu 0x2185 0x0400>, 4972 <&apps_smmu 0x21c5 0x04a0>, 4973 <&apps_smmu 0x21e5 0x04a0>, 4974 <&apps_smmu 0x2545 0x04a0>, 4975 <&apps_smmu 0x2565 0x04a0>, 4976 <&apps_smmu 0x2585 0x0400>, 4977 <&apps_smmu 0x25c5 0x04a0>, 4978 <&apps_smmu 0x25e5 0x04a0>; 4979 dma-coherent; 4980 }; 4981 4982 compute-cb@6 { 4983 compatible = "qcom,fastrpc-compute-cb"; 4984 reg = <6>; 4985 iommus = <&apps_smmu 0x2146 0x04a0>, 4986 <&apps_smmu 0x2166 0x04a0>, 4987 <&apps_smmu 0x2186 0x0400>, 4988 <&apps_smmu 0x21c6 0x04a0>, 4989 <&apps_smmu 0x21e6 0x04a0>, 4990 <&apps_smmu 0x2546 0x04a0>, 4991 <&apps_smmu 0x2566 0x04a0>, 4992 <&apps_smmu 0x2586 0x0400>, 4993 <&apps_smmu 0x25c6 0x04a0>, 4994 <&apps_smmu 0x25e6 0x04a0>; 4995 dma-coherent; 4996 }; 4997 4998 compute-cb@7 { 4999 compatible = "qcom,fastrpc-compute-cb"; 5000 reg = <7>; 5001 iommus = <&apps_smmu 0x2147 0x04a0>, 5002 <&apps_smmu 0x2167 0x04a0>, 5003 <&apps_smmu 0x2187 0x0400>, 5004 <&apps_smmu 0x21c7 0x04a0>, 5005 <&apps_smmu 0x21e7 0x04a0>, 5006 <&apps_smmu 0x2547 0x04a0>, 5007 <&apps_smmu 0x2567 0x04a0>, 5008 <&apps_smmu 0x2587 0x0400>, 5009 <&apps_smmu 0x25c7 0x04a0>, 5010 <&apps_smmu 0x25e7 0x04a0>; 5011 dma-coherent; 5012 }; 5013 5014 compute-cb@8 { 5015 compatible = "qcom,fastrpc-compute-cb"; 5016 reg = <8>; 5017 iommus = <&apps_smmu 0x2148 0x04a0>, 5018 <&apps_smmu 0x2168 0x04a0>, 5019 <&apps_smmu 0x2188 0x0400>, 5020 <&apps_smmu 0x21c8 0x04a0>, 5021 <&apps_smmu 0x21e8 0x04a0>, 5022 <&apps_smmu 0x2548 0x04a0>, 5023 <&apps_smmu 0x2568 0x04a0>, 5024 <&apps_smmu 0x2588 0x0400>, 5025 <&apps_smmu 0x25c8 0x04a0>, 5026 <&apps_smmu 0x25e8 0x04a0>; 5027 dma-coherent; 5028 }; 5029 5030 compute-cb@9 { 5031 compatible = "qcom,fastrpc-compute-cb"; 5032 reg = <9>; 5033 iommus = <&apps_smmu 0x2149 0x04a0>, 5034 <&apps_smmu 0x2169 0x04a0>, 5035 <&apps_smmu 0x2189 0x0400>, 5036 <&apps_smmu 0x21c9 0x04a0>, 5037 <&apps_smmu 0x21e9 0x04a0>, 5038 <&apps_smmu 0x2549 0x04a0>, 5039 <&apps_smmu 0x2569 0x04a0>, 5040 <&apps_smmu 0x2589 0x0400>, 5041 <&apps_smmu 0x25c9 0x04a0>, 5042 <&apps_smmu 0x25e9 0x04a0>; 5043 dma-coherent; 5044 }; 5045 5046 compute-cb@10 { 5047 compatible = "qcom,fastrpc-compute-cb"; 5048 reg = <10>; 5049 iommus = <&apps_smmu 0x214a 0x04a0>, 5050 <&apps_smmu 0x216a 0x04a0>, 5051 <&apps_smmu 0x218a 0x0400>, 5052 <&apps_smmu 0x21ca 0x04a0>, 5053 <&apps_smmu 0x21ea 0x04a0>, 5054 <&apps_smmu 0x254a 0x04a0>, 5055 <&apps_smmu 0x256a 0x04a0>, 5056 <&apps_smmu 0x258a 0x0400>, 5057 <&apps_smmu 0x25ca 0x04a0>, 5058 <&apps_smmu 0x25ea 0x04a0>; 5059 dma-coherent; 5060 }; 5061 5062 compute-cb@11 { 5063 compatible = "qcom,fastrpc-compute-cb"; 5064 reg = <11>; 5065 iommus = <&apps_smmu 0x214b 0x04a0>, 5066 <&apps_smmu 0x216b 0x04a0>, 5067 <&apps_smmu 0x218b 0x0400>, 5068 <&apps_smmu 0x21cb 0x04a0>, 5069 <&apps_smmu 0x21eb 0x04a0>, 5070 <&apps_smmu 0x254b 0x04a0>, 5071 <&apps_smmu 0x256b 0x04a0>, 5072 <&apps_smmu 0x258b 0x0400>, 5073 <&apps_smmu 0x25cb 0x04a0>, 5074 <&apps_smmu 0x25eb 0x04a0>; 5075 dma-coherent; 5076 }; 5077 }; 5078 }; 5079 }; 5080 5081 remoteproc_cdsp1: remoteproc@2a300000 { 5082 compatible = "qcom,sa8775p-cdsp1-pas"; 5083 reg = <0x0 0x2A300000 0x0 0x10000>; 5084 5085 interrupts-extended = <&intc GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 5086 <&smp2p_cdsp1_in 0 IRQ_TYPE_EDGE_RISING>, 5087 <&smp2p_cdsp1_in 2 IRQ_TYPE_EDGE_RISING>, 5088 <&smp2p_cdsp1_in 1 IRQ_TYPE_EDGE_RISING>, 5089 <&smp2p_cdsp1_in 3 IRQ_TYPE_EDGE_RISING>; 5090 interrupt-names = "wdog", "fatal", "ready", 5091 "handover", "stop-ack"; 5092 5093 clocks = <&rpmhcc RPMH_CXO_CLK>; 5094 clock-names = "xo"; 5095 5096 power-domains = <&rpmhpd RPMHPD_CX>, 5097 <&rpmhpd RPMHPD_MXC>, 5098 <&rpmhpd RPMHPD_NSP1>; 5099 power-domain-names = "cx", "mxc", "nsp"; 5100 5101 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 5102 &mc_virt SLAVE_EBI1 0>; 5103 5104 memory-region = <&pil_cdsp1_mem>; 5105 5106 qcom,qmp = <&aoss_qmp>; 5107 5108 qcom,smem-states = <&smp2p_cdsp1_out 0>; 5109 qcom,smem-state-names = "stop"; 5110 5111 status = "disabled"; 5112 5113 glink-edge { 5114 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 5115 IPCC_MPROC_SIGNAL_GLINK_QMP 5116 IRQ_TYPE_EDGE_RISING>; 5117 mboxes = <&ipcc IPCC_CLIENT_NSP1 5118 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5119 5120 label = "cdsp"; 5121 qcom,remote-pid = <12>; 5122 5123 fastrpc { 5124 compatible = "qcom,fastrpc"; 5125 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5126 label = "cdsp1"; 5127 #address-cells = <1>; 5128 #size-cells = <0>; 5129 5130 compute-cb@1 { 5131 compatible = "qcom,fastrpc-compute-cb"; 5132 reg = <1>; 5133 iommus = <&apps_smmu 0x2941 0x04a0>, 5134 <&apps_smmu 0x2961 0x04a0>, 5135 <&apps_smmu 0x2981 0x0400>, 5136 <&apps_smmu 0x29c1 0x04a0>, 5137 <&apps_smmu 0x29e1 0x04a0>, 5138 <&apps_smmu 0x2d41 0x04a0>, 5139 <&apps_smmu 0x2d61 0x04a0>, 5140 <&apps_smmu 0x2d81 0x0400>, 5141 <&apps_smmu 0x2dc1 0x04a0>, 5142 <&apps_smmu 0x2de1 0x04a0>; 5143 dma-coherent; 5144 }; 5145 5146 compute-cb@2 { 5147 compatible = "qcom,fastrpc-compute-cb"; 5148 reg = <2>; 5149 iommus = <&apps_smmu 0x2942 0x04a0>, 5150 <&apps_smmu 0x2962 0x04a0>, 5151 <&apps_smmu 0x2982 0x0400>, 5152 <&apps_smmu 0x29c2 0x04a0>, 5153 <&apps_smmu 0x29e2 0x04a0>, 5154 <&apps_smmu 0x2d42 0x04a0>, 5155 <&apps_smmu 0x2d62 0x04a0>, 5156 <&apps_smmu 0x2d82 0x0400>, 5157 <&apps_smmu 0x2dc2 0x04a0>, 5158 <&apps_smmu 0x2de2 0x04a0>; 5159 dma-coherent; 5160 }; 5161 5162 compute-cb@3 { 5163 compatible = "qcom,fastrpc-compute-cb"; 5164 reg = <3>; 5165 iommus = <&apps_smmu 0x2943 0x04a0>, 5166 <&apps_smmu 0x2963 0x04a0>, 5167 <&apps_smmu 0x2983 0x0400>, 5168 <&apps_smmu 0x29c3 0x04a0>, 5169 <&apps_smmu 0x29e3 0x04a0>, 5170 <&apps_smmu 0x2d43 0x04a0>, 5171 <&apps_smmu 0x2d63 0x04a0>, 5172 <&apps_smmu 0x2d83 0x0400>, 5173 <&apps_smmu 0x2dc3 0x04a0>, 5174 <&apps_smmu 0x2de3 0x04a0>; 5175 dma-coherent; 5176 }; 5177 5178 compute-cb@4 { 5179 compatible = "qcom,fastrpc-compute-cb"; 5180 reg = <4>; 5181 iommus = <&apps_smmu 0x2944 0x04a0>, 5182 <&apps_smmu 0x2964 0x04a0>, 5183 <&apps_smmu 0x2984 0x0400>, 5184 <&apps_smmu 0x29c4 0x04a0>, 5185 <&apps_smmu 0x29e4 0x04a0>, 5186 <&apps_smmu 0x2d44 0x04a0>, 5187 <&apps_smmu 0x2d64 0x04a0>, 5188 <&apps_smmu 0x2d84 0x0400>, 5189 <&apps_smmu 0x2dc4 0x04a0>, 5190 <&apps_smmu 0x2de4 0x04a0>; 5191 dma-coherent; 5192 }; 5193 5194 compute-cb@5 { 5195 compatible = "qcom,fastrpc-compute-cb"; 5196 reg = <5>; 5197 iommus = <&apps_smmu 0x2945 0x04a0>, 5198 <&apps_smmu 0x2965 0x04a0>, 5199 <&apps_smmu 0x2985 0x0400>, 5200 <&apps_smmu 0x29c5 0x04a0>, 5201 <&apps_smmu 0x29e5 0x04a0>, 5202 <&apps_smmu 0x2d45 0x04a0>, 5203 <&apps_smmu 0x2d65 0x04a0>, 5204 <&apps_smmu 0x2d85 0x0400>, 5205 <&apps_smmu 0x2dc5 0x04a0>, 5206 <&apps_smmu 0x2de5 0x04a0>; 5207 dma-coherent; 5208 }; 5209 5210 compute-cb@6 { 5211 compatible = "qcom,fastrpc-compute-cb"; 5212 reg = <6>; 5213 iommus = <&apps_smmu 0x2946 0x04a0>, 5214 <&apps_smmu 0x2966 0x04a0>, 5215 <&apps_smmu 0x2986 0x0400>, 5216 <&apps_smmu 0x29c6 0x04a0>, 5217 <&apps_smmu 0x29e6 0x04a0>, 5218 <&apps_smmu 0x2d46 0x04a0>, 5219 <&apps_smmu 0x2d66 0x04a0>, 5220 <&apps_smmu 0x2d86 0x0400>, 5221 <&apps_smmu 0x2dc6 0x04a0>, 5222 <&apps_smmu 0x2de6 0x04a0>; 5223 dma-coherent; 5224 }; 5225 5226 compute-cb@7 { 5227 compatible = "qcom,fastrpc-compute-cb"; 5228 reg = <7>; 5229 iommus = <&apps_smmu 0x2947 0x04a0>, 5230 <&apps_smmu 0x2967 0x04a0>, 5231 <&apps_smmu 0x2987 0x0400>, 5232 <&apps_smmu 0x29c7 0x04a0>, 5233 <&apps_smmu 0x29e7 0x04a0>, 5234 <&apps_smmu 0x2d47 0x04a0>, 5235 <&apps_smmu 0x2d67 0x04a0>, 5236 <&apps_smmu 0x2d87 0x0400>, 5237 <&apps_smmu 0x2dc7 0x04a0>, 5238 <&apps_smmu 0x2de7 0x04a0>; 5239 dma-coherent; 5240 }; 5241 5242 compute-cb@8 { 5243 compatible = "qcom,fastrpc-compute-cb"; 5244 reg = <8>; 5245 iommus = <&apps_smmu 0x2948 0x04a0>, 5246 <&apps_smmu 0x2968 0x04a0>, 5247 <&apps_smmu 0x2988 0x0400>, 5248 <&apps_smmu 0x29c8 0x04a0>, 5249 <&apps_smmu 0x29e8 0x04a0>, 5250 <&apps_smmu 0x2d48 0x04a0>, 5251 <&apps_smmu 0x2d68 0x04a0>, 5252 <&apps_smmu 0x2d88 0x0400>, 5253 <&apps_smmu 0x2dc8 0x04a0>, 5254 <&apps_smmu 0x2de8 0x04a0>; 5255 dma-coherent; 5256 }; 5257 5258 compute-cb@9 { 5259 compatible = "qcom,fastrpc-compute-cb"; 5260 reg = <9>; 5261 iommus = <&apps_smmu 0x2949 0x04a0>, 5262 <&apps_smmu 0x2969 0x04a0>, 5263 <&apps_smmu 0x2989 0x0400>, 5264 <&apps_smmu 0x29c9 0x04a0>, 5265 <&apps_smmu 0x29e9 0x04a0>, 5266 <&apps_smmu 0x2d49 0x04a0>, 5267 <&apps_smmu 0x2d69 0x04a0>, 5268 <&apps_smmu 0x2d89 0x0400>, 5269 <&apps_smmu 0x2dc9 0x04a0>, 5270 <&apps_smmu 0x2de9 0x04a0>; 5271 dma-coherent; 5272 }; 5273 5274 compute-cb@10 { 5275 compatible = "qcom,fastrpc-compute-cb"; 5276 reg = <10>; 5277 iommus = <&apps_smmu 0x294a 0x04a0>, 5278 <&apps_smmu 0x296a 0x04a0>, 5279 <&apps_smmu 0x298a 0x0400>, 5280 <&apps_smmu 0x29ca 0x04a0>, 5281 <&apps_smmu 0x29ea 0x04a0>, 5282 <&apps_smmu 0x2d4a 0x04a0>, 5283 <&apps_smmu 0x2d6a 0x04a0>, 5284 <&apps_smmu 0x2d8a 0x0400>, 5285 <&apps_smmu 0x2dca 0x04a0>, 5286 <&apps_smmu 0x2dea 0x04a0>; 5287 dma-coherent; 5288 }; 5289 5290 compute-cb@11 { 5291 compatible = "qcom,fastrpc-compute-cb"; 5292 reg = <11>; 5293 iommus = <&apps_smmu 0x294b 0x04a0>, 5294 <&apps_smmu 0x296b 0x04a0>, 5295 <&apps_smmu 0x298b 0x0400>, 5296 <&apps_smmu 0x29cb 0x04a0>, 5297 <&apps_smmu 0x29eb 0x04a0>, 5298 <&apps_smmu 0x2d4b 0x04a0>, 5299 <&apps_smmu 0x2d6b 0x04a0>, 5300 <&apps_smmu 0x2d8b 0x0400>, 5301 <&apps_smmu 0x2dcb 0x04a0>, 5302 <&apps_smmu 0x2deb 0x04a0>; 5303 dma-coherent; 5304 }; 5305 5306 compute-cb@12 { 5307 compatible = "qcom,fastrpc-compute-cb"; 5308 reg = <12>; 5309 iommus = <&apps_smmu 0x294c 0x04a0>, 5310 <&apps_smmu 0x296c 0x04a0>, 5311 <&apps_smmu 0x298c 0x0400>, 5312 <&apps_smmu 0x29cc 0x04a0>, 5313 <&apps_smmu 0x29ec 0x04a0>, 5314 <&apps_smmu 0x2d4c 0x04a0>, 5315 <&apps_smmu 0x2d6c 0x04a0>, 5316 <&apps_smmu 0x2d8c 0x0400>, 5317 <&apps_smmu 0x2dcc 0x04a0>, 5318 <&apps_smmu 0x2dec 0x04a0>; 5319 dma-coherent; 5320 }; 5321 5322 compute-cb@13 { 5323 compatible = "qcom,fastrpc-compute-cb"; 5324 reg = <13>; 5325 iommus = <&apps_smmu 0x294d 0x04a0>, 5326 <&apps_smmu 0x296d 0x04a0>, 5327 <&apps_smmu 0x298d 0x0400>, 5328 <&apps_smmu 0x29Cd 0x04a0>, 5329 <&apps_smmu 0x29ed 0x04a0>, 5330 <&apps_smmu 0x2d4d 0x04a0>, 5331 <&apps_smmu 0x2d6d 0x04a0>, 5332 <&apps_smmu 0x2d8d 0x0400>, 5333 <&apps_smmu 0x2dcd 0x04a0>, 5334 <&apps_smmu 0x2ded 0x04a0>; 5335 dma-coherent; 5336 }; 5337 }; 5338 }; 5339 }; 5340 5341 remoteproc_adsp: remoteproc@30000000 { 5342 compatible = "qcom,sa8775p-adsp-pas"; 5343 reg = <0x0 0x30000000 0x0 0x100>; 5344 5345 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 5346 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5347 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5348 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5349 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5350 interrupt-names = "wdog", "fatal", "ready", "handover", 5351 "stop-ack"; 5352 5353 clocks = <&rpmhcc RPMH_CXO_CLK>; 5354 clock-names = "xo"; 5355 5356 power-domains = <&rpmhpd RPMHPD_LCX>, 5357 <&rpmhpd RPMHPD_LMX>; 5358 power-domain-names = "lcx", "lmx"; 5359 5360 interconnects = <&lpass_ag_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; 5361 5362 memory-region = <&pil_adsp_mem>; 5363 5364 qcom,qmp = <&aoss_qmp>; 5365 5366 qcom,smem-states = <&smp2p_adsp_out 0>; 5367 qcom,smem-state-names = "stop"; 5368 5369 status = "disabled"; 5370 5371 remoteproc_adsp_glink: glink-edge { 5372 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5373 IPCC_MPROC_SIGNAL_GLINK_QMP 5374 IRQ_TYPE_EDGE_RISING>; 5375 mboxes = <&ipcc IPCC_CLIENT_LPASS 5376 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5377 5378 label = "lpass"; 5379 qcom,remote-pid = <2>; 5380 5381 fastrpc { 5382 compatible = "qcom,fastrpc"; 5383 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5384 label = "adsp"; 5385 memory-region = <&adsp_rpc_remote_heap_mem>; 5386 qcom,vmids = <QCOM_SCM_VMID_LPASS 5387 QCOM_SCM_VMID_ADSP_HEAP>; 5388 #address-cells = <1>; 5389 #size-cells = <0>; 5390 5391 compute-cb@3 { 5392 compatible = "qcom,fastrpc-compute-cb"; 5393 reg = <3>; 5394 iommus = <&apps_smmu 0x3003 0x0>; 5395 dma-coherent; 5396 }; 5397 5398 compute-cb@4 { 5399 compatible = "qcom,fastrpc-compute-cb"; 5400 reg = <4>; 5401 iommus = <&apps_smmu 0x3004 0x0>; 5402 dma-coherent; 5403 }; 5404 5405 compute-cb@5 { 5406 compatible = "qcom,fastrpc-compute-cb"; 5407 reg = <5>; 5408 iommus = <&apps_smmu 0x3005 0x0>; 5409 qcom,nsessions = <5>; 5410 dma-coherent; 5411 }; 5412 }; 5413 }; 5414 }; 5415 }; 5416 5417 thermal-zones { 5418 aoss-0-thermal { 5419 thermal-sensors = <&tsens0 0>; 5420 5421 trips { 5422 trip-point0 { 5423 temperature = <105000>; 5424 hysteresis = <5000>; 5425 type = "passive"; 5426 }; 5427 5428 trip-point1 { 5429 temperature = <115000>; 5430 hysteresis = <5000>; 5431 type = "passive"; 5432 }; 5433 }; 5434 }; 5435 5436 cpu-0-0-0-thermal { 5437 polling-delay-passive = <10>; 5438 5439 thermal-sensors = <&tsens0 1>; 5440 5441 trips { 5442 trip-point0 { 5443 temperature = <105000>; 5444 hysteresis = <5000>; 5445 type = "passive"; 5446 }; 5447 5448 trip-point1 { 5449 temperature = <115000>; 5450 hysteresis = <5000>; 5451 type = "passive"; 5452 }; 5453 }; 5454 }; 5455 5456 cpu-0-1-0-thermal { 5457 polling-delay-passive = <10>; 5458 5459 thermal-sensors = <&tsens0 2>; 5460 5461 trips { 5462 trip-point0 { 5463 temperature = <105000>; 5464 hysteresis = <5000>; 5465 type = "passive"; 5466 }; 5467 5468 trip-point1 { 5469 temperature = <115000>; 5470 hysteresis = <5000>; 5471 type = "passive"; 5472 }; 5473 }; 5474 }; 5475 5476 cpu-0-2-0-thermal { 5477 polling-delay-passive = <10>; 5478 5479 thermal-sensors = <&tsens0 3>; 5480 5481 trips { 5482 trip-point0 { 5483 temperature = <105000>; 5484 hysteresis = <5000>; 5485 type = "passive"; 5486 }; 5487 5488 trip-point1 { 5489 temperature = <115000>; 5490 hysteresis = <5000>; 5491 type = "passive"; 5492 }; 5493 }; 5494 }; 5495 5496 cpu-0-3-0-thermal { 5497 polling-delay-passive = <10>; 5498 5499 thermal-sensors = <&tsens0 4>; 5500 5501 trips { 5502 trip-point0 { 5503 temperature = <105000>; 5504 hysteresis = <5000>; 5505 type = "passive"; 5506 }; 5507 5508 trip-point1 { 5509 temperature = <115000>; 5510 hysteresis = <5000>; 5511 type = "passive"; 5512 }; 5513 }; 5514 }; 5515 5516 gpuss-0-thermal { 5517 polling-delay-passive = <10>; 5518 5519 thermal-sensors = <&tsens0 5>; 5520 5521 trips { 5522 trip-point0 { 5523 temperature = <105000>; 5524 hysteresis = <5000>; 5525 type = "passive"; 5526 }; 5527 5528 trip-point1 { 5529 temperature = <115000>; 5530 hysteresis = <5000>; 5531 type = "passive"; 5532 }; 5533 }; 5534 }; 5535 5536 gpuss-1-thermal { 5537 polling-delay-passive = <10>; 5538 5539 thermal-sensors = <&tsens0 6>; 5540 5541 trips { 5542 trip-point0 { 5543 temperature = <105000>; 5544 hysteresis = <5000>; 5545 type = "passive"; 5546 }; 5547 5548 trip-point1 { 5549 temperature = <115000>; 5550 hysteresis = <5000>; 5551 type = "passive"; 5552 }; 5553 }; 5554 }; 5555 5556 gpuss-2-thermal { 5557 polling-delay-passive = <10>; 5558 5559 thermal-sensors = <&tsens0 7>; 5560 5561 trips { 5562 trip-point0 { 5563 temperature = <105000>; 5564 hysteresis = <5000>; 5565 type = "passive"; 5566 }; 5567 5568 trip-point1 { 5569 temperature = <115000>; 5570 hysteresis = <5000>; 5571 type = "passive"; 5572 }; 5573 }; 5574 }; 5575 5576 audio-thermal { 5577 thermal-sensors = <&tsens0 8>; 5578 5579 trips { 5580 trip-point0 { 5581 temperature = <105000>; 5582 hysteresis = <5000>; 5583 type = "passive"; 5584 }; 5585 5586 trip-point1 { 5587 temperature = <115000>; 5588 hysteresis = <5000>; 5589 type = "passive"; 5590 }; 5591 }; 5592 }; 5593 5594 camss-0-thermal { 5595 thermal-sensors = <&tsens0 9>; 5596 5597 trips { 5598 trip-point0 { 5599 temperature = <105000>; 5600 hysteresis = <5000>; 5601 type = "passive"; 5602 }; 5603 5604 trip-point1 { 5605 temperature = <115000>; 5606 hysteresis = <5000>; 5607 type = "passive"; 5608 }; 5609 }; 5610 }; 5611 5612 pcie-0-thermal { 5613 thermal-sensors = <&tsens0 10>; 5614 5615 trips { 5616 trip-point0 { 5617 temperature = <105000>; 5618 hysteresis = <5000>; 5619 type = "passive"; 5620 }; 5621 5622 trip-point1 { 5623 temperature = <115000>; 5624 hysteresis = <5000>; 5625 type = "passive"; 5626 }; 5627 }; 5628 }; 5629 5630 cpuss-0-0-thermal { 5631 thermal-sensors = <&tsens0 11>; 5632 5633 trips { 5634 trip-point0 { 5635 temperature = <105000>; 5636 hysteresis = <5000>; 5637 type = "passive"; 5638 }; 5639 5640 trip-point1 { 5641 temperature = <115000>; 5642 hysteresis = <5000>; 5643 type = "passive"; 5644 }; 5645 }; 5646 }; 5647 5648 aoss-1-thermal { 5649 thermal-sensors = <&tsens1 0>; 5650 5651 trips { 5652 trip-point0 { 5653 temperature = <105000>; 5654 hysteresis = <5000>; 5655 type = "passive"; 5656 }; 5657 5658 trip-point1 { 5659 temperature = <115000>; 5660 hysteresis = <5000>; 5661 type = "passive"; 5662 }; 5663 }; 5664 }; 5665 5666 cpu-0-0-1-thermal { 5667 polling-delay-passive = <10>; 5668 5669 thermal-sensors = <&tsens1 1>; 5670 5671 trips { 5672 trip-point0 { 5673 temperature = <105000>; 5674 hysteresis = <5000>; 5675 type = "passive"; 5676 }; 5677 5678 trip-point1 { 5679 temperature = <115000>; 5680 hysteresis = <5000>; 5681 type = "passive"; 5682 }; 5683 }; 5684 }; 5685 5686 cpu-0-1-1-thermal { 5687 polling-delay-passive = <10>; 5688 5689 thermal-sensors = <&tsens1 2>; 5690 5691 trips { 5692 trip-point0 { 5693 temperature = <105000>; 5694 hysteresis = <5000>; 5695 type = "passive"; 5696 }; 5697 5698 trip-point1 { 5699 temperature = <115000>; 5700 hysteresis = <5000>; 5701 type = "passive"; 5702 }; 5703 }; 5704 }; 5705 5706 cpu-0-2-1-thermal { 5707 polling-delay-passive = <10>; 5708 5709 thermal-sensors = <&tsens1 3>; 5710 5711 trips { 5712 trip-point0 { 5713 temperature = <105000>; 5714 hysteresis = <5000>; 5715 type = "passive"; 5716 }; 5717 5718 trip-point1 { 5719 temperature = <115000>; 5720 hysteresis = <5000>; 5721 type = "passive"; 5722 }; 5723 }; 5724 }; 5725 5726 cpu-0-3-1-thermal { 5727 polling-delay-passive = <10>; 5728 5729 thermal-sensors = <&tsens1 4>; 5730 5731 trips { 5732 trip-point0 { 5733 temperature = <105000>; 5734 hysteresis = <5000>; 5735 type = "passive"; 5736 }; 5737 5738 trip-point1 { 5739 temperature = <115000>; 5740 hysteresis = <5000>; 5741 type = "passive"; 5742 }; 5743 }; 5744 }; 5745 5746 gpuss-3-thermal { 5747 polling-delay-passive = <10>; 5748 5749 thermal-sensors = <&tsens1 5>; 5750 5751 trips { 5752 trip-point0 { 5753 temperature = <105000>; 5754 hysteresis = <5000>; 5755 type = "passive"; 5756 }; 5757 5758 trip-point1 { 5759 temperature = <115000>; 5760 hysteresis = <5000>; 5761 type = "passive"; 5762 }; 5763 }; 5764 }; 5765 5766 gpuss-4-thermal { 5767 polling-delay-passive = <10>; 5768 5769 thermal-sensors = <&tsens1 6>; 5770 5771 trips { 5772 trip-point0 { 5773 temperature = <105000>; 5774 hysteresis = <5000>; 5775 type = "passive"; 5776 }; 5777 5778 trip-point1 { 5779 temperature = <115000>; 5780 hysteresis = <5000>; 5781 type = "passive"; 5782 }; 5783 }; 5784 }; 5785 5786 gpuss-5-thermal { 5787 polling-delay-passive = <10>; 5788 5789 thermal-sensors = <&tsens1 7>; 5790 5791 trips { 5792 trip-point0 { 5793 temperature = <105000>; 5794 hysteresis = <5000>; 5795 type = "passive"; 5796 }; 5797 5798 trip-point1 { 5799 temperature = <115000>; 5800 hysteresis = <5000>; 5801 type = "passive"; 5802 }; 5803 }; 5804 }; 5805 5806 video-thermal { 5807 thermal-sensors = <&tsens1 8>; 5808 5809 trips { 5810 trip-point0 { 5811 temperature = <105000>; 5812 hysteresis = <5000>; 5813 type = "passive"; 5814 }; 5815 5816 trip-point1 { 5817 temperature = <115000>; 5818 hysteresis = <5000>; 5819 type = "passive"; 5820 }; 5821 }; 5822 }; 5823 5824 camss-1-thermal { 5825 thermal-sensors = <&tsens1 9>; 5826 5827 trips { 5828 trip-point0 { 5829 temperature = <105000>; 5830 hysteresis = <5000>; 5831 type = "passive"; 5832 }; 5833 5834 trip-point1 { 5835 temperature = <115000>; 5836 hysteresis = <5000>; 5837 type = "passive"; 5838 }; 5839 }; 5840 }; 5841 5842 pcie-1-thermal { 5843 thermal-sensors = <&tsens1 10>; 5844 5845 trips { 5846 trip-point0 { 5847 temperature = <105000>; 5848 hysteresis = <5000>; 5849 type = "passive"; 5850 }; 5851 5852 trip-point1 { 5853 temperature = <115000>; 5854 hysteresis = <5000>; 5855 type = "passive"; 5856 }; 5857 }; 5858 }; 5859 5860 cpuss-0-1-thermal { 5861 thermal-sensors = <&tsens1 11>; 5862 5863 trips { 5864 trip-point0 { 5865 temperature = <105000>; 5866 hysteresis = <5000>; 5867 type = "passive"; 5868 }; 5869 5870 trip-point1 { 5871 temperature = <115000>; 5872 hysteresis = <5000>; 5873 type = "passive"; 5874 }; 5875 }; 5876 }; 5877 5878 aoss-2-thermal { 5879 thermal-sensors = <&tsens2 0>; 5880 5881 trips { 5882 trip-point0 { 5883 temperature = <105000>; 5884 hysteresis = <5000>; 5885 type = "passive"; 5886 }; 5887 5888 trip-point1 { 5889 temperature = <115000>; 5890 hysteresis = <5000>; 5891 type = "passive"; 5892 }; 5893 }; 5894 }; 5895 5896 cpu-1-0-0-thermal { 5897 polling-delay-passive = <10>; 5898 5899 thermal-sensors = <&tsens2 1>; 5900 5901 trips { 5902 trip-point0 { 5903 temperature = <105000>; 5904 hysteresis = <5000>; 5905 type = "passive"; 5906 }; 5907 5908 trip-point1 { 5909 temperature = <115000>; 5910 hysteresis = <5000>; 5911 type = "passive"; 5912 }; 5913 }; 5914 }; 5915 5916 cpu-1-1-0-thermal { 5917 polling-delay-passive = <10>; 5918 5919 thermal-sensors = <&tsens2 2>; 5920 5921 trips { 5922 trip-point0 { 5923 temperature = <105000>; 5924 hysteresis = <5000>; 5925 type = "passive"; 5926 }; 5927 5928 trip-point1 { 5929 temperature = <115000>; 5930 hysteresis = <5000>; 5931 type = "passive"; 5932 }; 5933 }; 5934 }; 5935 5936 cpu-1-2-0-thermal { 5937 polling-delay-passive = <10>; 5938 5939 thermal-sensors = <&tsens2 3>; 5940 5941 trips { 5942 trip-point0 { 5943 temperature = <105000>; 5944 hysteresis = <5000>; 5945 type = "passive"; 5946 }; 5947 5948 trip-point1 { 5949 temperature = <115000>; 5950 hysteresis = <5000>; 5951 type = "passive"; 5952 }; 5953 }; 5954 }; 5955 5956 cpu-1-3-0-thermal { 5957 polling-delay-passive = <10>; 5958 5959 thermal-sensors = <&tsens2 4>; 5960 5961 trips { 5962 trip-point0 { 5963 temperature = <105000>; 5964 hysteresis = <5000>; 5965 type = "passive"; 5966 }; 5967 5968 trip-point1 { 5969 temperature = <115000>; 5970 hysteresis = <5000>; 5971 type = "passive"; 5972 }; 5973 }; 5974 }; 5975 5976 nsp-0-0-0-thermal { 5977 polling-delay-passive = <10>; 5978 5979 thermal-sensors = <&tsens2 5>; 5980 5981 trips { 5982 trip-point0 { 5983 temperature = <105000>; 5984 hysteresis = <5000>; 5985 type = "passive"; 5986 }; 5987 5988 trip-point1 { 5989 temperature = <115000>; 5990 hysteresis = <5000>; 5991 type = "passive"; 5992 }; 5993 }; 5994 }; 5995 5996 nsp-0-1-0-thermal { 5997 polling-delay-passive = <10>; 5998 5999 thermal-sensors = <&tsens2 6>; 6000 6001 trips { 6002 trip-point0 { 6003 temperature = <105000>; 6004 hysteresis = <5000>; 6005 type = "passive"; 6006 }; 6007 6008 trip-point1 { 6009 temperature = <115000>; 6010 hysteresis = <5000>; 6011 type = "passive"; 6012 }; 6013 }; 6014 }; 6015 6016 nsp-0-2-0-thermal { 6017 polling-delay-passive = <10>; 6018 6019 thermal-sensors = <&tsens2 7>; 6020 6021 trips { 6022 trip-point0 { 6023 temperature = <105000>; 6024 hysteresis = <5000>; 6025 type = "passive"; 6026 }; 6027 6028 trip-point1 { 6029 temperature = <115000>; 6030 hysteresis = <5000>; 6031 type = "passive"; 6032 }; 6033 }; 6034 }; 6035 6036 nsp-1-0-0-thermal { 6037 polling-delay-passive = <10>; 6038 6039 thermal-sensors = <&tsens2 8>; 6040 6041 trips { 6042 trip-point0 { 6043 temperature = <105000>; 6044 hysteresis = <5000>; 6045 type = "passive"; 6046 }; 6047 6048 trip-point1 { 6049 temperature = <115000>; 6050 hysteresis = <5000>; 6051 type = "passive"; 6052 }; 6053 }; 6054 }; 6055 6056 nsp-1-1-0-thermal { 6057 polling-delay-passive = <10>; 6058 6059 thermal-sensors = <&tsens2 9>; 6060 6061 trips { 6062 trip-point0 { 6063 temperature = <105000>; 6064 hysteresis = <5000>; 6065 type = "passive"; 6066 }; 6067 6068 trip-point1 { 6069 temperature = <115000>; 6070 hysteresis = <5000>; 6071 type = "passive"; 6072 }; 6073 }; 6074 }; 6075 6076 nsp-1-2-0-thermal { 6077 polling-delay-passive = <10>; 6078 6079 thermal-sensors = <&tsens2 10>; 6080 6081 trips { 6082 trip-point0 { 6083 temperature = <105000>; 6084 hysteresis = <5000>; 6085 type = "passive"; 6086 }; 6087 6088 trip-point1 { 6089 temperature = <115000>; 6090 hysteresis = <5000>; 6091 type = "passive"; 6092 }; 6093 }; 6094 }; 6095 6096 ddrss-0-thermal { 6097 thermal-sensors = <&tsens2 11>; 6098 6099 trips { 6100 trip-point0 { 6101 temperature = <105000>; 6102 hysteresis = <5000>; 6103 type = "passive"; 6104 }; 6105 6106 trip-point1 { 6107 temperature = <115000>; 6108 hysteresis = <5000>; 6109 type = "passive"; 6110 }; 6111 }; 6112 }; 6113 6114 cpuss-1-0-thermal { 6115 thermal-sensors = <&tsens2 12>; 6116 6117 trips { 6118 trip-point0 { 6119 temperature = <105000>; 6120 hysteresis = <5000>; 6121 type = "passive"; 6122 }; 6123 6124 trip-point1 { 6125 temperature = <115000>; 6126 hysteresis = <5000>; 6127 type = "passive"; 6128 }; 6129 }; 6130 }; 6131 6132 aoss-3-thermal { 6133 thermal-sensors = <&tsens3 0>; 6134 6135 trips { 6136 trip-point0 { 6137 temperature = <105000>; 6138 hysteresis = <5000>; 6139 type = "passive"; 6140 }; 6141 6142 trip-point1 { 6143 temperature = <115000>; 6144 hysteresis = <5000>; 6145 type = "passive"; 6146 }; 6147 }; 6148 }; 6149 6150 cpu-1-0-1-thermal { 6151 polling-delay-passive = <10>; 6152 6153 thermal-sensors = <&tsens3 1>; 6154 6155 trips { 6156 trip-point0 { 6157 temperature = <105000>; 6158 hysteresis = <5000>; 6159 type = "passive"; 6160 }; 6161 6162 trip-point1 { 6163 temperature = <115000>; 6164 hysteresis = <5000>; 6165 type = "passive"; 6166 }; 6167 }; 6168 }; 6169 6170 cpu-1-1-1-thermal { 6171 polling-delay-passive = <10>; 6172 6173 thermal-sensors = <&tsens3 2>; 6174 6175 trips { 6176 trip-point0 { 6177 temperature = <105000>; 6178 hysteresis = <5000>; 6179 type = "passive"; 6180 }; 6181 6182 trip-point1 { 6183 temperature = <115000>; 6184 hysteresis = <5000>; 6185 type = "passive"; 6186 }; 6187 }; 6188 }; 6189 6190 cpu-1-2-1-thermal { 6191 polling-delay-passive = <10>; 6192 6193 thermal-sensors = <&tsens3 3>; 6194 6195 trips { 6196 trip-point0 { 6197 temperature = <105000>; 6198 hysteresis = <5000>; 6199 type = "passive"; 6200 }; 6201 6202 trip-point1 { 6203 temperature = <115000>; 6204 hysteresis = <5000>; 6205 type = "passive"; 6206 }; 6207 }; 6208 }; 6209 6210 cpu-1-3-1-thermal { 6211 polling-delay-passive = <10>; 6212 6213 thermal-sensors = <&tsens3 4>; 6214 6215 trips { 6216 trip-point0 { 6217 temperature = <105000>; 6218 hysteresis = <5000>; 6219 type = "passive"; 6220 }; 6221 6222 trip-point1 { 6223 temperature = <115000>; 6224 hysteresis = <5000>; 6225 type = "passive"; 6226 }; 6227 }; 6228 }; 6229 6230 nsp-0-0-1-thermal { 6231 polling-delay-passive = <10>; 6232 6233 thermal-sensors = <&tsens3 5>; 6234 6235 trips { 6236 trip-point0 { 6237 temperature = <105000>; 6238 hysteresis = <5000>; 6239 type = "passive"; 6240 }; 6241 6242 trip-point1 { 6243 temperature = <115000>; 6244 hysteresis = <5000>; 6245 type = "passive"; 6246 }; 6247 }; 6248 }; 6249 6250 nsp-0-1-1-thermal { 6251 polling-delay-passive = <10>; 6252 6253 thermal-sensors = <&tsens3 6>; 6254 6255 trips { 6256 trip-point0 { 6257 temperature = <105000>; 6258 hysteresis = <5000>; 6259 type = "passive"; 6260 }; 6261 6262 trip-point1 { 6263 temperature = <115000>; 6264 hysteresis = <5000>; 6265 type = "passive"; 6266 }; 6267 }; 6268 }; 6269 6270 nsp-0-2-1-thermal { 6271 polling-delay-passive = <10>; 6272 6273 thermal-sensors = <&tsens3 7>; 6274 6275 trips { 6276 trip-point0 { 6277 temperature = <105000>; 6278 hysteresis = <5000>; 6279 type = "passive"; 6280 }; 6281 6282 trip-point1 { 6283 temperature = <115000>; 6284 hysteresis = <5000>; 6285 type = "passive"; 6286 }; 6287 }; 6288 }; 6289 6290 nsp-1-0-1-thermal { 6291 polling-delay-passive = <10>; 6292 6293 thermal-sensors = <&tsens3 8>; 6294 6295 trips { 6296 trip-point0 { 6297 temperature = <105000>; 6298 hysteresis = <5000>; 6299 type = "passive"; 6300 }; 6301 6302 trip-point1 { 6303 temperature = <115000>; 6304 hysteresis = <5000>; 6305 type = "passive"; 6306 }; 6307 }; 6308 }; 6309 6310 nsp-1-1-1-thermal { 6311 polling-delay-passive = <10>; 6312 6313 thermal-sensors = <&tsens3 9>; 6314 6315 trips { 6316 trip-point0 { 6317 temperature = <105000>; 6318 hysteresis = <5000>; 6319 type = "passive"; 6320 }; 6321 6322 trip-point1 { 6323 temperature = <115000>; 6324 hysteresis = <5000>; 6325 type = "passive"; 6326 }; 6327 }; 6328 }; 6329 6330 nsp-1-2-1-thermal { 6331 polling-delay-passive = <10>; 6332 6333 thermal-sensors = <&tsens3 10>; 6334 6335 trips { 6336 trip-point0 { 6337 temperature = <105000>; 6338 hysteresis = <5000>; 6339 type = "passive"; 6340 }; 6341 6342 trip-point1 { 6343 temperature = <115000>; 6344 hysteresis = <5000>; 6345 type = "passive"; 6346 }; 6347 }; 6348 }; 6349 6350 ddrss-1-thermal { 6351 thermal-sensors = <&tsens3 11>; 6352 6353 trips { 6354 trip-point0 { 6355 temperature = <105000>; 6356 hysteresis = <5000>; 6357 type = "passive"; 6358 }; 6359 6360 trip-point1 { 6361 temperature = <115000>; 6362 hysteresis = <5000>; 6363 type = "passive"; 6364 }; 6365 }; 6366 }; 6367 6368 cpuss-1-1-thermal { 6369 thermal-sensors = <&tsens3 12>; 6370 6371 trips { 6372 trip-point0 { 6373 temperature = <105000>; 6374 hysteresis = <5000>; 6375 type = "passive"; 6376 }; 6377 6378 trip-point1 { 6379 temperature = <115000>; 6380 hysteresis = <5000>; 6381 type = "passive"; 6382 }; 6383 }; 6384 }; 6385 }; 6386 6387 arch_timer: timer { 6388 compatible = "arm,armv8-timer"; 6389 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6390 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6391 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6392 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6393 }; 6394 6395 pcie0: pcie@1c00000 { 6396 compatible = "qcom,pcie-sa8775p"; 6397 reg = <0x0 0x01c00000 0x0 0x3000>, 6398 <0x0 0x40000000 0x0 0xf20>, 6399 <0x0 0x40000f20 0x0 0xa8>, 6400 <0x0 0x40001000 0x0 0x4000>, 6401 <0x0 0x40100000 0x0 0x100000>, 6402 <0x0 0x01c03000 0x0 0x1000>; 6403 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 6404 device_type = "pci"; 6405 6406 #address-cells = <3>; 6407 #size-cells = <2>; 6408 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 6409 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 6410 bus-range = <0x00 0xff>; 6411 6412 dma-coherent; 6413 6414 linux,pci-domain = <0>; 6415 num-lanes = <2>; 6416 6417 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 6418 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 6419 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 6420 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 6421 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 6422 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 6423 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 6424 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 6425 interrupt-names = "msi0", "msi1", "msi2", "msi3", 6426 "msi4", "msi5", "msi6", "msi7"; 6427 #interrupt-cells = <1>; 6428 interrupt-map-mask = <0 0 0 0x7>; 6429 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 6430 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 6431 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 6432 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 6433 6434 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 6435 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 6436 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 6437 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 6438 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 6439 6440 clock-names = "aux", 6441 "cfg", 6442 "bus_master", 6443 "bus_slave", 6444 "slave_q2a"; 6445 6446 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 6447 assigned-clock-rates = <19200000>; 6448 6449 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 6450 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 6451 interconnect-names = "pcie-mem", "cpu-pcie"; 6452 6453 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 6454 <0x100 &pcie_smmu 0x0001 0x1>; 6455 6456 resets = <&gcc GCC_PCIE_0_BCR>; 6457 reset-names = "pci"; 6458 power-domains = <&gcc PCIE_0_GDSC>; 6459 6460 phys = <&pcie0_phy>; 6461 phy-names = "pciephy"; 6462 6463 status = "disabled"; 6464 6465 pcieport0: pcie@0 { 6466 device_type = "pci"; 6467 reg = <0x0 0x0 0x0 0x0 0x0>; 6468 bus-range = <0x01 0xff>; 6469 6470 #address-cells = <3>; 6471 #size-cells = <2>; 6472 ranges; 6473 }; 6474 }; 6475 6476 pcie0_ep: pcie-ep@1c00000 { 6477 compatible = "qcom,sa8775p-pcie-ep"; 6478 reg = <0x0 0x01c00000 0x0 0x3000>, 6479 <0x0 0x40000000 0x0 0xf20>, 6480 <0x0 0x40000f20 0x0 0xa8>, 6481 <0x0 0x40001000 0x0 0x4000>, 6482 <0x0 0x40200000 0x0 0x1fe00000>, 6483 <0x0 0x01c03000 0x0 0x1000>, 6484 <0x0 0x40005000 0x0 0x2000>; 6485 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 6486 "mmio", "dma"; 6487 6488 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 6489 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 6490 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 6491 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 6492 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 6493 6494 clock-names = "aux", 6495 "cfg", 6496 "bus_master", 6497 "bus_slave", 6498 "slave_q2a"; 6499 6500 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 6501 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 6502 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>; 6503 6504 interrupt-names = "global", "doorbell", "dma"; 6505 6506 interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, 6507 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; 6508 interconnect-names = "pcie-mem", "cpu-pcie"; 6509 6510 dma-coherent; 6511 iommus = <&pcie_smmu 0x0000 0x7f>; 6512 resets = <&gcc GCC_PCIE_0_BCR>; 6513 reset-names = "core"; 6514 power-domains = <&gcc PCIE_0_GDSC>; 6515 phys = <&pcie0_phy>; 6516 phy-names = "pciephy"; 6517 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ 6518 num-lanes = <2>; 6519 linux,pci-domain = <0>; 6520 6521 status = "disabled"; 6522 }; 6523 6524 pcie0_phy: phy@1c04000 { 6525 compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; 6526 reg = <0x0 0x1c04000 0x0 0x2000>; 6527 6528 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 6529 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 6530 <&gcc GCC_PCIE_CLKREF_EN>, 6531 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 6532 <&gcc GCC_PCIE_0_PIPE_CLK>, 6533 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, 6534 <&gcc GCC_PCIE_0_PHY_AUX_CLK>; 6535 6536 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 6537 "pipediv2", "phy_aux"; 6538 6539 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 6540 assigned-clock-rates = <100000000>; 6541 6542 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 6543 reset-names = "phy"; 6544 6545 #clock-cells = <0>; 6546 clock-output-names = "pcie_0_pipe_clk"; 6547 6548 #phy-cells = <0>; 6549 6550 status = "disabled"; 6551 }; 6552 6553 pcie1: pcie@1c10000 { 6554 compatible = "qcom,pcie-sa8775p"; 6555 reg = <0x0 0x01c10000 0x0 0x3000>, 6556 <0x0 0x60000000 0x0 0xf20>, 6557 <0x0 0x60000f20 0x0 0xa8>, 6558 <0x0 0x60001000 0x0 0x4000>, 6559 <0x0 0x60100000 0x0 0x100000>, 6560 <0x0 0x01c13000 0x0 0x1000>; 6561 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 6562 device_type = "pci"; 6563 6564 #address-cells = <3>; 6565 #size-cells = <2>; 6566 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 6567 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 6568 bus-range = <0x00 0xff>; 6569 6570 dma-coherent; 6571 6572 linux,pci-domain = <1>; 6573 num-lanes = <4>; 6574 6575 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 6576 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 6577 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 6578 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 6579 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 6580 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 6581 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 6582 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 6583 interrupt-names = "msi0", "msi1", "msi2", "msi3", 6584 "msi4", "msi5", "msi6", "msi7"; 6585 #interrupt-cells = <1>; 6586 interrupt-map-mask = <0 0 0 0x7>; 6587 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 6588 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 6589 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 6590 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 6591 6592 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 6593 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 6594 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 6595 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 6596 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 6597 6598 clock-names = "aux", 6599 "cfg", 6600 "bus_master", 6601 "bus_slave", 6602 "slave_q2a"; 6603 6604 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 6605 assigned-clock-rates = <19200000>; 6606 6607 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 6608 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 6609 interconnect-names = "pcie-mem", "cpu-pcie"; 6610 6611 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 6612 <0x100 &pcie_smmu 0x0081 0x1>; 6613 6614 resets = <&gcc GCC_PCIE_1_BCR>; 6615 reset-names = "pci"; 6616 power-domains = <&gcc PCIE_1_GDSC>; 6617 6618 phys = <&pcie1_phy>; 6619 phy-names = "pciephy"; 6620 6621 status = "disabled"; 6622 6623 pcie@0 { 6624 device_type = "pci"; 6625 reg = <0x0 0x0 0x0 0x0 0x0>; 6626 bus-range = <0x01 0xff>; 6627 6628 #address-cells = <3>; 6629 #size-cells = <2>; 6630 ranges; 6631 }; 6632 }; 6633 6634 pcie1_ep: pcie-ep@1c10000 { 6635 compatible = "qcom,sa8775p-pcie-ep"; 6636 reg = <0x0 0x01c10000 0x0 0x3000>, 6637 <0x0 0x60000000 0x0 0xf20>, 6638 <0x0 0x60000f20 0x0 0xa8>, 6639 <0x0 0x60001000 0x0 0x4000>, 6640 <0x0 0x60200000 0x0 0x1fe00000>, 6641 <0x0 0x01c13000 0x0 0x1000>, 6642 <0x0 0x60005000 0x0 0x2000>; 6643 reg-names = "parf", "dbi", "elbi", "atu", "addr_space", 6644 "mmio", "dma"; 6645 6646 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 6647 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 6648 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 6649 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 6650 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 6651 6652 clock-names = "aux", 6653 "cfg", 6654 "bus_master", 6655 "bus_slave", 6656 "slave_q2a"; 6657 6658 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 6659 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 6660 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 6661 6662 interrupt-names = "global", "doorbell", "dma"; 6663 6664 interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, 6665 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; 6666 interconnect-names = "pcie-mem", "cpu-pcie"; 6667 6668 dma-coherent; 6669 iommus = <&pcie_smmu 0x80 0x7f>; 6670 resets = <&gcc GCC_PCIE_1_BCR>; 6671 reset-names = "core"; 6672 power-domains = <&gcc PCIE_1_GDSC>; 6673 phys = <&pcie1_phy>; 6674 phy-names = "pciephy"; 6675 max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ 6676 num-lanes = <4>; 6677 linux,pci-domain = <1>; 6678 6679 status = "disabled"; 6680 }; 6681 6682 pcie1_phy: phy@1c14000 { 6683 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 6684 reg = <0x0 0x1c14000 0x0 0x4000>; 6685 6686 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 6687 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 6688 <&gcc GCC_PCIE_CLKREF_EN>, 6689 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 6690 <&gcc GCC_PCIE_1_PIPE_CLK>, 6691 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, 6692 <&gcc GCC_PCIE_1_PHY_AUX_CLK>; 6693 6694 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", 6695 "pipediv2", "phy_aux"; 6696 6697 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 6698 assigned-clock-rates = <100000000>; 6699 6700 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 6701 reset-names = "phy"; 6702 6703 #clock-cells = <0>; 6704 clock-output-names = "pcie_1_pipe_clk"; 6705 6706 #phy-cells = <0>; 6707 6708 status = "disabled"; 6709 }; 6710}; 6711