1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple S8001 "A9X" SoC 4 * 5 * Other names: H8G, "Elba" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "apple,twister"; 33 reg = <0x0 0x0>; 34 cpu-release-addr = <0 0>; /* To be filled in by loader */ 35 operating-points-v2 = <&twister_opp>; 36 performance-domains = <&cpufreq>; 37 enable-method = "spin-table"; 38 device_type = "cpu"; 39 next-level-cache = <&l2_cache>; 40 i-cache-size = <0x10000>; 41 d-cache-size = <0x10000>; 42 }; 43 44 cpu1: cpu@1 { 45 compatible = "apple,twister"; 46 reg = <0x0 0x1>; 47 cpu-release-addr = <0 0>; /* To be filled in by loader */ 48 operating-points-v2 = <&twister_opp>; 49 performance-domains = <&cpufreq>; 50 enable-method = "spin-table"; 51 device_type = "cpu"; 52 next-level-cache = <&l2_cache>; 53 i-cache-size = <0x10000>; 54 d-cache-size = <0x10000>; 55 }; 56 57 l2_cache: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 cache-unified; 61 cache-size = <0x300000>; 62 }; 63 }; 64 65 twister_opp: opp-table { 66 compatible = "operating-points-v2"; 67 68 opp01 { 69 opp-hz = /bits/ 64 <300000000>; 70 opp-level = <1>; 71 clock-latency-ns = <800>; 72 }; 73 opp02 { 74 opp-hz = /bits/ 64 <396000000>; 75 opp-level = <2>; 76 clock-latency-ns = <53000>; 77 }; 78 opp03 { 79 opp-hz = /bits/ 64 <792000000>; 80 opp-level = <3>; 81 clock-latency-ns = <18000>; 82 }; 83 opp04 { 84 opp-hz = /bits/ 64 <1080000000>; 85 opp-level = <4>; 86 clock-latency-ns = <21000>; 87 }; 88 opp05 { 89 opp-hz = /bits/ 64 <1440000000>; 90 opp-level = <5>; 91 clock-latency-ns = <25000>; 92 }; 93 opp06 { 94 opp-hz = /bits/ 64 <1800000000>; 95 opp-level = <6>; 96 clock-latency-ns = <33000>; 97 }; 98 opp07 { 99 opp-hz = /bits/ 64 <2160000000>; 100 opp-level = <7>; 101 clock-latency-ns = <45000>; 102 }; 103#if 0 104 /* Not available until CPU deep sleep is implemented */ 105 opp08 { 106 opp-hz = /bits/ 64 <2160000000>; 107 opp-level = <8>; 108 clock-latency-ns = <45000>; 109 turbo-mode; 110 }; 111#endif 112 }; 113 114 soc { 115 compatible = "simple-bus"; 116 #address-cells = <2>; 117 #size-cells = <2>; 118 nonposted-mmio; 119 ranges; 120 121 cpufreq: performance-controller@202220000 { 122 compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 123 reg = <0x2 0x02220000 0 0x1000>; 124 #performance-domain-cells = <0>; 125 }; 126 127 serial0: serial@20a0c0000 { 128 compatible = "apple,s5l-uart"; 129 reg = <0x2 0x0a0c0000 0x0 0x4000>; 130 reg-io-width = <4>; 131 interrupt-parent = <&aic>; 132 interrupts = <AIC_IRQ 218 IRQ_TYPE_LEVEL_HIGH>; 133 /* Use the bootloader-enabled clocks for now. */ 134 clocks = <&clkref>, <&clkref>; 135 clock-names = "uart", "clk_uart_baud0"; 136 power-domains = <&ps_uart0>; 137 status = "disabled"; 138 }; 139 140 pmgr: power-management@20e000000 { 141 compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 142 #address-cells = <1>; 143 #size-cells = <1>; 144 145 reg = <0x2 0xe000000 0 0x8c000>; 146 }; 147 148 aic: interrupt-controller@20e100000 { 149 compatible = "apple,s8000-aic", "apple,aic"; 150 reg = <0x2 0x0e100000 0x0 0x100000>; 151 #interrupt-cells = <3>; 152 interrupt-controller; 153 power-domains = <&ps_aic>; 154 }; 155 156 pinctrl_ap: pinctrl@20f100000 { 157 compatible = "apple,s8000-pinctrl", "apple,pinctrl"; 158 reg = <0x2 0x0f100000 0x0 0x100000>; 159 power-domains = <&ps_gpio>; 160 161 gpio-controller; 162 #gpio-cells = <2>; 163 gpio-ranges = <&pinctrl_ap 0 0 219>; 164 apple,npins = <219>; 165 166 interrupt-controller; 167 #interrupt-cells = <2>; 168 interrupt-parent = <&aic>; 169 interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, 170 <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, 171 <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, 172 <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 173 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 174 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 175 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; 176 }; 177 178 pinctrl_aop: pinctrl@2100f0000 { 179 compatible = "apple,s8000-pinctrl", "apple,pinctrl"; 180 reg = <0x2 0x100f0000 0x0 0x100000>; 181 power-domains = <&ps_aop_gpio>; 182 183 gpio-controller; 184 #gpio-cells = <2>; 185 gpio-ranges = <&pinctrl_aop 0 0 28>; 186 apple,npins = <28>; 187 188 interrupt-controller; 189 #interrupt-cells = <2>; 190 interrupt-parent = <&aic>; 191 interrupts = <AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH>, 192 <AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH>, 193 <AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH>, 194 <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>, 195 <AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH>, 196 <AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH>, 197 <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>; 198 }; 199 200 pmgr_mini: power-management@210200000 { 201 compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 205 reg = <0x2 0x10200000 0 0x84000>; 206 }; 207 208 wdt: watchdog@2102b0000 { 209 compatible = "apple,s8000-wdt", "apple,wdt"; 210 reg = <0x2 0x102b0000 0x0 0x4000>; 211 clocks = <&clkref>; 212 interrupt-parent = <&aic>; 213 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 214 }; 215 }; 216 217 timer { 218 compatible = "arm,armv8-timer"; 219 interrupt-parent = <&aic>; 220 interrupt-names = "phys", "virt"; 221 /* Note that A9X doesn't actually have a hypervisor (EL2 is not implemented). */ 222 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 223 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 224 }; 225}; 226 227#include "s8001-pmgr.dtsi" 228