1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple S5L8960X "A7" SoC 4 * 5 * Other Names: H6, "Alcatraz" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts. 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/apple-aic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/pinctrl/apple.h> 15 16/ { 17 interrupt-parent = <&aic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 clkref: clock-ref { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <24000000>; 25 clock-output-names = "clkref"; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 compatible = "apple,cyclone"; 34 reg = <0x0 0x0>; 35 cpu-release-addr = <0 0>; /* To be filled by loader */ 36 operating-points-v2 = <&cyclone_opp>; 37 performance-domains = <&cpufreq>; 38 enable-method = "spin-table"; 39 device_type = "cpu"; 40 next-level-cache = <&l2_cache>; 41 i-cache-size = <0x10000>; 42 d-cache-size = <0x10000>; 43 }; 44 45 cpu1: cpu@1 { 46 compatible = "apple,cyclone"; 47 reg = <0x0 0x1>; 48 cpu-release-addr = <0 0>; /* To be filled by loader */ 49 operating-points-v2 = <&cyclone_opp>; 50 performance-domains = <&cpufreq>; 51 enable-method = "spin-table"; 52 device_type = "cpu"; 53 next-level-cache = <&l2_cache>; 54 i-cache-size = <0x10000>; 55 d-cache-size = <0x10000>; 56 }; 57 58 l2_cache: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 cache-size = <0x100000>; 63 }; 64 }; 65 66 soc { 67 compatible = "simple-bus"; 68 #address-cells = <2>; 69 #size-cells = <2>; 70 nonposted-mmio; 71 ranges; 72 73 cpufreq: performance-controller@202220000 { 74 compatible = "apple,s5l8960x-cluster-cpufreq"; 75 reg = <0x2 0x02220000 0 0x1000>; 76 #performance-domain-cells = <0>; 77 }; 78 79 serial0: serial@20a0a0000 { 80 compatible = "apple,s5l-uart"; 81 reg = <0x2 0x0a0a0000 0x0 0x4000>; 82 reg-io-width = <4>; 83 interrupt-parent = <&aic>; 84 interrupts = <AIC_IRQ 140 IRQ_TYPE_LEVEL_HIGH>; 85 /* Use the bootloader-enabled clocks for now. */ 86 clocks = <&clkref>, <&clkref>; 87 clock-names = "uart", "clk_uart_baud0"; 88 power-domains = <&ps_uart0>; 89 status = "disabled"; 90 }; 91 92 pmgr: power-management@20e000000 { 93 compatible = "apple,s5l8960x-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 94 #address-cells = <1>; 95 #size-cells = <1>; 96 97 reg = <0x2 0xe000000 0 0x24000>; 98 }; 99 100 wdt: watchdog@20e027000 { 101 compatible = "apple,s5l8960x-wdt", "apple,wdt"; 102 reg = <0x2 0x0e027000 0x0 0x1000>; 103 clocks = <&clkref>; 104 interrupt-parent = <&aic>; 105 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 106 }; 107 108 aic: interrupt-controller@20e100000 { 109 compatible = "apple,s5l8960x-aic", "apple,aic"; 110 reg = <0x2 0x0e100000 0x0 0x100000>; 111 #interrupt-cells = <3>; 112 interrupt-controller; 113 power-domains = <&ps_aic>; 114 }; 115 116 dwi_bl: backlight@20e200010 { 117 compatible = "apple,s5l8960x-dwi-bl", "apple,dwi-bl"; 118 reg = <0x2 0x0e200010 0x0 0x8>; 119 power-domains = <&ps_dwi>; 120 status = "disabled"; 121 }; 122 123 pinctrl: pinctrl@20e300000 { 124 compatible = "apple,s5l8960x-pinctrl", "apple,pinctrl"; 125 reg = <0x2 0x0e300000 0x0 0x100000>; 126 power-domains = <&ps_gpio>; 127 128 gpio-controller; 129 #gpio-cells = <2>; 130 gpio-ranges = <&pinctrl 0 0 200>; 131 apple,npins = <200>; 132 133 interrupt-controller; 134 #interrupt-cells = <2>; 135 interrupt-parent = <&aic>; 136 interrupts = <AIC_IRQ 108 IRQ_TYPE_LEVEL_HIGH>, 137 <AIC_IRQ 109 IRQ_TYPE_LEVEL_HIGH>, 138 <AIC_IRQ 110 IRQ_TYPE_LEVEL_HIGH>, 139 <AIC_IRQ 111 IRQ_TYPE_LEVEL_HIGH>, 140 <AIC_IRQ 112 IRQ_TYPE_LEVEL_HIGH>, 141 <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>, 142 <AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>; 143 }; 144 }; 145 146 timer { 147 compatible = "arm,armv8-timer"; 148 interrupt-parent = <&aic>; 149 interrupt-names = "phys", "virt"; 150 /* Note that A7 doesn't actually have a hypervisor (EL2 is not implemented). */ 151 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 152 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 153 }; 154}; 155 156#include "s5l8960x-pmgr.dtsi" 157