xref: /linux/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi (revision 2f24482304ebd32c5aa374f31465b9941a860b92) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board.
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11
12#include "rzg3s-smarc-switches.h"
13
14/ {
15	compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
16
17	aliases {
18		i2c1 = &i2c1;
19		mmc0 = &sdhi0;
20#if SW_CONFIG3 == SW_OFF
21		mmc2 = &sdhi2;
22#else
23		ethernet0 = &eth0;
24		ethernet1 = &eth1;
25#endif
26	};
27
28	memory@48000000 {
29		device_type = "memory";
30		/* First 128MB is reserved for secure area. */
31		reg = <0x0 0x48000000 0x0 0x38000000>;
32	};
33
34	vcc_sdhi0: regulator0 {
35		compatible = "regulator-fixed";
36		regulator-name = "SDHI0 Vcc";
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>;
40		enable-active-high;
41	};
42
43	vccq_sdhi0: regulator1 {
44		compatible = "regulator-gpio";
45		regulator-name = "SDHI0 VccQ";
46		regulator-min-microvolt = <1800000>;
47		regulator-max-microvolt = <3300000>;
48		gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>;
49		gpios-states = <1>;
50		states = <3300000 1>, <1800000 0>;
51	};
52
53	reg_1p8v: regulator2 {
54		compatible = "regulator-fixed";
55		regulator-name = "fixed-1.8V";
56		regulator-min-microvolt = <1800000>;
57		regulator-max-microvolt = <1800000>;
58		regulator-boot-on;
59		regulator-always-on;
60	};
61
62	reg_3p3v: regulator3 {
63		compatible = "regulator-fixed";
64		regulator-name = "fixed-3.3V";
65		regulator-min-microvolt = <3300000>;
66		regulator-max-microvolt = <3300000>;
67		regulator-boot-on;
68		regulator-always-on;
69	};
70
71	vcc_sdhi2: regulator4 {
72		compatible = "regulator-fixed";
73		regulator-name = "SDHI2 Vcc";
74		regulator-min-microvolt = <3300000>;
75		regulator-max-microvolt = <3300000>;
76		gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
77		enable-active-high;
78	};
79
80	x3_clk: x3-clock {
81		compatible = "fixed-clock";
82		#clock-cells = <0>;
83		clock-frequency = <24000000>;
84	};
85};
86
87&adc {
88	status = "okay";
89};
90
91#if SW_CONFIG3 == SW_ON
92&eth0 {
93	pinctrl-0 = <&eth0_pins>;
94	pinctrl-names = "default";
95	phy-handle = <&phy0>;
96	phy-mode = "rgmii-id";
97	status = "okay";
98
99	phy0: ethernet-phy@7 {
100		reg = <7>;
101		interrupts-extended = <&pinctrl RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>;
102		rxc-skew-psec = <0>;
103		txc-skew-psec = <0>;
104		rxdv-skew-psec = <0>;
105		txen-skew-psec = <0>;
106		rxd0-skew-psec = <0>;
107		rxd1-skew-psec = <0>;
108		rxd2-skew-psec = <0>;
109		rxd3-skew-psec = <0>;
110		txd0-skew-psec = <0>;
111		txd1-skew-psec = <0>;
112		txd2-skew-psec = <0>;
113		txd3-skew-psec = <0>;
114	};
115};
116
117&eth1 {
118	pinctrl-0 = <&eth1_pins>;
119	pinctrl-names = "default";
120	phy-handle = <&phy1>;
121	phy-mode = "rgmii-id";
122	status = "okay";
123
124	phy1: ethernet-phy@7 {
125		reg = <7>;
126		interrupts-extended = <&pinctrl RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>;
127		rxc-skew-psec = <0>;
128		txc-skew-psec = <0>;
129		rxdv-skew-psec = <0>;
130		txen-skew-psec = <0>;
131		rxd0-skew-psec = <0>;
132		rxd1-skew-psec = <0>;
133		rxd2-skew-psec = <0>;
134		rxd3-skew-psec = <0>;
135		txd0-skew-psec = <0>;
136		txd1-skew-psec = <0>;
137		txd2-skew-psec = <0>;
138		txd3-skew-psec = <0>;
139	};
140};
141#endif
142
143&extal_clk {
144	clock-frequency = <24000000>;
145};
146
147&i2c1 {
148	status = "okay";
149
150	versa3: clock-generator@68 {
151		compatible = "renesas,5l35023";
152		reg = <0x68>;
153		clocks = <&x3_clk>;
154		#clock-cells = <1>;
155		assigned-clocks = <&versa3 0>,
156				  <&versa3 1>,
157				  <&versa3 2>,
158				  <&versa3 3>,
159				  <&versa3 4>,
160				  <&versa3 5>;
161		assigned-clock-rates = <24000000>,
162				       <12288000>,
163				       <11289600>,
164				       <25000000>,
165				       <100000000>,
166				       <100000000>;
167		renesas,settings = [
168		  80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
169		  00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86
170		  a0 80 30 30 9c
171		];
172	};
173};
174
175#if SW_CONFIG2 == SW_ON
176/* SD0 slot */
177&sdhi0 {
178	pinctrl-0 = <&sdhi0_pins>;
179	pinctrl-1 = <&sdhi0_uhs_pins>;
180	pinctrl-names = "default", "state_uhs";
181	vmmc-supply = <&vcc_sdhi0>;
182	vqmmc-supply = <&vccq_sdhi0>;
183	bus-width = <4>;
184	sd-uhs-sdr50;
185	sd-uhs-sdr104;
186	max-frequency = <125000000>;
187	status = "okay";
188};
189#else
190/* eMMC */
191&sdhi0 {
192	pinctrl-0 = <&sdhi0_emmc_pins>;
193	pinctrl-1 = <&sdhi0_emmc_pins>;
194	pinctrl-names = "default", "state_uhs";
195	vmmc-supply = <&vcc_sdhi0>;
196	vqmmc-supply = <&reg_1p8v>;
197	bus-width = <8>;
198	mmc-hs200-1_8v;
199	non-removable;
200	fixed-emmc-driver-type = <1>;
201	max-frequency = <125000000>;
202	status = "okay";
203};
204#endif
205
206#if SW_CONFIG3 == SW_OFF
207&sdhi2 {
208	pinctrl-0 = <&sdhi2_pins>;
209	pinctrl-names = "default";
210	vmmc-supply = <&vcc_sdhi2>;
211	bus-width = <4>;
212	max-frequency = <50000000>;
213	status = "okay";
214};
215#endif
216
217&pinctrl {
218#if SW_CONFIG3 == SW_ON
219	eth0-phy-irq-hog {
220		gpio-hog;
221		gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
222		input;
223		line-name = "eth0-phy-irq";
224	};
225#endif
226
227	eth0_pins: eth0 {
228		txc {
229			pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>;  /* ET0_TXC */
230			power-source = <1800>;
231			output-enable;
232			input-enable;
233			drive-strength-microamp = <5200>;
234		};
235
236		tx_ctl {
237			pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>;  /* ET0_TX_CTL */
238			power-source = <1800>;
239			output-enable;
240			drive-strength-microamp = <5200>;
241		};
242
243		mux {
244			pinmux = <RZG2L_PORT_PINMUX(1, 2, 1)>,	/* ET0_TXD0 */
245				 <RZG2L_PORT_PINMUX(1, 3, 1)>,	/* ET0_TXD1 */
246				 <RZG2L_PORT_PINMUX(1, 4, 1)>,	/* ET0_TXD2 */
247				 <RZG2L_PORT_PINMUX(2, 0, 1)>,	/* ET0_TXD3 */
248				 <RZG2L_PORT_PINMUX(3, 0, 1)>,	/* ET0_RXC */
249				 <RZG2L_PORT_PINMUX(3, 1, 1)>,	/* ET0_RX_CTL */
250				 <RZG2L_PORT_PINMUX(3, 2, 1)>,	/* ET0_RXD0 */
251				 <RZG2L_PORT_PINMUX(3, 3, 1)>,	/* ET0_RXD1 */
252				 <RZG2L_PORT_PINMUX(4, 0, 1)>,	/* ET0_RXD2 */
253				 <RZG2L_PORT_PINMUX(4, 1, 1)>,	/* ET0_RXD3 */
254				 <RZG2L_PORT_PINMUX(4, 3, 1)>,	/* ET0_MDC */
255				 <RZG2L_PORT_PINMUX(4, 4, 1)>,	/* ET0_MDIO */
256				 <RZG2L_PORT_PINMUX(4, 5, 1)>;	/* ET0_LINKSTA */
257			power-source = <1800>;
258		};
259	};
260
261#if SW_CONFIG3 == SW_ON
262	eth1-phy-irq-hog {
263		gpio-hog;
264		gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
265		input;
266		line-name = "eth1-phy-irq";
267	};
268#endif
269
270	eth1_pins: eth1 {
271		txc {
272			pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>;	/* ET1_TXC */
273			power-source = <1800>;
274			output-enable;
275			input-enable;
276			drive-strength-microamp = <5200>;
277		};
278
279		tx_ctl {
280			pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>;	/* ET1_TX_CTL */
281			power-source = <1800>;
282			output-enable;
283			drive-strength-microamp = <5200>;
284		};
285
286		mux {
287			pinmux = <RZG2L_PORT_PINMUX(7, 2, 1)>,	/* ET1_TXD0 */
288				 <RZG2L_PORT_PINMUX(7, 3, 1)>,	/* ET1_TXD1 */
289				 <RZG2L_PORT_PINMUX(7, 4, 1)>,	/* ET1_TXD2 */
290				 <RZG2L_PORT_PINMUX(8, 0, 1)>,	/* ET1_TXD3 */
291				 <RZG2L_PORT_PINMUX(8, 4, 1)>,	/* ET1_RXC */
292				 <RZG2L_PORT_PINMUX(9, 0, 1)>,	/* ET1_RX_CTL */
293				 <RZG2L_PORT_PINMUX(9, 1, 1)>,	/* ET1_RXD0 */
294				 <RZG2L_PORT_PINMUX(9, 2, 1)>,	/* ET1_RXD1 */
295				 <RZG2L_PORT_PINMUX(9, 3, 1)>,	/* ET1_RXD2 */
296				 <RZG2L_PORT_PINMUX(10, 0, 1)>,	/* ET1_RXD3 */
297				 <RZG2L_PORT_PINMUX(10, 2, 1)>,	/* ET1_MDC */
298				 <RZG2L_PORT_PINMUX(10, 3, 1)>,	/* ET1_MDIO */
299				 <RZG2L_PORT_PINMUX(10, 4, 1)>;	/* ET1_LINKSTA */
300			power-source = <1800>;
301		};
302	};
303
304	sdhi0_pins: sd0 {
305		data {
306			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
307			power-source = <3300>;
308		};
309
310		ctrl {
311			pins = "SD0_CLK", "SD0_CMD";
312			power-source = <3300>;
313		};
314
315		cd {
316			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
317		};
318	};
319
320	sdhi0_uhs_pins: sd0-uhs {
321		data {
322			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
323			power-source = <1800>;
324		};
325
326		ctrl {
327			pins = "SD0_CLK", "SD0_CMD";
328			power-source = <1800>;
329		};
330
331		cd {
332			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
333		};
334	};
335
336	sdhi0_emmc_pins: sd0-emmc {
337		pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
338		       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
339		       "SD0_CLK", "SD0_CMD", "SD0_RST#";
340		power-source = <1800>;
341	};
342
343	sdhi2_pins: sd2 {
344		data {
345			pins = "P11_2", "P11_3", "P12_0", "P12_1";
346			input-enable;
347		};
348
349		ctrl {
350			pins = "P11_1";
351			input-enable;
352		};
353
354		mux {
355			pinmux = <RZG2L_PORT_PINMUX(11, 0, 8)>, /* SD2_CLK */
356				 <RZG2L_PORT_PINMUX(11, 1, 8)>, /* SD2_CMD */
357				 <RZG2L_PORT_PINMUX(11, 2, 8)>, /* SD2_DATA0 */
358				 <RZG2L_PORT_PINMUX(11, 3, 8)>, /* SD2_DATA1 */
359				 <RZG2L_PORT_PINMUX(12, 0, 8)>, /* SD2_DATA2 */
360				 <RZG2L_PORT_PINMUX(12, 1, 8)>, /* SD2_DATA3 */
361				 <RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */
362		};
363	};
364};
365
366&rtc {
367	status = "okay";
368};
369
370&vbattb {
371	assigned-clocks = <&vbattb VBATTB_MUX>;
372	assigned-clock-parents = <&vbattb VBATTB_XC>;
373	quartz-load-femtofarads = <12500>;
374	status = "okay";
375};
376
377&vbattb_xtal {
378	clock-frequency = <32768>;
379};
380
381&wdt0 {
382	timeout-sec = <60>;
383	status = "okay";
384};
385