1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 10 11/ { 12 aliases { 13 serial1 = &scif2; 14 i2c3 = &i2c3; 15 }; 16 17 osc1: cec-clock { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 clock-frequency = <12000000>; 21 }; 22 23 hdmi-out { 24 compatible = "hdmi-connector"; 25 type = "d"; 26 27 port { 28 hdmi_con_out: endpoint { 29 remote-endpoint = <&adv7535_out>; 30 }; 31 }; 32 }; 33 34 sound_card { 35 compatible = "audio-graph-card"; 36 label = "HDMI-Audio"; 37 dais = <&i2s2_port>; 38 }; 39}; 40 41&cpu_dai { 42 sound-dai = <&ssi0>; 43}; 44 45&dsi { 46 status = "okay"; 47 48 ports { 49 port@1 { 50 dsi0_out: endpoint { 51 data-lanes = <1 2 3 4>; 52 remote-endpoint = <&adv7535_in>; 53 }; 54 }; 55 }; 56}; 57 58&du { 59 status = "okay"; 60}; 61 62&i2c1 { 63 adv7535: hdmi@3d { 64 compatible = "adi,adv7535"; 65 reg = <0x3d>; 66 67 interrupts-extended = <&pinctrl RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>; 68 clocks = <&osc1>; 69 clock-names = "cec"; 70 avdd-supply = <®_1p8v>; 71 dvdd-supply = <®_1p8v>; 72 pvdd-supply = <®_1p8v>; 73 a2vdd-supply = <®_1p8v>; 74 v3p3-supply = <®_3p3v>; 75 v1p2-supply = <®_1p8v>; 76 77 adi,dsi-lanes = <4>; 78 79 ports { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 port@0 { 84 reg = <0>; 85 adv7535_in: endpoint { 86 remote-endpoint = <&dsi0_out>; 87 }; 88 }; 89 90 port@1 { 91 reg = <1>; 92 adv7535_out: endpoint { 93 remote-endpoint = <&hdmi_con_out>; 94 }; 95 }; 96 97 port@2 { 98 reg = <2>; 99 codec_endpoint: endpoint { 100 remote-endpoint = <&i2s2_cpu_endpoint>; 101 }; 102 }; 103 }; 104 }; 105}; 106 107&i2c3 { 108 pinctrl-0 = <&i2c3_pins>; 109 pinctrl-names = "default"; 110 clock-frequency = <400000>; 111 112 status = "okay"; 113 114 wm8978: codec@1a { 115 compatible = "wlf,wm8978"; 116 #sound-dai-cells = <0>; 117 reg = <0x1a>; 118 }; 119 120 versa3: clock-generator@68 { 121 compatible = "renesas,5p35023"; 122 reg = <0x68>; 123 #clock-cells = <1>; 124 clocks = <&x1>; 125 126 renesas,settings = [ 127 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf 128 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 129 80 b0 45 c4 95 130 ]; 131 132 assigned-clocks = <&versa3 0>, <&versa3 1>, 133 <&versa3 2>, <&versa3 3>, 134 <&versa3 4>, <&versa3 5>; 135 assigned-clock-rates = <24000000>, <11289600>, 136 <11289600>, <12000000>, 137 <25000000>, <12288000>; 138 }; 139}; 140 141#if PMOD_MTU3 142&mtu3 { 143 pinctrl-0 = <&mtu3_pins>; 144 pinctrl-names = "default"; 145 146 status = "okay"; 147}; 148 149#if MTU3_COUNTER_Z_PHASE_SIGNAL 150/* SDHI cd pin is muxed with counter Z phase signal */ 151&sdhi1 { 152 status = "disabled"; 153}; 154#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ 155 156&spi1 { 157 status = "disabled"; 158}; 159#endif /* PMOD_MTU3 */ 160 161/* 162 * To enable SCIF2 (SER0) on PMOD1 (CN7) 163 * SW1 should be at position 2->3 so that SER0_CTS# line is activated 164 * SW2 should be at position 2->3 so that SER0_TX line is activated 165 * SW3 should be at position 2->3 so that SER0_RX line is activated 166 * SW4 should be at position 2->3 so that SER0_RTS# line is activated 167 */ 168#if PMOD1_SER0 169&scif2 { 170 pinctrl-0 = <&scif2_pins>; 171 pinctrl-names = "default"; 172 173 uart-has-rtscts; 174 status = "okay"; 175}; 176#endif 177 178&ssi0 { 179 pinctrl-0 = <&ssi0_pins>; 180 pinctrl-names = "default"; 181 182 status = "okay"; 183}; 184 185&ssi1 { 186 pinctrl-0 = <&ssi1_pins>; 187 pinctrl-names = "default"; 188 189 status = "okay"; 190 191 i2s2_port: port { 192 i2s2_cpu_endpoint: endpoint { 193 remote-endpoint = <&codec_endpoint>; 194 dai-format = "i2s"; 195 196 bitclock-master = <&i2s2_cpu_endpoint>; 197 frame-master = <&i2s2_cpu_endpoint>; 198 }; 199 }; 200}; 201 202&vccq_sdhi1 { 203 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; 204}; 205