1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 10 11/ { 12 aliases { 13 serial1 = &scif2; 14 i2c3 = &i2c3; 15 }; 16 17 osc1: cec-clock { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 clock-frequency = <12000000>; 21 }; 22 23 hdmi-out { 24 compatible = "hdmi-connector"; 25 type = "d"; 26 27 port { 28 hdmi_con_out: endpoint { 29 remote-endpoint = <&adv7535_out>; 30 }; 31 }; 32 }; 33 34 sound_card { 35 compatible = "audio-graph-card"; 36 label = "HDMI-Audio"; 37 dais = <&i2s2_port>; 38 }; 39}; 40 41&cpu_dai { 42 sound-dai = <&ssi0>; 43}; 44 45&dsi { 46 status = "okay"; 47 48 ports { 49 port@1 { 50 dsi0_out: endpoint { 51 data-lanes = <1 2 3 4>; 52 remote-endpoint = <&adv7535_in>; 53 }; 54 }; 55 }; 56}; 57 58&du { 59 status = "okay"; 60}; 61 62&i2c1 { 63 adv7535: hdmi@3d { 64 compatible = "adi,adv7535"; 65 reg = <0x3d>; 66 67 interrupts-extended = <&pinctrl RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>; 68 clocks = <&osc1>; 69 clock-names = "cec"; 70 avdd-supply = <®_1p8v>; 71 dvdd-supply = <®_1p8v>; 72 pvdd-supply = <®_1p8v>; 73 a2vdd-supply = <®_1p8v>; 74 v3p3-supply = <®_3p3v>; 75 v1p2-supply = <®_1p8v>; 76 77 adi,dsi-lanes = <4>; 78 79 ports { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 port@0 { 84 reg = <0>; 85 adv7535_in: endpoint { 86 remote-endpoint = <&dsi0_out>; 87 }; 88 }; 89 90 port@1 { 91 reg = <1>; 92 adv7535_out: endpoint { 93 remote-endpoint = <&hdmi_con_out>; 94 }; 95 }; 96 97 port@2 { 98 reg = <2>; 99 codec_endpoint: endpoint { 100 remote-endpoint = <&i2s2_cpu_endpoint>; 101 }; 102 }; 103 }; 104 }; 105}; 106 107#if PMOD0_GPT 108&gpt { 109 pinctrl-0 = <&gpt_pins>; 110 pinctrl-names = "default"; 111 status = "okay"; 112}; 113#endif /* PMOD0_GPT */ 114 115&i2c3 { 116 pinctrl-0 = <&i2c3_pins>; 117 pinctrl-names = "default"; 118 clock-frequency = <400000>; 119 120 status = "okay"; 121 122 wm8978: codec@1a { 123 compatible = "wlf,wm8978"; 124 #sound-dai-cells = <0>; 125 reg = <0x1a>; 126 }; 127 128 versa3: clock-generator@68 { 129 compatible = "renesas,5p35023"; 130 reg = <0x68>; 131 #clock-cells = <1>; 132 clocks = <&x1>; 133 134 renesas,settings = [ 135 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf 136 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 137 80 b0 45 c4 95 138 ]; 139 140 assigned-clocks = <&versa3 0>, <&versa3 1>, 141 <&versa3 2>, <&versa3 3>, 142 <&versa3 4>, <&versa3 5>; 143 assigned-clock-rates = <24000000>, <11289600>, 144 <11289600>, <12000000>, 145 <25000000>, <12288000>; 146 }; 147}; 148 149#if PMOD_MTU3 150&mtu3 { 151 pinctrl-0 = <&mtu3_pins>; 152 pinctrl-names = "default"; 153 154 status = "okay"; 155}; 156 157#if MTU3_COUNTER_Z_PHASE_SIGNAL 158/* SDHI cd pin is muxed with counter Z phase signal */ 159&sdhi1 { 160 status = "disabled"; 161}; 162#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ 163 164&spi1 { 165 status = "disabled"; 166}; 167#endif /* PMOD_MTU3 */ 168 169/* 170 * To enable SCIF2 (SER0) on PMOD1 (CN7) 171 * SW1 should be at position 2->3 so that SER0_CTS# line is activated 172 * SW2 should be at position 2->3 so that SER0_TX line is activated 173 * SW3 should be at position 2->3 so that SER0_RX line is activated 174 * SW4 should be at position 2->3 so that SER0_RTS# line is activated 175 */ 176#if PMOD1_SER0 177&scif2 { 178 pinctrl-0 = <&scif2_pins>; 179 pinctrl-names = "default"; 180 181 uart-has-rtscts; 182 status = "okay"; 183}; 184#endif 185 186&ssi0 { 187 pinctrl-0 = <&ssi0_pins>; 188 pinctrl-names = "default"; 189 190 status = "okay"; 191}; 192 193&ssi1 { 194 pinctrl-0 = <&ssi1_pins>; 195 pinctrl-names = "default"; 196 197 status = "okay"; 198 199 i2s2_port: port { 200 i2s2_cpu_endpoint: endpoint { 201 remote-endpoint = <&codec_endpoint>; 202 dai-format = "i2s"; 203 204 bitclock-master = <&i2s2_cpu_endpoint>; 205 frame-master = <&i2s2_cpu_endpoint>; 206 }; 207 }; 208}; 209 210&vccq_sdhi1 { 211 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; 212}; 213