1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rv1126-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rockchip,rv1126-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 compatible = "rockchip,rv1126"; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 serial0 = &uart0; 27 serial1 = &uart1; 28 serial2 = &uart2; 29 serial3 = &uart3; 30 serial4 = &uart4; 31 serial5 = &uart5; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu0: cpu@f00 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a7"; 41 reg = <0xf00>; 42 enable-method = "psci"; 43 clocks = <&cru ARMCLK>; 44 }; 45 46 cpu1: cpu@f01 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf01>; 50 enable-method = "psci"; 51 clocks = <&cru ARMCLK>; 52 }; 53 54 cpu2: cpu@f02 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a7"; 57 reg = <0xf02>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 }; 61 62 cpu3: cpu@f03 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a7"; 65 reg = <0xf03>; 66 enable-method = "psci"; 67 clocks = <&cru ARMCLK>; 68 }; 69 }; 70 71 arm-pmu { 72 compatible = "arm,cortex-a7-pmu"; 73 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 77 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 78 }; 79 80 psci { 81 compatible = "arm,psci-1.0"; 82 method = "smc"; 83 }; 84 85 timer { 86 compatible = "arm,armv7-timer"; 87 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 88 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 89 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 90 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 91 clock-frequency = <24000000>; 92 }; 93 94 display_subsystem { 95 compatible = "rockchip,display-subsystem"; 96 ports = <&vop_out>; 97 }; 98 99 xin24m: oscillator { 100 compatible = "fixed-clock"; 101 clock-frequency = <24000000>; 102 clock-output-names = "xin24m"; 103 #clock-cells = <0>; 104 }; 105 106 grf: syscon@fe000000 { 107 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; 108 reg = <0xfe000000 0x20000>; 109 }; 110 111 pmugrf: syscon@fe020000 { 112 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; 113 reg = <0xfe020000 0x1000>; 114 115 pmu_io_domains: io-domains { 116 compatible = "rockchip,rv1126-pmu-io-voltage-domain"; 117 status = "disabled"; 118 }; 119 }; 120 121 qos_emmc: qos@fe860000 { 122 compatible = "rockchip,rv1126-qos", "syscon"; 123 reg = <0xfe860000 0x20>; 124 }; 125 126 qos_nandc: qos@fe860080 { 127 compatible = "rockchip,rv1126-qos", "syscon"; 128 reg = <0xfe860080 0x20>; 129 }; 130 131 qos_sfc: qos@fe860200 { 132 compatible = "rockchip,rv1126-qos", "syscon"; 133 reg = <0xfe860200 0x20>; 134 }; 135 136 qos_sdio: qos@fe86c000 { 137 compatible = "rockchip,rv1126-qos", "syscon"; 138 reg = <0xfe86c000 0x20>; 139 }; 140 141 qos_iep: qos@fe8a0000 { 142 compatible = "rockchip,rv1126-qos", "syscon"; 143 reg = <0xfe8a0000 0x20>; 144 }; 145 146 qos_rga_rd: qos@fe8a0080 { 147 compatible = "rockchip,rv1126-qos", "syscon"; 148 reg = <0xfe8a0080 0x20>; 149 }; 150 151 qos_rga_wr: qos@fe8a0100 { 152 compatible = "rockchip,rv1126-qos", "syscon"; 153 reg = <0xfe8a0100 0x20>; 154 }; 155 156 qos_vop: qos@fe8a0180 { 157 compatible = "rockchip,rv1126-qos", "syscon"; 158 reg = <0xfe8a0180 0x20>; 159 }; 160 161 gic: interrupt-controller@feff0000 { 162 compatible = "arm,gic-400"; 163 interrupt-controller; 164 #interrupt-cells = <3>; 165 #address-cells = <0>; 166 167 reg = <0xfeff1000 0x1000>, 168 <0xfeff2000 0x2000>, 169 <0xfeff4000 0x2000>, 170 <0xfeff6000 0x2000>; 171 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 172 }; 173 174 pmu: power-management@ff3e0000 { 175 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; 176 reg = <0xff3e0000 0x1000>; 177 178 power: power-controller { 179 compatible = "rockchip,rv1126-power-controller"; 180 #power-domain-cells = <1>; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 184 power-domain@RV1126_PD_NVM { 185 reg = <RV1126_PD_NVM>; 186 clocks = <&cru HCLK_EMMC>, 187 <&cru CLK_EMMC>, 188 <&cru HCLK_NANDC>, 189 <&cru CLK_NANDC>, 190 <&cru HCLK_SFC>, 191 <&cru HCLK_SFCXIP>, 192 <&cru SCLK_SFC>; 193 pm_qos = <&qos_emmc>, 194 <&qos_nandc>, 195 <&qos_sfc>; 196 #power-domain-cells = <0>; 197 }; 198 199 power-domain@RV1126_PD_SDIO { 200 reg = <RV1126_PD_SDIO>; 201 clocks = <&cru HCLK_SDIO>, 202 <&cru CLK_SDIO>; 203 pm_qos = <&qos_sdio>; 204 #power-domain-cells = <0>; 205 }; 206 207 power-domain@RV1126_PD_VO { 208 reg = <RV1126_PD_VO>; 209 clocks = <&cru ACLK_RGA>, 210 <&cru HCLK_RGA>, 211 <&cru CLK_RGA_CORE>, 212 <&cru ACLK_VOP>, 213 <&cru HCLK_VOP>, 214 <&cru DCLK_VOP>, 215 <&cru PCLK_DSIHOST>, 216 <&cru ACLK_IEP>, 217 <&cru HCLK_IEP>, 218 <&cru CLK_IEP_CORE>; 219 pm_qos = <&qos_rga_rd>, 220 <&qos_rga_wr>, 221 <&qos_vop>, 222 <&qos_iep>; 223 #power-domain-cells = <0>; 224 }; 225 }; 226 }; 227 228 i2c0: i2c@ff3f0000 { 229 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 230 reg = <0xff3f0000 0x1000>; 231 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 232 rockchip,grf = <&pmugrf>; 233 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 234 clock-names = "i2c", "pclk"; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&i2c0_xfer>; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 status = "disabled"; 240 }; 241 242 i2c2: i2c@ff400000 { 243 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 244 reg = <0xff400000 0x1000>; 245 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 246 rockchip,grf = <&pmugrf>; 247 clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>; 248 clock-names = "i2c", "pclk"; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&i2c2_xfer>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 status = "disabled"; 254 }; 255 256 uart1: serial@ff410000 { 257 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 258 reg = <0xff410000 0x100>; 259 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 260 clock-frequency = <24000000>; 261 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; 262 clock-names = "baudclk", "apb_pclk"; 263 dmas = <&dmac 7>, <&dmac 6>; 264 dma-names = "tx", "rx"; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&uart1m0_xfer>; 267 reg-shift = <2>; 268 reg-io-width = <4>; 269 status = "disabled"; 270 }; 271 272 pwm0: pwm@ff430000 { 273 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 274 reg = <0xff430000 0x10>; 275 clock-names = "pwm", "pclk"; 276 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pwm0m0_pins>; 279 #pwm-cells = <3>; 280 status = "disabled"; 281 }; 282 283 pwm1: pwm@ff430010 { 284 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 285 reg = <0xff430010 0x10>; 286 clock-names = "pwm", "pclk"; 287 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&pwm1m0_pins>; 290 #pwm-cells = <3>; 291 status = "disabled"; 292 }; 293 294 pwm2: pwm@ff430020 { 295 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 296 reg = <0xff430020 0x10>; 297 clock-names = "pwm", "pclk"; 298 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pwm2m0_pins>; 301 #pwm-cells = <3>; 302 status = "disabled"; 303 }; 304 305 pwm3: pwm@ff430030 { 306 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 307 reg = <0xff430030 0x10>; 308 clock-names = "pwm", "pclk"; 309 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&pwm3m0_pins>; 312 #pwm-cells = <3>; 313 status = "disabled"; 314 }; 315 316 pwm4: pwm@ff440000 { 317 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 318 reg = <0xff440000 0x10>; 319 clock-names = "pwm", "pclk"; 320 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 321 pinctrl-names = "default"; 322 pinctrl-0 = <&pwm4m0_pins>; 323 #pwm-cells = <3>; 324 status = "disabled"; 325 }; 326 327 pwm5: pwm@ff440010 { 328 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 329 reg = <0xff440010 0x10>; 330 clock-names = "pwm", "pclk"; 331 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pwm5m0_pins>; 334 #pwm-cells = <3>; 335 status = "disabled"; 336 }; 337 338 pwm6: pwm@ff440020 { 339 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 340 reg = <0xff440020 0x10>; 341 clock-names = "pwm", "pclk"; 342 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pwm6m0_pins>; 345 #pwm-cells = <3>; 346 status = "disabled"; 347 }; 348 349 pwm7: pwm@ff440030 { 350 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 351 reg = <0xff440030 0x10>; 352 clock-names = "pwm", "pclk"; 353 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&pwm7m0_pins>; 356 #pwm-cells = <3>; 357 status = "disabled"; 358 }; 359 360 pmucru: clock-controller@ff480000 { 361 compatible = "rockchip,rv1126-pmucru"; 362 reg = <0xff480000 0x1000>; 363 rockchip,grf = <&grf>; 364 #clock-cells = <1>; 365 #reset-cells = <1>; 366 }; 367 368 cru: clock-controller@ff490000 { 369 compatible = "rockchip,rv1126-cru"; 370 reg = <0xff490000 0x1000>; 371 clocks = <&xin24m>; 372 clock-names = "xin24m"; 373 rockchip,grf = <&grf>; 374 #clock-cells = <1>; 375 #reset-cells = <1>; 376 }; 377 378 dmac: dma-controller@ff4e0000 { 379 compatible = "arm,pl330", "arm,primecell"; 380 reg = <0xff4e0000 0x4000>; 381 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 383 #dma-cells = <1>; 384 arm,pl330-periph-burst; 385 clocks = <&cru ACLK_DMAC>; 386 clock-names = "apb_pclk"; 387 }; 388 389 i2c3: i2c@ff520000 { 390 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 391 reg = <0xff520000 0x1000>; 392 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 394 clock-names = "i2c", "pclk"; 395 pinctrl-names = "default"; 396 pinctrl-0 = <&i2c3m0_xfer>; 397 rockchip,grf = <&pmugrf>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 status = "disabled"; 401 }; 402 403 pwm8: pwm@ff550000 { 404 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 405 reg = <0xff550000 0x10>; 406 clock-names = "pwm", "pclk"; 407 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 408 pinctrl-0 = <&pwm8m0_pins>; 409 pinctrl-names = "default"; 410 #pwm-cells = <3>; 411 status = "disabled"; 412 }; 413 414 pwm9: pwm@ff550010 { 415 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 416 reg = <0xff550010 0x10>; 417 clock-names = "pwm", "pclk"; 418 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 419 pinctrl-0 = <&pwm9m0_pins>; 420 pinctrl-names = "default"; 421 #pwm-cells = <3>; 422 status = "disabled"; 423 }; 424 425 pwm10: pwm@ff550020 { 426 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 427 reg = <0xff550020 0x10>; 428 clock-names = "pwm", "pclk"; 429 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 430 pinctrl-0 = <&pwm10m0_pins>; 431 pinctrl-names = "default"; 432 #pwm-cells = <3>; 433 status = "disabled"; 434 }; 435 436 pwm11: pwm@ff550030 { 437 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 438 reg = <0xff550030 0x10>; 439 clock-names = "pwm", "pclk"; 440 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 441 pinctrl-0 = <&pwm11m0_pins>; 442 pinctrl-names = "default"; 443 #pwm-cells = <3>; 444 status = "disabled"; 445 }; 446 447 uart0: serial@ff560000 { 448 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 449 reg = <0xff560000 0x100>; 450 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 451 clock-frequency = <24000000>; 452 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 453 clock-names = "baudclk", "apb_pclk"; 454 dmas = <&dmac 5>, <&dmac 4>; 455 dma-names = "tx", "rx"; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&uart0_xfer>; 458 reg-shift = <2>; 459 reg-io-width = <4>; 460 status = "disabled"; 461 }; 462 463 uart2: serial@ff570000 { 464 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 465 reg = <0xff570000 0x100>; 466 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 467 clock-frequency = <24000000>; 468 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 469 clock-names = "baudclk", "apb_pclk"; 470 dmas = <&dmac 9>, <&dmac 8>; 471 dma-names = "tx", "rx"; 472 pinctrl-names = "default"; 473 pinctrl-0 = <&uart2m1_xfer>; 474 reg-shift = <2>; 475 reg-io-width = <4>; 476 status = "disabled"; 477 }; 478 479 uart3: serial@ff580000 { 480 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 481 reg = <0xff580000 0x100>; 482 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 483 clock-frequency = <24000000>; 484 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 485 clock-names = "baudclk", "apb_pclk"; 486 dmas = <&dmac 11>, <&dmac 10>; 487 dma-names = "tx", "rx"; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&uart3m0_xfer>; 490 reg-shift = <2>; 491 reg-io-width = <4>; 492 status = "disabled"; 493 }; 494 495 uart4: serial@ff590000 { 496 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 497 reg = <0xff590000 0x100>; 498 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 499 clock-frequency = <24000000>; 500 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 501 clock-names = "baudclk", "apb_pclk"; 502 dmas = <&dmac 13>, <&dmac 12>; 503 dma-names = "tx", "rx"; 504 pinctrl-names = "default"; 505 pinctrl-0 = <&uart4m0_xfer>; 506 reg-shift = <2>; 507 reg-io-width = <4>; 508 status = "disabled"; 509 }; 510 511 uart5: serial@ff5a0000 { 512 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 513 reg = <0xff5a0000 0x100>; 514 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 515 clock-frequency = <24000000>; 516 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 517 clock-names = "baudclk", "apb_pclk"; 518 dmas = <&dmac 15>, <&dmac 14>; 519 dma-names = "tx", "rx"; 520 pinctrl-names = "default"; 521 pinctrl-0 = <&uart5m0_xfer>; 522 reg-shift = <2>; 523 reg-io-width = <4>; 524 status = "disabled"; 525 }; 526 527 saradc: adc@ff5e0000 { 528 compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc"; 529 reg = <0xff5e0000 0x100>; 530 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 531 #io-channel-cells = <1>; 532 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 533 clock-names = "saradc", "apb_pclk"; 534 resets = <&cru SRST_SARADC_P>; 535 reset-names = "saradc-apb"; 536 status = "disabled"; 537 }; 538 539 timer0: timer@ff660000 { 540 compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer"; 541 reg = <0xff660000 0x20>; 542 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 544 clock-names = "pclk", "timer"; 545 }; 546 547 wdt: watchdog@ff680000 { 548 compatible = "rockchip,rv1126-wdt", "snps,dw-wdt"; 549 reg = <0xff680000 0x100>; 550 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&cru PCLK_WDT>; 552 status = "disabled"; 553 }; 554 555 i2s0: i2s@ff800000 { 556 compatible = "rockchip,rv1126-i2s-tdm"; 557 reg = <0xff800000 0x1000>; 558 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>; 560 clock-names = "mclk_tx", "mclk_rx", "hclk"; 561 dmas = <&dmac 20>, <&dmac 19>; 562 dma-names = "tx", "rx"; 563 pinctrl-names = "default"; 564 pinctrl-0 = <&i2s0m0_sclk_tx>, 565 <&i2s0m0_sclk_rx>, 566 <&i2s0m0_mclk>, 567 <&i2s0m0_lrck_tx>, 568 <&i2s0m0_lrck_rx>, 569 <&i2s0m0_sdi0>, 570 <&i2s0m0_sdo0>, 571 <&i2s0m0_sdo1_sdi3>, 572 <&i2s0m0_sdo2_sdi2>, 573 <&i2s0m0_sdo3_sdi1>; 574 resets = <&cru SRST_I2S0_TX_M>, <&cru SRST_I2S0_RX_M>; 575 reset-names = "tx-m", "rx-m"; 576 rockchip,grf = <&grf>; 577 #sound-dai-cells = <0>; 578 status = "disabled"; 579 }; 580 581 vop: vop@ffb00000 { 582 compatible = "rockchip,rv1126-vop"; 583 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; 584 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 585 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 586 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 587 reset-names = "axi", "ahb", "dclk"; 588 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 589 iommus = <&vop_mmu>; 590 power-domains = <&power RV1126_PD_VO>; 591 status = "disabled"; 592 593 vop_out: port { 594 #address-cells = <1>; 595 #size-cells = <0>; 596 597 vop_out_rgb: endpoint@0 { 598 reg = <0>; 599 }; 600 601 vop_out_dsi: endpoint@1 { 602 reg = <1>; 603 }; 604 }; 605 }; 606 607 vop_mmu: iommu@ffb00f00 { 608 compatible = "rockchip,iommu"; 609 reg = <0xffb00f00 0x100>; 610 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 611 clock-names = "aclk", "iface"; 612 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 613 #iommu-cells = <0>; 614 power-domains = <&power RV1126_PD_VO>; 615 status = "disabled"; 616 }; 617 618 gmac: ethernet@ffc40000 { 619 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; 620 reg = <0xffc40000 0x4000>; 621 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 623 interrupt-names = "macirq", "eth_wake_irq"; 624 rockchip,grf = <&grf>; 625 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 626 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, 627 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 628 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; 629 clock-names = "stmmaceth", "mac_clk_rx", 630 "mac_clk_tx", "clk_mac_ref", 631 "aclk_mac", "pclk_mac", 632 "clk_mac_speed", "ptp_ref"; 633 resets = <&cru SRST_GMAC_A>; 634 reset-names = "stmmaceth"; 635 636 snps,mixed-burst; 637 snps,tso; 638 639 snps,axi-config = <&stmmac_axi_setup>; 640 snps,mtl-rx-config = <&mtl_rx_setup>; 641 snps,mtl-tx-config = <&mtl_tx_setup>; 642 status = "disabled"; 643 644 mdio: mdio { 645 compatible = "snps,dwmac-mdio"; 646 #address-cells = <0x1>; 647 #size-cells = <0x0>; 648 }; 649 650 stmmac_axi_setup: stmmac-axi-config { 651 snps,wr_osr_lmt = <4>; 652 snps,rd_osr_lmt = <8>; 653 snps,blen = <0 0 0 0 16 8 4>; 654 }; 655 656 mtl_rx_setup: rx-queues-config { 657 snps,rx-queues-to-use = <1>; 658 queue0 {}; 659 }; 660 661 mtl_tx_setup: tx-queues-config { 662 snps,tx-queues-to-use = <1>; 663 queue0 {}; 664 }; 665 }; 666 667 emmc: mmc@ffc50000 { 668 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 669 reg = <0xffc50000 0x4000>; 670 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, 672 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 673 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 674 fifo-depth = <0x100>; 675 max-frequency = <200000000>; 676 power-domains = <&power RV1126_PD_NVM>; 677 status = "disabled"; 678 }; 679 680 sdmmc: mmc@ffc60000 { 681 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 682 reg = <0xffc60000 0x4000>; 683 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, 685 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 686 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 687 fifo-depth = <0x100>; 688 max-frequency = <200000000>; 689 status = "disabled"; 690 }; 691 692 sdio: mmc@ffc70000 { 693 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 694 reg = <0xffc70000 0x4000>; 695 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, 697 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 698 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 699 fifo-depth = <0x100>; 700 max-frequency = <200000000>; 701 power-domains = <&power RV1126_PD_SDIO>; 702 status = "disabled"; 703 }; 704 705 sfc: spi@ffc90000 { 706 compatible = "rockchip,sfc"; 707 reg = <0xffc90000 0x4000>; 708 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 709 assigned-clocks = <&cru SCLK_SFC>; 710 assigned-clock-rates = <80000000>; 711 clock-names = "clk_sfc", "hclk_sfc"; 712 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 713 power-domains = <&power RV1126_PD_NVM>; 714 status = "disabled"; 715 }; 716 717 pinctrl: pinctrl { 718 compatible = "rockchip,rv1126-pinctrl"; 719 rockchip,grf = <&grf>; 720 rockchip,pmu = <&pmugrf>; 721 #address-cells = <1>; 722 #size-cells = <1>; 723 ranges; 724 725 gpio0: gpio@ff460000 { 726 compatible = "rockchip,gpio-bank"; 727 reg = <0xff460000 0x100>; 728 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 730 gpio-controller; 731 #gpio-cells = <2>; 732 interrupt-controller; 733 #interrupt-cells = <2>; 734 }; 735 736 gpio1: gpio@ff620000 { 737 compatible = "rockchip,gpio-bank"; 738 reg = <0xff620000 0x100>; 739 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 741 gpio-controller; 742 #gpio-cells = <2>; 743 interrupt-controller; 744 #interrupt-cells = <2>; 745 }; 746 747 gpio2: gpio@ff630000 { 748 compatible = "rockchip,gpio-bank"; 749 reg = <0xff630000 0x100>; 750 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 752 gpio-controller; 753 #gpio-cells = <2>; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 }; 757 758 gpio3: gpio@ff640000 { 759 compatible = "rockchip,gpio-bank"; 760 reg = <0xff640000 0x100>; 761 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 763 gpio-controller; 764 #gpio-cells = <2>; 765 interrupt-controller; 766 #interrupt-cells = <2>; 767 }; 768 769 gpio4: gpio@ff650000 { 770 compatible = "rockchip,gpio-bank"; 771 reg = <0xff650000 0x100>; 772 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 774 gpio-controller; 775 #gpio-cells = <2>; 776 interrupt-controller; 777 #interrupt-cells = <2>; 778 }; 779 }; 780}; 781 782#include "rv1126-pinctrl.dtsi" 783