1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/rv1108-cru.h> 7#include <dt-bindings/pinctrl/rockchip.h> 8#include <dt-bindings/thermal/thermal.h> 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 13 compatible = "rockchip,rv1108"; 14 15 interrupt-parent = <&gic>; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 serial0 = &uart0; 23 serial1 = &uart1; 24 serial2 = &uart2; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@f00 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a7"; 34 reg = <0xf00>; 35 clocks = <&cru ARMCLK>; 36 #cooling-cells = <2>; /* min followed by max */ 37 dynamic-power-coefficient = <75>; 38 operating-points-v2 = <&cpu_opp_table>; 39 }; 40 }; 41 42 cpu_opp_table: opp-table-0 { 43 compatible = "operating-points-v2"; 44 45 opp-408000000 { 46 opp-hz = /bits/ 64 <408000000>; 47 opp-microvolt = <975000>; 48 clock-latency-ns = <40000>; 49 }; 50 opp-600000000 { 51 opp-hz = /bits/ 64 <600000000>; 52 opp-microvolt = <975000>; 53 clock-latency-ns = <40000>; 54 }; 55 opp-816000000 { 56 opp-hz = /bits/ 64 <816000000>; 57 opp-microvolt = <1025000>; 58 clock-latency-ns = <40000>; 59 }; 60 opp-1008000000 { 61 opp-hz = /bits/ 64 <1008000000>; 62 opp-microvolt = <1150000>; 63 clock-latency-ns = <40000>; 64 }; 65 }; 66 67 arm-pmu { 68 compatible = "arm,cortex-a7-pmu"; 69 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 70 }; 71 72 timer { 73 compatible = "arm,armv7-timer"; 74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, 75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 76 arm,cpu-registers-not-fw-configured; 77 clock-frequency = <24000000>; 78 }; 79 80 xin24m: oscillator { 81 compatible = "fixed-clock"; 82 clock-frequency = <24000000>; 83 clock-output-names = "xin24m"; 84 #clock-cells = <0>; 85 }; 86 87 bus_intmem: sram@10080000 { 88 compatible = "mmio-sram"; 89 reg = <0x10080000 0x2000>; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 ranges = <0 0x10080000 0x2000>; 93 }; 94 95 uart2: serial@10210000 { 96 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 97 reg = <0x10210000 0x100>; 98 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 99 reg-shift = <2>; 100 reg-io-width = <4>; 101 clock-frequency = <24000000>; 102 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 103 clock-names = "baudclk", "apb_pclk"; 104 dmas = <&pdma 6>, <&pdma 7>; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&uart2m0_xfer>; 107 status = "disabled"; 108 }; 109 110 uart1: serial@10220000 { 111 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 112 reg = <0x10220000 0x100>; 113 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 114 reg-shift = <2>; 115 reg-io-width = <4>; 116 clock-frequency = <24000000>; 117 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 118 clock-names = "baudclk", "apb_pclk"; 119 dmas = <&pdma 4>, <&pdma 5>; 120 pinctrl-names = "default"; 121 pinctrl-0 = <&uart1_xfer>; 122 status = "disabled"; 123 }; 124 125 uart0: serial@10230000 { 126 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart"; 127 reg = <0x10230000 0x100>; 128 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 129 reg-shift = <2>; 130 reg-io-width = <4>; 131 clock-frequency = <24000000>; 132 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 133 clock-names = "baudclk", "apb_pclk"; 134 dmas = <&pdma 2>, <&pdma 3>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 137 status = "disabled"; 138 }; 139 140 i2c1: i2c@10240000 { 141 compatible = "rockchip,rv1108-i2c"; 142 reg = <0x10240000 0x1000>; 143 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 147 clock-names = "i2c", "pclk"; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&i2c1_xfer>; 150 rockchip,grf = <&grf>; 151 status = "disabled"; 152 }; 153 154 i2c2: i2c@10250000 { 155 compatible = "rockchip,rv1108-i2c"; 156 reg = <0x10250000 0x1000>; 157 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 158 #address-cells = <1>; 159 #size-cells = <0>; 160 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 161 clock-names = "i2c", "pclk"; 162 pinctrl-names = "default"; 163 pinctrl-0 = <&i2c2m1_xfer>; 164 rockchip,grf = <&grf>; 165 status = "disabled"; 166 }; 167 168 i2c3: i2c@10260000 { 169 compatible = "rockchip,rv1108-i2c"; 170 reg = <0x10260000 0x1000>; 171 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 175 clock-names = "i2c", "pclk"; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&i2c3_xfer>; 178 rockchip,grf = <&grf>; 179 status = "disabled"; 180 }; 181 182 spi: spi@10270000 { 183 compatible = "rockchip,rv1108-spi"; 184 reg = <0x10270000 0x1000>; 185 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; 187 clock-names = "spiclk", "apb_pclk"; 188 dmas = <&pdma 8>, <&pdma 9>; 189 dma-names = "tx", "rx"; 190 #address-cells = <1>; 191 #size-cells = <0>; 192 status = "disabled"; 193 }; 194 195 pwm4: pwm@10280000 { 196 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 197 reg = <0x10280000 0x10>; 198 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 199 clock-names = "pwm", "pclk"; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pwm4_pin>; 202 #pwm-cells = <3>; 203 status = "disabled"; 204 }; 205 206 pwm5: pwm@10280010 { 207 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 208 reg = <0x10280010 0x10>; 209 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 210 clock-names = "pwm", "pclk"; 211 pinctrl-names = "default"; 212 pinctrl-0 = <&pwm5_pin>; 213 #pwm-cells = <3>; 214 status = "disabled"; 215 }; 216 217 pwm6: pwm@10280020 { 218 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 219 reg = <0x10280020 0x10>; 220 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 221 clock-names = "pwm", "pclk"; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&pwm6_pin>; 224 #pwm-cells = <3>; 225 status = "disabled"; 226 }; 227 228 pwm7: pwm@10280030 { 229 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 230 reg = <0x10280030 0x10>; 231 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 232 clock-names = "pwm", "pclk"; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pwm7_pin>; 235 #pwm-cells = <3>; 236 status = "disabled"; 237 }; 238 239 pdma: dma-controller@102a0000 { 240 compatible = "arm,pl330", "arm,primecell"; 241 reg = <0x102a0000 0x4000>; 242 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 243 #dma-cells = <1>; 244 arm,pl330-broken-no-flushp; 245 arm,pl330-periph-burst; 246 clocks = <&cru ACLK_DMAC>; 247 clock-names = "apb_pclk"; 248 }; 249 250 grf: syscon@10300000 { 251 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd"; 252 reg = <0x10300000 0x1000>; 253 #address-cells = <1>; 254 #size-cells = <1>; 255 256 io_domains: io-domains { 257 compatible = "rockchip,rv1108-io-voltage-domain"; 258 status = "disabled"; 259 }; 260 261 u2phy: usb2phy@100 { 262 compatible = "rockchip,rv1108-usb2phy"; 263 reg = <0x100 0x0c>; 264 clocks = <&cru SCLK_USBPHY>; 265 clock-names = "phyclk"; 266 #clock-cells = <0>; 267 clock-output-names = "usbphy"; 268 rockchip,usbgrf = <&usbgrf>; 269 status = "disabled"; 270 271 u2phy_otg: otg-port { 272 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 273 interrupt-names = "otg-mux"; 274 #phy-cells = <0>; 275 status = "disabled"; 276 }; 277 278 u2phy_host: host-port { 279 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 280 interrupt-names = "linestate"; 281 #phy-cells = <0>; 282 status = "disabled"; 283 }; 284 }; 285 }; 286 287 timer: timer@10350000 { 288 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer"; 289 reg = <0x10350000 0x20>; 290 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&cru PCLK_TIMER>, <&xin24m>; 292 clock-names = "pclk", "timer"; 293 }; 294 295 watchdog: watchdog@10360000 { 296 compatible = "rockchip,rv1108-wdt", "snps,dw-wdt"; 297 reg = <0x10360000 0x100>; 298 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&cru PCLK_WDT>; 300 status = "disabled"; 301 }; 302 303 thermal-zones { 304 soc_thermal: soc-thermal { 305 polling-delay-passive = <20>; 306 polling-delay = <1000>; 307 sustainable-power = <50>; 308 thermal-sensors = <&tsadc 0>; 309 310 trips { 311 threshold: trip-point0 { 312 temperature = <70000>; 313 hysteresis = <2000>; 314 type = "passive"; 315 }; 316 target: trip-point1 { 317 temperature = <85000>; 318 hysteresis = <2000>; 319 type = "passive"; 320 }; 321 soc_crit: soc-crit { 322 temperature = <95000>; 323 hysteresis = <2000>; 324 type = "critical"; 325 }; 326 }; 327 328 cooling-maps { 329 map0 { 330 trip = <&target>; 331 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 332 contribution = <4096>; 333 }; 334 }; 335 }; 336 }; 337 338 tsadc: tsadc@10370000 { 339 compatible = "rockchip,rv1108-tsadc"; 340 reg = <0x10370000 0x100>; 341 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 342 assigned-clocks = <&cru SCLK_TSADC>; 343 assigned-clock-rates = <750000>; 344 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 345 clock-names = "tsadc", "apb_pclk"; 346 pinctrl-names = "init", "default", "sleep"; 347 pinctrl-0 = <&otp_pin>; 348 pinctrl-1 = <&otp_out>; 349 pinctrl-2 = <&otp_pin>; 350 resets = <&cru SRST_TSADC>; 351 reset-names = "tsadc-apb"; 352 rockchip,hw-tshut-temp = <120000>; 353 #thermal-sensor-cells = <1>; 354 status = "disabled"; 355 }; 356 357 adc: adc@1038c000 { 358 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; 359 reg = <0x1038c000 0x100>; 360 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 361 #io-channel-cells = <1>; 362 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 363 clock-names = "saradc", "apb_pclk"; 364 status = "disabled"; 365 }; 366 367 i2c0: i2c@20000000 { 368 compatible = "rockchip,rv1108-i2c"; 369 reg = <0x20000000 0x1000>; 370 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>; 374 clock-names = "i2c", "pclk"; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&i2c0_xfer>; 377 rockchip,grf = <&grf>; 378 status = "disabled"; 379 }; 380 381 pwm0: pwm@20040000 { 382 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 383 reg = <0x20040000 0x10>; 384 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; 385 clock-names = "pwm", "pclk"; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pwm0_pin>; 388 #pwm-cells = <3>; 389 status = "disabled"; 390 }; 391 392 pwm1: pwm@20040010 { 393 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 394 reg = <0x20040010 0x10>; 395 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; 396 clock-names = "pwm", "pclk"; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&pwm1_pin>; 399 #pwm-cells = <3>; 400 status = "disabled"; 401 }; 402 403 pwm2: pwm@20040020 { 404 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 405 reg = <0x20040020 0x10>; 406 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; 407 clock-names = "pwm", "pclk"; 408 pinctrl-names = "default"; 409 pinctrl-0 = <&pwm2_pin>; 410 #pwm-cells = <3>; 411 status = "disabled"; 412 }; 413 414 pwm3: pwm@20040030 { 415 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm"; 416 reg = <0x20040030 0x10>; 417 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>; 418 clock-names = "pwm", "pclk"; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&pwm3_pin>; 421 #pwm-cells = <3>; 422 status = "disabled"; 423 }; 424 425 pmugrf: syscon@20060000 { 426 compatible = "rockchip,rv1108-pmugrf", "syscon", "simple-mfd"; 427 reg = <0x20060000 0x1000>; 428 429 pmu_io_domains: io-domains { 430 compatible = "rockchip,rv1108-pmu-io-voltage-domain"; 431 status = "disabled"; 432 }; 433 }; 434 435 usbgrf: syscon@202a0000 { 436 compatible = "rockchip,rv1108-usbgrf", "syscon"; 437 reg = <0x202a0000 0x1000>; 438 }; 439 440 cru: clock-controller@20200000 { 441 compatible = "rockchip,rv1108-cru"; 442 reg = <0x20200000 0x1000>; 443 clocks = <&xin24m>; 444 clock-names = "xin24m"; 445 rockchip,grf = <&grf>; 446 #clock-cells = <1>; 447 #reset-cells = <1>; 448 }; 449 450 nfc: nand-controller@30100000 { 451 compatible = "rockchip,rv1108-nfc"; 452 reg = <0x30100000 0x1000>; 453 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 455 clock-names = "ahb", "nfc"; 456 assigned-clocks = <&cru SCLK_NANDC>; 457 assigned-clock-rates = <150000000>; 458 status = "disabled"; 459 }; 460 461 emmc: mmc@30110000 { 462 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 463 reg = <0x30110000 0x4000>; 464 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 466 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 467 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 468 fifo-depth = <0x100>; 469 max-frequency = <150000000>; 470 status = "disabled"; 471 }; 472 473 sdio: mmc@30120000 { 474 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 475 reg = <0x30120000 0x4000>; 476 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 478 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 479 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 480 fifo-depth = <0x100>; 481 max-frequency = <150000000>; 482 status = "disabled"; 483 }; 484 485 sdmmc: mmc@30130000 { 486 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; 487 reg = <0x30130000 0x4000>; 488 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 490 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 491 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 492 fifo-depth = <0x100>; 493 max-frequency = <100000000>; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; 496 status = "disabled"; 497 }; 498 499 usb_host_ehci: usb@30140000 { 500 compatible = "generic-ehci"; 501 reg = <0x30140000 0x20000>; 502 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&cru HCLK_HOST0>, <&u2phy>; 504 phys = <&u2phy_host>; 505 phy-names = "usb"; 506 status = "disabled"; 507 }; 508 509 usb_host_ohci: usb@30160000 { 510 compatible = "generic-ohci"; 511 reg = <0x30160000 0x20000>; 512 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&cru HCLK_HOST0>, <&u2phy>; 514 phys = <&u2phy_host>; 515 phy-names = "usb"; 516 status = "disabled"; 517 }; 518 519 usb_otg: usb@30180000 { 520 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb", 521 "snps,dwc2"; 522 reg = <0x30180000 0x40000>; 523 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&cru HCLK_OTG>; 525 clock-names = "otg"; 526 dr_mode = "otg"; 527 g-np-tx-fifo-size = <16>; 528 g-rx-fifo-size = <280>; 529 g-tx-fifo-size = <256 128 128 64 32 16>; 530 phys = <&u2phy_otg>; 531 phy-names = "usb2-phy"; 532 status = "disabled"; 533 }; 534 535 sfc: spi@301c0000 { 536 compatible = "rockchip,sfc"; 537 reg = <0x301c0000 0x4000>; 538 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 540 clock-names = "clk_sfc", "hclk_sfc"; 541 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; 542 pinctrl-names = "default"; 543 status = "disabled"; 544 }; 545 546 gmac: ethernet@30200000 { 547 compatible = "rockchip,rv1108-gmac"; 548 reg = <0x30200000 0x10000>; 549 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 551 interrupt-names = "macirq", "eth_wake_irq"; 552 clocks = <&cru SCLK_MAC>, 553 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>, 554 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, 555 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 556 clock-names = "stmmaceth", 557 "mac_clk_rx", "mac_clk_tx", 558 "clk_mac_ref", "clk_mac_refout", 559 "aclk_mac", "pclk_mac"; 560 /* rv1108 only supports an rmii interface */ 561 phy-mode = "rmii"; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&rmii_pins>; 564 rockchip,grf = <&grf>; 565 status = "disabled"; 566 }; 567 568 gic: interrupt-controller@32010000 { 569 compatible = "arm,gic-400"; 570 interrupt-controller; 571 #interrupt-cells = <3>; 572 #address-cells = <0>; 573 574 reg = <0x32011000 0x1000>, 575 <0x32012000 0x2000>, 576 <0x32014000 0x2000>, 577 <0x32016000 0x2000>; 578 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 579 }; 580 581 pinctrl: pinctrl { 582 compatible = "rockchip,rv1108-pinctrl"; 583 rockchip,grf = <&grf>; 584 rockchip,pmu = <&pmugrf>; 585 #address-cells = <1>; 586 #size-cells = <1>; 587 ranges; 588 589 gpio0: gpio@20030000 { 590 compatible = "rockchip,gpio-bank"; 591 reg = <0x20030000 0x100>; 592 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 593 clocks = <&cru PCLK_GPIO0_PMU>; 594 595 gpio-controller; 596 #gpio-cells = <2>; 597 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 }; 601 602 gpio1: gpio@10310000 { 603 compatible = "rockchip,gpio-bank"; 604 reg = <0x10310000 0x100>; 605 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&cru PCLK_GPIO1>; 607 608 gpio-controller; 609 #gpio-cells = <2>; 610 611 interrupt-controller; 612 #interrupt-cells = <2>; 613 }; 614 615 gpio2: gpio@10320000 { 616 compatible = "rockchip,gpio-bank"; 617 reg = <0x10320000 0x100>; 618 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&cru PCLK_GPIO2>; 620 621 gpio-controller; 622 #gpio-cells = <2>; 623 624 interrupt-controller; 625 #interrupt-cells = <2>; 626 }; 627 628 gpio3: gpio@10330000 { 629 compatible = "rockchip,gpio-bank"; 630 reg = <0x10330000 0x100>; 631 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&cru PCLK_GPIO3>; 633 634 gpio-controller; 635 #gpio-cells = <2>; 636 637 interrupt-controller; 638 #interrupt-cells = <2>; 639 }; 640 641 pcfg_pull_up: pcfg-pull-up { 642 bias-pull-up; 643 }; 644 645 pcfg_pull_down: pcfg-pull-down { 646 bias-pull-down; 647 }; 648 649 pcfg_pull_none: pcfg-pull-none { 650 bias-disable; 651 }; 652 653 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { 654 drive-strength = <8>; 655 }; 656 657 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { 658 drive-strength = <12>; 659 }; 660 661 pcfg_pull_none_smt: pcfg-pull-none-smt { 662 bias-disable; 663 input-schmitt-enable; 664 }; 665 666 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { 667 bias-pull-up; 668 drive-strength = <8>; 669 }; 670 671 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma { 672 drive-strength = <4>; 673 }; 674 675 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma { 676 bias-pull-up; 677 drive-strength = <4>; 678 }; 679 680 pcfg_output_high: pcfg-output-high { 681 output-high; 682 }; 683 684 pcfg_output_low: pcfg-output-low { 685 output-low; 686 }; 687 688 pcfg_input_high: pcfg-input-high { 689 bias-pull-up; 690 input-enable; 691 }; 692 693 emmc { 694 emmc_bus8: emmc-bus8 { 695 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>, 696 <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>, 697 <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>, 698 <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>, 699 <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>, 700 <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>, 701 <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>, 702 <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>; 703 }; 704 705 emmc_clk: emmc-clk { 706 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>; 707 }; 708 709 emmc_cmd: emmc-cmd { 710 rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>; 711 }; 712 }; 713 714 sfc { 715 sfc_bus4: sfc-bus4 { 716 rockchip,pins = 717 <2 RK_PA0 3 &pcfg_pull_none>, 718 <2 RK_PA1 3 &pcfg_pull_none>, 719 <2 RK_PA2 3 &pcfg_pull_none>, 720 <2 RK_PA3 3 &pcfg_pull_none>; 721 }; 722 723 sfc_bus2: sfc-bus2 { 724 rockchip,pins = 725 <2 RK_PA0 3 &pcfg_pull_none>, 726 <2 RK_PA1 3 &pcfg_pull_none>; 727 }; 728 729 sfc_cs0: sfc-cs0 { 730 rockchip,pins = 731 <2 RK_PB4 3 &pcfg_pull_none>; 732 }; 733 734 sfc_clk: sfc-clk { 735 rockchip,pins = 736 <2 RK_PB7 2 &pcfg_pull_none>; 737 }; 738 }; 739 740 gmac { 741 rmii_pins: rmii-pins { 742 rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>, 743 <1 RK_PC3 2 &pcfg_pull_none>, 744 <1 RK_PC4 2 &pcfg_pull_none>, 745 <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>, 746 <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>, 747 <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>, 748 <1 RK_PB5 3 &pcfg_pull_none>, 749 <1 RK_PB6 3 &pcfg_pull_none>, 750 <1 RK_PB7 3 &pcfg_pull_none>, 751 <1 RK_PC2 3 &pcfg_pull_none>; 752 }; 753 }; 754 755 i2c0 { 756 i2c0_xfer: i2c0-xfer { 757 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>, 758 <0 RK_PB2 1 &pcfg_pull_none_smt>; 759 }; 760 }; 761 762 i2c1 { 763 i2c1_xfer: i2c1-xfer { 764 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>, 765 <2 RK_PD4 1 &pcfg_pull_up>; 766 }; 767 }; 768 769 i2c2m1 { 770 i2c2m1_xfer: i2c2m1-xfer { 771 rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>, 772 <0 RK_PC6 3 &pcfg_pull_none>; 773 }; 774 775 i2c2m1_pins: i2c2m1-pins { 776 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, 777 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 778 }; 779 }; 780 781 i2c2m05v { 782 i2c2m05v_xfer: i2c2m05v-xfer { 783 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>, 784 <1 RK_PD4 2 &pcfg_pull_none>; 785 }; 786 787 i2c2m05v_pins: i2c2m05v-pins { 788 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, 789 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 790 }; 791 }; 792 793 i2c3 { 794 i2c3_xfer: i2c3-xfer { 795 rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>, 796 <0 RK_PC4 2 &pcfg_pull_none>; 797 }; 798 }; 799 800 pwm0 { 801 pwm0_pin: pwm0-pin { 802 rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>; 803 }; 804 }; 805 806 pwm1 { 807 pwm1_pin: pwm1-pin { 808 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; 809 }; 810 }; 811 812 pwm2 { 813 pwm2_pin: pwm2-pin { 814 rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>; 815 }; 816 }; 817 818 pwm3 { 819 pwm3_pin: pwm3-pin { 820 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>; 821 }; 822 }; 823 824 pwm4 { 825 pwm4_pin: pwm4-pin { 826 rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>; 827 }; 828 }; 829 830 pwm5 { 831 pwm5_pin: pwm5-pin { 832 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>; 833 }; 834 }; 835 836 pwm6 { 837 pwm6_pin: pwm6-pin { 838 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; 839 }; 840 }; 841 842 pwm7 { 843 pwm7_pin: pwm7-pin { 844 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>; 845 }; 846 }; 847 848 sdmmc { 849 sdmmc_clk: sdmmc-clk { 850 rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>; 851 }; 852 853 sdmmc_cmd: sdmmc-cmd { 854 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>; 855 }; 856 857 sdmmc_cd: sdmmc-cd { 858 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>; 859 }; 860 861 sdmmc_bus1: sdmmc-bus1 { 862 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>; 863 }; 864 865 sdmmc_bus4: sdmmc-bus4 { 866 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>, 867 <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>, 868 <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>, 869 <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>; 870 }; 871 }; 872 873 spim0 { 874 spim0_clk: spim0-clk { 875 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>; 876 }; 877 878 spim0_cs0: spim0-cs0 { 879 rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>; 880 }; 881 882 spim0_tx: spim0-tx { 883 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; 884 }; 885 886 spim0_rx: spim0-rx { 887 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; 888 }; 889 }; 890 891 spim1 { 892 spim1_clk: spim1-clk { 893 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; 894 }; 895 896 spim1_cs0: spim1-cs0 { 897 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>; 898 }; 899 900 spim1_rx: spim1-rx { 901 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>; 902 }; 903 904 spim1_tx: spim1-tx { 905 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>; 906 }; 907 }; 908 909 tsadc { 910 otp_out: otp-out { 911 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; 912 }; 913 914 otp_pin: otp-pin { 915 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; 916 }; 917 }; 918 919 uart0 { 920 uart0_xfer: uart0-xfer { 921 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>, 922 <3 RK_PA5 1 &pcfg_pull_none>; 923 }; 924 925 uart0_cts: uart0-cts { 926 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; 927 }; 928 929 uart0_rts: uart0-rts { 930 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; 931 }; 932 933 uart0_rts_pin: uart0-rts-pin { 934 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 935 }; 936 }; 937 938 uart1 { 939 uart1_xfer: uart1-xfer { 940 rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>, 941 <1 RK_PD2 1 &pcfg_pull_none>; 942 }; 943 944 uart1_cts: uart1-cts { 945 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; 946 }; 947 948 uart1_rts: uart1-rts { 949 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; 950 }; 951 }; 952 953 uart2m0 { 954 uart2m0_xfer: uart2m0-xfer { 955 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>, 956 <2 RK_PD1 1 &pcfg_pull_none>; 957 }; 958 }; 959 960 uart2m1 { 961 uart2m1_xfer: uart2m1-xfer { 962 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>, 963 <3 RK_PC2 2 &pcfg_pull_none>; 964 }; 965 }; 966 967 uart2_5v { 968 uart2_5v_cts: uart2_5v-cts { 969 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; 970 }; 971 972 uart2_5v_rts: uart2_5v-rts { 973 rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>; 974 }; 975 }; 976 }; 977}; 978