1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rtq9124.c -- RTQ9124 ALSA SoC Codec driver
4 //
5 // Author: ChiYuan Huang <cy_huang@richtek.com>
6
7 #include <linux/bitfield.h>
8 #include <linux/bits.h>
9 #include <linux/byteorder/generic.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/i2c.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/property.h>
19 #include <linux/regmap.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/soc-dai.h>
24 #include <sound/soc-dapm.h>
25 #include <sound/tlv.h>
26
27 #define RTQ9124_REG_SDI_SEL 0x00
28 #define RTQ9124_REG_SDO_SEL 0x01
29 #define RTQ9124_REG_I2S_OPT 0x02
30 #define RTQ9124_REG_AMP_OPT 0x03
31 #define RTQ9124_REG_STATE_CTRL 0x04
32 #define RTQ9124_REG_PWM_PHASE 0x05
33 #define RTQ9124_REG_SIL_CTRL 0x06
34 #define RTQ9124_REG_PWM_SS_OPT 0x07
35 #define RTQ9124_REG_ERR_INT_0 0x10
36 #define RTQ9124_REG_ERR_MASK6 0x26
37 #define RTQ9124_REG_TDM_TX_CH0 0x32
38 #define RTQ9124_REG_TDM_RX_CH0 0x34
39 #define RTQ9124_REG_VOL_OPT 0x38
40 #define RTQ9124_REG_DCR_TH 0x4B
41 #define RTQ9124_REG_ERR_TH 0x4C
42 #define RTQ9124_REG_PROT_EN 0x5B
43 #define RTQ9124_REG_PRJ_CODE 0xF9
44
45 #define RTQ9124_MASK_CS_DATA_INV BIT(9)
46 #define RTQ9124_MASK_VDDIO_SDO_SEL BIT(8)
47 #define RTQ9124_MASK_AUD_BITS GENMASK(5, 4)
48 #define RTQ9124_MASK_AUD_FMT GENMASK(3, 0)
49 #define RTQ9124_MASK_CH_STATE GENMASK(1, 0)
50 #define RTQ9124_MASK_SF_RESET BIT(15)
51
52 #define RTQ9124_FIXED_VENID 0x9124
53
54 struct rtq9124_priv {
55 struct gpio_desc *enable;
56 unsigned int dai_fmt;
57 int tdm_slots;
58 int tdm_slot_width;
59 };
60
rtq9124_enable_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)61 static int rtq9124_enable_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
62 int event)
63 {
64 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
65 unsigned int i, chan_state;
66
67 switch (event) {
68 case SND_SOC_DAPM_POST_PMU:
69 /* Change state to normal */
70 chan_state = 0;
71 break;
72 case SND_SOC_DAPM_POST_PMD:
73 /* Change state to HiZ */
74 chan_state = 1;
75 break;
76 default:
77 return -EINVAL;
78 }
79
80 /* Before amp turn on, clear old events first */
81 for (i = 0; !chan_state && i < 8; i++)
82 snd_soc_component_write(comp, RTQ9124_REG_ERR_INT_0 + i, 0xffff);
83
84 snd_soc_component_write_field(comp, RTQ9124_REG_STATE_CTRL, RTQ9124_MASK_CH_STATE,
85 chan_state);
86
87 return 0;
88 }
89
90 static const struct snd_soc_dapm_widget rtq9124_dapm_widgets[] = {
91 SND_SOC_DAPM_OUTPUT("SPK"),
92 SND_SOC_DAPM_OUT_DRV_E("Amp Drv", SND_SOC_NOPM, 0, 0, NULL, 0, rtq9124_enable_event,
93 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
94 };
95
96 static const struct snd_soc_dapm_route rtq9124_dapm_routes[] = {
97 { "Amp Drv", NULL, "HiFi Playback" },
98 { "SPK", NULL, "Amp Drv" },
99 };
100
101 static const DECLARE_TLV_DB_SCALE(dig_tlv, -10375, 25, 0);
102 static const DECLARE_TLV_DB_RANGE(ana_tlv,
103 0, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
104 4, 6, TLV_DB_SCALE_ITEM(1400, 200, 0));
105 static const char * const i2sch_text[] = { "(L+R)/2", "LCH", "RCH", "(L+R)/2" };
106 static const struct soc_enum rtq9124_i2sch_select_enum =
107 SOC_ENUM_SINGLE(RTQ9124_REG_SDI_SEL, 0, ARRAY_SIZE(i2sch_text), i2sch_text);
108 static const char * const sdo_vsel_text[] = { "1.8V", "3.3V" };
109 static const struct soc_enum rtq9124_sdo_vselect_enum =
110 SOC_ENUM_SINGLE(RTQ9124_REG_SDO_SEL, 8, ARRAY_SIZE(sdo_vsel_text), sdo_vsel_text);
111 static const char * const pwmfreq_text[] = { "8*fs", "10*fs", "40*fs", "44*fs", "48*fs" };
112 static const struct soc_enum rtq9124_pwm_freq_enum =
113 SOC_ENUM_SINGLE(RTQ9124_REG_AMP_OPT, 4, ARRAY_SIZE(pwmfreq_text), pwmfreq_text);
114 static const char * const out_angle_text[] = { "0", "45", "90", "135", "180", "225", "270", "315" };
115 static const struct soc_enum rtq9124_out_angle_enum =
116 SOC_ENUM_SINGLE(RTQ9124_REG_PWM_PHASE, 0, ARRAY_SIZE(out_angle_text), out_angle_text);
117 static const char * const sdo_select_text[] = {
118 "None", "I2S DataI", "Interface", "DSP", "DF", "ISense", "ACLoad Cos", "ACLoad Sin",
119 "DCR",
120 };
121 static const struct soc_enum rtq9124_sdo_select_enum =
122 SOC_ENUM_DOUBLE(RTQ9124_REG_SDO_SEL, 4, 0, ARRAY_SIZE(sdo_select_text), sdo_select_text);
123 static const char * const ulqm_dcvt_text[] = { "Disable", "DC", "VT", "DC+VT" };
124 static const struct soc_enum rtq9124_ulqm_dcvt_select_enum =
125 SOC_ENUM_SINGLE(RTQ9124_REG_STATE_CTRL, 10, ARRAY_SIZE(ulqm_dcvt_text), ulqm_dcvt_text);
126
127 static const struct snd_kcontrol_new rtq9124_controls[] = {
128 SOC_SINGLE_TLV("Master Volume", RTQ9124_REG_VOL_OPT, 2, 511, 1, dig_tlv),
129 SOC_SINGLE_TLV("Speaker Volume", RTQ9124_REG_AMP_OPT, 0, 6, 0, ana_tlv),
130 SOC_ENUM("I2S CH Select", rtq9124_i2sch_select_enum),
131 SOC_ENUM("SDO VDDIO Select", rtq9124_sdo_vselect_enum),
132 SOC_ENUM("PWM Frequency Select", rtq9124_pwm_freq_enum),
133 SOC_ENUM("PWM Output Phase Select", rtq9124_out_angle_enum),
134 SOC_ENUM("SDO Select", rtq9124_sdo_select_enum),
135 SOC_ENUM("ULQM DCVT Select", rtq9124_ulqm_dcvt_select_enum),
136 SOC_SINGLE("Silence Detect Enable Switch", RTQ9124_REG_SIL_CTRL, 7, 1, 0),
137 SOC_SINGLE("Spread Spectrum Enable Switch", RTQ9124_REG_PWM_SS_OPT, 7, 1, 0),
138 };
139
rtq9124_comp_probe(struct snd_soc_component * comp)140 static int rtq9124_comp_probe(struct snd_soc_component *comp)
141 {
142 /* CS Data INV */
143 snd_soc_component_write_field(comp, RTQ9124_REG_SDO_SEL, RTQ9124_MASK_CS_DATA_INV, 1);
144
145 /* RTLD */
146 snd_soc_component_write(comp, RTQ9124_REG_DCR_TH, 0x5e30);
147 snd_soc_component_write(comp, RTQ9124_REG_ERR_TH, 0x3ff);
148 snd_soc_component_write(comp, RTQ9124_REG_PROT_EN, 0x3fc);
149 snd_soc_component_write(comp, RTQ9124_REG_ERR_MASK6, 0);
150
151 return 0;
152 }
153
154 static const struct snd_soc_component_driver rtq9124_comp_driver = {
155 .probe = rtq9124_comp_probe,
156 .controls = rtq9124_controls,
157 .num_controls = ARRAY_SIZE(rtq9124_controls),
158 .dapm_widgets = rtq9124_dapm_widgets,
159 .num_dapm_widgets = ARRAY_SIZE(rtq9124_dapm_widgets),
160 .dapm_routes = rtq9124_dapm_routes,
161 .num_dapm_routes = ARRAY_SIZE(rtq9124_dapm_routes),
162 .use_pmdown_time = 1,
163 .endianness = 1,
164 };
165
rtq9124_dai_set_format(struct snd_soc_dai * dai,unsigned int fmt)166 static int rtq9124_dai_set_format(struct snd_soc_dai *dai, unsigned int fmt)
167 {
168 struct rtq9124_priv *rtq9124 = snd_soc_dai_get_drvdata(dai);
169
170 rtq9124->dai_fmt = fmt;
171 return 0;
172 }
173
rtq9124_dai_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)174 static int rtq9124_dai_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
175 unsigned int rx_mask, int slots, int slot_width)
176 {
177 struct rtq9124_priv *rtq9124 = snd_soc_dai_get_drvdata(dai);
178 struct snd_soc_component *comp = dai->component;
179 struct device *dev = dai->dev;
180 unsigned int byte_loc, i;
181
182 dev_dbg(dev, "(slots, slot_width) = (%d, %d), (txmask, rxmask) = 0x%x, 0x%x\n", slots,
183 slot_width, tx_mask, rx_mask);
184
185 if (slots <= 0 || slots > 16 || slot_width <= 0 || slots % 2 || slot_width % 8) {
186 dev_err(dev, "Invalid slot parameter (%d, %d)\n", slots, slot_width);
187 return -EINVAL;
188 }
189
190 if (tx_mask && (hweight_long(tx_mask) > 2 || fls(tx_mask) > slots)) {
191 dev_err(dev, "Invalid tx_mask 0x%08x, slots = %d\n", tx_mask, slots);
192 return -EINVAL;
193 }
194
195 if (!rx_mask || hweight_long(rx_mask) > 1 || fls(rx_mask) > slots) {
196 dev_err(dev, "Invalid rx_mask 0x%08x, slots = %d\n", rx_mask, slots);
197 return -EINVAL;
198 }
199
200 /* Configure tx channel data location */
201 for (i = 0; tx_mask; i++, tx_mask ^= BIT(ffs(tx_mask) - 1)) {
202 byte_loc = (ffs(tx_mask) - 1) * slot_width / 8;
203 snd_soc_component_write(comp, RTQ9124_REG_TDM_TX_CH0 + i, byte_loc);
204 }
205
206 /* Configure rx channel data location */
207 byte_loc = (ffs(rx_mask) - 1) * slot_width / 8;
208 snd_soc_component_write(comp, RTQ9124_REG_TDM_RX_CH0, byte_loc);
209
210 rtq9124->tdm_slots = slots;
211 rtq9124->tdm_slot_width = slot_width;
212
213 return 0;
214 }
215
rtq9124_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * param,struct snd_soc_dai * dai)216 static int rtq9124_dai_hw_params(struct snd_pcm_substream *substream,
217 struct snd_pcm_hw_params *param, struct snd_soc_dai *dai)
218 {
219 struct rtq9124_priv *rtq9124 = snd_soc_dai_get_drvdata(dai);
220 struct snd_soc_component *comp = dai->component;
221 unsigned int fmtval, width, slot_width, bitrate;
222 struct device *dev = dai->dev;
223 unsigned int audfmt, audbit;
224
225 fmtval = FIELD_GET(SND_SOC_DAIFMT_FORMAT_MASK, rtq9124->dai_fmt);
226 if (rtq9124->tdm_slots && fmtval != SND_SOC_DAIFMT_DSP_A &&
227 fmtval != SND_SOC_DAIFMT_DSP_B) {
228 dev_err(dev, "TDM only can support DSP_A or DSP_B format\n");
229 return -EINVAL;
230 }
231
232 switch (fmtval) {
233 case SND_SOC_DAIFMT_I2S:
234 audfmt = 0;
235 break;
236 case SND_SOC_DAIFMT_LEFT_J:
237 audfmt = 1;
238 break;
239 case SND_SOC_DAIFMT_RIGHT_J:
240 audfmt = 2;
241 break;
242 case SND_SOC_DAIFMT_DSP_B:
243 audfmt = rtq9124->tdm_slots ? 7 : 3;
244 break;
245 case SND_SOC_DAIFMT_DSP_A:
246 audfmt = rtq9124->tdm_slots ? 15 : 11;
247 break;
248 default:
249 dev_err(dev, "Unsupported format %d\n", fmtval);
250 return -EINVAL;
251 }
252
253 switch (width = params_width(param)) {
254 case 16:
255 audbit = 0;
256 break;
257 case 20:
258 audbit = 1;
259 break;
260 case 24:
261 case 32:
262 audbit = 3;
263 break;
264 default:
265 dev_err(dev, "Unsupported width %d\n", width);
266 return -EINVAL;
267 }
268
269 if (rtq9124->tdm_slots) {
270 slot_width = params_physical_width(param);
271 if (slot_width > rtq9124->tdm_slot_width) {
272 dev_err(dev, "Slot width is larger than TDM slot width\n");
273 return -EINVAL;
274 }
275
276 bitrate = rtq9124->tdm_slots * rtq9124->tdm_slot_width * params_rate(param);
277 if (bitrate > 24576000) {
278 dev_err(dev, "Bitrate exceed the internal PLL 24.576MHz (%d)\n", bitrate);
279 return -EINVAL;
280 }
281 }
282
283 snd_soc_component_write_field(comp, RTQ9124_REG_I2S_OPT, RTQ9124_MASK_AUD_FMT, audfmt);
284 snd_soc_component_write_field(comp, RTQ9124_REG_I2S_OPT, RTQ9124_MASK_AUD_BITS, audbit);
285
286 return 0;
287 }
288
289 static const struct snd_soc_dai_ops rtq9124_dai_ops = {
290 .set_fmt = rtq9124_dai_set_format,
291 .set_tdm_slot = rtq9124_dai_set_tdm_slot,
292 .hw_params = rtq9124_dai_hw_params,
293 };
294
295 static struct snd_soc_dai_driver rtq9124_dai_driver = {
296 .name = "HiFi",
297 .playback = {
298 .stream_name = "HiFi Playback",
299 .formats = SNDRV_PCM_FMTBIT_S16 | SNDRV_PCM_FMTBIT_S24 |
300 SNDRV_PCM_FMTBIT_S32,
301 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_24000 |
302 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
303 SNDRV_PCM_RATE_192000,
304 .rate_min = 8000,
305 .rate_max = 192000,
306 .channels_min = 1,
307 .channels_max = 2,
308 },
309 .ops = &rtq9124_dai_ops,
310 .symmetric_rate = 1,
311 .symmetric_sample_bits = 1,
312 };
313
rtq9124_readable_reg(struct device * dev,unsigned int reg)314 static bool rtq9124_readable_reg(struct device *dev, unsigned int reg)
315 {
316 switch (reg) {
317 case 0x00 ... 0x17:
318 case 0x20 ... 0x27:
319 case 0x30 ... 0x3D:
320 case 0x40 ... 0x68:
321 case 0x80 ... 0xBC:
322 case 0xC0 ... 0xDE:
323 case 0xE0 ... 0xE7:
324 case 0xF0 ... 0xFD:
325 return true;
326 default:
327 return false;
328 }
329 }
330
rtq9124_writeable_reg(struct device * dev,unsigned int reg)331 static bool rtq9124_writeable_reg(struct device *dev, unsigned int reg)
332 {
333 switch (reg) {
334 case 0x00 ... 0x09:
335 case 0x0C ... 0x0E:
336 case 0x10 ... 0x17:
337 case 0x20 ... 0x27:
338 case 0x30:
339 case 0x32 ... 0x3D:
340 case 0x40 ... 0x4E:
341 case 0x50 ... 0x68:
342 case 0x80 ... 0xBC:
343 case 0xC0 ... 0xDE:
344 case 0xE0 ... 0xE7:
345 case 0xF0 ... 0xFD:
346 return true;
347 default:
348 return false;
349 }
350 }
351
rtq9124_volatile_reg(struct device * dev,unsigned int reg)352 static bool rtq9124_volatile_reg(struct device *dev, unsigned int reg)
353 {
354 switch (reg) {
355 case 0x0A ... 0x0B:
356 case 0x0F ... 0x17:
357 case 0x31:
358 case 0x4F:
359 case 0x51:
360 case 0x53 ... 0x57:
361 case 0x80 ... 0xBC:
362 case 0xC0 ... 0xDE:
363 case 0xE0 ... 0xE7:
364 case 0xF0 ... 0xFD:
365 return true;
366 default:
367 return false;
368 }
369 }
370
rtq9124_get_reg_len(unsigned int reg)371 static inline u8 rtq9124_get_reg_len(unsigned int reg)
372 {
373 return (reg >= 0x40 && reg <= 0x47) ? 4 : 2;
374 }
375
rtq9124_regmap_read(void * context,const void * reg_buf,size_t reg_size,void * val_buf,size_t val_size)376 static int rtq9124_regmap_read(void *context, const void *reg_buf, size_t reg_size, void *val_buf,
377 size_t val_size)
378 {
379 struct i2c_client *i2c = context;
380 u8 reg = *(u8 *)reg_buf;
381 u8 size = rtq9124_get_reg_len(reg);
382 u32 *val = val_buf;
383 int ret;
384
385 ret = i2c_smbus_read_i2c_block_data(i2c, reg, size, val_buf);
386 if (ret < 0)
387 return ret;
388 else if (ret != size)
389 return -EIO;
390
391 *val = size == 4 ? be32_to_cpup(val_buf) : be16_to_cpup(val_buf);
392
393 return 0;
394 }
395
rtq9124_regmap_write(void * context,const void * data,size_t count)396 static int rtq9124_regmap_write(void *context, const void *data, size_t count)
397 {
398 struct i2c_client *i2c = context;
399 u8 reg = *(u8 *)data, *vbuf;
400 u8 size = rtq9124_get_reg_len(reg);
401 __be16 val16 = cpu_to_be16p(data + 1);
402 __be32 val32 = cpu_to_be32p(data + 1);
403
404 vbuf = size == 4 ? (u8 *)&val32 : (u8 *)&val16;
405 return i2c_smbus_write_i2c_block_data(i2c, reg, size, vbuf);
406 }
407
408 static const struct regmap_config rtq9124_regmap_config = {
409 .name = "rtq9124",
410 .reg_bits = 8,
411 .val_bits = 32,
412 .read = rtq9124_regmap_read,
413 .write = rtq9124_regmap_write,
414 .readable_reg = rtq9124_readable_reg,
415 .writeable_reg = rtq9124_writeable_reg,
416 .volatile_reg = rtq9124_volatile_reg,
417 .cache_type = REGCACHE_MAPLE,
418 .num_reg_defaults_raw = 0xFD + 1,
419 .use_single_read = 1,
420 .use_single_write = 1,
421 };
422
423 static const struct reg_sequence rtq9124_init_regs[] = {
424 { 0xfb, 0x0065 },
425 { 0x93, 0x2000 },
426 { 0xfb, 0x0000 },
427 };
428
rtq9124_probe(struct i2c_client * i2c)429 static int rtq9124_probe(struct i2c_client *i2c)
430 {
431 struct device *dev = &i2c->dev;
432 struct rtq9124_priv *rtq9124;
433 struct regmap *regmap;
434 int ret;
435
436 rtq9124 = devm_kzalloc(dev, sizeof(*rtq9124), GFP_KERNEL);
437 if (!rtq9124)
438 return -ENOMEM;
439
440 rtq9124->enable = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_HIGH);
441 if (IS_ERR(rtq9124->enable))
442 return PTR_ERR(rtq9124->enable);
443 else if (rtq9124->enable)
444 usleep_range(6000, 7000);
445 else
446 dev_dbg(dev, "No 'enable' GPIO specified, treat it as default on\n");
447
448 /* Check vendor id information */
449 ret = i2c_smbus_read_word_swapped(i2c, RTQ9124_REG_PRJ_CODE);
450 if (ret < 0)
451 return dev_err_probe(dev, ret, "Failed to read project code\n");
452 else if (ret != RTQ9124_FIXED_VENID)
453 return dev_err_probe(dev, -ENODEV, "Incorrect project-code 0x%04x\n", ret);
454
455 /* Trigger RG reset before regmap init */
456 ret = i2c_smbus_write_word_swapped(i2c, RTQ9124_REG_STATE_CTRL, RTQ9124_MASK_SF_RESET);
457 if (ret)
458 return dev_err_probe(dev, ret, "Failed to trigger RG reset\n");
459
460 /* Need to wait 10ms for the reset to complete */
461 usleep_range(10000, 11000);
462
463 regmap = devm_regmap_init(dev, NULL, i2c, &rtq9124_regmap_config);
464 if (IS_ERR(regmap))
465 return dev_err_probe(dev, PTR_ERR(regmap), "Failed to init regmap\n");
466
467 ret = regmap_register_patch(regmap, rtq9124_init_regs, ARRAY_SIZE(rtq9124_init_regs));
468 if (ret)
469 return dev_err_probe(dev, ret, "Failed to register regmap patch\n");
470
471 i2c_set_clientdata(i2c, rtq9124);
472
473 pm_runtime_set_autosuspend_delay(dev, 1000);
474 pm_runtime_use_autosuspend(dev);
475 pm_runtime_set_active(dev);
476 ret = devm_pm_runtime_enable(dev);
477 if (ret)
478 return dev_err_probe(dev, ret, "Failed to enable pm runtime\n");
479
480 return devm_snd_soc_register_component(dev, &rtq9124_comp_driver, &rtq9124_dai_driver, 1);
481 }
482
483 #ifdef CONFIG_PM
rtq9124_runtime_suspend(struct device * dev)484 static int rtq9124_runtime_suspend(struct device *dev)
485 {
486 struct rtq9124_priv *rtq9124 = dev_get_drvdata(dev);
487 struct regmap *regmap = dev_get_regmap(dev, NULL);
488
489 if (rtq9124->enable) {
490 regcache_cache_only(regmap, true);
491 regcache_mark_dirty(regmap);
492 gpiod_set_value(rtq9124->enable, 0);
493 }
494
495 return 0;
496 }
497
rtq9124_runtime_resume(struct device * dev)498 static int rtq9124_runtime_resume(struct device *dev)
499 {
500 struct rtq9124_priv *rtq9124 = dev_get_drvdata(dev);
501 struct regmap *regmap = dev_get_regmap(dev, NULL);
502 int ret;
503
504 if (rtq9124->enable) {
505 gpiod_set_value(rtq9124->enable, 1);
506 usleep_range(6000, 7000);
507
508 regcache_cache_only(regmap, false);
509 ret = regcache_sync(regmap);
510 if (ret)
511 return ret;
512 }
513
514 return 0;
515 }
516 #endif
517
518 static const struct dev_pm_ops rtq9124_dev_pm_ops = {
519 SET_RUNTIME_PM_OPS(rtq9124_runtime_suspend, rtq9124_runtime_resume, NULL)
520 };
521
522 #ifdef CONFIG_OF
523 static const struct of_device_id rtq9124_device_id[] = {
524 { .compatible = "richtek,rtq9124" },
525 {}
526 };
527 MODULE_DEVICE_TABLE(of, rtq9124_device_id);
528 #endif
529
530 static struct i2c_driver rtq9124_driver = {
531 .driver = {
532 .name = "rtq9124",
533 .of_match_table = of_match_ptr(rtq9124_device_id),
534 .pm = pm_ptr(&rtq9124_dev_pm_ops),
535 },
536 .probe = rtq9124_probe,
537 };
538 module_i2c_driver(rtq9124_driver);
539
540 MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
541 MODULE_DESCRIPTION("ASoC RTQ9124 Driver");
542 MODULE_LICENSE("GPL");
543