1// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause 2 3/ { 4 compatible = "realtek,rtl9302-soc"; 5 6 #address-cells = <1>; 7 #size-cells = <1>; 8 9 aliases { 10 serial0 = &uart0; 11 serial1 = &uart1; 12 }; 13 14 cpuintc: cpuintc { 15 compatible = "mti,cpu-interrupt-controller"; 16 #address-cells = <0>; 17 #interrupt-cells = <1>; 18 interrupt-controller; 19 }; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu@0 { 26 device_type = "cpu"; 27 compatible = "mips,mips34Kc"; 28 reg = <0>; 29 clocks = <&baseclk>; 30 }; 31 }; 32 33 baseclk: clock-800mhz { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <800000000>; 37 }; 38 39 lx_clk: clock-175mhz { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <175000000>; 43 }; 44 45 switch0: switch@1b000000 { 46 compatible = "realtek,rtl9301-switch", "syscon", "simple-mfd"; 47 reg = <0x1b000000 0x10000>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 51 reboot@c { 52 compatible = "syscon-reboot"; 53 reg = <0x0c 0x4>; 54 value = <0x01>; 55 }; 56 57 i2c0: i2c@36c { 58 compatible = "realtek,rtl9301-i2c"; 59 reg = <0x36c 0x14>; 60 #address-cells = <1>; 61 #size-cells = <0>; 62 status = "disabled"; 63 }; 64 65 i2c1: i2c@388 { 66 compatible = "realtek,rtl9301-i2c"; 67 reg = <0x388 0x14>; 68 #address-cells = <1>; 69 #size-cells = <0>; 70 status = "disabled"; 71 }; 72 73 mdio_controller: mdio-controller@ca00 { 74 compatible = "realtek,rtl9301-mdio"; 75 reg = <0xca00 0x200>; 76 #address-cells = <1>; 77 #size-cells = <0>; 78 status = "disabled"; 79 80 mdio0: mdio-bus@0 { 81 reg = <0>; 82 #address-cells = <1>; 83 #size-cells = <0>; 84 status = "disabled"; 85 }; 86 mdio1: mdio-bus@1 { 87 reg = <1>; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 status = "disabled"; 91 }; 92 mdio2: mdio-bus@2 { 93 reg = <2>; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 status = "disabled"; 97 }; 98 mdio3: mdio-bus@3 { 99 reg = <3>; 100 #address-cells = <1>; 101 #size-cells = <0>; 102 status = "disabled"; 103 }; 104 }; 105 }; 106 107 soc: soc@18000000 { 108 compatible = "simple-bus"; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0x0 0x18000000 0x20000>; 112 113 intc: interrupt-controller@3000 { 114 compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; 115 reg = <0x3000 0x18>, <0x3018 0x18>; 116 interrupt-controller; 117 #interrupt-cells = <1>; 118 119 interrupt-parent = <&cpuintc>; 120 interrupts = <2>, <3>, <4>, <5>, <6>, <7>; 121 }; 122 123 spi0: spi@1200 { 124 compatible = "realtek,rtl8380-spi"; 125 reg = <0x1200 0x100>; 126 127 #address-cells = <1>; 128 #size-cells = <0>; 129 }; 130 131 timer0: timer@3200 { 132 compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; 133 reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, 134 <0x3230 0x10>, <0x3240 0x10>; 135 136 interrupt-parent = <&intc>; 137 interrupts = <7>, <8>, <9>, <10>, <11>; 138 clocks = <&lx_clk>; 139 }; 140 141 snand: spi@1a400 { 142 compatible = "realtek,rtl9301-snand"; 143 reg = <0x1a400 0x44>; 144 interrupt-parent = <&intc>; 145 interrupts = <19>; 146 clocks = <&lx_clk>; 147 #address-cells = <1>; 148 #size-cells = <0>; 149 status = "disabled"; 150 }; 151 152 uart0: serial@2000 { 153 compatible = "ns16550a"; 154 reg = <0x2000 0x100>; 155 156 clocks = <&lx_clk>; 157 158 interrupt-parent = <&intc>; 159 interrupts = <30>; 160 161 reg-io-width = <1>; 162 reg-shift = <2>; 163 fifo-size = <1>; 164 no-loopback-test; 165 166 status = "disabled"; 167 }; 168 169 uart1: serial@2100 { 170 compatible = "ns16550a"; 171 reg = <0x2100 0x100>; 172 173 clocks = <&lx_clk>; 174 175 interrupt-parent = <&intc>; 176 interrupts = <31>; 177 178 reg-io-width = <1>; 179 reg-shift = <2>; 180 fifo-size = <1>; 181 no-loopback-test; 182 183 status = "disabled"; 184 }; 185 }; 186}; 187