1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include "rk3588-base.dtsi" 7#include "rk3588-extra-pinctrl.dtsi" 8 9/ { 10 hdmi1_sound: hdmi1-sound { 11 compatible = "simple-audio-card"; 12 simple-audio-card,format = "i2s"; 13 simple-audio-card,mclk-fs = <128>; 14 simple-audio-card,name = "hdmi1"; 15 status = "disabled"; 16 17 simple-audio-card,codec { 18 sound-dai = <&hdmi1>; 19 }; 20 21 simple-audio-card,cpu { 22 sound-dai = <&i2s6_8ch>; 23 }; 24 }; 25 26 reserved-memory { 27 #address-cells = <2>; 28 #size-cells = <2>; 29 ranges; 30 31 /* 32 * The 4k HDMI capture controller works only with 32bit 33 * phys addresses and doesn't support IOMMU. HDMI RX CMA 34 * must be reserved below 4GB. 35 * The size of 160MB was determined as follows: 36 * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB 37 * To ensure sufficient support for practical use-cases, 38 * we doubled the 66MB value. 39 */ 40 hdmi_receiver_cma: hdmi-receiver-cma { 41 compatible = "shared-dma-pool"; 42 alloc-ranges = <0x0 0x0 0x0 0xffffffff>; 43 size = <0x0 (160 * 0x100000)>; /* 160MiB */ 44 alignment = <0x0 0x40000>; /* 64K */ 45 no-map; 46 status = "disabled"; 47 }; 48 }; 49 50 usb_host1_xhci: usb@fc400000 { 51 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 52 reg = <0x0 0xfc400000 0x0 0x400000>; 53 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; 54 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, 55 <&cru ACLK_USB3OTG1>; 56 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 57 dr_mode = "otg"; 58 phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; 59 phy-names = "usb2-phy", "usb3-phy"; 60 phy_type = "utmi_wide"; 61 power-domains = <&power RK3588_PD_USB>; 62 resets = <&cru SRST_A_USB3OTG1>; 63 snps,dis_enblslpm_quirk; 64 snps,dis-u2-freeclk-exists-quirk; 65 snps,dis-del-phy-power-chg-quirk; 66 snps,dis-tx-ipgap-linecheck-quirk; 67 status = "disabled"; 68 }; 69 70 pcie30_phy_grf: syscon@fd5b8000 { 71 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; 72 reg = <0x0 0xfd5b8000 0x0 0x10000>; 73 }; 74 75 pipe_phy1_grf: syscon@fd5c0000 { 76 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 77 reg = <0x0 0xfd5c0000 0x0 0x100>; 78 }; 79 80 usbdpphy1_grf: syscon@fd5cc000 { 81 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 82 reg = <0x0 0xfd5cc000 0x0 0x4000>; 83 }; 84 85 usb2phy1_grf: syscon@fd5d4000 { 86 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 87 reg = <0x0 0xfd5d4000 0x0 0x4000>; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 91 u2phy1: usb2phy@4000 { 92 compatible = "rockchip,rk3588-usb2phy"; 93 reg = <0x4000 0x10>; 94 #clock-cells = <0>; 95 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 96 clock-names = "phyclk"; 97 clock-output-names = "usb480m_phy1"; 98 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; 99 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; 100 reset-names = "phy", "apb"; 101 status = "disabled"; 102 103 u2phy1_otg: otg-port { 104 #phy-cells = <0>; 105 status = "disabled"; 106 }; 107 }; 108 }; 109 110 hdptxphy1_grf: syscon@fd5e4000 { 111 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 112 reg = <0x0 0xfd5e4000 0x0 0x100>; 113 }; 114 115 spdif_tx5: spdif-tx@fddb8000 { 116 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 117 reg = <0x0 0xfddb8000 0x0 0x1000>; 118 assigned-clock-parents = <&cru PLL_AUPLL>; 119 assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>; 120 clock-names = "mclk", "hclk"; 121 clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>; 122 dma-names = "tx"; 123 dmas = <&dmac1 22>; 124 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 125 power-domains = <&power RK3588_PD_VO0>; 126 #sound-dai-cells = <0>; 127 status = "disabled"; 128 }; 129 130 i2s8_8ch: i2s@fddc8000 { 131 compatible = "rockchip,rk3588-i2s-tdm"; 132 reg = <0x0 0xfddc8000 0x0 0x1000>; 133 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; 134 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; 135 clock-names = "mclk_tx", "mclk_rx", "hclk"; 136 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; 137 assigned-clock-parents = <&cru PLL_AUPLL>; 138 dmas = <&dmac2 22>; 139 dma-names = "tx"; 140 power-domains = <&power RK3588_PD_VO0>; 141 resets = <&cru SRST_M_I2S8_8CH_TX>; 142 reset-names = "tx-m"; 143 #sound-dai-cells = <0>; 144 status = "disabled"; 145 }; 146 147 spdif_tx4: spdif-tx@fdde8000 { 148 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 149 reg = <0x0 0xfdde8000 0x0 0x1000>; 150 assigned-clock-parents = <&cru PLL_AUPLL>; 151 assigned-clocks = <&cru CLK_SPDIF4_SRC>; 152 clock-names = "mclk", "hclk"; 153 clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; 154 dma-names = "tx"; 155 dmas = <&dmac1 8>; 156 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 157 power-domains = <&power RK3588_PD_VO1>; 158 #sound-dai-cells = <0>; 159 status = "disabled"; 160 }; 161 162 i2s6_8ch: i2s@fddf4000 { 163 compatible = "rockchip,rk3588-i2s-tdm"; 164 reg = <0x0 0xfddf4000 0x0 0x1000>; 165 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 166 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; 167 clock-names = "mclk_tx", "mclk_rx", "hclk"; 168 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; 169 assigned-clock-parents = <&cru PLL_AUPLL>; 170 dmas = <&dmac2 4>; 171 dma-names = "tx"; 172 power-domains = <&power RK3588_PD_VO1>; 173 resets = <&cru SRST_M_I2S6_8CH_TX>; 174 reset-names = "tx-m"; 175 #sound-dai-cells = <0>; 176 status = "disabled"; 177 }; 178 179 i2s7_8ch: i2s@fddf8000 { 180 compatible = "rockchip,rk3588-i2s-tdm"; 181 reg = <0x0 0xfddf8000 0x0 0x1000>; 182 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; 183 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; 184 clock-names = "mclk_tx", "mclk_rx", "hclk"; 185 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; 186 assigned-clock-parents = <&cru PLL_AUPLL>; 187 dmas = <&dmac2 21>; 188 dma-names = "rx"; 189 power-domains = <&power RK3588_PD_VO1>; 190 resets = <&cru SRST_M_I2S7_8CH_RX>; 191 reset-names = "rx-m"; 192 #sound-dai-cells = <0>; 193 status = "disabled"; 194 }; 195 196 i2s10_8ch: i2s@fde00000 { 197 compatible = "rockchip,rk3588-i2s-tdm"; 198 reg = <0x0 0xfde00000 0x0 0x1000>; 199 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; 200 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; 201 clock-names = "mclk_tx", "mclk_rx", "hclk"; 202 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; 203 assigned-clock-parents = <&cru PLL_AUPLL>; 204 dmas = <&dmac2 24>; 205 dma-names = "rx"; 206 power-domains = <&power RK3588_PD_VO1>; 207 resets = <&cru SRST_M_I2S10_8CH_RX>; 208 reset-names = "rx-m"; 209 #sound-dai-cells = <0>; 210 status = "disabled"; 211 }; 212 213 hdmi1: hdmi@fdea0000 { 214 compatible = "rockchip,rk3588-dw-hdmi-qp"; 215 reg = <0x0 0xfdea0000 0x0 0x20000>; 216 clocks = <&cru PCLK_HDMITX1>, 217 <&cru CLK_HDMITX1_EARC>, 218 <&cru CLK_HDMITX1_REF>, 219 <&cru MCLK_I2S6_8CH_TX>, 220 <&cru CLK_HDMIHDP1>, 221 <&cru HCLK_VO1>; 222 clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; 223 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>, 224 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>, 225 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>, 226 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>, 227 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>; 228 interrupt-names = "avp", "cec", "earc", "main", "hpd"; 229 phys = <&hdptxphy1>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd 232 &hdmim1_tx1_scl &hdmim1_tx1_sda>; 233 power-domains = <&power RK3588_PD_VO1>; 234 resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; 235 reset-names = "ref", "hdp"; 236 rockchip,grf = <&sys_grf>; 237 rockchip,vo-grf = <&vo1_grf>; 238 #sound-dai-cells = <0>; 239 status = "disabled"; 240 241 ports { 242 #address-cells = <1>; 243 #size-cells = <0>; 244 245 hdmi1_in: port@0 { 246 reg = <0>; 247 }; 248 249 hdmi1_out: port@1 { 250 reg = <1>; 251 }; 252 }; 253 }; 254 255 edp1: edp@fded0000 { 256 compatible = "rockchip,rk3588-edp"; 257 reg = <0x0 0xfded0000 0x0 0x1000>; 258 clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>; 259 clock-names = "dp", "pclk"; 260 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 261 phys = <&hdptxphy1>; 262 phy-names = "dp"; 263 power-domains = <&power RK3588_PD_VO1>; 264 resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>; 265 reset-names = "dp", "apb"; 266 rockchip,grf = <&vo1_grf>; 267 status = "disabled"; 268 269 ports { 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 edp1_in: port@0 { 274 reg = <0>; 275 }; 276 277 edp1_out: port@1 { 278 reg = <1>; 279 }; 280 }; 281 }; 282 283 hdmi_receiver: hdmi_receiver@fdee0000 { 284 compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; 285 reg = <0x0 0xfdee0000 0x0 0x6000>; 286 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>, 287 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>, 288 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>; 289 interrupt-names = "cec", "hdmi", "dma"; 290 clocks = <&cru ACLK_HDMIRX>, 291 <&cru CLK_HDMIRX_AUD>, 292 <&cru CLK_CR_PARA>, 293 <&cru PCLK_HDMIRX>, 294 <&cru CLK_HDMIRX_REF>, 295 <&cru PCLK_S_HDMIRX>, 296 <&cru HCLK_VO1>; 297 clock-names = "aclk", 298 "audio", 299 "cr_para", 300 "pclk", 301 "ref", 302 "hclk_s_hdmirx", 303 "hclk_vo1"; 304 memory-region = <&hdmi_receiver_cma>; 305 power-domains = <&power RK3588_PD_VO1>; 306 resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, 307 <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; 308 reset-names = "axi", "apb", "ref", "biu"; 309 rockchip,grf = <&sys_grf>; 310 rockchip,vo1-grf = <&vo1_grf>; 311 status = "disabled"; 312 }; 313 314 pcie3x4: pcie@fe150000 { 315 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 316 #address-cells = <3>; 317 #size-cells = <2>; 318 bus-range = <0x00 0x0f>; 319 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 320 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 321 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; 322 clock-names = "aclk_mst", "aclk_slv", 323 "aclk_dbi", "pclk", 324 "aux", "pipe"; 325 device_type = "pci"; 326 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, 327 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, 328 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, 329 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, 330 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 331 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 332 #interrupt-cells = <1>; 333 interrupt-map-mask = <0 0 0 7>; 334 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, 335 <0 0 0 2 &pcie3x4_intc 1>, 336 <0 0 0 3 &pcie3x4_intc 2>, 337 <0 0 0 4 &pcie3x4_intc 3>; 338 linux,pci-domain = <0>; 339 max-link-speed = <3>; 340 msi-map = <0x0000 &its1 0x0000 0x1000>; 341 iommu-map = <0x0000 &mmu600_pcie 0x0000 0x1000>; 342 num-lanes = <4>; 343 phys = <&pcie30phy>; 344 phy-names = "pcie-phy"; 345 power-domains = <&power RK3588_PD_PCIE>; 346 ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, 347 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, 348 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; 349 reg = <0xa 0x40000000 0x0 0x00400000>, 350 <0x0 0xfe150000 0x0 0x00010000>, 351 <0x0 0xf0000000 0x0 0x00100000>; 352 reg-names = "dbi", "apb", "config"; 353 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 354 reset-names = "pwr", "pipe"; 355 status = "disabled"; 356 357 pcie3x4_intc: legacy-interrupt-controller { 358 interrupt-controller; 359 #address-cells = <0>; 360 #interrupt-cells = <1>; 361 interrupt-parent = <&gic>; 362 interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; 363 }; 364 }; 365 366 pcie3x4_ep: pcie-ep@fe150000 { 367 compatible = "rockchip,rk3588-pcie-ep"; 368 reg = <0xa 0x40000000 0x0 0x00100000>, 369 <0xa 0x40100000 0x0 0x00100000>, 370 <0x0 0xfe150000 0x0 0x00010000>, 371 <0x9 0x00000000 0x0 0x40000000>, 372 <0xa 0x40300000 0x0 0x00100000>; 373 reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; 374 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 375 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 376 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; 377 clock-names = "aclk_mst", "aclk_slv", 378 "aclk_dbi", "pclk", 379 "aux", "pipe"; 380 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, 381 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, 382 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, 383 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, 384 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>, 385 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>, 386 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>, 387 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>, 388 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 389 interrupt-names = "sys", "pmc", "msg", "legacy", "err", 390 "dma0", "dma1", "dma2", "dma3"; 391 max-link-speed = <3>; 392 num-lanes = <4>; 393 phys = <&pcie30phy>; 394 phy-names = "pcie-phy"; 395 power-domains = <&power RK3588_PD_PCIE>; 396 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 397 reset-names = "pwr", "pipe"; 398 status = "disabled"; 399 }; 400 401 pcie3x2: pcie@fe160000 { 402 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 403 #address-cells = <3>; 404 #size-cells = <2>; 405 bus-range = <0x10 0x1f>; 406 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, 407 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, 408 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; 409 clock-names = "aclk_mst", "aclk_slv", 410 "aclk_dbi", "pclk", 411 "aux", "pipe"; 412 device_type = "pci"; 413 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, 414 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, 415 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, 416 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, 417 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 418 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 419 #interrupt-cells = <1>; 420 interrupt-map-mask = <0 0 0 7>; 421 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, 422 <0 0 0 2 &pcie3x2_intc 1>, 423 <0 0 0 3 &pcie3x2_intc 2>, 424 <0 0 0 4 &pcie3x2_intc 3>; 425 linux,pci-domain = <1>; 426 max-link-speed = <3>; 427 msi-map = <0x1000 &its1 0x1000 0x1000>; 428 iommu-map = <0x1000 &mmu600_pcie 0x1000 0x1000>; 429 num-lanes = <2>; 430 phys = <&pcie30phy>; 431 phy-names = "pcie-phy"; 432 power-domains = <&power RK3588_PD_PCIE>; 433 ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, 434 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, 435 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; 436 reg = <0xa 0x40400000 0x0 0x00400000>, 437 <0x0 0xfe160000 0x0 0x00010000>, 438 <0x0 0xf1000000 0x0 0x00100000>; 439 reg-names = "dbi", "apb", "config"; 440 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; 441 reset-names = "pwr", "pipe"; 442 status = "disabled"; 443 444 pcie3x2_intc: legacy-interrupt-controller { 445 interrupt-controller; 446 #address-cells = <0>; 447 #interrupt-cells = <1>; 448 interrupt-parent = <&gic>; 449 interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; 450 }; 451 }; 452 453 pcie2x1l0: pcie@fe170000 { 454 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 455 bus-range = <0x20 0x2f>; 456 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, 457 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, 458 <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; 459 clock-names = "aclk_mst", "aclk_slv", 460 "aclk_dbi", "pclk", 461 "aux", "pipe"; 462 device_type = "pci"; 463 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, 464 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, 465 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, 466 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, 467 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; 468 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 469 #interrupt-cells = <1>; 470 interrupt-map-mask = <0 0 0 7>; 471 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, 472 <0 0 0 2 &pcie2x1l0_intc 1>, 473 <0 0 0 3 &pcie2x1l0_intc 2>, 474 <0 0 0 4 &pcie2x1l0_intc 3>; 475 linux,pci-domain = <2>; 476 max-link-speed = <2>; 477 msi-map = <0x2000 &its0 0x2000 0x1000>; 478 iommu-map = <0x2000 &mmu600_pcie 0x2000 0x1000>; 479 num-lanes = <1>; 480 phys = <&combphy1_ps PHY_TYPE_PCIE>; 481 phy-names = "pcie-phy"; 482 power-domains = <&power RK3588_PD_PCIE>; 483 ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, 484 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, 485 <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; 486 reg = <0xa 0x40800000 0x0 0x00400000>, 487 <0x0 0xfe170000 0x0 0x00010000>, 488 <0x0 0xf2000000 0x0 0x00100000>; 489 reg-names = "dbi", "apb", "config"; 490 resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; 491 reset-names = "pwr", "pipe"; 492 #address-cells = <3>; 493 #size-cells = <2>; 494 status = "disabled"; 495 496 pcie2x1l0_intc: legacy-interrupt-controller { 497 interrupt-controller; 498 #address-cells = <0>; 499 #interrupt-cells = <1>; 500 interrupt-parent = <&gic>; 501 interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; 502 }; 503 }; 504 505 gmac0: ethernet@fe1b0000 { 506 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 507 reg = <0x0 0xfe1b0000 0x0 0x10000>; 508 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>, 509 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 510 interrupt-names = "macirq", "eth_wake_irq"; 511 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 512 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 513 <&cru CLK_GMAC0_PTP_REF>; 514 clock-names = "stmmaceth", "clk_mac_ref", 515 "pclk_mac", "aclk_mac", 516 "ptp_ref"; 517 power-domains = <&power RK3588_PD_GMAC>; 518 resets = <&cru SRST_A_GMAC0>; 519 reset-names = "stmmaceth"; 520 rockchip,grf = <&sys_grf>; 521 rockchip,php-grf = <&php_grf>; 522 snps,axi-config = <&gmac0_stmmac_axi_setup>; 523 snps,mixed-burst; 524 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 525 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 526 snps,tso; 527 status = "disabled"; 528 529 mdio0: mdio { 530 compatible = "snps,dwmac-mdio"; 531 #address-cells = <0x1>; 532 #size-cells = <0x0>; 533 }; 534 535 gmac0_stmmac_axi_setup: stmmac-axi-config { 536 snps,blen = <0 0 0 0 16 8 4>; 537 snps,wr_osr_lmt = <4>; 538 snps,rd_osr_lmt = <8>; 539 }; 540 541 gmac0_mtl_rx_setup: rx-queues-config { 542 snps,rx-queues-to-use = <2>; 543 queue0 {}; 544 queue1 {}; 545 }; 546 547 gmac0_mtl_tx_setup: tx-queues-config { 548 snps,tx-queues-to-use = <2>; 549 queue0 {}; 550 queue1 {}; 551 }; 552 }; 553 554 sata1: sata@fe220000 { 555 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 556 reg = <0 0xfe220000 0 0x1000>; 557 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 558 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 559 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, 560 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; 561 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 562 ports-implemented = <0x1>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 567 sata-port@0 { 568 reg = <0>; 569 hba-port-cap = <HBA_PORT_FBSCP>; 570 phys = <&combphy1_ps PHY_TYPE_SATA>; 571 phy-names = "sata-phy"; 572 snps,rx-ts-max = <32>; 573 snps,tx-ts-max = <32>; 574 }; 575 }; 576 577 hdptxphy1: phy@fed70000 { 578 compatible = "rockchip,rk3588-hdptx-phy"; 579 reg = <0x0 0xfed70000 0x0 0x2000>; 580 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; 581 clock-names = "ref", "apb"; 582 #clock-cells = <0>; 583 #phy-cells = <0>; 584 resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, 585 <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, 586 <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, 587 <&cru SRST_HDPTX1_LCPLL>; 588 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 589 "lcpll"; 590 rockchip,grf = <&hdptxphy1_grf>; 591 status = "disabled"; 592 }; 593 594 usbdp_phy1: phy@fed90000 { 595 compatible = "rockchip,rk3588-usbdp-phy"; 596 reg = <0x0 0xfed90000 0x0 0x10000>; 597 #phy-cells = <1>; 598 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 599 <&cru CLK_USBDP_PHY1_IMMORTAL>, 600 <&cru PCLK_USBDPPHY1>, 601 <&u2phy1>; 602 clock-names = "refclk", "immortal", "pclk", "utmi"; 603 resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, 604 <&cru SRST_USBDP_COMBO_PHY1_CMN>, 605 <&cru SRST_USBDP_COMBO_PHY1_LANE>, 606 <&cru SRST_USBDP_COMBO_PHY1_PCS>, 607 <&cru SRST_P_USBDPPHY1>; 608 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 609 rockchip,u2phy-grf = <&usb2phy1_grf>; 610 rockchip,usb-grf = <&usb_grf>; 611 rockchip,usbdpphy-grf = <&usbdpphy1_grf>; 612 rockchip,vo-grf = <&vo0_grf>; 613 status = "disabled"; 614 }; 615 616 combphy1_ps: phy@fee10000 { 617 compatible = "rockchip,rk3588-naneng-combphy"; 618 reg = <0x0 0xfee10000 0x0 0x100>; 619 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, 620 <&cru PCLK_PHP_ROOT>; 621 clock-names = "ref", "apb", "pipe"; 622 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; 623 assigned-clock-rates = <100000000>; 624 #phy-cells = <1>; 625 resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; 626 reset-names = "phy", "apb"; 627 rockchip,pipe-grf = <&php_grf>; 628 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 629 status = "disabled"; 630 }; 631 632 pcie30phy: phy@fee80000 { 633 compatible = "rockchip,rk3588-pcie3-phy"; 634 reg = <0x0 0xfee80000 0x0 0x20000>; 635 #phy-cells = <0>; 636 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; 637 clock-names = "pclk"; 638 resets = <&cru SRST_PCIE30_PHY>; 639 reset-names = "phy"; 640 rockchip,pipe-grf = <&php_grf>; 641 rockchip,phy-grf = <&pcie30_phy_grf>; 642 status = "disabled"; 643 }; 644}; 645 646&vop { 647 clocks = <&cru ACLK_VOP>, 648 <&cru HCLK_VOP>, 649 <&cru DCLK_VOP0>, 650 <&cru DCLK_VOP1>, 651 <&cru DCLK_VOP2>, 652 <&cru DCLK_VOP3>, 653 <&cru PCLK_VOP_ROOT>, 654 <&hdptxphy0>, 655 <&hdptxphy1>; 656 clock-names = "aclk", 657 "hclk", 658 "dclk_vp0", 659 "dclk_vp1", 660 "dclk_vp2", 661 "dclk_vp3", 662 "pclk_vop", 663 "pll_hdmiphy0", 664 "pll_hdmiphy1"; 665}; 666