1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include "rk3588-base.dtsi" 7#include "rk3588-extra-pinctrl.dtsi" 8 9/ { 10 usb_host1_xhci: usb@fc400000 { 11 compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; 12 reg = <0x0 0xfc400000 0x0 0x400000>; 13 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; 14 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, 15 <&cru ACLK_USB3OTG1>; 16 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 17 dr_mode = "otg"; 18 phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>; 19 phy-names = "usb2-phy", "usb3-phy"; 20 phy_type = "utmi_wide"; 21 power-domains = <&power RK3588_PD_USB>; 22 resets = <&cru SRST_A_USB3OTG1>; 23 snps,dis_enblslpm_quirk; 24 snps,dis-u2-freeclk-exists-quirk; 25 snps,dis-del-phy-power-chg-quirk; 26 snps,dis-tx-ipgap-linecheck-quirk; 27 status = "disabled"; 28 }; 29 30 pcie30_phy_grf: syscon@fd5b8000 { 31 compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; 32 reg = <0x0 0xfd5b8000 0x0 0x10000>; 33 }; 34 35 pipe_phy1_grf: syscon@fd5c0000 { 36 compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; 37 reg = <0x0 0xfd5c0000 0x0 0x100>; 38 }; 39 40 usbdpphy1_grf: syscon@fd5cc000 { 41 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 42 reg = <0x0 0xfd5cc000 0x0 0x4000>; 43 }; 44 45 usb2phy1_grf: syscon@fd5d4000 { 46 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; 47 reg = <0x0 0xfd5d4000 0x0 0x4000>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 51 u2phy1: usb2phy@4000 { 52 compatible = "rockchip,rk3588-usb2phy"; 53 reg = <0x4000 0x10>; 54 #clock-cells = <0>; 55 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 56 clock-names = "phyclk"; 57 clock-output-names = "usb480m_phy1"; 58 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; 59 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; 60 reset-names = "phy", "apb"; 61 status = "disabled"; 62 63 u2phy1_otg: otg-port { 64 #phy-cells = <0>; 65 status = "disabled"; 66 }; 67 }; 68 }; 69 70 i2s8_8ch: i2s@fddc8000 { 71 compatible = "rockchip,rk3588-i2s-tdm"; 72 reg = <0x0 0xfddc8000 0x0 0x1000>; 73 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; 74 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; 75 clock-names = "mclk_tx", "mclk_rx", "hclk"; 76 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; 77 assigned-clock-parents = <&cru PLL_AUPLL>; 78 dmas = <&dmac2 22>; 79 dma-names = "tx"; 80 power-domains = <&power RK3588_PD_VO0>; 81 resets = <&cru SRST_M_I2S8_8CH_TX>; 82 reset-names = "tx-m"; 83 #sound-dai-cells = <0>; 84 status = "disabled"; 85 }; 86 87 i2s6_8ch: i2s@fddf4000 { 88 compatible = "rockchip,rk3588-i2s-tdm"; 89 reg = <0x0 0xfddf4000 0x0 0x1000>; 90 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; 91 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; 92 clock-names = "mclk_tx", "mclk_rx", "hclk"; 93 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; 94 assigned-clock-parents = <&cru PLL_AUPLL>; 95 dmas = <&dmac2 4>; 96 dma-names = "tx"; 97 power-domains = <&power RK3588_PD_VO1>; 98 resets = <&cru SRST_M_I2S6_8CH_TX>; 99 reset-names = "tx-m"; 100 #sound-dai-cells = <0>; 101 status = "disabled"; 102 }; 103 104 i2s7_8ch: i2s@fddf8000 { 105 compatible = "rockchip,rk3588-i2s-tdm"; 106 reg = <0x0 0xfddf8000 0x0 0x1000>; 107 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; 108 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; 109 clock-names = "mclk_tx", "mclk_rx", "hclk"; 110 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; 111 assigned-clock-parents = <&cru PLL_AUPLL>; 112 dmas = <&dmac2 21>; 113 dma-names = "rx"; 114 power-domains = <&power RK3588_PD_VO1>; 115 resets = <&cru SRST_M_I2S7_8CH_RX>; 116 reset-names = "rx-m"; 117 #sound-dai-cells = <0>; 118 status = "disabled"; 119 }; 120 121 i2s10_8ch: i2s@fde00000 { 122 compatible = "rockchip,rk3588-i2s-tdm"; 123 reg = <0x0 0xfde00000 0x0 0x1000>; 124 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; 125 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; 126 clock-names = "mclk_tx", "mclk_rx", "hclk"; 127 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; 128 assigned-clock-parents = <&cru PLL_AUPLL>; 129 dmas = <&dmac2 24>; 130 dma-names = "rx"; 131 power-domains = <&power RK3588_PD_VO1>; 132 resets = <&cru SRST_M_I2S10_8CH_RX>; 133 reset-names = "rx-m"; 134 #sound-dai-cells = <0>; 135 status = "disabled"; 136 }; 137 138 pcie3x4: pcie@fe150000 { 139 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 140 #address-cells = <3>; 141 #size-cells = <2>; 142 bus-range = <0x00 0x0f>; 143 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 144 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 145 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; 146 clock-names = "aclk_mst", "aclk_slv", 147 "aclk_dbi", "pclk", 148 "aux", "pipe"; 149 device_type = "pci"; 150 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, 151 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, 152 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, 153 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, 154 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; 155 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 156 #interrupt-cells = <1>; 157 interrupt-map-mask = <0 0 0 7>; 158 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, 159 <0 0 0 2 &pcie3x4_intc 1>, 160 <0 0 0 3 &pcie3x4_intc 2>, 161 <0 0 0 4 &pcie3x4_intc 3>; 162 linux,pci-domain = <0>; 163 max-link-speed = <3>; 164 msi-map = <0x0000 &its1 0x0000 0x1000>; 165 iommu-map = <0x0000 &mmu600_pcie 0x0000 0x1000>; 166 num-lanes = <4>; 167 phys = <&pcie30phy>; 168 phy-names = "pcie-phy"; 169 power-domains = <&power RK3588_PD_PCIE>; 170 ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, 171 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, 172 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; 173 reg = <0xa 0x40000000 0x0 0x00400000>, 174 <0x0 0xfe150000 0x0 0x00010000>, 175 <0x0 0xf0000000 0x0 0x00100000>; 176 reg-names = "dbi", "apb", "config"; 177 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 178 reset-names = "pwr", "pipe"; 179 status = "disabled"; 180 181 pcie3x4_intc: legacy-interrupt-controller { 182 interrupt-controller; 183 #address-cells = <0>; 184 #interrupt-cells = <1>; 185 interrupt-parent = <&gic>; 186 interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; 187 }; 188 }; 189 190 pcie3x4_ep: pcie-ep@fe150000 { 191 compatible = "rockchip,rk3588-pcie-ep"; 192 reg = <0xa 0x40000000 0x0 0x00100000>, 193 <0xa 0x40100000 0x0 0x00100000>, 194 <0x0 0xfe150000 0x0 0x00010000>, 195 <0x9 0x00000000 0x0 0x40000000>, 196 <0xa 0x40300000 0x0 0x00100000>; 197 reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; 198 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 199 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 200 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; 201 clock-names = "aclk_mst", "aclk_slv", 202 "aclk_dbi", "pclk", 203 "aux", "pipe"; 204 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, 205 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, 206 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, 207 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, 208 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>, 209 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>, 210 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>, 211 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>, 212 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 213 interrupt-names = "sys", "pmc", "msg", "legacy", "err", 214 "dma0", "dma1", "dma2", "dma3"; 215 max-link-speed = <3>; 216 num-lanes = <4>; 217 phys = <&pcie30phy>; 218 phy-names = "pcie-phy"; 219 power-domains = <&power RK3588_PD_PCIE>; 220 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 221 reset-names = "pwr", "pipe"; 222 status = "disabled"; 223 }; 224 225 pcie3x2: pcie@fe160000 { 226 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 227 #address-cells = <3>; 228 #size-cells = <2>; 229 bus-range = <0x10 0x1f>; 230 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, 231 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, 232 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; 233 clock-names = "aclk_mst", "aclk_slv", 234 "aclk_dbi", "pclk", 235 "aux", "pipe"; 236 device_type = "pci"; 237 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, 238 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, 239 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, 240 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, 241 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; 242 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 243 #interrupt-cells = <1>; 244 interrupt-map-mask = <0 0 0 7>; 245 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, 246 <0 0 0 2 &pcie3x2_intc 1>, 247 <0 0 0 3 &pcie3x2_intc 2>, 248 <0 0 0 4 &pcie3x2_intc 3>; 249 linux,pci-domain = <1>; 250 max-link-speed = <3>; 251 msi-map = <0x1000 &its1 0x1000 0x1000>; 252 iommu-map = <0x1000 &mmu600_pcie 0x1000 0x1000>; 253 num-lanes = <2>; 254 phys = <&pcie30phy>; 255 phy-names = "pcie-phy"; 256 power-domains = <&power RK3588_PD_PCIE>; 257 ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, 258 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, 259 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; 260 reg = <0xa 0x40400000 0x0 0x00400000>, 261 <0x0 0xfe160000 0x0 0x00010000>, 262 <0x0 0xf1000000 0x0 0x00100000>; 263 reg-names = "dbi", "apb", "config"; 264 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; 265 reset-names = "pwr", "pipe"; 266 status = "disabled"; 267 268 pcie3x2_intc: legacy-interrupt-controller { 269 interrupt-controller; 270 #address-cells = <0>; 271 #interrupt-cells = <1>; 272 interrupt-parent = <&gic>; 273 interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; 274 }; 275 }; 276 277 pcie2x1l0: pcie@fe170000 { 278 compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; 279 bus-range = <0x20 0x2f>; 280 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, 281 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, 282 <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; 283 clock-names = "aclk_mst", "aclk_slv", 284 "aclk_dbi", "pclk", 285 "aux", "pipe"; 286 device_type = "pci"; 287 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, 288 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, 289 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, 290 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, 291 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; 292 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 293 #interrupt-cells = <1>; 294 interrupt-map-mask = <0 0 0 7>; 295 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, 296 <0 0 0 2 &pcie2x1l0_intc 1>, 297 <0 0 0 3 &pcie2x1l0_intc 2>, 298 <0 0 0 4 &pcie2x1l0_intc 3>; 299 linux,pci-domain = <2>; 300 max-link-speed = <2>; 301 msi-map = <0x2000 &its0 0x2000 0x1000>; 302 iommu-map = <0x2000 &mmu600_pcie 0x2000 0x1000>; 303 num-lanes = <1>; 304 phys = <&combphy1_ps PHY_TYPE_PCIE>; 305 phy-names = "pcie-phy"; 306 power-domains = <&power RK3588_PD_PCIE>; 307 ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, 308 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, 309 <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; 310 reg = <0xa 0x40800000 0x0 0x00400000>, 311 <0x0 0xfe170000 0x0 0x00010000>, 312 <0x0 0xf2000000 0x0 0x00100000>; 313 reg-names = "dbi", "apb", "config"; 314 resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; 315 reset-names = "pwr", "pipe"; 316 #address-cells = <3>; 317 #size-cells = <2>; 318 status = "disabled"; 319 320 pcie2x1l0_intc: legacy-interrupt-controller { 321 interrupt-controller; 322 #address-cells = <0>; 323 #interrupt-cells = <1>; 324 interrupt-parent = <&gic>; 325 interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; 326 }; 327 }; 328 329 gmac0: ethernet@fe1b0000 { 330 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 331 reg = <0x0 0xfe1b0000 0x0 0x10000>; 332 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>, 333 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 334 interrupt-names = "macirq", "eth_wake_irq"; 335 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 336 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 337 <&cru CLK_GMAC0_PTP_REF>; 338 clock-names = "stmmaceth", "clk_mac_ref", 339 "pclk_mac", "aclk_mac", 340 "ptp_ref"; 341 power-domains = <&power RK3588_PD_GMAC>; 342 resets = <&cru SRST_A_GMAC0>; 343 reset-names = "stmmaceth"; 344 rockchip,grf = <&sys_grf>; 345 rockchip,php-grf = <&php_grf>; 346 snps,axi-config = <&gmac0_stmmac_axi_setup>; 347 snps,mixed-burst; 348 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 349 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 350 snps,tso; 351 status = "disabled"; 352 353 mdio0: mdio { 354 compatible = "snps,dwmac-mdio"; 355 #address-cells = <0x1>; 356 #size-cells = <0x0>; 357 }; 358 359 gmac0_stmmac_axi_setup: stmmac-axi-config { 360 snps,blen = <0 0 0 0 16 8 4>; 361 snps,wr_osr_lmt = <4>; 362 snps,rd_osr_lmt = <8>; 363 }; 364 365 gmac0_mtl_rx_setup: rx-queues-config { 366 snps,rx-queues-to-use = <2>; 367 queue0 {}; 368 queue1 {}; 369 }; 370 371 gmac0_mtl_tx_setup: tx-queues-config { 372 snps,tx-queues-to-use = <2>; 373 queue0 {}; 374 queue1 {}; 375 }; 376 }; 377 378 sata1: sata@fe220000 { 379 compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; 380 reg = <0 0xfe220000 0 0x1000>; 381 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; 382 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 383 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, 384 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; 385 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 386 ports-implemented = <0x1>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 status = "disabled"; 390 391 sata-port@0 { 392 reg = <0>; 393 hba-port-cap = <HBA_PORT_FBSCP>; 394 phys = <&combphy1_ps PHY_TYPE_SATA>; 395 phy-names = "sata-phy"; 396 snps,rx-ts-max = <32>; 397 snps,tx-ts-max = <32>; 398 }; 399 }; 400 401 usbdp_phy1: phy@fed90000 { 402 compatible = "rockchip,rk3588-usbdp-phy"; 403 reg = <0x0 0xfed90000 0x0 0x10000>; 404 #phy-cells = <1>; 405 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 406 <&cru CLK_USBDP_PHY1_IMMORTAL>, 407 <&cru PCLK_USBDPPHY1>, 408 <&u2phy1>; 409 clock-names = "refclk", "immortal", "pclk", "utmi"; 410 resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, 411 <&cru SRST_USBDP_COMBO_PHY1_CMN>, 412 <&cru SRST_USBDP_COMBO_PHY1_LANE>, 413 <&cru SRST_USBDP_COMBO_PHY1_PCS>, 414 <&cru SRST_P_USBDPPHY1>; 415 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 416 rockchip,u2phy-grf = <&usb2phy1_grf>; 417 rockchip,usb-grf = <&usb_grf>; 418 rockchip,usbdpphy-grf = <&usbdpphy1_grf>; 419 rockchip,vo-grf = <&vo0_grf>; 420 status = "disabled"; 421 }; 422 423 combphy1_ps: phy@fee10000 { 424 compatible = "rockchip,rk3588-naneng-combphy"; 425 reg = <0x0 0xfee10000 0x0 0x100>; 426 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, 427 <&cru PCLK_PHP_ROOT>; 428 clock-names = "ref", "apb", "pipe"; 429 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; 430 assigned-clock-rates = <100000000>; 431 #phy-cells = <1>; 432 resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; 433 reset-names = "phy", "apb"; 434 rockchip,pipe-grf = <&php_grf>; 435 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 436 status = "disabled"; 437 }; 438 439 pcie30phy: phy@fee80000 { 440 compatible = "rockchip,rk3588-pcie3-phy"; 441 reg = <0x0 0xfee80000 0x0 0x20000>; 442 #phy-cells = <0>; 443 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; 444 clock-names = "pclk"; 445 resets = <&cru SRST_PCIE30_PHY>; 446 reset-names = "phy"; 447 rockchip,pipe-grf = <&php_grf>; 448 rockchip,phy-grf = <&pcie30_phy_grf>; 449 status = "disabled"; 450 }; 451}; 452