1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3568-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3568-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 gpio0 = &gpio0; 22 gpio1 = &gpio1; 23 gpio2 = &gpio2; 24 gpio3 = &gpio3; 25 gpio4 = &gpio4; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 serial5 = &uart5; 38 serial6 = &uart6; 39 serial7 = &uart7; 40 serial8 = &uart8; 41 serial9 = &uart9; 42 spi0 = &spi0; 43 spi1 = &spi1; 44 spi2 = &spi2; 45 spi3 = &spi3; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a55"; 55 reg = <0x0 0x0>; 56 clocks = <&scmi_clk 0>; 57 #cooling-cells = <2>; 58 enable-method = "psci"; 59 i-cache-size = <0x8000>; 60 i-cache-line-size = <64>; 61 i-cache-sets = <128>; 62 d-cache-size = <0x8000>; 63 d-cache-line-size = <64>; 64 d-cache-sets = <128>; 65 next-level-cache = <&l3_cache>; 66 }; 67 68 cpu1: cpu@100 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a55"; 71 reg = <0x0 0x100>; 72 #cooling-cells = <2>; 73 enable-method = "psci"; 74 i-cache-size = <0x8000>; 75 i-cache-line-size = <64>; 76 i-cache-sets = <128>; 77 d-cache-size = <0x8000>; 78 d-cache-line-size = <64>; 79 d-cache-sets = <128>; 80 next-level-cache = <&l3_cache>; 81 }; 82 83 cpu2: cpu@200 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a55"; 86 reg = <0x0 0x200>; 87 #cooling-cells = <2>; 88 enable-method = "psci"; 89 i-cache-size = <0x8000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <128>; 92 d-cache-size = <0x8000>; 93 d-cache-line-size = <64>; 94 d-cache-sets = <128>; 95 next-level-cache = <&l3_cache>; 96 }; 97 98 cpu3: cpu@300 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a55"; 101 reg = <0x0 0x300>; 102 #cooling-cells = <2>; 103 enable-method = "psci"; 104 i-cache-size = <0x8000>; 105 i-cache-line-size = <64>; 106 i-cache-sets = <128>; 107 d-cache-size = <0x8000>; 108 d-cache-line-size = <64>; 109 d-cache-sets = <128>; 110 next-level-cache = <&l3_cache>; 111 }; 112 }; 113 114 /* 115 * There are no private per-core L2 caches, but only the 116 * L3 cache that appears to the CPU cores as L2 caches 117 */ 118 l3_cache: l3-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-unified; 122 cache-size = <0x80000>; 123 cache-line-size = <64>; 124 cache-sets = <512>; 125 }; 126 127 display_subsystem: display-subsystem { 128 compatible = "rockchip,display-subsystem"; 129 ports = <&vop_out>; 130 }; 131 132 firmware { 133 scmi: scmi { 134 compatible = "arm,scmi-smc"; 135 arm,smc-id = <0x82000010>; 136 shmem = <&scmi_shmem>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 140 scmi_clk: protocol@14 { 141 reg = <0x14>; 142 #clock-cells = <1>; 143 }; 144 }; 145 }; 146 147 hdmi_sound: hdmi-sound { 148 compatible = "simple-audio-card"; 149 simple-audio-card,name = "HDMI"; 150 simple-audio-card,format = "i2s"; 151 simple-audio-card,mclk-fs = <256>; 152 status = "disabled"; 153 154 simple-audio-card,codec { 155 sound-dai = <&hdmi>; 156 }; 157 158 simple-audio-card,cpu { 159 sound-dai = <&i2s0_8ch>; 160 }; 161 }; 162 163 pmu { 164 compatible = "arm,cortex-a55-pmu"; 165 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 169 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 170 }; 171 172 psci { 173 compatible = "arm,psci-1.0"; 174 method = "smc"; 175 }; 176 177 reserved-memory { 178 #address-cells = <2>; 179 #size-cells = <2>; 180 ranges; 181 182 scmi_shmem: shmem@10f000 { 183 compatible = "arm,scmi-shmem"; 184 reg = <0x0 0x0010f000 0x0 0x100>; 185 no-map; 186 }; 187 }; 188 189 timer { 190 compatible = "arm,armv8-timer"; 191 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 195 arm,no-tick-in-suspend; 196 }; 197 198 xin24m: xin24m { 199 compatible = "fixed-clock"; 200 clock-frequency = <24000000>; 201 clock-output-names = "xin24m"; 202 #clock-cells = <0>; 203 }; 204 205 xin32k: xin32k { 206 compatible = "fixed-clock"; 207 clock-frequency = <32768>; 208 clock-output-names = "xin32k"; 209 pinctrl-0 = <&clk32k_out0>; 210 pinctrl-names = "default"; 211 #clock-cells = <0>; 212 }; 213 214 sata1: sata@fc400000 { 215 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 216 reg = <0 0xfc400000 0 0x1000>; 217 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, 218 <&cru CLK_SATA1_RXOOB>; 219 clock-names = "sata", "pmalive", "rxoob"; 220 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 221 phys = <&combphy1 PHY_TYPE_SATA>; 222 phy-names = "sata-phy"; 223 ports-implemented = <0x1>; 224 power-domains = <&power RK3568_PD_PIPE>; 225 status = "disabled"; 226 }; 227 228 sata2: sata@fc800000 { 229 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; 230 reg = <0 0xfc800000 0 0x1000>; 231 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, 232 <&cru CLK_SATA2_RXOOB>; 233 clock-names = "sata", "pmalive", "rxoob"; 234 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 235 phys = <&combphy2 PHY_TYPE_SATA>; 236 phy-names = "sata-phy"; 237 ports-implemented = <0x1>; 238 power-domains = <&power RK3568_PD_PIPE>; 239 status = "disabled"; 240 }; 241 242 usb_host0_xhci: usb@fcc00000 { 243 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 244 reg = <0x0 0xfcc00000 0x0 0x400000>; 245 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, 247 <&cru ACLK_USB3OTG0>; 248 clock-names = "ref_clk", "suspend_clk", 249 "bus_clk"; 250 dr_mode = "otg"; 251 phy_type = "utmi_wide"; 252 power-domains = <&power RK3568_PD_PIPE>; 253 resets = <&cru SRST_USB3OTG0>; 254 snps,dis_u2_susphy_quirk; 255 status = "disabled"; 256 }; 257 258 usb_host1_xhci: usb@fd000000 { 259 compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; 260 reg = <0x0 0xfd000000 0x0 0x400000>; 261 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, 263 <&cru ACLK_USB3OTG1>; 264 clock-names = "ref_clk", "suspend_clk", 265 "bus_clk"; 266 dr_mode = "host"; 267 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; 268 phy-names = "usb2-phy", "usb3-phy"; 269 phy_type = "utmi_wide"; 270 power-domains = <&power RK3568_PD_PIPE>; 271 resets = <&cru SRST_USB3OTG1>; 272 snps,dis_u2_susphy_quirk; 273 status = "disabled"; 274 }; 275 276 gic: interrupt-controller@fd400000 { 277 compatible = "arm,gic-v3"; 278 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ 279 <0x0 0xfd460000 0 0x80000>; /* GICR */ 280 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 281 interrupt-controller; 282 #interrupt-cells = <3>; 283 mbi-alias = <0x0 0xfd410000>; 284 mbi-ranges = <296 24>; 285 msi-controller; 286 ranges; 287 #address-cells = <2>; 288 #size-cells = <2>; 289 dma-noncoherent; 290 291 its: msi-controller@fd440000 { 292 compatible = "arm,gic-v3-its"; 293 reg = <0x0 0xfd440000 0 0x20000>; 294 dma-noncoherent; 295 msi-controller; 296 #msi-cells = <1>; 297 }; 298 }; 299 300 usb_host0_ehci: usb@fd800000 { 301 compatible = "generic-ehci"; 302 reg = <0x0 0xfd800000 0x0 0x40000>; 303 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 305 <&cru PCLK_USB>; 306 phys = <&usb2phy1_otg>; 307 phy-names = "usb"; 308 status = "disabled"; 309 }; 310 311 usb_host0_ohci: usb@fd840000 { 312 compatible = "generic-ohci"; 313 reg = <0x0 0xfd840000 0x0 0x40000>; 314 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, 316 <&cru PCLK_USB>; 317 phys = <&usb2phy1_otg>; 318 phy-names = "usb"; 319 status = "disabled"; 320 }; 321 322 usb_host1_ehci: usb@fd880000 { 323 compatible = "generic-ehci"; 324 reg = <0x0 0xfd880000 0x0 0x40000>; 325 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 327 <&cru PCLK_USB>; 328 phys = <&usb2phy1_host>; 329 phy-names = "usb"; 330 status = "disabled"; 331 }; 332 333 usb_host1_ohci: usb@fd8c0000 { 334 compatible = "generic-ohci"; 335 reg = <0x0 0xfd8c0000 0x0 0x40000>; 336 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, 338 <&cru PCLK_USB>; 339 phys = <&usb2phy1_host>; 340 phy-names = "usb"; 341 status = "disabled"; 342 }; 343 344 pmugrf: syscon@fdc20000 { 345 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; 346 reg = <0x0 0xfdc20000 0x0 0x10000>; 347 348 pmu_io_domains: io-domains { 349 compatible = "rockchip,rk3568-pmu-io-voltage-domain"; 350 status = "disabled"; 351 }; 352 }; 353 354 pipegrf: syscon@fdc50000 { 355 reg = <0x0 0xfdc50000 0x0 0x1000>; 356 }; 357 358 grf: syscon@fdc60000 { 359 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; 360 reg = <0x0 0xfdc60000 0x0 0x10000>; 361 }; 362 363 pipe_phy_grf1: syscon@fdc80000 { 364 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 365 reg = <0x0 0xfdc80000 0x0 0x1000>; 366 }; 367 368 pipe_phy_grf2: syscon@fdc90000 { 369 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; 370 reg = <0x0 0xfdc90000 0x0 0x1000>; 371 }; 372 373 usb2phy0_grf: syscon@fdca0000 { 374 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 375 reg = <0x0 0xfdca0000 0x0 0x8000>; 376 }; 377 378 usb2phy1_grf: syscon@fdca8000 { 379 compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; 380 reg = <0x0 0xfdca8000 0x0 0x8000>; 381 }; 382 383 pmucru: clock-controller@fdd00000 { 384 compatible = "rockchip,rk3568-pmucru"; 385 reg = <0x0 0xfdd00000 0x0 0x1000>; 386 #clock-cells = <1>; 387 #reset-cells = <1>; 388 }; 389 390 cru: clock-controller@fdd20000 { 391 compatible = "rockchip,rk3568-cru"; 392 reg = <0x0 0xfdd20000 0x0 0x1000>; 393 clocks = <&xin24m>; 394 clock-names = "xin24m"; 395 #clock-cells = <1>; 396 #reset-cells = <1>; 397 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; 398 assigned-clock-rates = <32768>, <1200000000>, <200000000>; 399 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>; 400 rockchip,grf = <&grf>; 401 }; 402 403 i2c0: i2c@fdd40000 { 404 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 405 reg = <0x0 0xfdd40000 0x0 0x1000>; 406 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 407 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 408 clock-names = "i2c", "pclk"; 409 pinctrl-0 = <&i2c0_xfer>; 410 pinctrl-names = "default"; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 status = "disabled"; 414 }; 415 416 uart0: serial@fdd50000 { 417 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 418 reg = <0x0 0xfdd50000 0x0 0x100>; 419 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; 421 clock-names = "baudclk", "apb_pclk"; 422 dmas = <&dmac0 0>, <&dmac0 1>; 423 pinctrl-0 = <&uart0_xfer>; 424 pinctrl-names = "default"; 425 reg-io-width = <4>; 426 reg-shift = <2>; 427 status = "disabled"; 428 }; 429 430 pwm0: pwm@fdd70000 { 431 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 432 reg = <0x0 0xfdd70000 0x0 0x10>; 433 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 434 clock-names = "pwm", "pclk"; 435 pinctrl-0 = <&pwm0m0_pins>; 436 pinctrl-names = "default"; 437 #pwm-cells = <3>; 438 status = "disabled"; 439 }; 440 441 pwm1: pwm@fdd70010 { 442 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 443 reg = <0x0 0xfdd70010 0x0 0x10>; 444 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 445 clock-names = "pwm", "pclk"; 446 pinctrl-0 = <&pwm1m0_pins>; 447 pinctrl-names = "default"; 448 #pwm-cells = <3>; 449 status = "disabled"; 450 }; 451 452 pwm2: pwm@fdd70020 { 453 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 454 reg = <0x0 0xfdd70020 0x0 0x10>; 455 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 456 clock-names = "pwm", "pclk"; 457 pinctrl-0 = <&pwm2m0_pins>; 458 pinctrl-names = "default"; 459 #pwm-cells = <3>; 460 status = "disabled"; 461 }; 462 463 pwm3: pwm@fdd70030 { 464 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 465 reg = <0x0 0xfdd70030 0x0 0x10>; 466 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 467 clock-names = "pwm", "pclk"; 468 pinctrl-0 = <&pwm3_pins>; 469 pinctrl-names = "default"; 470 #pwm-cells = <3>; 471 status = "disabled"; 472 }; 473 474 pmu: power-management@fdd90000 { 475 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; 476 reg = <0x0 0xfdd90000 0x0 0x1000>; 477 478 power: power-controller { 479 compatible = "rockchip,rk3568-power-controller"; 480 #power-domain-cells = <1>; 481 #address-cells = <1>; 482 #size-cells = <0>; 483 484 /* These power domains are grouped by VD_GPU */ 485 power-domain@RK3568_PD_GPU { 486 reg = <RK3568_PD_GPU>; 487 clocks = <&cru ACLK_GPU_PRE>, 488 <&cru PCLK_GPU_PRE>; 489 pm_qos = <&qos_gpu>; 490 #power-domain-cells = <0>; 491 }; 492 493 /* These power domains are grouped by VD_LOGIC */ 494 power-domain@RK3568_PD_VI { 495 reg = <RK3568_PD_VI>; 496 clocks = <&cru HCLK_VI>, 497 <&cru PCLK_VI>; 498 pm_qos = <&qos_isp>, 499 <&qos_vicap0>, 500 <&qos_vicap1>; 501 #power-domain-cells = <0>; 502 }; 503 504 power-domain@RK3568_PD_VO { 505 reg = <RK3568_PD_VO>; 506 clocks = <&cru HCLK_VO>, 507 <&cru PCLK_VO>, 508 <&cru ACLK_VOP_PRE>; 509 pm_qos = <&qos_hdcp>, 510 <&qos_vop_m0>, 511 <&qos_vop_m1>; 512 #power-domain-cells = <0>; 513 }; 514 515 power-domain@RK3568_PD_RGA { 516 reg = <RK3568_PD_RGA>; 517 clocks = <&cru HCLK_RGA_PRE>, 518 <&cru PCLK_RGA_PRE>; 519 pm_qos = <&qos_ebc>, 520 <&qos_iep>, 521 <&qos_jpeg_dec>, 522 <&qos_jpeg_enc>, 523 <&qos_rga_rd>, 524 <&qos_rga_wr>; 525 #power-domain-cells = <0>; 526 }; 527 528 power-domain@RK3568_PD_VPU { 529 reg = <RK3568_PD_VPU>; 530 clocks = <&cru HCLK_VPU_PRE>; 531 pm_qos = <&qos_vpu>; 532 #power-domain-cells = <0>; 533 }; 534 535 power-domain@RK3568_PD_RKVDEC { 536 clocks = <&cru HCLK_RKVDEC_PRE>; 537 reg = <RK3568_PD_RKVDEC>; 538 pm_qos = <&qos_rkvdec>; 539 #power-domain-cells = <0>; 540 }; 541 542 power-domain@RK3568_PD_RKVENC { 543 reg = <RK3568_PD_RKVENC>; 544 clocks = <&cru HCLK_RKVENC_PRE>; 545 pm_qos = <&qos_rkvenc_rd_m0>, 546 <&qos_rkvenc_rd_m1>, 547 <&qos_rkvenc_wr_m0>; 548 #power-domain-cells = <0>; 549 }; 550 }; 551 }; 552 553 gpu: gpu@fde60000 { 554 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; 555 reg = <0x0 0xfde60000 0x0 0x4000>; 556 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 559 interrupt-names = "job", "mmu", "gpu"; 560 clocks = <&scmi_clk 1>, <&cru CLK_GPU>; 561 clock-names = "gpu", "bus"; 562 #cooling-cells = <2>; 563 power-domains = <&power RK3568_PD_GPU>; 564 status = "disabled"; 565 }; 566 567 vpu: video-codec@fdea0400 { 568 compatible = "rockchip,rk3568-vpu"; 569 reg = <0x0 0xfdea0000 0x0 0x800>; 570 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 571 interrupt-names = "vdpu"; 572 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 573 clock-names = "aclk", "hclk"; 574 iommus = <&vdpu_mmu>; 575 power-domains = <&power RK3568_PD_VPU>; 576 }; 577 578 vdpu_mmu: iommu@fdea0800 { 579 compatible = "rockchip,rk3568-iommu"; 580 reg = <0x0 0xfdea0800 0x0 0x40>; 581 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 582 clock-names = "aclk", "iface"; 583 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 584 power-domains = <&power RK3568_PD_VPU>; 585 #iommu-cells = <0>; 586 }; 587 588 rga: rga@fdeb0000 { 589 compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga"; 590 reg = <0x0 0xfdeb0000 0x0 0x180>; 591 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; 593 clock-names = "aclk", "hclk", "sclk"; 594 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 595 reset-names = "core", "axi", "ahb"; 596 power-domains = <&power RK3568_PD_RGA>; 597 }; 598 599 vepu: video-codec@fdee0000 { 600 compatible = "rockchip,rk3568-vepu"; 601 reg = <0x0 0xfdee0000 0x0 0x800>; 602 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 604 clock-names = "aclk", "hclk"; 605 iommus = <&vepu_mmu>; 606 power-domains = <&power RK3568_PD_RGA>; 607 }; 608 609 vepu_mmu: iommu@fdee0800 { 610 compatible = "rockchip,rk3568-iommu"; 611 reg = <0x0 0xfdee0800 0x0 0x40>; 612 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; 614 clock-names = "aclk", "iface"; 615 power-domains = <&power RK3568_PD_RGA>; 616 #iommu-cells = <0>; 617 }; 618 619 sdmmc2: mmc@fe000000 { 620 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 621 reg = <0x0 0xfe000000 0x0 0x4000>; 622 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, 624 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; 625 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 626 fifo-depth = <0x100>; 627 max-frequency = <150000000>; 628 resets = <&cru SRST_SDMMC2>; 629 reset-names = "reset"; 630 status = "disabled"; 631 }; 632 633 gmac1: ethernet@fe010000 { 634 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; 635 reg = <0x0 0xfe010000 0x0 0x10000>; 636 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 638 interrupt-names = "macirq", "eth_wake_irq"; 639 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, 640 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, 641 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, 642 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; 643 clock-names = "stmmaceth", "mac_clk_rx", 644 "mac_clk_tx", "clk_mac_refout", 645 "aclk_mac", "pclk_mac", 646 "clk_mac_speed", "ptp_ref"; 647 resets = <&cru SRST_A_GMAC1>; 648 reset-names = "stmmaceth"; 649 rockchip,grf = <&grf>; 650 snps,axi-config = <&gmac1_stmmac_axi_setup>; 651 snps,mixed-burst; 652 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 653 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 654 snps,tso; 655 status = "disabled"; 656 657 mdio1: mdio { 658 compatible = "snps,dwmac-mdio"; 659 #address-cells = <0x1>; 660 #size-cells = <0x0>; 661 }; 662 663 gmac1_stmmac_axi_setup: stmmac-axi-config { 664 snps,blen = <0 0 0 0 16 8 4>; 665 snps,rd_osr_lmt = <8>; 666 snps,wr_osr_lmt = <4>; 667 }; 668 669 gmac1_mtl_rx_setup: rx-queues-config { 670 snps,rx-queues-to-use = <1>; 671 queue0 {}; 672 }; 673 674 gmac1_mtl_tx_setup: tx-queues-config { 675 snps,tx-queues-to-use = <1>; 676 queue0 {}; 677 }; 678 }; 679 680 vop: vop@fe040000 { 681 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; 682 reg-names = "vop", "gamma-lut"; 683 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 684 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, 685 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; 686 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2"; 687 iommus = <&vop_mmu>; 688 power-domains = <&power RK3568_PD_VO>; 689 rockchip,grf = <&grf>; 690 status = "disabled"; 691 692 vop_out: ports { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 696 vp0: port@0 { 697 reg = <0>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 }; 701 702 vp1: port@1 { 703 reg = <1>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 }; 707 708 vp2: port@2 { 709 reg = <2>; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 }; 713 }; 714 }; 715 716 vop_mmu: iommu@fe043e00 { 717 compatible = "rockchip,rk3568-iommu"; 718 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; 719 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 721 clock-names = "aclk", "iface"; 722 #iommu-cells = <0>; 723 power-domains = <&power RK3568_PD_VO>; 724 status = "disabled"; 725 }; 726 727 dsi0: dsi@fe060000 { 728 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 729 reg = <0x00 0xfe060000 0x00 0x10000>; 730 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 731 clock-names = "pclk"; 732 clocks = <&cru PCLK_DSITX_0>; 733 phy-names = "dphy"; 734 phys = <&dsi_dphy0>; 735 power-domains = <&power RK3568_PD_VO>; 736 reset-names = "apb"; 737 resets = <&cru SRST_P_DSITX_0>; 738 rockchip,grf = <&grf>; 739 status = "disabled"; 740 741 ports { 742 #address-cells = <1>; 743 #size-cells = <0>; 744 745 dsi0_in: port@0 { 746 reg = <0>; 747 }; 748 749 dsi0_out: port@1 { 750 reg = <1>; 751 }; 752 }; 753 }; 754 755 dsi1: dsi@fe070000 { 756 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"; 757 reg = <0x0 0xfe070000 0x0 0x10000>; 758 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 759 clock-names = "pclk"; 760 clocks = <&cru PCLK_DSITX_1>; 761 phy-names = "dphy"; 762 phys = <&dsi_dphy1>; 763 power-domains = <&power RK3568_PD_VO>; 764 reset-names = "apb"; 765 resets = <&cru SRST_P_DSITX_1>; 766 rockchip,grf = <&grf>; 767 status = "disabled"; 768 769 ports { 770 #address-cells = <1>; 771 #size-cells = <0>; 772 773 dsi1_in: port@0 { 774 reg = <0>; 775 }; 776 777 dsi1_out: port@1 { 778 reg = <1>; 779 }; 780 }; 781 }; 782 783 hdmi: hdmi@fe0a0000 { 784 compatible = "rockchip,rk3568-dw-hdmi"; 785 reg = <0x0 0xfe0a0000 0x0 0x20000>; 786 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&cru PCLK_HDMI_HOST>, 788 <&cru CLK_HDMI_SFR>, 789 <&cru CLK_HDMI_CEC>, 790 <&pmucru CLK_HDMI_REF>, 791 <&cru HCLK_VO>; 792 clock-names = "iahb", "isfr", "cec", "ref"; 793 pinctrl-names = "default"; 794 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; 795 power-domains = <&power RK3568_PD_VO>; 796 reg-io-width = <4>; 797 rockchip,grf = <&grf>; 798 #sound-dai-cells = <0>; 799 status = "disabled"; 800 801 ports { 802 #address-cells = <1>; 803 #size-cells = <0>; 804 805 hdmi_in: port@0 { 806 reg = <0>; 807 }; 808 809 hdmi_out: port@1 { 810 reg = <1>; 811 }; 812 }; 813 }; 814 815 qos_gpu: qos@fe128000 { 816 compatible = "rockchip,rk3568-qos", "syscon"; 817 reg = <0x0 0xfe128000 0x0 0x20>; 818 }; 819 820 qos_rkvenc_rd_m0: qos@fe138080 { 821 compatible = "rockchip,rk3568-qos", "syscon"; 822 reg = <0x0 0xfe138080 0x0 0x20>; 823 }; 824 825 qos_rkvenc_rd_m1: qos@fe138100 { 826 compatible = "rockchip,rk3568-qos", "syscon"; 827 reg = <0x0 0xfe138100 0x0 0x20>; 828 }; 829 830 qos_rkvenc_wr_m0: qos@fe138180 { 831 compatible = "rockchip,rk3568-qos", "syscon"; 832 reg = <0x0 0xfe138180 0x0 0x20>; 833 }; 834 835 qos_isp: qos@fe148000 { 836 compatible = "rockchip,rk3568-qos", "syscon"; 837 reg = <0x0 0xfe148000 0x0 0x20>; 838 }; 839 840 qos_vicap0: qos@fe148080 { 841 compatible = "rockchip,rk3568-qos", "syscon"; 842 reg = <0x0 0xfe148080 0x0 0x20>; 843 }; 844 845 qos_vicap1: qos@fe148100 { 846 compatible = "rockchip,rk3568-qos", "syscon"; 847 reg = <0x0 0xfe148100 0x0 0x20>; 848 }; 849 850 qos_vpu: qos@fe150000 { 851 compatible = "rockchip,rk3568-qos", "syscon"; 852 reg = <0x0 0xfe150000 0x0 0x20>; 853 }; 854 855 qos_ebc: qos@fe158000 { 856 compatible = "rockchip,rk3568-qos", "syscon"; 857 reg = <0x0 0xfe158000 0x0 0x20>; 858 }; 859 860 qos_iep: qos@fe158100 { 861 compatible = "rockchip,rk3568-qos", "syscon"; 862 reg = <0x0 0xfe158100 0x0 0x20>; 863 }; 864 865 qos_jpeg_dec: qos@fe158180 { 866 compatible = "rockchip,rk3568-qos", "syscon"; 867 reg = <0x0 0xfe158180 0x0 0x20>; 868 }; 869 870 qos_jpeg_enc: qos@fe158200 { 871 compatible = "rockchip,rk3568-qos", "syscon"; 872 reg = <0x0 0xfe158200 0x0 0x20>; 873 }; 874 875 qos_rga_rd: qos@fe158280 { 876 compatible = "rockchip,rk3568-qos", "syscon"; 877 reg = <0x0 0xfe158280 0x0 0x20>; 878 }; 879 880 qos_rga_wr: qos@fe158300 { 881 compatible = "rockchip,rk3568-qos", "syscon"; 882 reg = <0x0 0xfe158300 0x0 0x20>; 883 }; 884 885 qos_npu: qos@fe180000 { 886 compatible = "rockchip,rk3568-qos", "syscon"; 887 reg = <0x0 0xfe180000 0x0 0x20>; 888 }; 889 890 qos_pcie2x1: qos@fe190000 { 891 compatible = "rockchip,rk3568-qos", "syscon"; 892 reg = <0x0 0xfe190000 0x0 0x20>; 893 }; 894 895 qos_sata1: qos@fe190280 { 896 compatible = "rockchip,rk3568-qos", "syscon"; 897 reg = <0x0 0xfe190280 0x0 0x20>; 898 }; 899 900 qos_sata2: qos@fe190300 { 901 compatible = "rockchip,rk3568-qos", "syscon"; 902 reg = <0x0 0xfe190300 0x0 0x20>; 903 }; 904 905 qos_usb3_0: qos@fe190380 { 906 compatible = "rockchip,rk3568-qos", "syscon"; 907 reg = <0x0 0xfe190380 0x0 0x20>; 908 }; 909 910 qos_usb3_1: qos@fe190400 { 911 compatible = "rockchip,rk3568-qos", "syscon"; 912 reg = <0x0 0xfe190400 0x0 0x20>; 913 }; 914 915 qos_rkvdec: qos@fe198000 { 916 compatible = "rockchip,rk3568-qos", "syscon"; 917 reg = <0x0 0xfe198000 0x0 0x20>; 918 }; 919 920 qos_hdcp: qos@fe1a8000 { 921 compatible = "rockchip,rk3568-qos", "syscon"; 922 reg = <0x0 0xfe1a8000 0x0 0x20>; 923 }; 924 925 qos_vop_m0: qos@fe1a8080 { 926 compatible = "rockchip,rk3568-qos", "syscon"; 927 reg = <0x0 0xfe1a8080 0x0 0x20>; 928 }; 929 930 qos_vop_m1: qos@fe1a8100 { 931 compatible = "rockchip,rk3568-qos", "syscon"; 932 reg = <0x0 0xfe1a8100 0x0 0x20>; 933 }; 934 935 dfi: dfi@fe230000 { 936 compatible = "rockchip,rk3568-dfi"; 937 reg = <0x00 0xfe230000 0x00 0x400>; 938 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 939 rockchip,pmu = <&pmugrf>; 940 }; 941 942 pcie2x1: pcie@fe260000 { 943 compatible = "rockchip,rk3568-pcie"; 944 reg = <0x3 0xc0000000 0x0 0x00400000>, 945 <0x0 0xfe260000 0x0 0x00010000>, 946 <0x0 0xf4000000 0x0 0x00100000>; 947 reg-names = "dbi", "apb", "config"; 948 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 953 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 954 bus-range = <0x0 0xf>; 955 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, 956 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, 957 <&cru CLK_PCIE20_AUX_NDFT>; 958 clock-names = "aclk_mst", "aclk_slv", 959 "aclk_dbi", "pclk", "aux"; 960 device_type = "pci"; 961 #interrupt-cells = <1>; 962 interrupt-map-mask = <0 0 0 7>; 963 interrupt-map = <0 0 0 1 &pcie_intc 0>, 964 <0 0 0 2 &pcie_intc 1>, 965 <0 0 0 3 &pcie_intc 2>, 966 <0 0 0 4 &pcie_intc 3>; 967 linux,pci-domain = <0>; 968 num-ib-windows = <6>; 969 num-ob-windows = <2>; 970 max-link-speed = <2>; 971 msi-map = <0x0 &its 0x0 0x1000>; 972 num-lanes = <1>; 973 phys = <&combphy2 PHY_TYPE_PCIE>; 974 phy-names = "pcie-phy"; 975 power-domains = <&power RK3568_PD_PIPE>; 976 ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, 977 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>, 978 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>; 979 resets = <&cru SRST_PCIE20_POWERUP>; 980 reset-names = "pipe"; 981 #address-cells = <3>; 982 #size-cells = <2>; 983 status = "disabled"; 984 985 pcie_intc: legacy-interrupt-controller { 986 #address-cells = <0>; 987 #interrupt-cells = <1>; 988 interrupt-controller; 989 interrupt-parent = <&gic>; 990 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 991 }; 992 }; 993 994 sdmmc0: mmc@fe2b0000 { 995 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 996 reg = <0x0 0xfe2b0000 0x0 0x4000>; 997 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, 999 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; 1000 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1001 fifo-depth = <0x100>; 1002 max-frequency = <150000000>; 1003 resets = <&cru SRST_SDMMC0>; 1004 reset-names = "reset"; 1005 status = "disabled"; 1006 }; 1007 1008 sdmmc1: mmc@fe2c0000 { 1009 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; 1010 reg = <0x0 0xfe2c0000 0x0 0x4000>; 1011 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, 1013 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; 1014 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 1015 fifo-depth = <0x100>; 1016 max-frequency = <150000000>; 1017 resets = <&cru SRST_SDMMC1>; 1018 reset-names = "reset"; 1019 status = "disabled"; 1020 }; 1021 1022 sfc: spi@fe300000 { 1023 compatible = "rockchip,sfc"; 1024 reg = <0x0 0xfe300000 0x0 0x4000>; 1025 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 1027 clock-names = "clk_sfc", "hclk_sfc"; 1028 pinctrl-0 = <&fspi_pins>; 1029 pinctrl-names = "default"; 1030 status = "disabled"; 1031 }; 1032 1033 sdhci: mmc@fe310000 { 1034 compatible = "rockchip,rk3568-dwcmshc"; 1035 reg = <0x0 0xfe310000 0x0 0x10000>; 1036 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1037 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; 1038 assigned-clock-rates = <200000000>, <24000000>; 1039 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 1040 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1041 <&cru TCLK_EMMC>; 1042 clock-names = "core", "bus", "axi", "block", "timer"; 1043 status = "disabled"; 1044 }; 1045 1046 /* 1047 * Testing showed that the HWRNG found in RK3566 produces unacceptably 1048 * low quality of random data, so the HWRNG isn't enabled for all RK356x 1049 * SoC variants despite its presence. 1050 */ 1051 rng: rng@fe388000 { 1052 compatible = "rockchip,rk3568-rng"; 1053 reg = <0x0 0xfe388000 0x0 0x4000>; 1054 clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; 1055 clock-names = "core", "ahb"; 1056 resets = <&cru SRST_TRNG_NS>; 1057 status = "disabled"; 1058 }; 1059 1060 i2s0_8ch: i2s@fe400000 { 1061 compatible = "rockchip,rk3568-i2s-tdm"; 1062 reg = <0x0 0xfe400000 0x0 0x1000>; 1063 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1064 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 1065 assigned-clock-rates = <1188000000>, <1188000000>; 1066 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 1067 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1068 dmas = <&dmac1 0>; 1069 dma-names = "tx"; 1070 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 1071 reset-names = "tx-m", "rx-m"; 1072 rockchip,grf = <&grf>; 1073 #sound-dai-cells = <0>; 1074 status = "disabled"; 1075 }; 1076 1077 i2s1_8ch: i2s@fe410000 { 1078 compatible = "rockchip,rk3568-i2s-tdm"; 1079 reg = <0x0 0xfe410000 0x0 0x1000>; 1080 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1081 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; 1082 assigned-clock-rates = <1188000000>, <1188000000>; 1083 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, 1084 <&cru HCLK_I2S1_8CH>; 1085 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1086 dmas = <&dmac1 3>, <&dmac1 2>; 1087 dma-names = "rx", "tx"; 1088 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 1089 reset-names = "tx-m", "rx-m"; 1090 rockchip,grf = <&grf>; 1091 pinctrl-names = "default"; 1092 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx 1093 &i2s1m0_lrcktx &i2s1m0_lrckrx 1094 &i2s1m0_sdi0 &i2s1m0_sdi1 1095 &i2s1m0_sdi2 &i2s1m0_sdi3 1096 &i2s1m0_sdo0 &i2s1m0_sdo1 1097 &i2s1m0_sdo2 &i2s1m0_sdo3>; 1098 #sound-dai-cells = <0>; 1099 status = "disabled"; 1100 }; 1101 1102 i2s2_2ch: i2s@fe420000 { 1103 compatible = "rockchip,rk3568-i2s-tdm"; 1104 reg = <0x0 0xfe420000 0x0 0x1000>; 1105 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1106 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 1107 assigned-clock-rates = <1188000000>; 1108 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 1109 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1110 dmas = <&dmac1 4>, <&dmac1 5>; 1111 dma-names = "tx", "rx"; 1112 resets = <&cru SRST_M_I2S2_2CH>; 1113 reset-names = "tx-m"; 1114 rockchip,grf = <&grf>; 1115 pinctrl-names = "default"; 1116 pinctrl-0 = <&i2s2m0_sclktx 1117 &i2s2m0_lrcktx 1118 &i2s2m0_sdi 1119 &i2s2m0_sdo>; 1120 #sound-dai-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 1124 i2s3_2ch: i2s@fe430000 { 1125 compatible = "rockchip,rk3568-i2s-tdm"; 1126 reg = <0x0 0xfe430000 0x0 0x1000>; 1127 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1128 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, 1129 <&cru HCLK_I2S3_2CH>; 1130 clock-names = "mclk_tx", "mclk_rx", "hclk"; 1131 dmas = <&dmac1 6>, <&dmac1 7>; 1132 dma-names = "tx", "rx"; 1133 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; 1134 reset-names = "tx-m", "rx-m"; 1135 rockchip,grf = <&grf>; 1136 #sound-dai-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 pdm: pdm@fe440000 { 1141 compatible = "rockchip,rk3568-pdm"; 1142 reg = <0x0 0xfe440000 0x0 0x1000>; 1143 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 1145 clock-names = "pdm_clk", "pdm_hclk"; 1146 dmas = <&dmac1 9>; 1147 dma-names = "rx"; 1148 pinctrl-0 = <&pdmm0_clk 1149 &pdmm0_clk1 1150 &pdmm0_sdi0 1151 &pdmm0_sdi1 1152 &pdmm0_sdi2 1153 &pdmm0_sdi3>; 1154 pinctrl-names = "default"; 1155 resets = <&cru SRST_M_PDM>; 1156 reset-names = "pdm-m"; 1157 #sound-dai-cells = <0>; 1158 status = "disabled"; 1159 }; 1160 1161 spdif: spdif@fe460000 { 1162 compatible = "rockchip,rk3568-spdif"; 1163 reg = <0x0 0xfe460000 0x0 0x1000>; 1164 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1165 clock-names = "mclk", "hclk"; 1166 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; 1167 dmas = <&dmac1 1>; 1168 dma-names = "tx"; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&spdifm0_tx>; 1171 #sound-dai-cells = <0>; 1172 status = "disabled"; 1173 }; 1174 1175 dmac0: dma-controller@fe530000 { 1176 compatible = "arm,pl330", "arm,primecell"; 1177 reg = <0x0 0xfe530000 0x0 0x4000>; 1178 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1180 arm,pl330-periph-burst; 1181 clocks = <&cru ACLK_BUS>; 1182 clock-names = "apb_pclk"; 1183 #dma-cells = <1>; 1184 }; 1185 1186 dmac1: dma-controller@fe550000 { 1187 compatible = "arm,pl330", "arm,primecell"; 1188 reg = <0x0 0xfe550000 0x0 0x4000>; 1189 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1191 arm,pl330-periph-burst; 1192 clocks = <&cru ACLK_BUS>; 1193 clock-names = "apb_pclk"; 1194 #dma-cells = <1>; 1195 }; 1196 1197 i2c1: i2c@fe5a0000 { 1198 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1199 reg = <0x0 0xfe5a0000 0x0 0x1000>; 1200 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1201 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1202 clock-names = "i2c", "pclk"; 1203 pinctrl-0 = <&i2c1_xfer>; 1204 pinctrl-names = "default"; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 status = "disabled"; 1208 }; 1209 1210 i2c2: i2c@fe5b0000 { 1211 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1212 reg = <0x0 0xfe5b0000 0x0 0x1000>; 1213 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1214 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1215 clock-names = "i2c", "pclk"; 1216 pinctrl-0 = <&i2c2m0_xfer>; 1217 pinctrl-names = "default"; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 status = "disabled"; 1221 }; 1222 1223 i2c3: i2c@fe5c0000 { 1224 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1225 reg = <0x0 0xfe5c0000 0x0 0x1000>; 1226 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1227 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1228 clock-names = "i2c", "pclk"; 1229 pinctrl-0 = <&i2c3m0_xfer>; 1230 pinctrl-names = "default"; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 status = "disabled"; 1234 }; 1235 1236 i2c4: i2c@fe5d0000 { 1237 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1238 reg = <0x0 0xfe5d0000 0x0 0x1000>; 1239 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1241 clock-names = "i2c", "pclk"; 1242 pinctrl-0 = <&i2c4m0_xfer>; 1243 pinctrl-names = "default"; 1244 #address-cells = <1>; 1245 #size-cells = <0>; 1246 status = "disabled"; 1247 }; 1248 1249 i2c5: i2c@fe5e0000 { 1250 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; 1251 reg = <0x0 0xfe5e0000 0x0 0x1000>; 1252 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1253 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1254 clock-names = "i2c", "pclk"; 1255 pinctrl-0 = <&i2c5m0_xfer>; 1256 pinctrl-names = "default"; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 status = "disabled"; 1260 }; 1261 1262 wdt: watchdog@fe600000 { 1263 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; 1264 reg = <0x0 0xfe600000 0x0 0x100>; 1265 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 1266 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1267 clock-names = "tclk", "pclk"; 1268 }; 1269 1270 spi0: spi@fe610000 { 1271 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1272 reg = <0x0 0xfe610000 0x0 0x1000>; 1273 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1275 clock-names = "spiclk", "apb_pclk"; 1276 dmas = <&dmac0 20>, <&dmac0 21>; 1277 dma-names = "tx", "rx"; 1278 pinctrl-names = "default"; 1279 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 status = "disabled"; 1283 }; 1284 1285 spi1: spi@fe620000 { 1286 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1287 reg = <0x0 0xfe620000 0x0 0x1000>; 1288 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1290 clock-names = "spiclk", "apb_pclk"; 1291 dmas = <&dmac0 22>, <&dmac0 23>; 1292 dma-names = "tx", "rx"; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; 1295 #address-cells = <1>; 1296 #size-cells = <0>; 1297 status = "disabled"; 1298 }; 1299 1300 spi2: spi@fe630000 { 1301 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1302 reg = <0x0 0xfe630000 0x0 0x1000>; 1303 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1305 clock-names = "spiclk", "apb_pclk"; 1306 dmas = <&dmac0 24>, <&dmac0 25>; 1307 dma-names = "tx", "rx"; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 status = "disabled"; 1313 }; 1314 1315 spi3: spi@fe640000 { 1316 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi"; 1317 reg = <0x0 0xfe640000 0x0 0x1000>; 1318 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1319 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1320 clock-names = "spiclk", "apb_pclk"; 1321 dmas = <&dmac0 26>, <&dmac0 27>; 1322 dma-names = "tx", "rx"; 1323 pinctrl-names = "default"; 1324 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 status = "disabled"; 1328 }; 1329 1330 uart1: serial@fe650000 { 1331 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1332 reg = <0x0 0xfe650000 0x0 0x100>; 1333 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1334 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1335 clock-names = "baudclk", "apb_pclk"; 1336 dmas = <&dmac0 2>, <&dmac0 3>; 1337 pinctrl-0 = <&uart1m0_xfer>; 1338 pinctrl-names = "default"; 1339 reg-io-width = <4>; 1340 reg-shift = <2>; 1341 status = "disabled"; 1342 }; 1343 1344 uart2: serial@fe660000 { 1345 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1346 reg = <0x0 0xfe660000 0x0 0x100>; 1347 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1348 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1349 clock-names = "baudclk", "apb_pclk"; 1350 dmas = <&dmac0 4>, <&dmac0 5>; 1351 pinctrl-0 = <&uart2m0_xfer>; 1352 pinctrl-names = "default"; 1353 reg-io-width = <4>; 1354 reg-shift = <2>; 1355 status = "disabled"; 1356 }; 1357 1358 uart3: serial@fe670000 { 1359 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1360 reg = <0x0 0xfe670000 0x0 0x100>; 1361 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1362 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1363 clock-names = "baudclk", "apb_pclk"; 1364 dmas = <&dmac0 6>, <&dmac0 7>; 1365 pinctrl-0 = <&uart3m0_xfer>; 1366 pinctrl-names = "default"; 1367 reg-io-width = <4>; 1368 reg-shift = <2>; 1369 status = "disabled"; 1370 }; 1371 1372 uart4: serial@fe680000 { 1373 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1374 reg = <0x0 0xfe680000 0x0 0x100>; 1375 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1376 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1377 clock-names = "baudclk", "apb_pclk"; 1378 dmas = <&dmac0 8>, <&dmac0 9>; 1379 pinctrl-0 = <&uart4m0_xfer>; 1380 pinctrl-names = "default"; 1381 reg-io-width = <4>; 1382 reg-shift = <2>; 1383 status = "disabled"; 1384 }; 1385 1386 uart5: serial@fe690000 { 1387 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1388 reg = <0x0 0xfe690000 0x0 0x100>; 1389 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1390 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1391 clock-names = "baudclk", "apb_pclk"; 1392 dmas = <&dmac0 10>, <&dmac0 11>; 1393 pinctrl-0 = <&uart5m0_xfer>; 1394 pinctrl-names = "default"; 1395 reg-io-width = <4>; 1396 reg-shift = <2>; 1397 status = "disabled"; 1398 }; 1399 1400 uart6: serial@fe6a0000 { 1401 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1402 reg = <0x0 0xfe6a0000 0x0 0x100>; 1403 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1404 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1405 clock-names = "baudclk", "apb_pclk"; 1406 dmas = <&dmac0 12>, <&dmac0 13>; 1407 pinctrl-0 = <&uart6m0_xfer>; 1408 pinctrl-names = "default"; 1409 reg-io-width = <4>; 1410 reg-shift = <2>; 1411 status = "disabled"; 1412 }; 1413 1414 uart7: serial@fe6b0000 { 1415 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1416 reg = <0x0 0xfe6b0000 0x0 0x100>; 1417 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1418 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1419 clock-names = "baudclk", "apb_pclk"; 1420 dmas = <&dmac0 14>, <&dmac0 15>; 1421 pinctrl-0 = <&uart7m0_xfer>; 1422 pinctrl-names = "default"; 1423 reg-io-width = <4>; 1424 reg-shift = <2>; 1425 status = "disabled"; 1426 }; 1427 1428 uart8: serial@fe6c0000 { 1429 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1430 reg = <0x0 0xfe6c0000 0x0 0x100>; 1431 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1432 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1433 clock-names = "baudclk", "apb_pclk"; 1434 dmas = <&dmac0 16>, <&dmac0 17>; 1435 pinctrl-0 = <&uart8m0_xfer>; 1436 pinctrl-names = "default"; 1437 reg-io-width = <4>; 1438 reg-shift = <2>; 1439 status = "disabled"; 1440 }; 1441 1442 uart9: serial@fe6d0000 { 1443 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; 1444 reg = <0x0 0xfe6d0000 0x0 0x100>; 1445 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1446 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1447 clock-names = "baudclk", "apb_pclk"; 1448 dmas = <&dmac0 18>, <&dmac0 19>; 1449 pinctrl-0 = <&uart9m0_xfer>; 1450 pinctrl-names = "default"; 1451 reg-io-width = <4>; 1452 reg-shift = <2>; 1453 status = "disabled"; 1454 }; 1455 1456 thermal_zones: thermal-zones { 1457 cpu_thermal: cpu-thermal { 1458 polling-delay-passive = <100>; 1459 polling-delay = <1000>; 1460 1461 thermal-sensors = <&tsadc 0>; 1462 1463 trips { 1464 cpu_alert0: cpu_alert0 { 1465 temperature = <70000>; 1466 hysteresis = <2000>; 1467 type = "passive"; 1468 }; 1469 cpu_alert1: cpu_alert1 { 1470 temperature = <75000>; 1471 hysteresis = <2000>; 1472 type = "passive"; 1473 }; 1474 cpu_crit: cpu_crit { 1475 temperature = <95000>; 1476 hysteresis = <2000>; 1477 type = "critical"; 1478 }; 1479 }; 1480 1481 cooling-maps { 1482 map0 { 1483 trip = <&cpu_alert0>; 1484 cooling-device = 1485 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1486 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1487 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1488 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1489 }; 1490 }; 1491 }; 1492 1493 gpu_thermal: gpu-thermal { 1494 polling-delay-passive = <20>; /* milliseconds */ 1495 polling-delay = <1000>; /* milliseconds */ 1496 1497 thermal-sensors = <&tsadc 1>; 1498 1499 trips { 1500 gpu_threshold: gpu-threshold { 1501 temperature = <70000>; 1502 hysteresis = <2000>; 1503 type = "passive"; 1504 }; 1505 gpu_target: gpu-target { 1506 temperature = <75000>; 1507 hysteresis = <2000>; 1508 type = "passive"; 1509 }; 1510 gpu_crit: gpu-crit { 1511 temperature = <95000>; 1512 hysteresis = <2000>; 1513 type = "critical"; 1514 }; 1515 }; 1516 1517 cooling-maps { 1518 map0 { 1519 trip = <&gpu_target>; 1520 cooling-device = 1521 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1522 }; 1523 }; 1524 }; 1525 }; 1526 1527 tsadc: tsadc@fe710000 { 1528 compatible = "rockchip,rk3568-tsadc"; 1529 reg = <0x0 0xfe710000 0x0 0x100>; 1530 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 1531 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; 1532 assigned-clock-rates = <17000000>, <700000>; 1533 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 1534 clock-names = "tsadc", "apb_pclk"; 1535 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, 1536 <&cru SRST_TSADCPHY>; 1537 rockchip,grf = <&grf>; 1538 rockchip,hw-tshut-temp = <95000>; 1539 pinctrl-names = "default", "sleep"; 1540 pinctrl-0 = <&tsadc_shutorg>; 1541 pinctrl-1 = <&tsadc_pin>; 1542 #thermal-sensor-cells = <1>; 1543 status = "disabled"; 1544 }; 1545 1546 saradc: saradc@fe720000 { 1547 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; 1548 reg = <0x0 0xfe720000 0x0 0x100>; 1549 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1550 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1551 clock-names = "saradc", "apb_pclk"; 1552 resets = <&cru SRST_P_SARADC>; 1553 reset-names = "saradc-apb"; 1554 #io-channel-cells = <1>; 1555 status = "disabled"; 1556 }; 1557 1558 pwm4: pwm@fe6e0000 { 1559 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1560 reg = <0x0 0xfe6e0000 0x0 0x10>; 1561 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1562 clock-names = "pwm", "pclk"; 1563 pinctrl-0 = <&pwm4_pins>; 1564 pinctrl-names = "default"; 1565 #pwm-cells = <3>; 1566 status = "disabled"; 1567 }; 1568 1569 pwm5: pwm@fe6e0010 { 1570 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1571 reg = <0x0 0xfe6e0010 0x0 0x10>; 1572 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1573 clock-names = "pwm", "pclk"; 1574 pinctrl-0 = <&pwm5_pins>; 1575 pinctrl-names = "default"; 1576 #pwm-cells = <3>; 1577 status = "disabled"; 1578 }; 1579 1580 pwm6: pwm@fe6e0020 { 1581 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1582 reg = <0x0 0xfe6e0020 0x0 0x10>; 1583 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1584 clock-names = "pwm", "pclk"; 1585 pinctrl-0 = <&pwm6_pins>; 1586 pinctrl-names = "default"; 1587 #pwm-cells = <3>; 1588 status = "disabled"; 1589 }; 1590 1591 pwm7: pwm@fe6e0030 { 1592 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1593 reg = <0x0 0xfe6e0030 0x0 0x10>; 1594 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1595 clock-names = "pwm", "pclk"; 1596 pinctrl-0 = <&pwm7_pins>; 1597 pinctrl-names = "default"; 1598 #pwm-cells = <3>; 1599 status = "disabled"; 1600 }; 1601 1602 pwm8: pwm@fe6f0000 { 1603 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1604 reg = <0x0 0xfe6f0000 0x0 0x10>; 1605 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1606 clock-names = "pwm", "pclk"; 1607 pinctrl-0 = <&pwm8m0_pins>; 1608 pinctrl-names = "default"; 1609 #pwm-cells = <3>; 1610 status = "disabled"; 1611 }; 1612 1613 pwm9: pwm@fe6f0010 { 1614 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1615 reg = <0x0 0xfe6f0010 0x0 0x10>; 1616 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1617 clock-names = "pwm", "pclk"; 1618 pinctrl-0 = <&pwm9m0_pins>; 1619 pinctrl-names = "default"; 1620 #pwm-cells = <3>; 1621 status = "disabled"; 1622 }; 1623 1624 pwm10: pwm@fe6f0020 { 1625 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1626 reg = <0x0 0xfe6f0020 0x0 0x10>; 1627 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1628 clock-names = "pwm", "pclk"; 1629 pinctrl-0 = <&pwm10m0_pins>; 1630 pinctrl-names = "default"; 1631 #pwm-cells = <3>; 1632 status = "disabled"; 1633 }; 1634 1635 pwm11: pwm@fe6f0030 { 1636 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1637 reg = <0x0 0xfe6f0030 0x0 0x10>; 1638 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 1639 clock-names = "pwm", "pclk"; 1640 pinctrl-0 = <&pwm11m0_pins>; 1641 pinctrl-names = "default"; 1642 #pwm-cells = <3>; 1643 status = "disabled"; 1644 }; 1645 1646 pwm12: pwm@fe700000 { 1647 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1648 reg = <0x0 0xfe700000 0x0 0x10>; 1649 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1650 clock-names = "pwm", "pclk"; 1651 pinctrl-0 = <&pwm12m0_pins>; 1652 pinctrl-names = "default"; 1653 #pwm-cells = <3>; 1654 status = "disabled"; 1655 }; 1656 1657 pwm13: pwm@fe700010 { 1658 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1659 reg = <0x0 0xfe700010 0x0 0x10>; 1660 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1661 clock-names = "pwm", "pclk"; 1662 pinctrl-0 = <&pwm13m0_pins>; 1663 pinctrl-names = "default"; 1664 #pwm-cells = <3>; 1665 status = "disabled"; 1666 }; 1667 1668 pwm14: pwm@fe700020 { 1669 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1670 reg = <0x0 0xfe700020 0x0 0x10>; 1671 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1672 clock-names = "pwm", "pclk"; 1673 pinctrl-0 = <&pwm14m0_pins>; 1674 pinctrl-names = "default"; 1675 #pwm-cells = <3>; 1676 status = "disabled"; 1677 }; 1678 1679 pwm15: pwm@fe700030 { 1680 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; 1681 reg = <0x0 0xfe700030 0x0 0x10>; 1682 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 1683 clock-names = "pwm", "pclk"; 1684 pinctrl-0 = <&pwm15m0_pins>; 1685 pinctrl-names = "default"; 1686 #pwm-cells = <3>; 1687 status = "disabled"; 1688 }; 1689 1690 combphy1: phy@fe830000 { 1691 compatible = "rockchip,rk3568-naneng-combphy"; 1692 reg = <0x0 0xfe830000 0x0 0x100>; 1693 clocks = <&pmucru CLK_PCIEPHY1_REF>, 1694 <&cru PCLK_PIPEPHY1>, 1695 <&cru PCLK_PIPE>; 1696 clock-names = "ref", "apb", "pipe"; 1697 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; 1698 assigned-clock-rates = <100000000>; 1699 resets = <&cru SRST_PIPEPHY1>; 1700 reset-names = "phy"; 1701 rockchip,pipe-grf = <&pipegrf>; 1702 rockchip,pipe-phy-grf = <&pipe_phy_grf1>; 1703 #phy-cells = <1>; 1704 status = "disabled"; 1705 }; 1706 1707 combphy2: phy@fe840000 { 1708 compatible = "rockchip,rk3568-naneng-combphy"; 1709 reg = <0x0 0xfe840000 0x0 0x100>; 1710 clocks = <&pmucru CLK_PCIEPHY2_REF>, 1711 <&cru PCLK_PIPEPHY2>, 1712 <&cru PCLK_PIPE>; 1713 clock-names = "ref", "apb", "pipe"; 1714 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; 1715 assigned-clock-rates = <100000000>; 1716 resets = <&cru SRST_PIPEPHY2>; 1717 reset-names = "phy"; 1718 rockchip,pipe-grf = <&pipegrf>; 1719 rockchip,pipe-phy-grf = <&pipe_phy_grf2>; 1720 #phy-cells = <1>; 1721 status = "disabled"; 1722 }; 1723 1724 csi_dphy: phy@fe870000 { 1725 compatible = "rockchip,rk3568-csi-dphy"; 1726 reg = <0x0 0xfe870000 0x0 0x10000>; 1727 clocks = <&cru PCLK_MIPICSIPHY>; 1728 clock-names = "pclk"; 1729 #phy-cells = <0>; 1730 resets = <&cru SRST_P_MIPICSIPHY>; 1731 reset-names = "apb"; 1732 rockchip,grf = <&grf>; 1733 status = "disabled"; 1734 }; 1735 1736 dsi_dphy0: mipi-dphy@fe850000 { 1737 compatible = "rockchip,rk3568-dsi-dphy"; 1738 reg = <0x0 0xfe850000 0x0 0x10000>; 1739 clock-names = "ref", "pclk"; 1740 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>; 1741 #phy-cells = <0>; 1742 power-domains = <&power RK3568_PD_VO>; 1743 reset-names = "apb"; 1744 resets = <&cru SRST_P_MIPIDSIPHY0>; 1745 status = "disabled"; 1746 }; 1747 1748 dsi_dphy1: mipi-dphy@fe860000 { 1749 compatible = "rockchip,rk3568-dsi-dphy"; 1750 reg = <0x0 0xfe860000 0x0 0x10000>; 1751 clock-names = "ref", "pclk"; 1752 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>; 1753 #phy-cells = <0>; 1754 power-domains = <&power RK3568_PD_VO>; 1755 reset-names = "apb"; 1756 resets = <&cru SRST_P_MIPIDSIPHY1>; 1757 status = "disabled"; 1758 }; 1759 1760 usb2phy0: usb2phy@fe8a0000 { 1761 compatible = "rockchip,rk3568-usb2phy"; 1762 reg = <0x0 0xfe8a0000 0x0 0x10000>; 1763 clocks = <&pmucru CLK_USBPHY0_REF>; 1764 clock-names = "phyclk"; 1765 clock-output-names = "clk_usbphy0_480m"; 1766 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1767 rockchip,usbgrf = <&usb2phy0_grf>; 1768 #clock-cells = <0>; 1769 status = "disabled"; 1770 1771 usb2phy0_host: host-port { 1772 #phy-cells = <0>; 1773 status = "disabled"; 1774 }; 1775 1776 usb2phy0_otg: otg-port { 1777 #phy-cells = <0>; 1778 status = "disabled"; 1779 }; 1780 }; 1781 1782 usb2phy1: usb2phy@fe8b0000 { 1783 compatible = "rockchip,rk3568-usb2phy"; 1784 reg = <0x0 0xfe8b0000 0x0 0x10000>; 1785 clocks = <&pmucru CLK_USBPHY1_REF>; 1786 clock-names = "phyclk"; 1787 clock-output-names = "clk_usbphy1_480m"; 1788 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1789 rockchip,usbgrf = <&usb2phy1_grf>; 1790 #clock-cells = <0>; 1791 status = "disabled"; 1792 1793 usb2phy1_host: host-port { 1794 #phy-cells = <0>; 1795 status = "disabled"; 1796 }; 1797 1798 usb2phy1_otg: otg-port { 1799 #phy-cells = <0>; 1800 status = "disabled"; 1801 }; 1802 }; 1803 1804 pinctrl: pinctrl { 1805 compatible = "rockchip,rk3568-pinctrl"; 1806 rockchip,grf = <&grf>; 1807 rockchip,pmu = <&pmugrf>; 1808 #address-cells = <2>; 1809 #size-cells = <2>; 1810 ranges; 1811 1812 gpio0: gpio@fdd60000 { 1813 compatible = "rockchip,gpio-bank"; 1814 reg = <0x0 0xfdd60000 0x0 0x100>; 1815 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1816 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 1817 gpio-controller; 1818 gpio-ranges = <&pinctrl 0 0 32>; 1819 #gpio-cells = <2>; 1820 interrupt-controller; 1821 #interrupt-cells = <2>; 1822 }; 1823 1824 gpio1: gpio@fe740000 { 1825 compatible = "rockchip,gpio-bank"; 1826 reg = <0x0 0xfe740000 0x0 0x100>; 1827 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1828 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1829 gpio-controller; 1830 gpio-ranges = <&pinctrl 0 32 32>; 1831 #gpio-cells = <2>; 1832 interrupt-controller; 1833 #interrupt-cells = <2>; 1834 }; 1835 1836 gpio2: gpio@fe750000 { 1837 compatible = "rockchip,gpio-bank"; 1838 reg = <0x0 0xfe750000 0x0 0x100>; 1839 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1840 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1841 gpio-controller; 1842 gpio-ranges = <&pinctrl 0 64 32>; 1843 #gpio-cells = <2>; 1844 interrupt-controller; 1845 #interrupt-cells = <2>; 1846 }; 1847 1848 gpio3: gpio@fe760000 { 1849 compatible = "rockchip,gpio-bank"; 1850 reg = <0x0 0xfe760000 0x0 0x100>; 1851 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1852 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1853 gpio-controller; 1854 gpio-ranges = <&pinctrl 0 96 32>; 1855 #gpio-cells = <2>; 1856 interrupt-controller; 1857 #interrupt-cells = <2>; 1858 }; 1859 1860 gpio4: gpio@fe770000 { 1861 compatible = "rockchip,gpio-bank"; 1862 reg = <0x0 0xfe770000 0x0 0x100>; 1863 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1864 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1865 gpio-controller; 1866 gpio-ranges = <&pinctrl 0 128 32>; 1867 #gpio-cells = <2>; 1868 interrupt-controller; 1869 #interrupt-cells = <2>; 1870 }; 1871 }; 1872}; 1873 1874#include "rk3568-pinctrl.dtsi" 1875