1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rockchip,rk3528-cru.h> 12#include <dt-bindings/reset/rockchip,rk3528-cru.h> 13 14/ { 15 compatible = "rockchip,rk3528"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 gpio4 = &gpio4; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu-map { 34 cluster0 { 35 core0 { 36 cpu = <&cpu0>; 37 }; 38 core1 { 39 cpu = <&cpu1>; 40 }; 41 core2 { 42 cpu = <&cpu2>; 43 }; 44 core3 { 45 cpu = <&cpu3>; 46 }; 47 }; 48 }; 49 50 cpu0: cpu@0 { 51 compatible = "arm,cortex-a53"; 52 reg = <0x0>; 53 device_type = "cpu"; 54 enable-method = "psci"; 55 clocks = <&scmi_clk SCMI_CLK_CPU>; 56 }; 57 58 cpu1: cpu@1 { 59 compatible = "arm,cortex-a53"; 60 reg = <0x1>; 61 device_type = "cpu"; 62 enable-method = "psci"; 63 clocks = <&scmi_clk SCMI_CLK_CPU>; 64 }; 65 66 cpu2: cpu@2 { 67 compatible = "arm,cortex-a53"; 68 reg = <0x2>; 69 device_type = "cpu"; 70 enable-method = "psci"; 71 clocks = <&scmi_clk SCMI_CLK_CPU>; 72 }; 73 74 cpu3: cpu@3 { 75 compatible = "arm,cortex-a53"; 76 reg = <0x3>; 77 device_type = "cpu"; 78 enable-method = "psci"; 79 clocks = <&scmi_clk SCMI_CLK_CPU>; 80 }; 81 }; 82 83 firmware { 84 scmi: scmi { 85 compatible = "arm,scmi-smc"; 86 arm,smc-id = <0x82000010>; 87 shmem = <&scmi_shmem>; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 91 scmi_clk: protocol@14 { 92 reg = <0x14>; 93 #clock-cells = <1>; 94 }; 95 }; 96 }; 97 98 pinctrl: pinctrl { 99 compatible = "rockchip,rk3528-pinctrl"; 100 rockchip,grf = <&ioc_grf>; 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges; 104 105 gpio0: gpio@ff610000 { 106 compatible = "rockchip,gpio-bank"; 107 reg = <0x0 0xff610000 0x0 0x200>; 108 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 109 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 110 gpio-controller; 111 #gpio-cells = <2>; 112 gpio-ranges = <&pinctrl 0 0 32>; 113 interrupt-controller; 114 #interrupt-cells = <2>; 115 }; 116 117 gpio1: gpio@ffaf0000 { 118 compatible = "rockchip,gpio-bank"; 119 reg = <0x0 0xffaf0000 0x0 0x200>; 120 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 121 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 122 gpio-controller; 123 #gpio-cells = <2>; 124 gpio-ranges = <&pinctrl 0 32 32>; 125 interrupt-controller; 126 #interrupt-cells = <2>; 127 }; 128 129 gpio2: gpio@ffb00000 { 130 compatible = "rockchip,gpio-bank"; 131 reg = <0x0 0xffb00000 0x0 0x200>; 132 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 133 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 134 gpio-controller; 135 #gpio-cells = <2>; 136 gpio-ranges = <&pinctrl 0 64 32>; 137 interrupt-controller; 138 #interrupt-cells = <2>; 139 }; 140 141 gpio3: gpio@ffb10000 { 142 compatible = "rockchip,gpio-bank"; 143 reg = <0x0 0xffb10000 0x0 0x200>; 144 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 145 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 146 gpio-controller; 147 #gpio-cells = <2>; 148 gpio-ranges = <&pinctrl 0 96 32>; 149 interrupt-controller; 150 #interrupt-cells = <2>; 151 }; 152 153 gpio4: gpio@ffb20000 { 154 compatible = "rockchip,gpio-bank"; 155 reg = <0x0 0xffb20000 0x0 0x200>; 156 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 157 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 158 gpio-controller; 159 #gpio-cells = <2>; 160 gpio-ranges = <&pinctrl 0 128 32>; 161 interrupt-controller; 162 #interrupt-cells = <2>; 163 }; 164 }; 165 166 psci { 167 compatible = "arm,psci-1.0", "arm,psci-0.2"; 168 method = "smc"; 169 }; 170 171 reserved-memory { 172 #address-cells = <2>; 173 #size-cells = <2>; 174 ranges; 175 176 scmi_shmem: shmem@10f000 { 177 compatible = "arm,scmi-shmem"; 178 reg = <0x0 0x0010f000 0x0 0x100>; 179 no-map; 180 }; 181 }; 182 183 timer { 184 compatible = "arm,armv8-timer"; 185 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 186 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 187 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 188 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 189 }; 190 191 xin24m: clock-xin24m { 192 compatible = "fixed-clock"; 193 clock-frequency = <24000000>; 194 clock-output-names = "xin24m"; 195 #clock-cells = <0>; 196 }; 197 198 gmac0_clk: clock-gmac50m { 199 compatible = "fixed-clock"; 200 clock-frequency = <50000000>; 201 clock-output-names = "gmac0"; 202 #clock-cells = <0>; 203 }; 204 205 soc { 206 compatible = "simple-bus"; 207 ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; 208 #address-cells = <2>; 209 #size-cells = <2>; 210 211 gic: interrupt-controller@fed01000 { 212 compatible = "arm,gic-400"; 213 reg = <0x0 0xfed01000 0 0x1000>, 214 <0x0 0xfed02000 0 0x2000>, 215 <0x0 0xfed04000 0 0x2000>, 216 <0x0 0xfed06000 0 0x2000>; 217 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 218 IRQ_TYPE_LEVEL_LOW)>; 219 interrupt-controller; 220 #address-cells = <0>; 221 #interrupt-cells = <3>; 222 }; 223 224 qos_crypto_a: qos@ff200000 { 225 compatible = "rockchip,rk3528-qos", "syscon"; 226 reg = <0x0 0xff200000 0x0 0x20>; 227 }; 228 229 qos_crypto_p: qos@ff200080 { 230 compatible = "rockchip,rk3528-qos", "syscon"; 231 reg = <0x0 0xff200080 0x0 0x20>; 232 }; 233 234 qos_dcf: qos@ff200100 { 235 compatible = "rockchip,rk3528-qos", "syscon"; 236 reg = <0x0 0xff200100 0x0 0x20>; 237 }; 238 239 qos_dft2apb: qos@ff200200 { 240 compatible = "rockchip,rk3528-qos", "syscon"; 241 reg = <0x0 0xff200200 0x0 0x20>; 242 }; 243 244 qos_dma2ddr: qos@ff200280 { 245 compatible = "rockchip,rk3528-qos", "syscon"; 246 reg = <0x0 0xff200280 0x0 0x20>; 247 }; 248 249 qos_dmac: qos@ff200300 { 250 compatible = "rockchip,rk3528-qos", "syscon"; 251 reg = <0x0 0xff200300 0x0 0x20>; 252 }; 253 254 qos_keyreader: qos@ff200380 { 255 compatible = "rockchip,rk3528-qos", "syscon"; 256 reg = <0x0 0xff200380 0x0 0x20>; 257 }; 258 259 qos_cpu: qos@ff210000 { 260 compatible = "rockchip,rk3528-qos", "syscon"; 261 reg = <0x0 0xff210000 0x0 0x20>; 262 }; 263 264 qos_debug: qos@ff210080 { 265 compatible = "rockchip,rk3528-qos", "syscon"; 266 reg = <0x0 0xff210080 0x0 0x20>; 267 }; 268 269 qos_gpu_m0: qos@ff220000 { 270 compatible = "rockchip,rk3528-qos", "syscon"; 271 reg = <0x0 0xff220000 0x0 0x20>; 272 }; 273 274 qos_gpu_m1: qos@ff220080 { 275 compatible = "rockchip,rk3528-qos", "syscon"; 276 reg = <0x0 0xff220080 0x0 0x20>; 277 }; 278 279 qos_pmu_mcu: qos@ff240000 { 280 compatible = "rockchip,rk3528-qos", "syscon"; 281 reg = <0x0 0xff240000 0x0 0x20>; 282 }; 283 284 qos_rkvdec: qos@ff250000 { 285 compatible = "rockchip,rk3528-qos", "syscon"; 286 reg = <0x0 0xff250000 0x0 0x20>; 287 }; 288 289 qos_rkvenc: qos@ff260000 { 290 compatible = "rockchip,rk3528-qos", "syscon"; 291 reg = <0x0 0xff260000 0x0 0x20>; 292 }; 293 294 qos_gmac0: qos@ff270000 { 295 compatible = "rockchip,rk3528-qos", "syscon"; 296 reg = <0x0 0xff270000 0x0 0x20>; 297 }; 298 299 qos_hdcp: qos@ff270080 { 300 compatible = "rockchip,rk3528-qos", "syscon"; 301 reg = <0x0 0xff270080 0x0 0x20>; 302 }; 303 304 qos_jpegdec: qos@ff270100 { 305 compatible = "rockchip,rk3528-qos", "syscon"; 306 reg = <0x0 0xff270100 0x0 0x20>; 307 }; 308 309 qos_rga2_m0ro: qos@ff270200 { 310 compatible = "rockchip,rk3528-qos", "syscon"; 311 reg = <0x0 0xff270200 0x0 0x20>; 312 }; 313 314 qos_rga2_m0wo: qos@ff270280 { 315 compatible = "rockchip,rk3528-qos", "syscon"; 316 reg = <0x0 0xff270280 0x0 0x20>; 317 }; 318 319 qos_sdmmc0: qos@ff270300 { 320 compatible = "rockchip,rk3528-qos", "syscon"; 321 reg = <0x0 0xff270300 0x0 0x20>; 322 }; 323 324 qos_usb2host: qos@ff270380 { 325 compatible = "rockchip,rk3528-qos", "syscon"; 326 reg = <0x0 0xff270380 0x0 0x20>; 327 }; 328 329 qos_vdpp: qos@ff270480 { 330 compatible = "rockchip,rk3528-qos", "syscon"; 331 reg = <0x0 0xff270480 0x0 0x20>; 332 }; 333 334 qos_vop: qos@ff270500 { 335 compatible = "rockchip,rk3528-qos", "syscon"; 336 reg = <0x0 0xff270500 0x0 0x20>; 337 }; 338 339 qos_emmc: qos@ff280000 { 340 compatible = "rockchip,rk3528-qos", "syscon"; 341 reg = <0x0 0xff280000 0x0 0x20>; 342 }; 343 344 qos_fspi: qos@ff280080 { 345 compatible = "rockchip,rk3528-qos", "syscon"; 346 reg = <0x0 0xff280080 0x0 0x20>; 347 }; 348 349 qos_gmac1: qos@ff280100 { 350 compatible = "rockchip,rk3528-qos", "syscon"; 351 reg = <0x0 0xff280100 0x0 0x20>; 352 }; 353 354 qos_pcie: qos@ff280180 { 355 compatible = "rockchip,rk3528-qos", "syscon"; 356 reg = <0x0 0xff280180 0x0 0x20>; 357 }; 358 359 qos_sdio0: qos@ff280200 { 360 compatible = "rockchip,rk3528-qos", "syscon"; 361 reg = <0x0 0xff280200 0x0 0x20>; 362 }; 363 364 qos_sdio1: qos@ff280280 { 365 compatible = "rockchip,rk3528-qos", "syscon"; 366 reg = <0x0 0xff280280 0x0 0x20>; 367 }; 368 369 qos_tsp: qos@ff280300 { 370 compatible = "rockchip,rk3528-qos", "syscon"; 371 reg = <0x0 0xff280300 0x0 0x20>; 372 }; 373 374 qos_usb3otg: qos@ff280380 { 375 compatible = "rockchip,rk3528-qos", "syscon"; 376 reg = <0x0 0xff280380 0x0 0x20>; 377 }; 378 379 qos_vpu: qos@ff280400 { 380 compatible = "rockchip,rk3528-qos", "syscon"; 381 reg = <0x0 0xff280400 0x0 0x20>; 382 }; 383 384 vpu_grf: syscon@ff340000 { 385 compatible = "rockchip,rk3528-vpu-grf", "syscon"; 386 reg = <0x0 0xff340000 0x0 0x8000>; 387 }; 388 389 vo_grf: syscon@ff360000 { 390 compatible = "rockchip,rk3528-vo-grf", "syscon"; 391 reg = <0x0 0xff360000 0x0 0x10000>; 392 }; 393 394 cru: clock-controller@ff4a0000 { 395 compatible = "rockchip,rk3528-cru"; 396 reg = <0x0 0xff4a0000 0x0 0x30000>; 397 assigned-clocks = 398 <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>, 399 <&cru PLL_PPLL>, <&cru PLL_CPLL>, 400 <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>, 401 <&cru CLK_MATRIX_500M_SRC>, 402 <&cru CLK_MATRIX_50M_SRC>, 403 <&cru CLK_MATRIX_100M_SRC>, 404 <&cru CLK_MATRIX_150M_SRC>, 405 <&cru CLK_MATRIX_200M_SRC>, 406 <&cru CLK_MATRIX_300M_SRC>, 407 <&cru CLK_MATRIX_339M_SRC>, 408 <&cru CLK_MATRIX_400M_SRC>, 409 <&cru CLK_MATRIX_600M_SRC>, 410 <&cru CLK_PPLL_50M_MATRIX>, 411 <&cru CLK_PPLL_100M_MATRIX>, 412 <&cru CLK_PPLL_125M_MATRIX>, 413 <&cru ACLK_BUS_VOPGL_ROOT>; 414 assigned-clock-rates = 415 <32768>, <1188000000>, 416 <1000000000>, <996000000>, 417 <408000000>, <250000000>, 418 <500000000>, 419 <50000000>, 420 <100000000>, 421 <150000000>, 422 <200000000>, 423 <300000000>, 424 <340000000>, 425 <400000000>, 426 <600000000>, 427 <50000000>, 428 <100000000>, 429 <125000000>, 430 <500000000>; 431 clocks = <&xin24m>, <&gmac0_clk>; 432 clock-names = "xin24m", "gmac0"; 433 #clock-cells = <1>; 434 #reset-cells = <1>; 435 }; 436 437 ioc_grf: syscon@ff540000 { 438 compatible = "rockchip,rk3528-ioc-grf", "syscon"; 439 reg = <0x0 0xff540000 0x0 0x40000>; 440 }; 441 442 uart0: serial@ff9f0000 { 443 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 444 reg = <0x0 0xff9f0000 0x0 0x100>; 445 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 446 clock-names = "baudclk", "apb_pclk"; 447 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 448 dmas = <&dmac 8>, <&dmac 9>; 449 reg-io-width = <4>; 450 reg-shift = <2>; 451 status = "disabled"; 452 }; 453 454 uart1: serial@ff9f8000 { 455 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 456 reg = <0x0 0xff9f8000 0x0 0x100>; 457 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 458 clock-names = "baudclk", "apb_pclk"; 459 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 460 dmas = <&dmac 10>, <&dmac 11>; 461 reg-io-width = <4>; 462 reg-shift = <2>; 463 status = "disabled"; 464 }; 465 466 uart2: serial@ffa00000 { 467 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 468 reg = <0x0 0xffa00000 0x0 0x100>; 469 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 470 clock-names = "baudclk", "apb_pclk"; 471 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 472 dmas = <&dmac 12>, <&dmac 13>; 473 reg-io-width = <4>; 474 reg-shift = <2>; 475 status = "disabled"; 476 }; 477 478 uart3: serial@ffa08000 { 479 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 480 reg = <0x0 0xffa08000 0x0 0x100>; 481 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 482 clock-names = "baudclk", "apb_pclk"; 483 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 484 dmas = <&dmac 14>, <&dmac 15>; 485 reg-io-width = <4>; 486 reg-shift = <2>; 487 status = "disabled"; 488 }; 489 490 uart4: serial@ffa10000 { 491 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 492 reg = <0x0 0xffa10000 0x0 0x100>; 493 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 494 clock-names = "baudclk", "apb_pclk"; 495 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 496 dmas = <&dmac 16>, <&dmac 17>; 497 reg-io-width = <4>; 498 reg-shift = <2>; 499 status = "disabled"; 500 }; 501 502 uart5: serial@ffa18000 { 503 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 504 reg = <0x0 0xffa18000 0x0 0x100>; 505 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 506 clock-names = "baudclk", "apb_pclk"; 507 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 508 dmas = <&dmac 18>, <&dmac 19>; 509 reg-io-width = <4>; 510 reg-shift = <2>; 511 status = "disabled"; 512 }; 513 514 uart6: serial@ffa20000 { 515 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 516 reg = <0x0 0xffa20000 0x0 0x100>; 517 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 518 clock-names = "baudclk", "apb_pclk"; 519 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 520 dmas = <&dmac 20>, <&dmac 21>; 521 reg-io-width = <4>; 522 reg-shift = <2>; 523 status = "disabled"; 524 }; 525 526 uart7: serial@ffa28000 { 527 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 528 reg = <0x0 0xffa28000 0x0 0x100>; 529 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 530 clock-names = "baudclk", "apb_pclk"; 531 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 532 dmas = <&dmac 22>, <&dmac 23>; 533 reg-io-width = <4>; 534 reg-shift = <2>; 535 status = "disabled"; 536 }; 537 538 i2c0: i2c@ffa50000 { 539 compatible = "rockchip,rk3528-i2c", 540 "rockchip,rk3399-i2c"; 541 reg = <0x0 0xffa50000 0x0 0x1000>; 542 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 543 clock-names = "i2c", "pclk"; 544 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 status = "disabled"; 548 }; 549 550 i2c1: i2c@ffa58000 { 551 compatible = "rockchip,rk3528-i2c", 552 "rockchip,rk3399-i2c"; 553 reg = <0x0 0xffa58000 0x0 0x1000>; 554 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 555 clock-names = "i2c", "pclk"; 556 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 status = "disabled"; 560 }; 561 562 i2c2: i2c@ffa60000 { 563 compatible = "rockchip,rk3528-i2c", 564 "rockchip,rk3399-i2c"; 565 reg = <0x0 0xffa60000 0x0 0x1000>; 566 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 567 clock-names = "i2c", "pclk"; 568 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&i2c2m1_xfer>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 status = "disabled"; 574 }; 575 576 i2c3: i2c@ffa68000 { 577 compatible = "rockchip,rk3528-i2c", 578 "rockchip,rk3399-i2c"; 579 reg = <0x0 0xffa68000 0x0 0x1000>; 580 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 581 clock-names = "i2c", "pclk"; 582 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 status = "disabled"; 586 }; 587 588 i2c4: i2c@ffa70000 { 589 compatible = "rockchip,rk3528-i2c", 590 "rockchip,rk3399-i2c"; 591 reg = <0x0 0xffa70000 0x0 0x1000>; 592 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 593 clock-names = "i2c", "pclk"; 594 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&i2c4_xfer>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 }; 601 602 i2c5: i2c@ffa78000 { 603 compatible = "rockchip,rk3528-i2c", 604 "rockchip,rk3399-i2c"; 605 reg = <0x0 0xffa78000 0x0 0x1000>; 606 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 607 clock-names = "i2c", "pclk"; 608 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 status = "disabled"; 612 }; 613 614 i2c6: i2c@ffa80000 { 615 compatible = "rockchip,rk3528-i2c", 616 "rockchip,rk3399-i2c"; 617 reg = <0x0 0xffa80000 0x0 0x1000>; 618 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 619 clock-names = "i2c", "pclk"; 620 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 621 #address-cells = <1>; 622 #size-cells = <0>; 623 status = "disabled"; 624 }; 625 626 i2c7: i2c@ffa88000 { 627 compatible = "rockchip,rk3528-i2c", 628 "rockchip,rk3399-i2c"; 629 reg = <0x0 0xffa88000 0x0 0x1000>; 630 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 631 clock-names = "i2c", "pclk"; 632 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 633 pinctrl-names = "default"; 634 pinctrl-0 = <&i2c7_xfer>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 status = "disabled"; 638 }; 639 640 pwm0: pwm@ffa90000 { 641 compatible = "rockchip,rk3528-pwm", 642 "rockchip,rk3328-pwm"; 643 reg = <0x0 0xffa90000 0x0 0x10>; 644 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 645 clock-names = "pwm", "pclk"; 646 #pwm-cells = <3>; 647 status = "disabled"; 648 }; 649 650 pwm1: pwm@ffa90010 { 651 compatible = "rockchip,rk3528-pwm", 652 "rockchip,rk3328-pwm"; 653 reg = <0x0 0xffa90010 0x0 0x10>; 654 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 655 clock-names = "pwm", "pclk"; 656 #pwm-cells = <3>; 657 status = "disabled"; 658 }; 659 660 pwm2: pwm@ffa90020 { 661 compatible = "rockchip,rk3528-pwm", 662 "rockchip,rk3328-pwm"; 663 reg = <0x0 0xffa90020 0x0 0x10>; 664 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 665 clock-names = "pwm", "pclk"; 666 #pwm-cells = <3>; 667 status = "disabled"; 668 }; 669 670 pwm3: pwm@ffa90030 { 671 compatible = "rockchip,rk3528-pwm", 672 "rockchip,rk3328-pwm"; 673 reg = <0x0 0xffa90030 0x0 0x10>; 674 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 675 clock-names = "pwm", "pclk"; 676 #pwm-cells = <3>; 677 status = "disabled"; 678 }; 679 680 pwm4: pwm@ffa98000 { 681 compatible = "rockchip,rk3528-pwm", 682 "rockchip,rk3328-pwm"; 683 reg = <0x0 0xffa98000 0x0 0x10>; 684 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 685 clock-names = "pwm", "pclk"; 686 #pwm-cells = <3>; 687 status = "disabled"; 688 }; 689 690 pwm5: pwm@ffa98010 { 691 compatible = "rockchip,rk3528-pwm", 692 "rockchip,rk3328-pwm"; 693 reg = <0x0 0xffa98010 0x0 0x10>; 694 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 695 clock-names = "pwm", "pclk"; 696 #pwm-cells = <3>; 697 status = "disabled"; 698 }; 699 700 pwm6: pwm@ffa98020 { 701 compatible = "rockchip,rk3528-pwm", 702 "rockchip,rk3328-pwm"; 703 reg = <0x0 0xffa98020 0x0 0x10>; 704 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 705 clock-names = "pwm", "pclk"; 706 #pwm-cells = <3>; 707 status = "disabled"; 708 }; 709 710 pwm7: pwm@ffa98030 { 711 compatible = "rockchip,rk3528-pwm", 712 "rockchip,rk3328-pwm"; 713 reg = <0x0 0xffa98030 0x0 0x10>; 714 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 715 clock-names = "pwm", "pclk"; 716 #pwm-cells = <3>; 717 status = "disabled"; 718 }; 719 720 saradc: adc@ffae0000 { 721 compatible = "rockchip,rk3528-saradc"; 722 reg = <0x0 0xffae0000 0x0 0x10000>; 723 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 724 clock-names = "saradc", "apb_pclk"; 725 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 726 resets = <&cru SRST_P_SARADC>; 727 reset-names = "saradc-apb"; 728 #io-channel-cells = <1>; 729 status = "disabled"; 730 }; 731 732 gmac0: ethernet@ffbd0000 { 733 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 734 reg = <0x0 0xffbd0000 0x0 0x10000>; 735 clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>, 736 <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>, 737 <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>; 738 clock-names = "stmmaceth", "clk_mac_ref", 739 "mac_clk_rx", "mac_clk_tx", 740 "pclk_mac", "aclk_mac"; 741 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 743 interrupt-names = "macirq", "eth_wake_irq"; 744 phy-handle = <&rmii0_phy>; 745 phy-mode = "rmii"; 746 resets = <&cru SRST_A_MAC_VO>; 747 reset-names = "stmmaceth"; 748 rockchip,grf = <&vo_grf>; 749 snps,axi-config = <&gmac0_stmmac_axi_setup>; 750 snps,mixed-burst; 751 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 752 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 753 snps,tso; 754 status = "disabled"; 755 756 mdio0: mdio { 757 compatible = "snps,dwmac-mdio"; 758 #address-cells = <0x1>; 759 #size-cells = <0x0>; 760 761 rmii0_phy: ethernet-phy@2 { 762 compatible = "ethernet-phy-ieee802.3-c22"; 763 reg = <0x2>; 764 clocks = <&cru CLK_MACPHY>; 765 phy-is-integrated; 766 pinctrl-names = "default"; 767 pinctrl-0 = <&fephym0_led_link>, 768 <&fephym0_led_spd>; 769 resets = <&cru SRST_MACPHY>; 770 }; 771 }; 772 773 gmac0_stmmac_axi_setup: stmmac-axi-config { 774 snps,blen = <0 0 0 0 16 8 4>; 775 snps,rd_osr_lmt = <8>; 776 snps,wr_osr_lmt = <4>; 777 }; 778 779 gmac0_mtl_rx_setup: rx-queues-config { 780 snps,rx-queues-to-use = <1>; 781 queue0 {}; 782 }; 783 784 gmac0_mtl_tx_setup: tx-queues-config { 785 snps,tx-queues-to-use = <1>; 786 queue0 {}; 787 }; 788 }; 789 790 gmac1: ethernet@ffbe0000 { 791 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 792 reg = <0x0 0xffbe0000 0x0 0x10000>; 793 clocks = <&cru CLK_GMAC1_SRC_VPU>, 794 <&cru CLK_GMAC1_RMII_VPU>, 795 <&cru PCLK_MAC_VPU>, 796 <&cru ACLK_MAC_VPU>; 797 clock-names = "stmmaceth", 798 "clk_mac_ref", 799 "pclk_mac", 800 "aclk_mac"; 801 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 803 interrupt-names = "macirq", "eth_wake_irq"; 804 resets = <&cru SRST_A_MAC>; 805 reset-names = "stmmaceth"; 806 rockchip,grf = <&vpu_grf>; 807 snps,axi-config = <&gmac1_stmmac_axi_setup>; 808 snps,mixed-burst; 809 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 810 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 811 snps,tso; 812 status = "disabled"; 813 814 mdio1: mdio { 815 compatible = "snps,dwmac-mdio"; 816 #address-cells = <0x1>; 817 #size-cells = <0x0>; 818 }; 819 820 gmac1_stmmac_axi_setup: stmmac-axi-config { 821 snps,blen = <0 0 0 0 16 8 4>; 822 snps,rd_osr_lmt = <8>; 823 snps,wr_osr_lmt = <4>; 824 }; 825 826 gmac1_mtl_rx_setup: rx-queues-config { 827 snps,rx-queues-to-use = <1>; 828 queue0 {}; 829 }; 830 831 gmac1_mtl_tx_setup: tx-queues-config { 832 snps,tx-queues-to-use = <1>; 833 queue0 {}; 834 }; 835 }; 836 837 sdhci: mmc@ffbf0000 { 838 compatible = "rockchip,rk3528-dwcmshc", 839 "rockchip,rk3588-dwcmshc"; 840 reg = <0x0 0xffbf0000 0x0 0x10000>; 841 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, 842 <&cru CCLK_SRC_EMMC>; 843 assigned-clock-rates = <200000000>, <24000000>, 844 <200000000>; 845 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 846 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 847 <&cru TCLK_EMMC>; 848 clock-names = "core", "bus", "axi", "block", "timer"; 849 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 850 max-frequency = <200000000>; 851 pinctrl-names = "default"; 852 pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, 853 <&emmc_strb>; 854 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 855 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 856 <&cru SRST_T_EMMC>; 857 reset-names = "core", "bus", "axi", "block", "timer"; 858 status = "disabled"; 859 }; 860 861 sdio0: mmc@ffc10000 { 862 compatible = "rockchip,rk3528-dw-mshc", 863 "rockchip,rk3288-dw-mshc"; 864 reg = <0x0 0xffc10000 0x0 0x4000>; 865 clocks = <&cru HCLK_SDIO0>, 866 <&cru CCLK_SRC_SDIO0>, 867 <&cru SCLK_SDIO0_DRV>, 868 <&cru SCLK_SDIO0_SAMPLE>; 869 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 870 fifo-depth = <0x100>; 871 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 872 max-frequency = <200000000>; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>; 875 resets = <&cru SRST_H_SDIO0>; 876 reset-names = "reset"; 877 status = "disabled"; 878 }; 879 880 sdio1: mmc@ffc20000 { 881 compatible = "rockchip,rk3528-dw-mshc", 882 "rockchip,rk3288-dw-mshc"; 883 reg = <0x0 0xffc20000 0x0 0x4000>; 884 clocks = <&cru HCLK_SDIO1>, 885 <&cru CCLK_SRC_SDIO1>, 886 <&cru SCLK_SDIO1_DRV>, 887 <&cru SCLK_SDIO1_SAMPLE>; 888 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 889 fifo-depth = <0x100>; 890 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 891 max-frequency = <200000000>; 892 pinctrl-names = "default"; 893 pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>; 894 resets = <&cru SRST_H_SDIO1>; 895 reset-names = "reset"; 896 status = "disabled"; 897 }; 898 899 sdmmc: mmc@ffc30000 { 900 compatible = "rockchip,rk3528-dw-mshc", 901 "rockchip,rk3288-dw-mshc"; 902 reg = <0x0 0xffc30000 0x0 0x4000>; 903 clocks = <&cru HCLK_SDMMC0>, 904 <&cru CCLK_SRC_SDMMC0>, 905 <&cru SCLK_SDMMC_DRV>, 906 <&cru SCLK_SDMMC_SAMPLE>; 907 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 908 fifo-depth = <0x100>; 909 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 910 max-frequency = <150000000>; 911 pinctrl-names = "default"; 912 pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>, 913 <&sdmmc_det>; 914 resets = <&cru SRST_H_SDMMC0>; 915 reset-names = "reset"; 916 rockchip,default-sample-phase = <90>; 917 status = "disabled"; 918 }; 919 920 dmac: dma-controller@ffd60000 { 921 compatible = "arm,pl330", "arm,primecell"; 922 reg = <0x0 0xffd60000 0x0 0x4000>; 923 clocks = <&cru ACLK_DMAC>; 924 clock-names = "apb_pclk"; 925 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 934 #dma-cells = <1>; 935 arm,pl330-periph-burst; 936 }; 937 }; 938}; 939 940#include "rk3528-pinctrl.dtsi" 941