1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 3#include <dt-bindings/gpio/gpio.h> 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <dt-bindings/clock/rk3288-cru.h> 8#include <dt-bindings/power/rk3288-power.h> 9#include <dt-bindings/thermal/thermal.h> 10#include <dt-bindings/soc/rockchip,boot-mode.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 compatible = "rockchip,rk3288"; 17 18 interrupt-parent = <&gic>; 19 20 aliases { 21 ethernet0 = &gmac; 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 gpio4 = &gpio4; 27 gpio5 = &gpio5; 28 gpio6 = &gpio6; 29 gpio7 = &gpio7; 30 gpio8 = &gpio8; 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 mshc0 = &emmc; 38 mshc1 = &sdmmc; 39 mshc2 = &sdio0; 40 mshc3 = &sdio1; 41 serial0 = &uart0; 42 serial1 = &uart1; 43 serial2 = &uart2; 44 serial3 = &uart3; 45 serial4 = &uart4; 46 spi0 = &spi0; 47 spi1 = &spi1; 48 spi2 = &spi2; 49 }; 50 51 arm-pmu { 52 compatible = "arm,cortex-a12-pmu"; 53 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 57 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 58 }; 59 60 cpus { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 enable-method = "rockchip,rk3066-smp"; 64 rockchip,pmu = <&pmu>; 65 66 cpu0: cpu@500 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a12"; 69 reg = <0x500>; 70 resets = <&cru SRST_CORE0>; 71 operating-points-v2 = <&cpu_opp_table>; 72 #cooling-cells = <2>; /* min followed by max */ 73 clocks = <&cru ARMCLK>; 74 dynamic-power-coefficient = <370>; 75 }; 76 cpu1: cpu@501 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a12"; 79 reg = <0x501>; 80 resets = <&cru SRST_CORE1>; 81 operating-points-v2 = <&cpu_opp_table>; 82 #cooling-cells = <2>; /* min followed by max */ 83 clocks = <&cru ARMCLK>; 84 dynamic-power-coefficient = <370>; 85 }; 86 cpu2: cpu@502 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a12"; 89 reg = <0x502>; 90 resets = <&cru SRST_CORE2>; 91 operating-points-v2 = <&cpu_opp_table>; 92 #cooling-cells = <2>; /* min followed by max */ 93 clocks = <&cru ARMCLK>; 94 dynamic-power-coefficient = <370>; 95 }; 96 cpu3: cpu@503 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a12"; 99 reg = <0x503>; 100 resets = <&cru SRST_CORE3>; 101 operating-points-v2 = <&cpu_opp_table>; 102 #cooling-cells = <2>; /* min followed by max */ 103 clocks = <&cru ARMCLK>; 104 dynamic-power-coefficient = <370>; 105 }; 106 }; 107 108 cpu_opp_table: opp-table-0 { 109 compatible = "operating-points-v2"; 110 opp-shared; 111 112 opp-126000000 { 113 opp-hz = /bits/ 64 <126000000>; 114 opp-microvolt = <900000>; 115 clock-latency-ns = <40000>; 116 }; 117 opp-216000000 { 118 opp-hz = /bits/ 64 <216000000>; 119 opp-microvolt = <900000>; 120 }; 121 opp-312000000 { 122 opp-hz = /bits/ 64 <312000000>; 123 opp-microvolt = <900000>; 124 }; 125 opp-408000000 { 126 opp-hz = /bits/ 64 <408000000>; 127 opp-microvolt = <900000>; 128 }; 129 opp-600000000 { 130 opp-hz = /bits/ 64 <600000000>; 131 opp-microvolt = <900000>; 132 }; 133 opp-696000000 { 134 opp-hz = /bits/ 64 <696000000>; 135 opp-microvolt = <950000>; 136 }; 137 opp-816000000 { 138 opp-hz = /bits/ 64 <816000000>; 139 opp-microvolt = <1000000>; 140 }; 141 opp-1008000000 { 142 opp-hz = /bits/ 64 <1008000000>; 143 opp-microvolt = <1050000>; 144 }; 145 opp-1200000000 { 146 opp-hz = /bits/ 64 <1200000000>; 147 opp-microvolt = <1100000>; 148 }; 149 opp-1416000000 { 150 opp-hz = /bits/ 64 <1416000000>; 151 opp-microvolt = <1200000>; 152 }; 153 opp-1512000000 { 154 opp-hz = /bits/ 64 <1512000000>; 155 opp-microvolt = <1300000>; 156 }; 157 opp-1608000000 { 158 opp-hz = /bits/ 64 <1608000000>; 159 opp-microvolt = <1350000>; 160 }; 161 }; 162 163 reserved-memory { 164 #address-cells = <2>; 165 #size-cells = <2>; 166 ranges; 167 168 /* 169 * The rk3288 cannot use the memory area above 0xfe000000 170 * for dma operations for some reason. While there is 171 * probably a better solution available somewhere, we 172 * haven't found it yet and while devices with 2GB of ram 173 * are not affected, this issue prevents 4GB from booting. 174 * So to make these devices at least bootable, block 175 * this area for the time being until the real solution 176 * is found. 177 */ 178 dma-unusable@fe000000 { 179 reg = <0x0 0xfe000000 0x0 0x1000000>; 180 }; 181 }; 182 183 xin24m: oscillator { 184 compatible = "fixed-clock"; 185 clock-frequency = <24000000>; 186 clock-output-names = "xin24m"; 187 #clock-cells = <0>; 188 }; 189 190 timer { 191 compatible = "arm,armv7-timer"; 192 arm,cpu-registers-not-fw-configured; 193 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 194 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 195 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 196 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 197 clock-frequency = <24000000>; 198 arm,no-tick-in-suspend; 199 }; 200 201 timer: timer@ff810000 { 202 compatible = "rockchip,rk3288-timer"; 203 reg = <0x0 0xff810000 0x0 0x20>; 204 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 205 clocks = <&cru PCLK_TIMER>, <&xin24m>; 206 clock-names = "pclk", "timer"; 207 }; 208 209 display-subsystem { 210 compatible = "rockchip,display-subsystem"; 211 ports = <&vopl_out>, <&vopb_out>; 212 }; 213 214 sdmmc: mmc@ff0c0000 { 215 compatible = "rockchip,rk3288-dw-mshc"; 216 max-frequency = <150000000>; 217 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 218 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 219 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 220 fifo-depth = <0x100>; 221 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 222 reg = <0x0 0xff0c0000 0x0 0x4000>; 223 resets = <&cru SRST_MMC0>; 224 reset-names = "reset"; 225 status = "disabled"; 226 }; 227 228 sdio0: mmc@ff0d0000 { 229 compatible = "rockchip,rk3288-dw-mshc"; 230 max-frequency = <150000000>; 231 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 232 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 233 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 234 fifo-depth = <0x100>; 235 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 236 reg = <0x0 0xff0d0000 0x0 0x4000>; 237 resets = <&cru SRST_SDIO0>; 238 reset-names = "reset"; 239 status = "disabled"; 240 }; 241 242 sdio1: mmc@ff0e0000 { 243 compatible = "rockchip,rk3288-dw-mshc"; 244 max-frequency = <150000000>; 245 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, 246 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; 247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 248 fifo-depth = <0x100>; 249 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 250 reg = <0x0 0xff0e0000 0x0 0x4000>; 251 resets = <&cru SRST_SDIO1>; 252 reset-names = "reset"; 253 status = "disabled"; 254 }; 255 256 emmc: mmc@ff0f0000 { 257 compatible = "rockchip,rk3288-dw-mshc"; 258 max-frequency = <150000000>; 259 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 260 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 261 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 262 fifo-depth = <0x100>; 263 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 264 reg = <0x0 0xff0f0000 0x0 0x4000>; 265 resets = <&cru SRST_EMMC>; 266 reset-names = "reset"; 267 status = "disabled"; 268 }; 269 270 saradc: saradc@ff100000 { 271 compatible = "rockchip,saradc"; 272 reg = <0x0 0xff100000 0x0 0x100>; 273 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 274 #io-channel-cells = <1>; 275 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 276 clock-names = "saradc", "apb_pclk"; 277 resets = <&cru SRST_SARADC>; 278 reset-names = "saradc-apb"; 279 status = "disabled"; 280 }; 281 282 spi0: spi@ff110000 { 283 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 284 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 285 clock-names = "spiclk", "apb_pclk"; 286 dmas = <&dmac_peri 11>, <&dmac_peri 12>; 287 dma-names = "tx", "rx"; 288 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 289 pinctrl-names = "default"; 290 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 291 reg = <0x0 0xff110000 0x0 0x1000>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 status = "disabled"; 295 }; 296 297 spi1: spi@ff120000 { 298 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 299 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 300 clock-names = "spiclk", "apb_pclk"; 301 dmas = <&dmac_peri 13>, <&dmac_peri 14>; 302 dma-names = "tx", "rx"; 303 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 306 reg = <0x0 0xff120000 0x0 0x1000>; 307 #address-cells = <1>; 308 #size-cells = <0>; 309 status = "disabled"; 310 }; 311 312 spi2: spi@ff130000 { 313 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; 314 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 315 clock-names = "spiclk", "apb_pclk"; 316 dmas = <&dmac_peri 15>, <&dmac_peri 16>; 317 dma-names = "tx", "rx"; 318 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 321 reg = <0x0 0xff130000 0x0 0x1000>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 status = "disabled"; 325 }; 326 327 i2c1: i2c@ff140000 { 328 compatible = "rockchip,rk3288-i2c"; 329 reg = <0x0 0xff140000 0x0 0x1000>; 330 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 clock-names = "i2c"; 334 clocks = <&cru PCLK_I2C1>; 335 pinctrl-names = "default"; 336 pinctrl-0 = <&i2c1_xfer>; 337 status = "disabled"; 338 }; 339 340 i2c3: i2c@ff150000 { 341 compatible = "rockchip,rk3288-i2c"; 342 reg = <0x0 0xff150000 0x0 0x1000>; 343 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 clock-names = "i2c"; 347 clocks = <&cru PCLK_I2C3>; 348 pinctrl-names = "default"; 349 pinctrl-0 = <&i2c3_xfer>; 350 status = "disabled"; 351 }; 352 353 i2c4: i2c@ff160000 { 354 compatible = "rockchip,rk3288-i2c"; 355 reg = <0x0 0xff160000 0x0 0x1000>; 356 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 clock-names = "i2c"; 360 clocks = <&cru PCLK_I2C4>; 361 pinctrl-names = "default"; 362 pinctrl-0 = <&i2c4_xfer>; 363 status = "disabled"; 364 }; 365 366 i2c5: i2c@ff170000 { 367 compatible = "rockchip,rk3288-i2c"; 368 reg = <0x0 0xff170000 0x0 0x1000>; 369 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 clock-names = "i2c"; 373 clocks = <&cru PCLK_I2C5>; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&i2c5_xfer>; 376 status = "disabled"; 377 }; 378 379 uart0: serial@ff180000 { 380 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 381 reg = <0x0 0xff180000 0x0 0x100>; 382 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 383 reg-shift = <2>; 384 reg-io-width = <4>; 385 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 386 clock-names = "baudclk", "apb_pclk"; 387 dmas = <&dmac_peri 1>, <&dmac_peri 2>; 388 dma-names = "tx", "rx"; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&uart0_xfer>; 391 status = "disabled"; 392 }; 393 394 uart1: serial@ff190000 { 395 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 396 reg = <0x0 0xff190000 0x0 0x100>; 397 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 398 reg-shift = <2>; 399 reg-io-width = <4>; 400 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 401 clock-names = "baudclk", "apb_pclk"; 402 dmas = <&dmac_peri 3>, <&dmac_peri 4>; 403 dma-names = "tx", "rx"; 404 pinctrl-names = "default"; 405 pinctrl-0 = <&uart1_xfer>; 406 status = "disabled"; 407 }; 408 409 uart2: serial@ff690000 { 410 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 411 reg = <0x0 0xff690000 0x0 0x100>; 412 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 413 reg-shift = <2>; 414 reg-io-width = <4>; 415 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 416 clock-names = "baudclk", "apb_pclk"; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&uart2_xfer>; 419 status = "disabled"; 420 }; 421 422 uart3: serial@ff1b0000 { 423 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 424 reg = <0x0 0xff1b0000 0x0 0x100>; 425 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 426 reg-shift = <2>; 427 reg-io-width = <4>; 428 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 429 clock-names = "baudclk", "apb_pclk"; 430 dmas = <&dmac_peri 7>, <&dmac_peri 8>; 431 dma-names = "tx", "rx"; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&uart3_xfer>; 434 status = "disabled"; 435 }; 436 437 uart4: serial@ff1c0000 { 438 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; 439 reg = <0x0 0xff1c0000 0x0 0x100>; 440 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 441 reg-shift = <2>; 442 reg-io-width = <4>; 443 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 444 clock-names = "baudclk", "apb_pclk"; 445 dmas = <&dmac_peri 9>, <&dmac_peri 10>; 446 dma-names = "tx", "rx"; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&uart4_xfer>; 449 status = "disabled"; 450 }; 451 452 dmac_peri: dma-controller@ff250000 { 453 compatible = "arm,pl330", "arm,primecell"; 454 reg = <0x0 0xff250000 0x0 0x4000>; 455 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 457 #dma-cells = <1>; 458 arm,pl330-broken-no-flushp; 459 arm,pl330-periph-burst; 460 clocks = <&cru ACLK_DMAC2>; 461 clock-names = "apb_pclk"; 462 }; 463 464 thermal-zones { 465 reserve_thermal: reserve-thermal { 466 polling-delay-passive = <1000>; /* milliseconds */ 467 polling-delay = <5000>; /* milliseconds */ 468 469 thermal-sensors = <&tsadc 0>; 470 }; 471 472 cpu_thermal: cpu-thermal { 473 polling-delay-passive = <100>; /* milliseconds */ 474 polling-delay = <5000>; /* milliseconds */ 475 476 thermal-sensors = <&tsadc 1>; 477 478 trips { 479 cpu_alert0: cpu_alert0 { 480 temperature = <70000>; /* millicelsius */ 481 hysteresis = <2000>; /* millicelsius */ 482 type = "passive"; 483 }; 484 cpu_alert1: cpu_alert1 { 485 temperature = <75000>; /* millicelsius */ 486 hysteresis = <2000>; /* millicelsius */ 487 type = "passive"; 488 }; 489 cpu_crit: cpu_crit { 490 temperature = <90000>; /* millicelsius */ 491 hysteresis = <2000>; /* millicelsius */ 492 type = "critical"; 493 }; 494 }; 495 496 cooling-maps { 497 map0 { 498 trip = <&cpu_alert0>; 499 cooling-device = 500 <&cpu0 THERMAL_NO_LIMIT 6>, 501 <&cpu1 THERMAL_NO_LIMIT 6>, 502 <&cpu2 THERMAL_NO_LIMIT 6>, 503 <&cpu3 THERMAL_NO_LIMIT 6>; 504 }; 505 map1 { 506 trip = <&cpu_alert1>; 507 cooling-device = 508 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 509 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 510 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 511 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 512 }; 513 }; 514 }; 515 516 gpu_thermal: gpu-thermal { 517 polling-delay-passive = <100>; /* milliseconds */ 518 polling-delay = <5000>; /* milliseconds */ 519 520 thermal-sensors = <&tsadc 2>; 521 522 trips { 523 gpu_alert0: gpu_alert0 { 524 temperature = <70000>; /* millicelsius */ 525 hysteresis = <2000>; /* millicelsius */ 526 type = "passive"; 527 }; 528 gpu_crit: gpu_crit { 529 temperature = <90000>; /* millicelsius */ 530 hysteresis = <2000>; /* millicelsius */ 531 type = "critical"; 532 }; 533 }; 534 535 cooling-maps { 536 map0 { 537 trip = <&gpu_alert0>; 538 cooling-device = 539 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 540 }; 541 }; 542 }; 543 }; 544 545 tsadc: tsadc@ff280000 { 546 compatible = "rockchip,rk3288-tsadc"; 547 reg = <0x0 0xff280000 0x0 0x100>; 548 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 550 clock-names = "tsadc", "apb_pclk"; 551 resets = <&cru SRST_TSADC>; 552 reset-names = "tsadc-apb"; 553 pinctrl-names = "init", "default", "sleep"; 554 pinctrl-0 = <&otp_pin>; 555 pinctrl-1 = <&otp_out>; 556 pinctrl-2 = <&otp_pin>; 557 #thermal-sensor-cells = <1>; 558 rockchip,grf = <&grf>; 559 rockchip,hw-tshut-temp = <95000>; 560 status = "disabled"; 561 }; 562 563 gmac: ethernet@ff290000 { 564 compatible = "rockchip,rk3288-gmac"; 565 reg = <0x0 0xff290000 0x0 0x10000>; 566 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 568 interrupt-names = "macirq", "eth_wake_irq"; 569 rockchip,grf = <&grf>; 570 clocks = <&cru SCLK_MAC>, 571 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 572 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 573 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 574 clock-names = "stmmaceth", 575 "mac_clk_rx", "mac_clk_tx", 576 "clk_mac_ref", "clk_mac_refout", 577 "aclk_mac", "pclk_mac"; 578 resets = <&cru SRST_MAC>; 579 reset-names = "stmmaceth"; 580 status = "disabled"; 581 }; 582 583 usb_host0_ehci: usb@ff500000 { 584 compatible = "generic-ehci"; 585 reg = <0x0 0xff500000 0x0 0x100>; 586 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&cru HCLK_USBHOST0>; 588 phys = <&usbphy1>; 589 phy-names = "usb"; 590 status = "disabled"; 591 }; 592 593 /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ 594 usb_host0_ohci: usb@ff520000 { 595 compatible = "generic-ohci"; 596 reg = <0x0 0xff520000 0x0 0x100>; 597 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&cru HCLK_USBHOST0>; 599 phys = <&usbphy1>; 600 phy-names = "usb"; 601 status = "disabled"; 602 }; 603 604 usb_host1: usb@ff540000 { 605 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 606 "snps,dwc2"; 607 reg = <0x0 0xff540000 0x0 0x40000>; 608 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&cru HCLK_USBHOST1>; 610 clock-names = "otg"; 611 dr_mode = "host"; 612 phys = <&usbphy2>; 613 phy-names = "usb2-phy"; 614 snps,reset-phy-on-wake; 615 status = "disabled"; 616 }; 617 618 usb_otg: usb@ff580000 { 619 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", 620 "snps,dwc2"; 621 reg = <0x0 0xff580000 0x0 0x40000>; 622 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&cru HCLK_OTG0>; 624 clock-names = "otg"; 625 dr_mode = "otg"; 626 g-np-tx-fifo-size = <16>; 627 g-rx-fifo-size = <275>; 628 g-tx-fifo-size = <256 128 128 64 64 32>; 629 phys = <&usbphy0>; 630 phy-names = "usb2-phy"; 631 status = "disabled"; 632 }; 633 634 usb_hsic: usb@ff5c0000 { 635 compatible = "generic-ehci"; 636 reg = <0x0 0xff5c0000 0x0 0x100>; 637 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&cru HCLK_HSIC>; 639 status = "disabled"; 640 }; 641 642 dmac_bus_ns: dma-controller@ff600000 { 643 compatible = "arm,pl330", "arm,primecell"; 644 reg = <0x0 0xff600000 0x0 0x4000>; 645 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 647 #dma-cells = <1>; 648 arm,pl330-broken-no-flushp; 649 arm,pl330-periph-burst; 650 clocks = <&cru ACLK_DMAC1>; 651 clock-names = "apb_pclk"; 652 status = "disabled"; 653 }; 654 655 i2c0: i2c@ff650000 { 656 compatible = "rockchip,rk3288-i2c"; 657 reg = <0x0 0xff650000 0x0 0x1000>; 658 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 clock-names = "i2c"; 662 clocks = <&cru PCLK_I2C0>; 663 pinctrl-names = "default"; 664 pinctrl-0 = <&i2c0_xfer>; 665 status = "disabled"; 666 }; 667 668 i2c2: i2c@ff660000 { 669 compatible = "rockchip,rk3288-i2c"; 670 reg = <0x0 0xff660000 0x0 0x1000>; 671 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 clock-names = "i2c"; 675 clocks = <&cru PCLK_I2C2>; 676 pinctrl-names = "default"; 677 pinctrl-0 = <&i2c2_xfer>; 678 status = "disabled"; 679 }; 680 681 pwm0: pwm@ff680000 { 682 compatible = "rockchip,rk3288-pwm"; 683 reg = <0x0 0xff680000 0x0 0x10>; 684 #pwm-cells = <3>; 685 pinctrl-names = "default"; 686 pinctrl-0 = <&pwm0_pin>; 687 clocks = <&cru PCLK_RKPWM>; 688 status = "disabled"; 689 }; 690 691 pwm1: pwm@ff680010 { 692 compatible = "rockchip,rk3288-pwm"; 693 reg = <0x0 0xff680010 0x0 0x10>; 694 #pwm-cells = <3>; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&pwm1_pin>; 697 clocks = <&cru PCLK_RKPWM>; 698 status = "disabled"; 699 }; 700 701 pwm2: pwm@ff680020 { 702 compatible = "rockchip,rk3288-pwm"; 703 reg = <0x0 0xff680020 0x0 0x10>; 704 #pwm-cells = <3>; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&pwm2_pin>; 707 clocks = <&cru PCLK_RKPWM>; 708 status = "disabled"; 709 }; 710 711 pwm3: pwm@ff680030 { 712 compatible = "rockchip,rk3288-pwm"; 713 reg = <0x0 0xff680030 0x0 0x10>; 714 #pwm-cells = <3>; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&pwm3_pin>; 717 clocks = <&cru PCLK_RKPWM>; 718 status = "disabled"; 719 }; 720 721 bus_intmem: sram@ff700000 { 722 compatible = "mmio-sram"; 723 reg = <0x0 0xff700000 0x0 0x18000>; 724 #address-cells = <1>; 725 #size-cells = <1>; 726 ranges = <0 0x0 0xff700000 0x18000>; 727 smp-sram@0 { 728 compatible = "rockchip,rk3066-smp-sram"; 729 reg = <0x00 0x10>; 730 }; 731 }; 732 733 pmu_sram: sram@ff720000 { 734 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; 735 reg = <0x0 0xff720000 0x0 0x1000>; 736 }; 737 738 pmu: power-management@ff730000 { 739 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd"; 740 reg = <0x0 0xff730000 0x0 0x100>; 741 742 power: power-controller { 743 compatible = "rockchip,rk3288-power-controller"; 744 #power-domain-cells = <1>; 745 #address-cells = <1>; 746 #size-cells = <0>; 747 748 assigned-clocks = <&cru SCLK_EDP_24M>; 749 assigned-clock-parents = <&xin24m>; 750 751 /* 752 * Note: Although SCLK_* are the working clocks 753 * of device without including on the NOC, needed for 754 * synchronous reset. 755 * 756 * The clocks on the which NOC: 757 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU. 758 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU. 759 * ACLK_RGA is on ACLK_RGA_NIU. 760 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU. 761 * 762 * Which clock are device clocks: 763 * clocks devices 764 * *_IEP IEP:Image Enhancement Processor 765 * *_ISP ISP:Image Signal Processing 766 * *_VIP VIP:Video Input Processor 767 * *_VOP* VOP:Visual Output Processor 768 * *_RGA RGA 769 * *_EDP* EDP 770 * *_LVDS_* LVDS 771 * *_HDMI HDMI 772 * *_MIPI_* MIPI 773 */ 774 power-domain@RK3288_PD_VIO { 775 reg = <RK3288_PD_VIO>; 776 clocks = <&cru ACLK_IEP>, 777 <&cru ACLK_ISP>, 778 <&cru ACLK_RGA>, 779 <&cru ACLK_VIP>, 780 <&cru ACLK_VOP0>, 781 <&cru ACLK_VOP1>, 782 <&cru DCLK_VOP0>, 783 <&cru DCLK_VOP1>, 784 <&cru HCLK_IEP>, 785 <&cru HCLK_ISP>, 786 <&cru HCLK_RGA>, 787 <&cru HCLK_VIP>, 788 <&cru HCLK_VOP0>, 789 <&cru HCLK_VOP1>, 790 <&cru PCLK_EDP_CTRL>, 791 <&cru PCLK_HDMI_CTRL>, 792 <&cru PCLK_LVDS_PHY>, 793 <&cru PCLK_MIPI_CSI>, 794 <&cru PCLK_MIPI_DSI0>, 795 <&cru PCLK_MIPI_DSI1>, 796 <&cru SCLK_EDP_24M>, 797 <&cru SCLK_EDP>, 798 <&cru SCLK_ISP_JPE>, 799 <&cru SCLK_ISP>, 800 <&cru SCLK_RGA>; 801 pm_qos = <&qos_vio0_iep>, 802 <&qos_vio1_vop>, 803 <&qos_vio1_isp_w0>, 804 <&qos_vio1_isp_w1>, 805 <&qos_vio0_vop>, 806 <&qos_vio0_vip>, 807 <&qos_vio2_rga_r>, 808 <&qos_vio2_rga_w>, 809 <&qos_vio1_isp_r>; 810 #power-domain-cells = <0>; 811 }; 812 813 /* 814 * Note: The following 3 are HEVC(H.265) clocks, 815 * and on the ACLK_HEVC_NIU (NOC). 816 */ 817 power-domain@RK3288_PD_HEVC { 818 reg = <RK3288_PD_HEVC>; 819 clocks = <&cru ACLK_HEVC>, 820 <&cru SCLK_HEVC_CABAC>, 821 <&cru SCLK_HEVC_CORE>; 822 pm_qos = <&qos_hevc_r>, 823 <&qos_hevc_w>; 824 #power-domain-cells = <0>; 825 }; 826 827 /* 828 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC 829 * (video endecoder & decoder) clocks that on the 830 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). 831 */ 832 power-domain@RK3288_PD_VIDEO { 833 reg = <RK3288_PD_VIDEO>; 834 clocks = <&cru ACLK_VCODEC>, 835 <&cru HCLK_VCODEC>; 836 pm_qos = <&qos_video>; 837 #power-domain-cells = <0>; 838 }; 839 840 /* 841 * Note: ACLK_GPU is the GPU clock, 842 * and on the ACLK_GPU_NIU (NOC). 843 */ 844 power-domain@RK3288_PD_GPU { 845 reg = <RK3288_PD_GPU>; 846 clocks = <&cru ACLK_GPU>; 847 pm_qos = <&qos_gpu_r>, 848 <&qos_gpu_w>; 849 #power-domain-cells = <0>; 850 }; 851 }; 852 853 reboot-mode { 854 compatible = "syscon-reboot-mode"; 855 offset = <0x94>; 856 mode-normal = <BOOT_NORMAL>; 857 mode-recovery = <BOOT_RECOVERY>; 858 mode-bootloader = <BOOT_FASTBOOT>; 859 mode-loader = <BOOT_BL_DOWNLOAD>; 860 }; 861 }; 862 863 sgrf: syscon@ff740000 { 864 compatible = "rockchip,rk3288-sgrf", "syscon"; 865 reg = <0x0 0xff740000 0x0 0x1000>; 866 }; 867 868 cru: clock-controller@ff760000 { 869 compatible = "rockchip,rk3288-cru"; 870 reg = <0x0 0xff760000 0x0 0x1000>; 871 clocks = <&xin24m>; 872 clock-names = "xin24m"; 873 rockchip,grf = <&grf>; 874 #clock-cells = <1>; 875 #reset-cells = <1>; 876 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, 877 <&cru PLL_NPLL>, <&cru ACLK_CPU>, 878 <&cru HCLK_CPU>, <&cru PCLK_CPU>, 879 <&cru ACLK_PERI>, <&cru HCLK_PERI>, 880 <&cru PCLK_PERI>; 881 assigned-clock-rates = <594000000>, <400000000>, 882 <500000000>, <300000000>, 883 <150000000>, <75000000>, 884 <300000000>, <150000000>, 885 <75000000>; 886 }; 887 888 grf: syscon@ff770000 { 889 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; 890 reg = <0x0 0xff770000 0x0 0x1000>; 891 892 edp_phy: edp-phy { 893 compatible = "rockchip,rk3288-dp-phy"; 894 clocks = <&cru SCLK_EDP_24M>; 895 clock-names = "24m"; 896 #phy-cells = <0>; 897 status = "disabled"; 898 }; 899 900 io_domains: io-domains { 901 compatible = "rockchip,rk3288-io-voltage-domain"; 902 status = "disabled"; 903 }; 904 905 usbphy: usbphy { 906 compatible = "rockchip,rk3288-usb-phy"; 907 #address-cells = <1>; 908 #size-cells = <0>; 909 status = "disabled"; 910 911 usbphy0: usb-phy@320 { 912 #phy-cells = <0>; 913 reg = <0x320>; 914 clocks = <&cru SCLK_OTGPHY0>; 915 clock-names = "phyclk"; 916 #clock-cells = <0>; 917 resets = <&cru SRST_USBOTG_PHY>; 918 reset-names = "phy-reset"; 919 }; 920 921 usbphy1: usb-phy@334 { 922 #phy-cells = <0>; 923 reg = <0x334>; 924 clocks = <&cru SCLK_OTGPHY1>; 925 clock-names = "phyclk"; 926 #clock-cells = <0>; 927 resets = <&cru SRST_USBHOST0_PHY>; 928 reset-names = "phy-reset"; 929 }; 930 931 usbphy2: usb-phy@348 { 932 #phy-cells = <0>; 933 reg = <0x348>; 934 clocks = <&cru SCLK_OTGPHY2>; 935 clock-names = "phyclk"; 936 #clock-cells = <0>; 937 resets = <&cru SRST_USBHOST1_PHY>; 938 reset-names = "phy-reset"; 939 }; 940 }; 941 }; 942 943 wdt: watchdog@ff800000 { 944 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; 945 reg = <0x0 0xff800000 0x0 0x100>; 946 clocks = <&cru PCLK_WDT>; 947 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 948 status = "disabled"; 949 }; 950 951 spdif: sound@ff8b0000 { 952 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; 953 reg = <0x0 0xff8b0000 0x0 0x10000>; 954 #sound-dai-cells = <0>; 955 clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; 956 clock-names = "mclk", "hclk"; 957 dmas = <&dmac_bus_s 3>; 958 dma-names = "tx"; 959 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 960 pinctrl-names = "default"; 961 pinctrl-0 = <&spdif_tx>; 962 rockchip,grf = <&grf>; 963 status = "disabled"; 964 }; 965 966 i2s: i2s@ff890000 { 967 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; 968 reg = <0x0 0xff890000 0x0 0x10000>; 969 #sound-dai-cells = <0>; 970 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 972 clock-names = "i2s_clk", "i2s_hclk"; 973 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; 974 dma-names = "tx", "rx"; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&i2s0_bus>; 977 rockchip,playback-channels = <8>; 978 rockchip,capture-channels = <2>; 979 status = "disabled"; 980 }; 981 982 crypto: crypto@ff8a0000 { 983 compatible = "rockchip,rk3288-crypto"; 984 reg = <0x0 0xff8a0000 0x0 0x4000>; 985 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 986 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 987 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; 988 clock-names = "aclk", "hclk", "sclk", "apb_pclk"; 989 resets = <&cru SRST_CRYPTO>; 990 reset-names = "crypto-rst"; 991 }; 992 993 iep_mmu: iommu@ff900800 { 994 compatible = "rockchip,iommu"; 995 reg = <0x0 0xff900800 0x0 0x40>; 996 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 998 clock-names = "aclk", "iface"; 999 #iommu-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 isp_mmu: iommu@ff914000 { 1004 compatible = "rockchip,iommu"; 1005 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1006 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 1008 clock-names = "aclk", "iface"; 1009 #iommu-cells = <0>; 1010 rockchip,disable-mmu-reset; 1011 status = "disabled"; 1012 }; 1013 1014 rga: rga@ff920000 { 1015 compatible = "rockchip,rk3288-rga"; 1016 reg = <0x0 0xff920000 0x0 0x180>; 1017 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; 1019 clock-names = "aclk", "hclk", "sclk"; 1020 power-domains = <&power RK3288_PD_VIO>; 1021 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; 1022 reset-names = "core", "axi", "ahb"; 1023 }; 1024 1025 vopb: vop@ff930000 { 1026 compatible = "rockchip,rk3288-vop"; 1027 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>; 1028 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1030 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1031 power-domains = <&power RK3288_PD_VIO>; 1032 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 1033 reset-names = "axi", "ahb", "dclk"; 1034 iommus = <&vopb_mmu>; 1035 status = "disabled"; 1036 1037 vopb_out: port { 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 1041 vopb_out_hdmi: endpoint@0 { 1042 reg = <0>; 1043 remote-endpoint = <&hdmi_in_vopb>; 1044 }; 1045 1046 vopb_out_edp: endpoint@1 { 1047 reg = <1>; 1048 remote-endpoint = <&edp_in_vopb>; 1049 }; 1050 1051 vopb_out_mipi: endpoint@2 { 1052 reg = <2>; 1053 remote-endpoint = <&mipi_in_vopb>; 1054 }; 1055 1056 vopb_out_lvds: endpoint@3 { 1057 reg = <3>; 1058 remote-endpoint = <&lvds_in_vopb>; 1059 }; 1060 }; 1061 }; 1062 1063 vopb_mmu: iommu@ff930300 { 1064 compatible = "rockchip,iommu"; 1065 reg = <0x0 0xff930300 0x0 0x100>; 1066 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1067 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1068 clock-names = "aclk", "iface"; 1069 power-domains = <&power RK3288_PD_VIO>; 1070 #iommu-cells = <0>; 1071 status = "disabled"; 1072 }; 1073 1074 vopl: vop@ff940000 { 1075 compatible = "rockchip,rk3288-vop"; 1076 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>; 1077 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1078 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1079 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1080 power-domains = <&power RK3288_PD_VIO>; 1081 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 1082 reset-names = "axi", "ahb", "dclk"; 1083 iommus = <&vopl_mmu>; 1084 status = "disabled"; 1085 1086 vopl_out: port { 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 1090 vopl_out_hdmi: endpoint@0 { 1091 reg = <0>; 1092 remote-endpoint = <&hdmi_in_vopl>; 1093 }; 1094 1095 vopl_out_edp: endpoint@1 { 1096 reg = <1>; 1097 remote-endpoint = <&edp_in_vopl>; 1098 }; 1099 1100 vopl_out_mipi: endpoint@2 { 1101 reg = <2>; 1102 remote-endpoint = <&mipi_in_vopl>; 1103 }; 1104 1105 vopl_out_lvds: endpoint@3 { 1106 reg = <3>; 1107 remote-endpoint = <&lvds_in_vopl>; 1108 }; 1109 }; 1110 }; 1111 1112 vopl_mmu: iommu@ff940300 { 1113 compatible = "rockchip,iommu"; 1114 reg = <0x0 0xff940300 0x0 0x100>; 1115 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1116 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1117 clock-names = "aclk", "iface"; 1118 power-domains = <&power RK3288_PD_VIO>; 1119 #iommu-cells = <0>; 1120 status = "disabled"; 1121 }; 1122 1123 mipi_dsi: dsi@ff960000 { 1124 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; 1125 reg = <0x0 0xff960000 0x0 0x4000>; 1126 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1127 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; 1128 clock-names = "ref", "pclk"; 1129 power-domains = <&power RK3288_PD_VIO>; 1130 rockchip,grf = <&grf>; 1131 status = "disabled"; 1132 1133 ports { 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 1137 mipi_in: port@0 { 1138 reg = <0>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 1142 mipi_in_vopb: endpoint@0 { 1143 reg = <0>; 1144 remote-endpoint = <&vopb_out_mipi>; 1145 }; 1146 1147 mipi_in_vopl: endpoint@1 { 1148 reg = <1>; 1149 remote-endpoint = <&vopl_out_mipi>; 1150 }; 1151 }; 1152 1153 mipi_out: port@1 { 1154 reg = <1>; 1155 }; 1156 }; 1157 }; 1158 1159 lvds: lvds@ff96c000 { 1160 compatible = "rockchip,rk3288-lvds"; 1161 reg = <0x0 0xff96c000 0x0 0x4000>; 1162 clocks = <&cru PCLK_LVDS_PHY>; 1163 clock-names = "pclk_lvds"; 1164 pinctrl-names = "lcdc"; 1165 pinctrl-0 = <&lcdc_ctl>; 1166 power-domains = <&power RK3288_PD_VIO>; 1167 rockchip,grf = <&grf>; 1168 status = "disabled"; 1169 1170 ports { 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 1174 lvds_in: port@0 { 1175 reg = <0>; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 1179 lvds_in_vopb: endpoint@0 { 1180 reg = <0>; 1181 remote-endpoint = <&vopb_out_lvds>; 1182 }; 1183 1184 lvds_in_vopl: endpoint@1 { 1185 reg = <1>; 1186 remote-endpoint = <&vopl_out_lvds>; 1187 }; 1188 }; 1189 1190 lvds_out: port@1 { 1191 reg = <1>; 1192 }; 1193 }; 1194 }; 1195 1196 edp: dp@ff970000 { 1197 compatible = "rockchip,rk3288-dp"; 1198 reg = <0x0 0xff970000 0x0 0x4000>; 1199 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1200 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; 1201 clock-names = "dp", "pclk"; 1202 phys = <&edp_phy>; 1203 phy-names = "dp"; 1204 power-domains = <&power RK3288_PD_VIO>; 1205 resets = <&cru SRST_EDP>; 1206 reset-names = "dp"; 1207 rockchip,grf = <&grf>; 1208 status = "disabled"; 1209 1210 ports { 1211 #address-cells = <1>; 1212 #size-cells = <0>; 1213 1214 edp_in: port@0 { 1215 reg = <0>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 1219 edp_in_vopb: endpoint@0 { 1220 reg = <0>; 1221 remote-endpoint = <&vopb_out_edp>; 1222 }; 1223 1224 edp_in_vopl: endpoint@1 { 1225 reg = <1>; 1226 remote-endpoint = <&vopl_out_edp>; 1227 }; 1228 }; 1229 1230 edp_out: port@1 { 1231 reg = <1>; 1232 }; 1233 }; 1234 }; 1235 1236 hdmi: hdmi@ff980000 { 1237 compatible = "rockchip,rk3288-dw-hdmi"; 1238 reg = <0x0 0xff980000 0x0 0x20000>; 1239 reg-io-width = <4>; 1240 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1241 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>; 1242 clock-names = "iahb", "isfr", "cec"; 1243 power-domains = <&power RK3288_PD_VIO>; 1244 rockchip,grf = <&grf>; 1245 #sound-dai-cells = <0>; 1246 status = "disabled"; 1247 1248 ports { 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 1252 hdmi_in: port@0 { 1253 reg = <0>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 1257 hdmi_in_vopb: endpoint@0 { 1258 reg = <0>; 1259 remote-endpoint = <&vopb_out_hdmi>; 1260 }; 1261 1262 hdmi_in_vopl: endpoint@1 { 1263 reg = <1>; 1264 remote-endpoint = <&vopl_out_hdmi>; 1265 }; 1266 }; 1267 1268 hdmi_out: port@1 { 1269 reg = <1>; 1270 }; 1271 }; 1272 }; 1273 1274 vpu: video-codec@ff9a0000 { 1275 compatible = "rockchip,rk3288-vpu"; 1276 reg = <0x0 0xff9a0000 0x0 0x800>; 1277 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1279 interrupt-names = "vepu", "vdpu"; 1280 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1281 clock-names = "aclk", "hclk"; 1282 iommus = <&vpu_mmu>; 1283 power-domains = <&power RK3288_PD_VIDEO>; 1284 }; 1285 1286 vpu_mmu: iommu@ff9a0800 { 1287 compatible = "rockchip,iommu"; 1288 reg = <0x0 0xff9a0800 0x0 0x100>; 1289 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1290 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1291 clock-names = "aclk", "iface"; 1292 #iommu-cells = <0>; 1293 power-domains = <&power RK3288_PD_VIDEO>; 1294 }; 1295 1296 hevc_mmu: iommu@ff9c0440 { 1297 compatible = "rockchip,iommu"; 1298 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; 1299 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1300 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; 1301 clock-names = "aclk", "iface"; 1302 #iommu-cells = <0>; 1303 status = "disabled"; 1304 }; 1305 1306 gpu: gpu@ffa30000 { 1307 compatible = "rockchip,rk3288-mali", "arm,mali-t760"; 1308 reg = <0x0 0xffa30000 0x0 0x10000>; 1309 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1312 interrupt-names = "job", "mmu", "gpu"; 1313 clocks = <&cru ACLK_GPU>; 1314 operating-points-v2 = <&gpu_opp_table>; 1315 #cooling-cells = <2>; /* min followed by max */ 1316 power-domains = <&power RK3288_PD_GPU>; 1317 status = "disabled"; 1318 }; 1319 1320 gpu_opp_table: opp-table-1 { 1321 compatible = "operating-points-v2"; 1322 1323 opp-100000000 { 1324 opp-hz = /bits/ 64 <100000000>; 1325 opp-microvolt = <950000>; 1326 }; 1327 opp-200000000 { 1328 opp-hz = /bits/ 64 <200000000>; 1329 opp-microvolt = <950000>; 1330 }; 1331 opp-300000000 { 1332 opp-hz = /bits/ 64 <300000000>; 1333 opp-microvolt = <1000000>; 1334 }; 1335 opp-400000000 { 1336 opp-hz = /bits/ 64 <400000000>; 1337 opp-microvolt = <1100000>; 1338 }; 1339 opp-600000000 { 1340 opp-hz = /bits/ 64 <600000000>; 1341 opp-microvolt = <1250000>; 1342 }; 1343 }; 1344 1345 qos_gpu_r: qos@ffaa0000 { 1346 compatible = "rockchip,rk3288-qos", "syscon"; 1347 reg = <0x0 0xffaa0000 0x0 0x20>; 1348 }; 1349 1350 qos_gpu_w: qos@ffaa0080 { 1351 compatible = "rockchip,rk3288-qos", "syscon"; 1352 reg = <0x0 0xffaa0080 0x0 0x20>; 1353 }; 1354 1355 qos_vio1_vop: qos@ffad0000 { 1356 compatible = "rockchip,rk3288-qos", "syscon"; 1357 reg = <0x0 0xffad0000 0x0 0x20>; 1358 }; 1359 1360 qos_vio1_isp_w0: qos@ffad0100 { 1361 compatible = "rockchip,rk3288-qos", "syscon"; 1362 reg = <0x0 0xffad0100 0x0 0x20>; 1363 }; 1364 1365 qos_vio1_isp_w1: qos@ffad0180 { 1366 compatible = "rockchip,rk3288-qos", "syscon"; 1367 reg = <0x0 0xffad0180 0x0 0x20>; 1368 }; 1369 1370 qos_vio0_vop: qos@ffad0400 { 1371 compatible = "rockchip,rk3288-qos", "syscon"; 1372 reg = <0x0 0xffad0400 0x0 0x20>; 1373 }; 1374 1375 qos_vio0_vip: qos@ffad0480 { 1376 compatible = "rockchip,rk3288-qos", "syscon"; 1377 reg = <0x0 0xffad0480 0x0 0x20>; 1378 }; 1379 1380 qos_vio0_iep: qos@ffad0500 { 1381 compatible = "rockchip,rk3288-qos", "syscon"; 1382 reg = <0x0 0xffad0500 0x0 0x20>; 1383 }; 1384 1385 qos_vio2_rga_r: qos@ffad0800 { 1386 compatible = "rockchip,rk3288-qos", "syscon"; 1387 reg = <0x0 0xffad0800 0x0 0x20>; 1388 }; 1389 1390 qos_vio2_rga_w: qos@ffad0880 { 1391 compatible = "rockchip,rk3288-qos", "syscon"; 1392 reg = <0x0 0xffad0880 0x0 0x20>; 1393 }; 1394 1395 qos_vio1_isp_r: qos@ffad0900 { 1396 compatible = "rockchip,rk3288-qos", "syscon"; 1397 reg = <0x0 0xffad0900 0x0 0x20>; 1398 }; 1399 1400 qos_video: qos@ffae0000 { 1401 compatible = "rockchip,rk3288-qos", "syscon"; 1402 reg = <0x0 0xffae0000 0x0 0x20>; 1403 }; 1404 1405 qos_hevc_r: qos@ffaf0000 { 1406 compatible = "rockchip,rk3288-qos", "syscon"; 1407 reg = <0x0 0xffaf0000 0x0 0x20>; 1408 }; 1409 1410 qos_hevc_w: qos@ffaf0080 { 1411 compatible = "rockchip,rk3288-qos", "syscon"; 1412 reg = <0x0 0xffaf0080 0x0 0x20>; 1413 }; 1414 1415 dmac_bus_s: dma-controller@ffb20000 { 1416 compatible = "arm,pl330", "arm,primecell"; 1417 reg = <0x0 0xffb20000 0x0 0x4000>; 1418 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1420 #dma-cells = <1>; 1421 arm,pl330-broken-no-flushp; 1422 arm,pl330-periph-burst; 1423 clocks = <&cru ACLK_DMAC1>; 1424 clock-names = "apb_pclk"; 1425 }; 1426 1427 efuse: efuse@ffb40000 { 1428 compatible = "rockchip,rk3288-efuse"; 1429 reg = <0x0 0xffb40000 0x0 0x20>; 1430 #address-cells = <1>; 1431 #size-cells = <1>; 1432 clocks = <&cru PCLK_EFUSE256>; 1433 clock-names = "pclk_efuse"; 1434 1435 cpu_id: cpu-id@7 { 1436 reg = <0x07 0x10>; 1437 }; 1438 cpu_leakage: cpu_leakage@17 { 1439 reg = <0x17 0x1>; 1440 }; 1441 }; 1442 1443 gic: interrupt-controller@ffc01000 { 1444 compatible = "arm,gic-400"; 1445 interrupt-controller; 1446 #interrupt-cells = <3>; 1447 #address-cells = <0>; 1448 1449 reg = <0x0 0xffc01000 0x0 0x1000>, 1450 <0x0 0xffc02000 0x0 0x2000>, 1451 <0x0 0xffc04000 0x0 0x2000>, 1452 <0x0 0xffc06000 0x0 0x2000>; 1453 interrupts = <GIC_PPI 9 0xf04>; 1454 }; 1455 1456 pinctrl: pinctrl { 1457 compatible = "rockchip,rk3288-pinctrl"; 1458 rockchip,grf = <&grf>; 1459 rockchip,pmu = <&pmu>; 1460 #address-cells = <2>; 1461 #size-cells = <2>; 1462 ranges; 1463 1464 gpio0: gpio@ff750000 { 1465 compatible = "rockchip,gpio-bank"; 1466 reg = <0x0 0xff750000 0x0 0x100>; 1467 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1468 clocks = <&cru PCLK_GPIO0>; 1469 1470 gpio-controller; 1471 #gpio-cells = <2>; 1472 1473 interrupt-controller; 1474 #interrupt-cells = <2>; 1475 }; 1476 1477 gpio1: gpio@ff780000 { 1478 compatible = "rockchip,gpio-bank"; 1479 reg = <0x0 0xff780000 0x0 0x100>; 1480 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1481 clocks = <&cru PCLK_GPIO1>; 1482 1483 gpio-controller; 1484 #gpio-cells = <2>; 1485 1486 interrupt-controller; 1487 #interrupt-cells = <2>; 1488 }; 1489 1490 gpio2: gpio@ff790000 { 1491 compatible = "rockchip,gpio-bank"; 1492 reg = <0x0 0xff790000 0x0 0x100>; 1493 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1494 clocks = <&cru PCLK_GPIO2>; 1495 1496 gpio-controller; 1497 #gpio-cells = <2>; 1498 1499 interrupt-controller; 1500 #interrupt-cells = <2>; 1501 }; 1502 1503 gpio3: gpio@ff7a0000 { 1504 compatible = "rockchip,gpio-bank"; 1505 reg = <0x0 0xff7a0000 0x0 0x100>; 1506 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1507 clocks = <&cru PCLK_GPIO3>; 1508 1509 gpio-controller; 1510 #gpio-cells = <2>; 1511 1512 interrupt-controller; 1513 #interrupt-cells = <2>; 1514 }; 1515 1516 gpio4: gpio@ff7b0000 { 1517 compatible = "rockchip,gpio-bank"; 1518 reg = <0x0 0xff7b0000 0x0 0x100>; 1519 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1520 clocks = <&cru PCLK_GPIO4>; 1521 1522 gpio-controller; 1523 #gpio-cells = <2>; 1524 1525 interrupt-controller; 1526 #interrupt-cells = <2>; 1527 }; 1528 1529 gpio5: gpio@ff7c0000 { 1530 compatible = "rockchip,gpio-bank"; 1531 reg = <0x0 0xff7c0000 0x0 0x100>; 1532 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1533 clocks = <&cru PCLK_GPIO5>; 1534 1535 gpio-controller; 1536 #gpio-cells = <2>; 1537 1538 interrupt-controller; 1539 #interrupt-cells = <2>; 1540 }; 1541 1542 gpio6: gpio@ff7d0000 { 1543 compatible = "rockchip,gpio-bank"; 1544 reg = <0x0 0xff7d0000 0x0 0x100>; 1545 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1546 clocks = <&cru PCLK_GPIO6>; 1547 1548 gpio-controller; 1549 #gpio-cells = <2>; 1550 1551 interrupt-controller; 1552 #interrupt-cells = <2>; 1553 }; 1554 1555 gpio7: gpio@ff7e0000 { 1556 compatible = "rockchip,gpio-bank"; 1557 reg = <0x0 0xff7e0000 0x0 0x100>; 1558 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1559 clocks = <&cru PCLK_GPIO7>; 1560 1561 gpio-controller; 1562 #gpio-cells = <2>; 1563 1564 interrupt-controller; 1565 #interrupt-cells = <2>; 1566 }; 1567 1568 gpio8: gpio@ff7f0000 { 1569 compatible = "rockchip,gpio-bank"; 1570 reg = <0x0 0xff7f0000 0x0 0x100>; 1571 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1572 clocks = <&cru PCLK_GPIO8>; 1573 1574 gpio-controller; 1575 #gpio-cells = <2>; 1576 1577 interrupt-controller; 1578 #interrupt-cells = <2>; 1579 }; 1580 1581 hdmi { 1582 hdmi_cec_c0: hdmi-cec-c0 { 1583 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; 1584 }; 1585 1586 hdmi_cec_c7: hdmi-cec-c7 { 1587 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; 1588 }; 1589 1590 hdmi_ddc: hdmi-ddc { 1591 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, 1592 <7 RK_PC4 2 &pcfg_pull_none>; 1593 }; 1594 1595 hdmi_ddc_unwedge: hdmi-ddc-unwedge { 1596 rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, 1597 <7 RK_PC4 2 &pcfg_pull_none>; 1598 }; 1599 }; 1600 1601 pcfg_output_low: pcfg-output-low { 1602 output-low; 1603 }; 1604 1605 pcfg_pull_up: pcfg-pull-up { 1606 bias-pull-up; 1607 }; 1608 1609 pcfg_pull_down: pcfg-pull-down { 1610 bias-pull-down; 1611 }; 1612 1613 pcfg_pull_none: pcfg-pull-none { 1614 bias-disable; 1615 }; 1616 1617 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1618 bias-disable; 1619 drive-strength = <12>; 1620 }; 1621 1622 suspend { 1623 global_pwroff: global-pwroff { 1624 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; 1625 }; 1626 1627 ddrio_pwroff: ddrio-pwroff { 1628 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 1629 }; 1630 1631 ddr0_retention: ddr0-retention { 1632 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; 1633 }; 1634 1635 ddr1_retention: ddr1-retention { 1636 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; 1637 }; 1638 }; 1639 1640 edp { 1641 edp_hpd: edp-hpd { 1642 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; 1643 }; 1644 }; 1645 1646 i2c0 { 1647 i2c0_xfer: i2c0-xfer { 1648 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, 1649 <0 RK_PC0 1 &pcfg_pull_none>; 1650 }; 1651 }; 1652 1653 i2c1 { 1654 i2c1_xfer: i2c1-xfer { 1655 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, 1656 <8 RK_PA5 1 &pcfg_pull_none>; 1657 }; 1658 }; 1659 1660 i2c2 { 1661 i2c2_xfer: i2c2-xfer { 1662 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, 1663 <6 RK_PB2 1 &pcfg_pull_none>; 1664 }; 1665 }; 1666 1667 i2c3 { 1668 i2c3_xfer: i2c3-xfer { 1669 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, 1670 <2 RK_PC1 1 &pcfg_pull_none>; 1671 }; 1672 }; 1673 1674 i2c4 { 1675 i2c4_xfer: i2c4-xfer { 1676 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, 1677 <7 RK_PC2 1 &pcfg_pull_none>; 1678 }; 1679 }; 1680 1681 i2c5 { 1682 i2c5_xfer: i2c5-xfer { 1683 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, 1684 <7 RK_PC4 1 &pcfg_pull_none>; 1685 }; 1686 }; 1687 1688 i2s0 { 1689 i2s0_bus: i2s0-bus { 1690 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, 1691 <6 RK_PA1 1 &pcfg_pull_none>, 1692 <6 RK_PA2 1 &pcfg_pull_none>, 1693 <6 RK_PA3 1 &pcfg_pull_none>, 1694 <6 RK_PA4 1 &pcfg_pull_none>, 1695 <6 RK_PB0 1 &pcfg_pull_none>; 1696 }; 1697 }; 1698 1699 lcdc { 1700 lcdc_ctl: lcdc-ctl { 1701 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 1702 <1 RK_PD1 1 &pcfg_pull_none>, 1703 <1 RK_PD2 1 &pcfg_pull_none>, 1704 <1 RK_PD3 1 &pcfg_pull_none>; 1705 }; 1706 }; 1707 1708 sdmmc { 1709 sdmmc_clk: sdmmc-clk { 1710 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; 1711 }; 1712 1713 sdmmc_cmd: sdmmc-cmd { 1714 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; 1715 }; 1716 1717 sdmmc_cd: sdmmc-cd { 1718 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; 1719 }; 1720 1721 sdmmc_bus1: sdmmc-bus1 { 1722 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; 1723 }; 1724 1725 sdmmc_bus4: sdmmc-bus4 { 1726 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, 1727 <6 RK_PC1 1 &pcfg_pull_up>, 1728 <6 RK_PC2 1 &pcfg_pull_up>, 1729 <6 RK_PC3 1 &pcfg_pull_up>; 1730 }; 1731 }; 1732 1733 sdio0 { 1734 sdio0_bus1: sdio0-bus1 { 1735 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; 1736 }; 1737 1738 sdio0_bus4: sdio0-bus4 { 1739 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, 1740 <4 RK_PC5 1 &pcfg_pull_up>, 1741 <4 RK_PC6 1 &pcfg_pull_up>, 1742 <4 RK_PC7 1 &pcfg_pull_up>; 1743 }; 1744 1745 sdio0_cmd: sdio0-cmd { 1746 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; 1747 }; 1748 1749 sdio0_clk: sdio0-clk { 1750 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; 1751 }; 1752 1753 sdio0_cd: sdio0-cd { 1754 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; 1755 }; 1756 1757 sdio0_wp: sdio0-wp { 1758 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; 1759 }; 1760 1761 sdio0_pwr: sdio0-pwr { 1762 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; 1763 }; 1764 1765 sdio0_bkpwr: sdio0-bkpwr { 1766 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; 1767 }; 1768 1769 sdio0_int: sdio0-int { 1770 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; 1771 }; 1772 }; 1773 1774 sdio1 { 1775 sdio1_bus1: sdio1-bus1 { 1776 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; 1777 }; 1778 1779 sdio1_bus4: sdio1-bus4 { 1780 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, 1781 <3 RK_PD1 4 &pcfg_pull_up>, 1782 <3 RK_PD2 4 &pcfg_pull_up>, 1783 <3 RK_PD3 4 &pcfg_pull_up>; 1784 }; 1785 1786 sdio1_cd: sdio1-cd { 1787 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; 1788 }; 1789 1790 sdio1_wp: sdio1-wp { 1791 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; 1792 }; 1793 1794 sdio1_bkpwr: sdio1-bkpwr { 1795 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; 1796 }; 1797 1798 sdio1_int: sdio1-int { 1799 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; 1800 }; 1801 1802 sdio1_cmd: sdio1-cmd { 1803 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; 1804 }; 1805 1806 sdio1_clk: sdio1-clk { 1807 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; 1808 }; 1809 1810 sdio1_pwr: sdio1-pwr { 1811 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; 1812 }; 1813 }; 1814 1815 emmc { 1816 emmc_clk: emmc-clk { 1817 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; 1818 }; 1819 1820 emmc_cmd: emmc-cmd { 1821 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; 1822 }; 1823 1824 emmc_pwr: emmc-pwr { 1825 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; 1826 }; 1827 1828 emmc_bus1: emmc-bus1 { 1829 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; 1830 }; 1831 1832 emmc_bus4: emmc-bus4 { 1833 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, 1834 <3 RK_PA1 2 &pcfg_pull_up>, 1835 <3 RK_PA2 2 &pcfg_pull_up>, 1836 <3 RK_PA3 2 &pcfg_pull_up>; 1837 }; 1838 1839 emmc_bus8: emmc-bus8 { 1840 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, 1841 <3 RK_PA1 2 &pcfg_pull_up>, 1842 <3 RK_PA2 2 &pcfg_pull_up>, 1843 <3 RK_PA3 2 &pcfg_pull_up>, 1844 <3 RK_PA4 2 &pcfg_pull_up>, 1845 <3 RK_PA5 2 &pcfg_pull_up>, 1846 <3 RK_PA6 2 &pcfg_pull_up>, 1847 <3 RK_PA7 2 &pcfg_pull_up>; 1848 }; 1849 }; 1850 1851 spi0 { 1852 spi0_clk: spi0-clk { 1853 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; 1854 }; 1855 spi0_cs0: spi0-cs0 { 1856 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; 1857 }; 1858 spi0_tx: spi0-tx { 1859 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; 1860 }; 1861 spi0_rx: spi0-rx { 1862 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; 1863 }; 1864 spi0_cs1: spi0-cs1 { 1865 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; 1866 }; 1867 }; 1868 spi1 { 1869 spi1_clk: spi1-clk { 1870 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; 1871 }; 1872 spi1_cs0: spi1-cs0 { 1873 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; 1874 }; 1875 spi1_rx: spi1-rx { 1876 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; 1877 }; 1878 spi1_tx: spi1-tx { 1879 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; 1880 }; 1881 }; 1882 1883 spi2 { 1884 spi2_cs1: spi2-cs1 { 1885 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; 1886 }; 1887 spi2_clk: spi2-clk { 1888 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; 1889 }; 1890 spi2_cs0: spi2-cs0 { 1891 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; 1892 }; 1893 spi2_rx: spi2-rx { 1894 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; 1895 }; 1896 spi2_tx: spi2-tx { 1897 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; 1898 }; 1899 }; 1900 1901 uart0 { 1902 uart0_xfer: uart0-xfer { 1903 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, 1904 <4 RK_PC1 1 &pcfg_pull_none>; 1905 }; 1906 1907 uart0_cts: uart0-cts { 1908 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; 1909 }; 1910 1911 uart0_rts: uart0-rts { 1912 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; 1913 }; 1914 }; 1915 1916 uart1 { 1917 uart1_xfer: uart1-xfer { 1918 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, 1919 <5 RK_PB1 1 &pcfg_pull_none>; 1920 }; 1921 1922 uart1_cts: uart1-cts { 1923 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; 1924 }; 1925 1926 uart1_rts: uart1-rts { 1927 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; 1928 }; 1929 }; 1930 1931 uart2 { 1932 uart2_xfer: uart2-xfer { 1933 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, 1934 <7 RK_PC7 1 &pcfg_pull_none>; 1935 }; 1936 /* no rts / cts for uart2 */ 1937 }; 1938 1939 uart3 { 1940 uart3_xfer: uart3-xfer { 1941 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, 1942 <7 RK_PB0 1 &pcfg_pull_none>; 1943 }; 1944 1945 uart3_cts: uart3-cts { 1946 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; 1947 }; 1948 1949 uart3_rts: uart3-rts { 1950 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; 1951 }; 1952 }; 1953 1954 uart4 { 1955 uart4_xfer: uart4-xfer { 1956 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, 1957 <5 RK_PB6 3 &pcfg_pull_none>; 1958 }; 1959 1960 uart4_cts: uart4-cts { 1961 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; 1962 }; 1963 1964 uart4_rts: uart4-rts { 1965 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; 1966 }; 1967 }; 1968 1969 tsadc { 1970 otp_pin: otp-pin { 1971 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 1972 }; 1973 1974 otp_out: otp-out { 1975 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; 1976 }; 1977 }; 1978 1979 pwm0 { 1980 pwm0_pin: pwm0-pin { 1981 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; 1982 }; 1983 }; 1984 1985 pwm1 { 1986 pwm1_pin: pwm1-pin { 1987 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; 1988 }; 1989 }; 1990 1991 pwm2 { 1992 pwm2_pin: pwm2-pin { 1993 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; 1994 }; 1995 }; 1996 1997 pwm3 { 1998 pwm3_pin: pwm3-pin { 1999 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; 2000 }; 2001 }; 2002 2003 gmac { 2004 rgmii_pins: rgmii-pins { 2005 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, 2006 <3 RK_PD7 3 &pcfg_pull_none>, 2007 <3 RK_PD2 3 &pcfg_pull_none>, 2008 <3 RK_PD3 3 &pcfg_pull_none>, 2009 <3 RK_PD4 3 &pcfg_pull_none_12ma>, 2010 <3 RK_PD5 3 &pcfg_pull_none_12ma>, 2011 <3 RK_PD0 3 &pcfg_pull_none_12ma>, 2012 <3 RK_PD1 3 &pcfg_pull_none_12ma>, 2013 <4 RK_PA0 3 &pcfg_pull_none>, 2014 <4 RK_PA5 3 &pcfg_pull_none>, 2015 <4 RK_PA6 3 &pcfg_pull_none>, 2016 <4 RK_PB1 3 &pcfg_pull_none_12ma>, 2017 <4 RK_PA4 3 &pcfg_pull_none_12ma>, 2018 <4 RK_PA1 3 &pcfg_pull_none>, 2019 <4 RK_PA3 3 &pcfg_pull_none>; 2020 }; 2021 2022 rmii_pins: rmii-pins { 2023 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, 2024 <3 RK_PD7 3 &pcfg_pull_none>, 2025 <3 RK_PD4 3 &pcfg_pull_none>, 2026 <3 RK_PD5 3 &pcfg_pull_none>, 2027 <4 RK_PA0 3 &pcfg_pull_none>, 2028 <4 RK_PA5 3 &pcfg_pull_none>, 2029 <4 RK_PA4 3 &pcfg_pull_none>, 2030 <4 RK_PA1 3 &pcfg_pull_none>, 2031 <4 RK_PA2 3 &pcfg_pull_none>, 2032 <4 RK_PA3 3 &pcfg_pull_none>; 2033 }; 2034 }; 2035 2036 spdif { 2037 spdif_tx: spdif-tx { 2038 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; 2039 }; 2040 }; 2041 }; 2042}; 2043