1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2013 MundoReader S.L. 4 * Author: Heiko Stuebner <heiko@sntech.de> 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/clock/rk3188-cru.h> 10#include <dt-bindings/power/rk3188-power.h> 11#include "rk3xxx.dtsi" 12 13/ { 14 compatible = "rockchip,rk3188"; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 enable-method = "rockchip,rk3066-smp"; 20 21 cpu0: cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a9"; 24 next-level-cache = <&L2>; 25 reg = <0x0>; 26 clocks = <&cru ARMCLK>; 27 operating-points-v2 = <&cpu0_opp_table>; 28 resets = <&cru SRST_CORE0>; 29 }; 30 cpu1: cpu@1 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a9"; 33 next-level-cache = <&L2>; 34 reg = <0x1>; 35 operating-points-v2 = <&cpu0_opp_table>; 36 resets = <&cru SRST_CORE1>; 37 }; 38 cpu2: cpu@2 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a9"; 41 next-level-cache = <&L2>; 42 reg = <0x2>; 43 operating-points-v2 = <&cpu0_opp_table>; 44 resets = <&cru SRST_CORE2>; 45 }; 46 cpu3: cpu@3 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a9"; 49 next-level-cache = <&L2>; 50 reg = <0x3>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 resets = <&cru SRST_CORE3>; 53 }; 54 }; 55 56 cpu0_opp_table: opp-table-0 { 57 compatible = "operating-points-v2"; 58 opp-shared; 59 60 opp-312000000 { 61 opp-hz = /bits/ 64 <312000000>; 62 opp-microvolt = <875000>; 63 clock-latency-ns = <40000>; 64 }; 65 opp-504000000 { 66 opp-hz = /bits/ 64 <504000000>; 67 opp-microvolt = <925000>; 68 }; 69 opp-600000000 { 70 opp-hz = /bits/ 64 <600000000>; 71 opp-microvolt = <950000>; 72 opp-suspend; 73 }; 74 opp-816000000 { 75 opp-hz = /bits/ 64 <816000000>; 76 opp-microvolt = <975000>; 77 }; 78 opp-1008000000 { 79 opp-hz = /bits/ 64 <1008000000>; 80 opp-microvolt = <1075000>; 81 }; 82 opp-1200000000 { 83 opp-hz = /bits/ 64 <1200000000>; 84 opp-microvolt = <1150000>; 85 }; 86 opp-1416000000 { 87 opp-hz = /bits/ 64 <1416000000>; 88 opp-microvolt = <1250000>; 89 }; 90 opp-1608000000 { 91 opp-hz = /bits/ 64 <1608000000>; 92 opp-microvolt = <1350000>; 93 }; 94 }; 95 96 display-subsystem { 97 compatible = "rockchip,display-subsystem"; 98 ports = <&vop0_out>, <&vop1_out>; 99 }; 100 101 sram: sram@10080000 { 102 compatible = "mmio-sram"; 103 reg = <0x10080000 0x8000>; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 ranges = <0 0x10080000 0x8000>; 107 108 smp-sram@0 { 109 compatible = "rockchip,rk3066-smp-sram"; 110 reg = <0x0 0x50>; 111 }; 112 }; 113 114 vop0: vop@1010c000 { 115 compatible = "rockchip,rk3188-vop"; 116 reg = <0x1010c000 0x1000>; 117 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; 119 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 120 power-domains = <&power RK3188_PD_VIO>; 121 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; 122 reset-names = "axi", "ahb", "dclk"; 123 status = "disabled"; 124 125 vop0_out: port { 126 #address-cells = <1>; 127 #size-cells = <0>; 128 }; 129 }; 130 131 vop1: vop@1010e000 { 132 compatible = "rockchip,rk3188-vop"; 133 reg = <0x1010e000 0x1000>; 134 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; 136 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 137 power-domains = <&power RK3188_PD_VIO>; 138 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; 139 reset-names = "axi", "ahb", "dclk"; 140 status = "disabled"; 141 142 vop1_out: port { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 }; 146 }; 147 148 timer3: timer@2000e000 { 149 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; 150 reg = <0x2000e000 0x20>; 151 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>; 153 clock-names = "pclk", "timer"; 154 }; 155 156 timer6: timer@200380a0 { 157 compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; 158 reg = <0x200380a0 0x20>; 159 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>; 161 clock-names = "pclk", "timer"; 162 }; 163 164 i2s0: i2s@1011a000 { 165 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; 166 reg = <0x1011a000 0x2000>; 167 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&i2s0_bus>; 170 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; 171 clock-names = "i2s_clk", "i2s_hclk"; 172 dmas = <&dmac1_s 6>, <&dmac1_s 7>; 173 dma-names = "tx", "rx"; 174 rockchip,playback-channels = <2>; 175 rockchip,capture-channels = <2>; 176 #sound-dai-cells = <0>; 177 status = "disabled"; 178 }; 179 180 spdif: sound@1011e000 { 181 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; 182 reg = <0x1011e000 0x2000>; 183 #sound-dai-cells = <0>; 184 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; 185 clock-names = "mclk", "hclk"; 186 dmas = <&dmac1_s 8>; 187 dma-names = "tx"; 188 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 189 pinctrl-names = "default"; 190 pinctrl-0 = <&spdif_tx>; 191 status = "disabled"; 192 }; 193 194 cru: clock-controller@20000000 { 195 compatible = "rockchip,rk3188-cru"; 196 reg = <0x20000000 0x1000>; 197 clocks = <&xin24m>; 198 clock-names = "xin24m"; 199 rockchip,grf = <&grf>; 200 #clock-cells = <1>; 201 #reset-cells = <1>; 202 }; 203 204 efuse: efuse@20010000 { 205 compatible = "rockchip,rk3188-efuse"; 206 reg = <0x20010000 0x4000>; 207 #address-cells = <1>; 208 #size-cells = <1>; 209 clocks = <&cru PCLK_EFUSE>; 210 clock-names = "pclk_efuse"; 211 212 cpu_leakage: cpu_leakage@17 { 213 reg = <0x17 0x1>; 214 }; 215 }; 216 217 pinctrl: pinctrl { 218 compatible = "rockchip,rk3188-pinctrl"; 219 rockchip,grf = <&grf>; 220 rockchip,pmu = <&pmu>; 221 222 #address-cells = <1>; 223 #size-cells = <1>; 224 ranges; 225 226 gpio0: gpio@2000a000 { 227 compatible = "rockchip,rk3188-gpio-bank0"; 228 reg = <0x2000a000 0x100>; 229 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&cru PCLK_GPIO0>; 231 232 gpio-controller; 233 #gpio-cells = <2>; 234 235 interrupt-controller; 236 #interrupt-cells = <2>; 237 }; 238 239 gpio1: gpio@2003c000 { 240 compatible = "rockchip,gpio-bank"; 241 reg = <0x2003c000 0x100>; 242 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru PCLK_GPIO1>; 244 245 gpio-controller; 246 #gpio-cells = <2>; 247 248 interrupt-controller; 249 #interrupt-cells = <2>; 250 }; 251 252 gpio2: gpio@2003e000 { 253 compatible = "rockchip,gpio-bank"; 254 reg = <0x2003e000 0x100>; 255 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&cru PCLK_GPIO2>; 257 258 gpio-controller; 259 #gpio-cells = <2>; 260 261 interrupt-controller; 262 #interrupt-cells = <2>; 263 }; 264 265 gpio3: gpio@20080000 { 266 compatible = "rockchip,gpio-bank"; 267 reg = <0x20080000 0x100>; 268 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 269 clocks = <&cru PCLK_GPIO3>; 270 271 gpio-controller; 272 #gpio-cells = <2>; 273 274 interrupt-controller; 275 #interrupt-cells = <2>; 276 }; 277 278 pcfg_pull_up: pcfg-pull-up { 279 bias-pull-up; 280 }; 281 282 pcfg_pull_down: pcfg-pull-down { 283 bias-pull-down; 284 }; 285 286 pcfg_pull_none: pcfg-pull-none { 287 bias-disable; 288 }; 289 290 emmc { 291 emmc_clk: emmc-clk { 292 rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; 293 }; 294 295 emmc_cmd: emmc-cmd { 296 rockchip,pins = <0 RK_PD2 2 &pcfg_pull_up>; 297 }; 298 299 emmc_rst: emmc-rst { 300 rockchip,pins = <0 RK_PD3 2 &pcfg_pull_none>; 301 }; 302 303 /* 304 * The data pins are shared between nandc and emmc and 305 * not accessible through pinctrl. Also they should've 306 * been already set correctly by firmware, as 307 * flash/emmc is the boot-device. 308 */ 309 }; 310 311 emac { 312 emac_xfer: emac-xfer { 313 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>, /* tx_en */ 314 <3 RK_PC1 2 &pcfg_pull_none>, /* txd1 */ 315 <3 RK_PC2 2 &pcfg_pull_none>, /* txd0 */ 316 <3 RK_PC3 2 &pcfg_pull_none>, /* rxd0 */ 317 <3 RK_PC4 2 &pcfg_pull_none>, /* rxd1 */ 318 <3 RK_PC5 2 &pcfg_pull_none>, /* mac_clk */ 319 <3 RK_PC6 2 &pcfg_pull_none>, /* rx_err */ 320 <3 RK_PC7 2 &pcfg_pull_none>; /* crs_dvalid */ 321 }; 322 323 emac_mdio: emac-mdio { 324 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, 325 <3 RK_PD1 2 &pcfg_pull_none>; 326 }; 327 }; 328 329 i2c0 { 330 i2c0_xfer: i2c0-xfer { 331 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, 332 <1 RK_PD1 1 &pcfg_pull_none>; 333 }; 334 }; 335 336 i2c1 { 337 i2c1_xfer: i2c1-xfer { 338 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>, 339 <1 RK_PD3 1 &pcfg_pull_none>; 340 }; 341 }; 342 343 i2c2 { 344 i2c2_xfer: i2c2-xfer { 345 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>, 346 <1 RK_PD5 1 &pcfg_pull_none>; 347 }; 348 }; 349 350 i2c3 { 351 i2c3_xfer: i2c3-xfer { 352 rockchip,pins = <3 RK_PB6 2 &pcfg_pull_none>, 353 <3 RK_PB7 2 &pcfg_pull_none>; 354 }; 355 }; 356 357 i2c4 { 358 i2c4_xfer: i2c4-xfer { 359 rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, 360 <1 RK_PD7 1 &pcfg_pull_none>; 361 }; 362 }; 363 364 lcdc1 { 365 lcdc1_dclk: lcdc1-dclk { 366 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; 367 }; 368 369 lcdc1_den: lcdc1-den { 370 rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; 371 }; 372 373 lcdc1_hsync: lcdc1-hsync { 374 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; 375 }; 376 377 lcdc1_vsync: lcdc1-vsync { 378 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; 379 }; 380 381 lcdc1_rgb24: lcdc1-rgb24 { 382 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, 383 <2 RK_PA1 1 &pcfg_pull_none>, 384 <2 RK_PA2 1 &pcfg_pull_none>, 385 <2 RK_PA3 1 &pcfg_pull_none>, 386 <2 RK_PA4 1 &pcfg_pull_none>, 387 <2 RK_PA5 1 &pcfg_pull_none>, 388 <2 RK_PA6 1 &pcfg_pull_none>, 389 <2 RK_PA7 1 &pcfg_pull_none>, 390 <2 RK_PB0 1 &pcfg_pull_none>, 391 <2 RK_PB1 1 &pcfg_pull_none>, 392 <2 RK_PB2 1 &pcfg_pull_none>, 393 <2 RK_PB3 1 &pcfg_pull_none>, 394 <2 RK_PB4 1 &pcfg_pull_none>, 395 <2 RK_PB5 1 &pcfg_pull_none>, 396 <2 RK_PB6 1 &pcfg_pull_none>, 397 <2 RK_PB7 1 &pcfg_pull_none>, 398 <2 RK_PC0 1 &pcfg_pull_none>, 399 <2 RK_PC1 1 &pcfg_pull_none>, 400 <2 RK_PC2 1 &pcfg_pull_none>, 401 <2 RK_PC3 1 &pcfg_pull_none>, 402 <2 RK_PC4 1 &pcfg_pull_none>, 403 <2 RK_PC5 1 &pcfg_pull_none>, 404 <2 RK_PC6 1 &pcfg_pull_none>, 405 <2 RK_PC7 1 &pcfg_pull_none>; 406 }; 407 }; 408 409 pwm0 { 410 pwm0_out: pwm0-out { 411 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; 412 }; 413 }; 414 415 pwm1 { 416 pwm1_out: pwm1-out { 417 rockchip,pins = <3 RK_PD4 1 &pcfg_pull_none>; 418 }; 419 }; 420 421 pwm2 { 422 pwm2_out: pwm2-out { 423 rockchip,pins = <3 RK_PD5 1 &pcfg_pull_none>; 424 }; 425 }; 426 427 pwm3 { 428 pwm3_out: pwm3-out { 429 rockchip,pins = <3 RK_PD6 1 &pcfg_pull_none>; 430 }; 431 }; 432 433 spi0 { 434 spi0_clk: spi0-clk { 435 rockchip,pins = <1 RK_PA6 2 &pcfg_pull_up>; 436 }; 437 spi0_cs0: spi0-cs0 { 438 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_up>; 439 }; 440 spi0_tx: spi0-tx { 441 rockchip,pins = <1 RK_PA5 2 &pcfg_pull_up>; 442 }; 443 spi0_rx: spi0-rx { 444 rockchip,pins = <1 RK_PA4 2 &pcfg_pull_up>; 445 }; 446 spi0_cs1: spi0-cs1 { 447 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_up>; 448 }; 449 }; 450 451 spi1 { 452 spi1_clk: spi1-clk { 453 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_up>; 454 }; 455 spi1_cs0: spi1-cs0 { 456 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_up>; 457 }; 458 spi1_rx: spi1-rx { 459 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_up>; 460 }; 461 spi1_tx: spi1-tx { 462 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_up>; 463 }; 464 spi1_cs1: spi1-cs1 { 465 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; 466 }; 467 }; 468 469 uart0 { 470 uart0_xfer: uart0-xfer { 471 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, 472 <1 RK_PA1 1 &pcfg_pull_none>; 473 }; 474 475 uart0_cts: uart0-cts { 476 rockchip,pins = <1 RK_PA2 1 &pcfg_pull_none>; 477 }; 478 479 uart0_rts: uart0-rts { 480 rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; 481 }; 482 }; 483 484 uart1 { 485 uart1_xfer: uart1-xfer { 486 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, 487 <1 RK_PA5 1 &pcfg_pull_none>; 488 }; 489 490 uart1_cts: uart1-cts { 491 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 492 }; 493 494 uart1_rts: uart1-rts { 495 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_none>; 496 }; 497 }; 498 499 uart2 { 500 uart2_xfer: uart2-xfer { 501 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, 502 <1 RK_PB1 1 &pcfg_pull_none>; 503 }; 504 /* no rts / cts for uart2 */ 505 }; 506 507 uart3 { 508 uart3_xfer: uart3-xfer { 509 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_up>, 510 <1 RK_PB3 1 &pcfg_pull_none>; 511 }; 512 513 uart3_cts: uart3-cts { 514 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none>; 515 }; 516 517 uart3_rts: uart3-rts { 518 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_none>; 519 }; 520 }; 521 522 sd0 { 523 sd0_clk: sd0-clk { 524 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; 525 }; 526 527 sd0_cmd: sd0-cmd { 528 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; 529 }; 530 531 sd0_cd: sd0-cd { 532 rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; 533 }; 534 535 sd0_wp: sd0-wp { 536 rockchip,pins = <3 RK_PB1 1 &pcfg_pull_none>; 537 }; 538 539 sd0_pwr: sd0-pwr { 540 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; 541 }; 542 543 sd0_bus1: sd0-bus-width1 { 544 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; 545 }; 546 547 sd0_bus4: sd0-bus-width4 { 548 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>, 549 <3 RK_PA5 1 &pcfg_pull_none>, 550 <3 RK_PA6 1 &pcfg_pull_none>, 551 <3 RK_PA7 1 &pcfg_pull_none>; 552 }; 553 }; 554 555 sd1 { 556 sd1_clk: sd1-clk { 557 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; 558 }; 559 560 sd1_cmd: sd1-cmd { 561 rockchip,pins = <3 RK_PC0 1 &pcfg_pull_none>; 562 }; 563 564 sd1_cd: sd1-cd { 565 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>; 566 }; 567 568 sd1_wp: sd1-wp { 569 rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>; 570 }; 571 572 sd1_bus1: sd1-bus-width1 { 573 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>; 574 }; 575 576 sd1_bus4: sd1-bus-width4 { 577 rockchip,pins = <3 RK_PC1 1 &pcfg_pull_none>, 578 <3 RK_PC2 1 &pcfg_pull_none>, 579 <3 RK_PC3 1 &pcfg_pull_none>, 580 <3 RK_PC4 1 &pcfg_pull_none>; 581 }; 582 }; 583 584 i2s0 { 585 i2s0_bus: i2s0-bus { 586 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, 587 <1 RK_PC1 1 &pcfg_pull_none>, 588 <1 RK_PC2 1 &pcfg_pull_none>, 589 <1 RK_PC3 1 &pcfg_pull_none>, 590 <1 RK_PC4 1 &pcfg_pull_none>, 591 <1 RK_PC5 1 &pcfg_pull_none>; 592 }; 593 }; 594 595 spdif { 596 spdif_tx: spdif-tx { 597 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_none>; 598 }; 599 }; 600 }; 601}; 602 603&emac { 604 compatible = "rockchip,rk3188-emac"; 605}; 606 607&global_timer { 608 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 609}; 610 611&local_timer { 612 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 613}; 614 615&gpu { 616 compatible = "rockchip,rk3188-mali", "arm,mali-400"; 617 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 627 interrupt-names = "gp", 628 "gpmmu", 629 "pp0", 630 "ppmmu0", 631 "pp1", 632 "ppmmu1", 633 "pp2", 634 "ppmmu2", 635 "pp3", 636 "ppmmu3"; 637 power-domains = <&power RK3188_PD_GPU>; 638}; 639 640&grf { 641 compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd"; 642 643 io_domains: io-domains { 644 compatible = "rockchip,rk3188-io-voltage-domain"; 645 status = "disabled"; 646 }; 647 648 usbphy: usbphy { 649 compatible = "rockchip,rk3188-usb-phy"; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 status = "disabled"; 653 654 usbphy0: usb-phy@10c { 655 reg = <0x10c>; 656 clocks = <&cru SCLK_OTGPHY0>; 657 clock-names = "phyclk"; 658 #clock-cells = <0>; 659 #phy-cells = <0>; 660 }; 661 662 usbphy1: usb-phy@11c { 663 reg = <0x11c>; 664 clocks = <&cru SCLK_OTGPHY1>; 665 clock-names = "phyclk"; 666 #clock-cells = <0>; 667 #phy-cells = <0>; 668 }; 669 }; 670}; 671 672&i2c0 { 673 compatible = "rockchip,rk3188-i2c"; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&i2c0_xfer>; 676}; 677 678&i2c1 { 679 compatible = "rockchip,rk3188-i2c"; 680 pinctrl-names = "default"; 681 pinctrl-0 = <&i2c1_xfer>; 682}; 683 684&i2c2 { 685 compatible = "rockchip,rk3188-i2c"; 686 pinctrl-names = "default"; 687 pinctrl-0 = <&i2c2_xfer>; 688}; 689 690&i2c3 { 691 compatible = "rockchip,rk3188-i2c"; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&i2c3_xfer>; 694}; 695 696&i2c4 { 697 compatible = "rockchip,rk3188-i2c"; 698 pinctrl-names = "default"; 699 pinctrl-0 = <&i2c4_xfer>; 700}; 701 702&pmu { 703 power: power-controller { 704 compatible = "rockchip,rk3188-power-controller"; 705 #power-domain-cells = <1>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 709 power-domain@RK3188_PD_VIO { 710 reg = <RK3188_PD_VIO>; 711 clocks = <&cru ACLK_LCDC0>, 712 <&cru ACLK_LCDC1>, 713 <&cru DCLK_LCDC0>, 714 <&cru DCLK_LCDC1>, 715 <&cru HCLK_LCDC0>, 716 <&cru HCLK_LCDC1>, 717 <&cru SCLK_CIF0>, 718 <&cru ACLK_CIF0>, 719 <&cru HCLK_CIF0>, 720 <&cru ACLK_IPP>, 721 <&cru HCLK_IPP>, 722 <&cru ACLK_RGA>, 723 <&cru HCLK_RGA>; 724 pm_qos = <&qos_lcdc0>, 725 <&qos_lcdc1>, 726 <&qos_cif0>, 727 <&qos_ipp>, 728 <&qos_rga>; 729 #power-domain-cells = <0>; 730 }; 731 732 power-domain@RK3188_PD_VIDEO { 733 reg = <RK3188_PD_VIDEO>; 734 clocks = <&cru ACLK_VDPU>, 735 <&cru ACLK_VEPU>, 736 <&cru HCLK_VDPU>, 737 <&cru HCLK_VEPU>; 738 pm_qos = <&qos_vpu>; 739 #power-domain-cells = <0>; 740 }; 741 742 power-domain@RK3188_PD_GPU { 743 reg = <RK3188_PD_GPU>; 744 clocks = <&cru ACLK_GPU>; 745 pm_qos = <&qos_gpu>; 746 #power-domain-cells = <0>; 747 }; 748 }; 749}; 750 751&pwm0 { 752 pinctrl-names = "default"; 753 pinctrl-0 = <&pwm0_out>; 754}; 755 756&pwm1 { 757 pinctrl-names = "default"; 758 pinctrl-0 = <&pwm1_out>; 759}; 760 761&pwm2 { 762 pinctrl-names = "default"; 763 pinctrl-0 = <&pwm2_out>; 764}; 765 766&pwm3 { 767 pinctrl-names = "default"; 768 pinctrl-0 = <&pwm3_out>; 769}; 770 771&spi0 { 772 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; 773 pinctrl-names = "default"; 774 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 775}; 776 777&spi1 { 778 compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; 779 pinctrl-names = "default"; 780 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 781}; 782 783&uart0 { 784 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 785 pinctrl-names = "default"; 786 pinctrl-0 = <&uart0_xfer>; 787}; 788 789&uart1 { 790 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 791 pinctrl-names = "default"; 792 pinctrl-0 = <&uart1_xfer>; 793}; 794 795&uart2 { 796 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&uart2_xfer>; 799}; 800 801&uart3 { 802 compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart"; 803 pinctrl-names = "default"; 804 pinctrl-0 = <&uart3_xfer>; 805}; 806 807&vpu { 808 compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu"; 809 power-domains = <&power RK3188_PD_VIDEO>; 810}; 811 812&wdt { 813 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt"; 814}; 815