1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/N2H SoC 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g087"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 interrupt-parent = <&gic>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a55"; 23 reg = <0>; 24 device_type = "cpu"; 25 next-level-cache = <&L3_CA55>; 26 enable-method = "psci"; 27 }; 28 29 cpu1: cpu@100 { 30 compatible = "arm,cortex-a55"; 31 reg = <0x100>; 32 device_type = "cpu"; 33 next-level-cache = <&L3_CA55>; 34 enable-method = "psci"; 35 }; 36 37 cpu2: cpu@200 { 38 compatible = "arm,cortex-a55"; 39 reg = <0x200>; 40 device_type = "cpu"; 41 next-level-cache = <&L3_CA55>; 42 enable-method = "psci"; 43 }; 44 45 cpu3: cpu@300 { 46 compatible = "arm,cortex-a55"; 47 reg = <0x300>; 48 device_type = "cpu"; 49 next-level-cache = <&L3_CA55>; 50 enable-method = "psci"; 51 }; 52 53 L3_CA55: cache-controller-0 { 54 compatible = "cache"; 55 cache-unified; 56 cache-size = <0x100000>; 57 cache-level = <3>; 58 }; 59 }; 60 61 extal_clk: extal { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 /* This value must be overridden by the board */ 65 clock-frequency = <0>; 66 }; 67 68 pmu { 69 compatible = "arm,cortex-a55-pmu"; 70 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 71 }; 72 73 psci { 74 compatible = "arm,psci-1.0", "arm,psci-0.2"; 75 method = "smc"; 76 }; 77 78 soc: soc { 79 compatible = "simple-bus"; 80 #address-cells = <2>; 81 #size-cells = <2>; 82 ranges; 83 84 sci0: serial@80005000 { 85 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 86 reg = <0 0x80005000 0 0x400>; 87 interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>, 89 <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>, 90 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>; 91 interrupt-names = "eri", "rxi", "txi", "tei"; 92 clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 93 clock-names = "operation", "bus"; 94 power-domains = <&cpg>; 95 status = "disabled"; 96 }; 97 98 sci1: serial@80005400 { 99 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 100 reg = <0 0x80005400 0 0x400>; 101 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>, 103 <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>, 104 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 105 interrupt-names = "eri", "rxi", "txi", "tei"; 106 clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 107 clock-names = "operation", "bus"; 108 power-domains = <&cpg>; 109 status = "disabled"; 110 }; 111 112 sci2: serial@80005800 { 113 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 114 reg = <0 0x80005800 0 0x400>; 115 interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>, 117 <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>, 118 <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 119 interrupt-names = "eri", "rxi", "txi", "tei"; 120 clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 121 clock-names = "operation", "bus"; 122 power-domains = <&cpg>; 123 status = "disabled"; 124 }; 125 126 sci3: serial@80005c00 { 127 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 128 reg = <0 0x80005c00 0 0x400>; 129 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, 131 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 132 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 133 interrupt-names = "eri", "rxi", "txi", "tei"; 134 clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 135 clock-names = "operation", "bus"; 136 power-domains = <&cpg>; 137 status = "disabled"; 138 }; 139 140 sci4: serial@80006000 { 141 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 142 reg = <0 0x80006000 0 0x400>; 143 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>, 145 <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>, 146 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 147 interrupt-names = "eri", "rxi", "txi", "tei"; 148 clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 149 clock-names = "operation", "bus"; 150 power-domains = <&cpg>; 151 status = "disabled"; 152 }; 153 154 sci5: serial@81005000 { 155 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 156 reg = <0 0x81005000 0 0x400>; 157 interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>, 159 <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>, 160 <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; 161 interrupt-names = "eri", "rxi", "txi", "tei"; 162 clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 163 clock-names = "operation", "bus"; 164 power-domains = <&cpg>; 165 status = "disabled"; 166 }; 167 168 wdt0: watchdog@80082000 { 169 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 170 reg = <0 0x80082000 0 0x400>, 171 <0 0x81295100 0 0x04>; 172 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 173 clock-names = "pclk"; 174 power-domains = <&cpg>; 175 status = "disabled"; 176 }; 177 178 wdt1: watchdog@80082400 { 179 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 180 reg = <0 0x80082400 0 0x400>, 181 <0 0x81295104 0 0x04>; 182 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 183 clock-names = "pclk"; 184 power-domains = <&cpg>; 185 status = "disabled"; 186 }; 187 188 wdt2: watchdog@80082800 { 189 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 190 reg = <0 0x80082800 0 0x400>, 191 <0 0x81295108 0 0x04>; 192 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 193 clock-names = "pclk"; 194 power-domains = <&cpg>; 195 status = "disabled"; 196 }; 197 198 wdt3: watchdog@80082c00 { 199 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 200 reg = <0 0x80082c00 0 0x400>, 201 <0 0x8129510c 0 0x04>; 202 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 203 clock-names = "pclk"; 204 power-domains = <&cpg>; 205 status = "disabled"; 206 }; 207 208 wdt4: watchdog@80083000 { 209 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 210 reg = <0 0x80083000 0 0x400>, 211 <0 0x81295110 0 0x04>; 212 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 213 clock-names = "pclk"; 214 power-domains = <&cpg>; 215 status = "disabled"; 216 }; 217 218 wdt5: watchdog@80083400 { 219 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 220 reg = <0 0x80083400 0 0x400>, 221 <0 0x81295114 0 0x04>; 222 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 223 clock-names = "pclk"; 224 power-domains = <&cpg>; 225 status = "disabled"; 226 }; 227 228 i2c0: i2c@80088000 { 229 compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; 230 reg = <0 0x80088000 0 0x400>; 231 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>, 233 <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>, 234 <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>; 235 interrupt-names = "eei", "rxi", "txi", "tei"; 236 clocks = <&cpg CPG_MOD 100>; 237 power-domains = <&cpg>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 status = "disabled"; 241 }; 242 243 i2c1: i2c@80088400 { 244 compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; 245 reg = <0 0x80088400 0 0x400>; 246 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>, 248 <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>, 249 <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>; 250 interrupt-names = "eei", "rxi", "txi", "tei"; 251 clocks = <&cpg CPG_MOD 101>; 252 power-domains = <&cpg>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 status = "disabled"; 256 }; 257 258 i2c2: i2c@81008000 { 259 compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; 260 reg = <0 0x81008000 0 0x400>; 261 interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>, 263 <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 264 <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-names = "eei", "rxi", "txi", "tei"; 266 clocks = <&cpg CPG_MOD 601>; 267 power-domains = <&cpg>; 268 #address-cells = <1>; 269 #size-cells = <0>; 270 status = "disabled"; 271 }; 272 273 gmac0: ethernet@80100000 { 274 compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", 275 "snps,dwmac-5.20"; 276 reg = <0 0x80100000 0 0x10000>; 277 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 296 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 297 "rx-queue-0", "rx-queue-1", "rx-queue-2", 298 "rx-queue-3", "rx-queue-4", "rx-queue-5", 299 "rx-queue-6", "rx-queue-7", "tx-queue-0", 300 "tx-queue-1", "tx-queue-2", "tx-queue-3", 301 "tx-queue-4", "tx-queue-5", "tx-queue-6", 302 "tx-queue-7"; 303 clocks = <&cpg CPG_MOD 400>, 304 <&cpg CPG_CORE R9A09G087_CLK_PCLKH>, 305 <&cpg CPG_CORE R9A09G087_ETCLKB>; 306 clock-names = "stmmaceth", "pclk", "tx"; 307 resets = <&cpg 400>, <&cpg 401>; 308 reset-names = "stmmaceth", "ahb"; 309 power-domains = <&cpg>; 310 snps,multicast-filter-bins = <256>; 311 snps,perfect-filter-entries = <32>; 312 rx-fifo-depth = <8192>; 313 tx-fifo-depth = <8192>; 314 snps,fixed-burst; 315 snps,no-pbl-x8; 316 snps,force_thresh_dma_mode; 317 snps,axi-config = <&stmmac_axi_setup>; 318 snps,mtl-rx-config = <&mtl_rx_setup0>; 319 snps,mtl-tx-config = <&mtl_tx_setup0>; 320 snps,txpbl = <16>; 321 snps,rxpbl = <16>; 322 status = "disabled"; 323 324 mdio0: mdio { 325 compatible = "snps,dwmac-mdio"; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 }; 329 330 mtl_rx_setup0: rx-queues-config { 331 snps,rx-queues-to-use = <8>; 332 snps,rx-sched-sp; 333 334 queue0 { 335 snps,dcb-algorithm; 336 snps,priority = <0x1>; 337 snps,map-to-dma-channel = <0>; 338 }; 339 340 queue1 { 341 snps,dcb-algorithm; 342 snps,priority = <0x2>; 343 snps,map-to-dma-channel = <1>; 344 }; 345 346 queue2 { 347 snps,dcb-algorithm; 348 snps,priority = <0x4>; 349 snps,map-to-dma-channel = <2>; 350 }; 351 352 queue3 { 353 snps,dcb-algorithm; 354 snps,priority = <0x8>; 355 snps,map-to-dma-channel = <3>; 356 }; 357 358 queue4 { 359 snps,dcb-algorithm; 360 snps,priority = <0x10>; 361 snps,map-to-dma-channel = <4>; 362 }; 363 364 queue5 { 365 snps,dcb-algorithm; 366 snps,priority = <0x20>; 367 snps,map-to-dma-channel = <5>; 368 }; 369 370 queue6 { 371 snps,dcb-algorithm; 372 snps,priority = <0x40>; 373 snps,map-to-dma-channel = <6>; 374 }; 375 376 queue7 { 377 snps,dcb-algorithm; 378 snps,priority = <0x80>; 379 snps,map-to-dma-channel = <7>; 380 }; 381 }; 382 383 mtl_tx_setup0: tx-queues-config { 384 snps,tx-queues-to-use = <8>; 385 386 queue0 { 387 snps,dcb-algorithm; 388 }; 389 390 queue1 { 391 snps,dcb-algorithm; 392 }; 393 394 queue2 { 395 snps,dcb-algorithm; 396 }; 397 398 queue3 { 399 snps,dcb-algorithm; 400 }; 401 402 queue4 { 403 snps,dcb-algorithm; 404 }; 405 406 queue5 { 407 snps,dcb-algorithm; 408 }; 409 410 queue6 { 411 snps,dcb-algorithm; 412 }; 413 414 queue7 { 415 snps,dcb-algorithm; 416 }; 417 }; 418 }; 419 420 gmac1: ethernet@92000000 { 421 compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", 422 "snps,dwmac-5.20"; 423 reg = <0 0x92000000 0 0x10000>; 424 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 432 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>; 443 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 444 "rx-queue-0", "rx-queue-1", "rx-queue-2", 445 "rx-queue-3", "rx-queue-4", "rx-queue-5", 446 "rx-queue-6", "rx-queue-7", "tx-queue-0", 447 "tx-queue-1", "tx-queue-2", "tx-queue-3", 448 "tx-queue-4", "tx-queue-5", "tx-queue-6", 449 "tx-queue-7"; 450 clocks = <&cpg CPG_MOD 416>, 451 <&cpg CPG_CORE R9A09G087_CLK_PCLKAH>, 452 <&cpg CPG_CORE R9A09G087_ETCLKB>; 453 clock-names = "stmmaceth", "pclk", "tx"; 454 resets = <&cpg 416>, <&cpg 417>; 455 reset-names = "stmmaceth", "ahb"; 456 power-domains = <&cpg>; 457 snps,multicast-filter-bins = <256>; 458 snps,perfect-filter-entries = <32>; 459 rx-fifo-depth = <8192>; 460 tx-fifo-depth = <8192>; 461 snps,fixed-burst; 462 snps,no-pbl-x8; 463 snps,force_thresh_dma_mode; 464 snps,axi-config = <&stmmac_axi_setup>; 465 snps,mtl-rx-config = <&mtl_rx_setup1>; 466 snps,mtl-tx-config = <&mtl_tx_setup1>; 467 snps,txpbl = <16>; 468 snps,rxpbl = <16>; 469 status = "disabled"; 470 471 mdio1: mdio { 472 compatible = "snps,dwmac-mdio"; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 }; 476 477 mtl_rx_setup1: rx-queues-config { 478 snps,rx-queues-to-use = <8>; 479 snps,rx-sched-sp; 480 481 queue0 { 482 snps,dcb-algorithm; 483 snps,priority = <0x1>; 484 snps,map-to-dma-channel = <0>; 485 }; 486 487 queue1 { 488 snps,dcb-algorithm; 489 snps,priority = <0x2>; 490 snps,map-to-dma-channel = <1>; 491 }; 492 493 queue2 { 494 snps,dcb-algorithm; 495 snps,priority = <0x4>; 496 snps,map-to-dma-channel = <2>; 497 }; 498 499 queue3 { 500 snps,dcb-algorithm; 501 snps,priority = <0x8>; 502 snps,map-to-dma-channel = <3>; 503 }; 504 505 queue4 { 506 snps,dcb-algorithm; 507 snps,priority = <0x10>; 508 snps,map-to-dma-channel = <4>; 509 }; 510 511 queue5 { 512 snps,dcb-algorithm; 513 snps,priority = <0x20>; 514 snps,map-to-dma-channel = <5>; 515 }; 516 517 queue6 { 518 snps,dcb-algorithm; 519 snps,priority = <0x40>; 520 snps,map-to-dma-channel = <6>; 521 }; 522 523 queue7 { 524 snps,dcb-algorithm; 525 snps,priority = <0x80>; 526 snps,map-to-dma-channel = <7>; 527 }; 528 }; 529 530 mtl_tx_setup1: tx-queues-config { 531 snps,tx-queues-to-use = <8>; 532 533 queue0 { 534 snps,dcb-algorithm; 535 }; 536 537 queue1 { 538 snps,dcb-algorithm; 539 }; 540 541 queue2 { 542 snps,dcb-algorithm; 543 }; 544 545 queue3 { 546 snps,dcb-algorithm; 547 }; 548 549 queue4 { 550 snps,dcb-algorithm; 551 }; 552 553 queue5 { 554 snps,dcb-algorithm; 555 }; 556 557 queue6 { 558 snps,dcb-algorithm; 559 }; 560 561 queue7 { 562 snps,dcb-algorithm; 563 }; 564 }; 565 }; 566 567 gmac2: ethernet@92010000 { 568 compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", 569 "snps,dwmac-5.20"; 570 reg = <0 0x92010000 0 0x10000>; 571 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>, 579 <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 580 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>, 581 <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>, 583 <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; 590 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 591 "rx-queue-0", "rx-queue-1", "rx-queue-2", 592 "rx-queue-3", "rx-queue-4", "rx-queue-5", 593 "rx-queue-6", "rx-queue-7", "tx-queue-0", 594 "tx-queue-1", "tx-queue-2", "tx-queue-3", 595 "tx-queue-4", "tx-queue-5", "tx-queue-6", 596 "tx-queue-7"; 597 clocks = <&cpg CPG_MOD 417>, 598 <&cpg CPG_CORE R9A09G087_CLK_PCLKAH>, 599 <&cpg CPG_CORE R9A09G087_ETCLKB>; 600 clock-names = "stmmaceth", "pclk", "tx"; 601 resets = <&cpg 418>, <&cpg 419>; 602 reset-names = "stmmaceth", "ahb"; 603 power-domains = <&cpg>; 604 snps,multicast-filter-bins = <256>; 605 snps,perfect-filter-entries = <32>; 606 rx-fifo-depth = <8192>; 607 tx-fifo-depth = <8192>; 608 snps,fixed-burst; 609 snps,no-pbl-x8; 610 snps,force_thresh_dma_mode; 611 snps,axi-config = <&stmmac_axi_setup>; 612 snps,mtl-rx-config = <&mtl_rx_setup2>; 613 snps,mtl-tx-config = <&mtl_tx_setup2>; 614 snps,txpbl = <16>; 615 snps,rxpbl = <16>; 616 status = "disabled"; 617 618 mdio2: mdio { 619 compatible = "snps,dwmac-mdio"; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 }; 623 624 mtl_rx_setup2: rx-queues-config { 625 snps,rx-queues-to-use = <8>; 626 snps,rx-sched-sp; 627 628 queue0 { 629 snps,dcb-algorithm; 630 snps,priority = <0x1>; 631 snps,map-to-dma-channel = <0>; 632 }; 633 634 queue1 { 635 snps,dcb-algorithm; 636 snps,priority = <0x2>; 637 snps,map-to-dma-channel = <1>; 638 }; 639 640 queue2 { 641 snps,dcb-algorithm; 642 snps,priority = <0x4>; 643 snps,map-to-dma-channel = <2>; 644 }; 645 646 queue3 { 647 snps,dcb-algorithm; 648 snps,priority = <0x8>; 649 snps,map-to-dma-channel = <3>; 650 }; 651 652 queue4 { 653 snps,dcb-algorithm; 654 snps,priority = <0x10>; 655 snps,map-to-dma-channel = <4>; 656 }; 657 658 queue5 { 659 snps,dcb-algorithm; 660 snps,priority = <0x20>; 661 snps,map-to-dma-channel = <5>; 662 }; 663 664 queue6 { 665 snps,dcb-algorithm; 666 snps,priority = <0x40>; 667 snps,map-to-dma-channel = <6>; 668 }; 669 670 queue7 { 671 snps,dcb-algorithm; 672 snps,priority = <0x80>; 673 snps,map-to-dma-channel = <7>; 674 }; 675 }; 676 677 mtl_tx_setup2: tx-queues-config { 678 snps,tx-queues-to-use = <8>; 679 680 queue0 { 681 snps,dcb-algorithm; 682 }; 683 684 queue1 { 685 snps,dcb-algorithm; 686 }; 687 688 queue2 { 689 snps,dcb-algorithm; 690 }; 691 692 queue3 { 693 snps,dcb-algorithm; 694 }; 695 696 queue4 { 697 snps,dcb-algorithm; 698 }; 699 700 queue5 { 701 snps,dcb-algorithm; 702 }; 703 704 queue6 { 705 snps,dcb-algorithm; 706 }; 707 708 queue7 { 709 snps,dcb-algorithm; 710 }; 711 }; 712 }; 713 714 ethss: ethss@80110000 { 715 compatible = "renesas,r9a09g087-miic", "renesas,r9a09g077-miic"; 716 reg = <0 0x80110000 0 0x10000>; 717 clocks = <&cpg CPG_CORE R9A09G087_ETCLKE>, 718 <&cpg CPG_CORE R9A09G087_ETCLKB>, 719 <&cpg CPG_CORE R9A09G087_ETCLKD>, 720 <&cpg CPG_MOD 403>; 721 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; 722 resets = <&cpg 405>, <&cpg 406>; 723 reset-names = "rst", "crst"; 724 power-domains = <&cpg>; 725 status = "disabled"; 726 727 #address-cells = <1>; 728 #size-cells = <0>; 729 730 mii_conv0: mii-conv@0 { 731 reg = <0>; 732 status = "disabled"; 733 }; 734 735 mii_conv1: mii-conv@1 { 736 reg = <1>; 737 status = "disabled"; 738 }; 739 740 mii_conv2: mii-conv@2 { 741 reg = <2>; 742 status = "disabled"; 743 }; 744 745 mii_conv3: mii-conv@3 { 746 reg = <3>; 747 status = "disabled"; 748 }; 749 }; 750 751 cpg: clock-controller@80280000 { 752 compatible = "renesas,r9a09g087-cpg-mssr"; 753 reg = <0 0x80280000 0 0x1000>, 754 <0 0x81280000 0 0x9000>; 755 clocks = <&extal_clk>; 756 clock-names = "extal"; 757 #clock-cells = <2>; 758 #reset-cells = <1>; 759 #power-domain-cells = <0>; 760 }; 761 762 pinctrl: pinctrl@802c0000 { 763 compatible = "renesas,r9a09g087-pinctrl"; 764 reg = <0 0x802c0000 0 0x10000>, 765 <0 0x812c0000 0 0x10000>, 766 <0 0x802b0000 0 0x10000>; 767 reg-names = "nsr", "srs", "srn"; 768 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 769 gpio-controller; 770 #gpio-cells = <2>; 771 gpio-ranges = <&pinctrl 0 0 280>; 772 power-domains = <&cpg>; 773 }; 774 775 gic: interrupt-controller@83000000 { 776 compatible = "arm,gic-v3"; 777 reg = <0x0 0x83000000 0 0x40000>, 778 <0x0 0x83040000 0 0x160000>; 779 #interrupt-cells = <3>; 780 #address-cells = <0>; 781 interrupt-controller; 782 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 783 }; 784 785 adc0: adc@90014000 { 786 compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc"; 787 reg = <0 0x90014000 0 0x400>; 788 interrupts = <GIC_SPI 698 IRQ_TYPE_EDGE_RISING>, 789 <GIC_SPI 699 IRQ_TYPE_EDGE_RISING>, 790 <GIC_SPI 700 IRQ_TYPE_EDGE_RISING>, 791 <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 851 IRQ_TYPE_EDGE_RISING>, 794 <GIC_SPI 852 IRQ_TYPE_EDGE_RISING>; 795 interrupt-names = "adi", "gbadi", "gcadi", 796 "cmpai", "cmpbi", "wcmpm", "wcmpum"; 797 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, 798 <&cpg CPG_MOD 206>; 799 clock-names = "adclk", "pclk"; 800 power-domains = <&cpg>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 #io-channel-cells = <1>; 804 status = "disabled"; 805 }; 806 807 adc1: adc@90014400 { 808 compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc"; 809 reg = <0 0x90014400 0 0x400>; 810 interrupts = <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>, 811 <GIC_SPI 704 IRQ_TYPE_EDGE_RISING>, 812 <GIC_SPI 705 IRQ_TYPE_EDGE_RISING>, 813 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 853 IRQ_TYPE_EDGE_RISING>, 816 <GIC_SPI 854 IRQ_TYPE_EDGE_RISING>; 817 interrupt-names = "adi", "gbadi", "gcadi", 818 "cmpai", "cmpbi", "wcmpm", "wcmpum"; 819 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, 820 <&cpg CPG_MOD 207>; 821 clock-names = "adclk", "pclk"; 822 power-domains = <&cpg>; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 #io-channel-cells = <1>; 826 status = "disabled"; 827 }; 828 829 adc2: adc@80008000 { 830 compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc"; 831 reg = <0 0x80008000 0 0x400>; 832 interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>, 833 <GIC_SPI 709 IRQ_TYPE_EDGE_RISING>, 834 <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>, 835 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 855 IRQ_TYPE_EDGE_RISING>, 838 <GIC_SPI 856 IRQ_TYPE_EDGE_RISING>; 839 interrupt-names = "adi", "gbadi", "gcadi", 840 "cmpai", "cmpbi", "wcmpm", "wcmpum"; 841 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, 842 <&cpg CPG_MOD 225>; 843 clock-names = "adclk", "pclk"; 844 power-domains = <&cpg>; 845 #address-cells = <1>; 846 #size-cells = <0>; 847 #io-channel-cells = <1>; 848 status = "disabled"; 849 }; 850 851 ohci: usb@92040000 { 852 compatible = "generic-ohci"; 853 reg = <0 0x92040000 0 0x100>; 854 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&cpg CPG_MOD 408>; 856 phys = <&usb2_phy 1>; 857 phy-names = "usb"; 858 power-domains = <&cpg>; 859 status = "disabled"; 860 }; 861 862 ehci: usb@92040100 { 863 compatible = "generic-ehci"; 864 reg = <0 0x92040100 0 0x100>; 865 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 866 clocks = <&cpg CPG_MOD 408>; 867 phys = <&usb2_phy 2>; 868 phy-names = "usb"; 869 companion = <&ohci>; 870 power-domains = <&cpg>; 871 status = "disabled"; 872 }; 873 874 usb2_phy: usb-phy@92040200 { 875 compatible = "renesas,usb2-phy-r9a09g087", "renesas,usb2-phy-r9a09g077"; 876 reg = <0 0x92040200 0 0x700>; 877 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&cpg CPG_MOD 408>, 879 <&cpg CPG_CORE R9A09G087_USB_CLK>; 880 #phy-cells = <1>; 881 power-domains = <&cpg>; 882 status = "disabled"; 883 }; 884 885 hsusb: usb@92041000 { 886 compatible = "renesas,usbhs-r9a09g087", "renesas,usbhs-r9a09g077"; 887 reg = <0 0x92041000 0 0x1000>; 888 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&cpg CPG_MOD 408>; 892 phys = <&usb2_phy 3>; 893 phy-names = "usb"; 894 power-domains = <&cpg>; 895 status = "disabled"; 896 }; 897 898 sdhi0: mmc@92080000 { 899 compatible = "renesas,sdhi-r9a09g087", 900 "renesas,sdhi-r9a09g057"; 901 reg = <0x0 0x92080000 0 0x10000>; 902 interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&cpg CPG_MOD 1212>, 905 <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>; 906 clock-names = "aclk", "clkh"; 907 power-domains = <&cpg>; 908 status = "disabled"; 909 910 sdhi0_vqmmc: vqmmc-regulator { 911 regulator-name = "SDHI0-VQMMC"; 912 regulator-min-microvolt = <1800000>; 913 regulator-max-microvolt = <3300000>; 914 status = "disabled"; 915 }; 916 }; 917 918 sdhi1: mmc@92090000 { 919 compatible = "renesas,sdhi-r9a09g087", 920 "renesas,sdhi-r9a09g057"; 921 reg = <0x0 0x92090000 0 0x10000>; 922 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 924 clocks = <&cpg CPG_MOD 1213>, 925 <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>; 926 clock-names = "aclk", "clkh"; 927 power-domains = <&cpg>; 928 status = "disabled"; 929 930 sdhi1_vqmmc: vqmmc-regulator { 931 regulator-name = "SDHI1-VQMMC"; 932 regulator-min-microvolt = <1800000>; 933 regulator-max-microvolt = <3300000>; 934 status = "disabled"; 935 }; 936 }; 937 }; 938 939 stmmac_axi_setup: stmmac-axi-config { 940 snps,lpi_en; 941 snps,wr_osr_lmt = <0xf>; 942 snps,rd_osr_lmt = <0xf>; 943 snps,blen = <16 8 4 0 0 0 0>; 944 }; 945 946 timer { 947 compatible = "arm,armv8-timer"; 948 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 949 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 950 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 951 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 952 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 953 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 954 }; 955}; 956