1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) 4 * 5 * Copyright (C) 2018 Renesas Electronics Europe Limited 6 * 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r9a06g032-sysctrl.h> 11 12/ { 13 compatible = "renesas,r9a06g032"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a7"; 24 reg = <0>; 25 clocks = <&sysctrl R9A06G032_CLK_A7MP>; 26 }; 27 28 cpu@1 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a7"; 31 reg = <1>; 32 clocks = <&sysctrl R9A06G032_CLK_A7MP>; 33 enable-method = "renesas,r9a06g032-smp"; 34 cpu-release-addr = <0 0x4000c204>; 35 }; 36 }; 37 38 ext_jtag_clk: extjtagclk { 39 #clock-cells = <0>; 40 compatible = "fixed-clock"; 41 clock-frequency = <0>; 42 }; 43 44 ext_mclk: extmclk { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <40000000>; 48 }; 49 50 ext_rgmii_ref: extrgmiiref { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <0>; 54 }; 55 56 ext_rtc_clk: extrtcclk { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <0>; 60 }; 61 62 soc { 63 compatible = "simple-bus"; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 interrupt-parent = <&gic>; 67 ranges; 68 69 rtc0: rtc@40006000 { 70 compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; 71 reg = <0x40006000 0x1000>; 72 interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 73 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 74 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 75 interrupt-names = "alarm", "timer", "pps"; 76 clocks = <&sysctrl R9A06G032_HCLK_RTC>; 77 clock-names = "hclk"; 78 power-domains = <&sysctrl>; 79 status = "disabled"; 80 }; 81 82 wdt0: watchdog@40008000 { 83 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; 84 reg = <0x40008000 0x1000>; 85 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 86 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; 87 status = "disabled"; 88 }; 89 90 wdt1: watchdog@40009000 { 91 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; 92 reg = <0x40009000 0x1000>; 93 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>; 94 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; 95 status = "disabled"; 96 }; 97 98 sysctrl: system-controller@4000c000 { 99 compatible = "renesas,r9a06g032-sysctrl"; 100 reg = <0x4000c000 0x1000>; 101 status = "okay"; 102 #clock-cells = <1>; 103 #power-domain-cells = <0>; 104 105 clocks = <&ext_mclk>, <&ext_rtc_clk>, 106 <&ext_jtag_clk>, <&ext_rgmii_ref>; 107 clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 111 dmamux: dma-router@a0 { 112 compatible = "renesas,rzn1-dmamux"; 113 reg = <0xa0 4>; 114 #dma-cells = <6>; 115 dma-requests = <32>; 116 dma-masters = <&dma0 &dma1>; 117 }; 118 }; 119 120 udc: usb@4001e000 { 121 compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf"; 122 reg = <0x4001e000 0x2000>; 123 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&sysctrl R9A06G032_HCLK_USBF>, 126 <&sysctrl R9A06G032_HCLK_USBPM>; 127 clock-names = "hclkf", "hclkpm"; 128 power-domains = <&sysctrl>; 129 status = "disabled"; 130 }; 131 132 pci_usb: pci@40030000 { 133 compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; 134 device_type = "pci"; 135 clocks = <&sysctrl R9A06G032_HCLK_USBH>, 136 <&sysctrl R9A06G032_HCLK_USBPM>, 137 <&sysctrl R9A06G032_CLK_PCI_USB>; 138 clock-names = "hclkh", "hclkpm", "pciclk"; 139 power-domains = <&sysctrl>; 140 reg = <0x40030000 0xc00>, 141 <0x40020000 0x1100>; 142 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 145 bus-range = <0 0>; 146 #address-cells = <3>; 147 #size-cells = <2>; 148 #interrupt-cells = <1>; 149 ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; 150 /* Should map all possible DDR as inbound ranges, but 151 * the IP only supports a 256MB, 512MB, or 1GB window. 152 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) 153 */ 154 dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; 155 interrupt-map-mask = <0xf800 0 0 0x7>; 156 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 157 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 158 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 159 160 usb@1,0 { 161 reg = <0x800 0 0 0 0>; 162 phys = <&usbphy>; 163 phy-names = "usb"; 164 }; 165 166 usb@2,0 { 167 reg = <0x1000 0 0 0 0>; 168 phys = <&usbphy>; 169 phy-names = "usb"; 170 }; 171 }; 172 173 uart0: serial@40060000 { 174 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 175 reg = <0x40060000 0x400>; 176 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 177 reg-shift = <2>; 178 reg-io-width = <4>; 179 clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; 180 clock-names = "baudclk", "apb_pclk"; 181 status = "disabled"; 182 }; 183 184 uart1: serial@40061000 { 185 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 186 reg = <0x40061000 0x400>; 187 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 188 reg-shift = <2>; 189 reg-io-width = <4>; 190 clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>; 191 clock-names = "baudclk", "apb_pclk"; 192 status = "disabled"; 193 }; 194 195 uart2: serial@40062000 { 196 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 197 reg = <0x40062000 0x400>; 198 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 199 reg-shift = <2>; 200 reg-io-width = <4>; 201 clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>; 202 clock-names = "baudclk", "apb_pclk"; 203 status = "disabled"; 204 }; 205 206 uart3: serial@50000000 { 207 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 208 reg = <0x50000000 0x400>; 209 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 210 reg-shift = <2>; 211 reg-io-width = <4>; 212 clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; 213 clock-names = "baudclk", "apb_pclk"; 214 dmas = <&dmamux 1 0 0 0 1 1>, <&dmamux 0 0 0 0 0 1>; 215 dma-names = "tx", "rx"; 216 status = "disabled"; 217 }; 218 219 uart4: serial@50001000 { 220 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 221 reg = <0x50001000 0x400>; 222 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 223 reg-shift = <2>; 224 reg-io-width = <4>; 225 clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; 226 clock-names = "baudclk", "apb_pclk"; 227 dmas = <&dmamux 3 0 0 0 3 1>, <&dmamux 2 0 0 0 2 1>; 228 dma-names = "tx", "rx"; 229 status = "disabled"; 230 }; 231 232 uart5: serial@50002000 { 233 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 234 reg = <0x50002000 0x400>; 235 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 236 reg-shift = <2>; 237 reg-io-width = <4>; 238 clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; 239 clock-names = "baudclk", "apb_pclk"; 240 dmas = <&dmamux 5 0 0 0 5 1>, <&dmamux 4 0 0 0 4 1>; 241 dma-names = "tx", "rx"; 242 status = "disabled"; 243 }; 244 245 uart6: serial@50003000 { 246 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 247 reg = <0x50003000 0x400>; 248 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 249 reg-shift = <2>; 250 reg-io-width = <4>; 251 clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; 252 clock-names = "baudclk", "apb_pclk"; 253 dmas = <&dmamux 7 0 0 0 7 1>, <&dmamux 6 0 0 0 6 1>; 254 dma-names = "tx", "rx"; 255 status = "disabled"; 256 }; 257 258 uart7: serial@50004000 { 259 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 260 reg = <0x50004000 0x400>; 261 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 262 reg-shift = <2>; 263 reg-io-width = <4>; 264 clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; 265 clock-names = "baudclk", "apb_pclk"; 266 dmas = <&dmamux 5 0 0 0 21 1>, <&dmamux 4 0 0 0 20 1>; 267 dma-names = "tx", "rx"; 268 status = "disabled"; 269 }; 270 271 i2c1: i2c@40063000 { 272 compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c"; 273 reg = <0x40063000 0x100>; 274 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&sysctrl R9A06G032_HCLK_I2C0>, <&sysctrl R9A06G032_CLK_I2C0>; 276 clock-names = "ref", "pclk"; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 status = "disabled"; 280 }; 281 282 i2c2: i2c@40064000 { 283 compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c"; 284 reg = <0x40064000 0x100>; 285 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&sysctrl R9A06G032_HCLK_I2C1>, <&sysctrl R9A06G032_CLK_I2C1>; 287 clock-names = "ref", "pclk"; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 status = "disabled"; 291 }; 292 293 pinctrl: pinctrl@40067000 { 294 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; 295 reg = <0x40067000 0x1000>, <0x51000000 0x480>; 296 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; 297 clock-names = "bus"; 298 status = "okay"; 299 }; 300 301 sdio1: mmc@40100000 { 302 compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a"; 303 reg = <0x40100000 0x1000>; 304 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 306 interrupt-names = "int", "wakeup"; 307 clocks = <&sysctrl R9A06G032_CLK_SDIO0>, <&sysctrl R9A06G032_HCLK_SDIO0>; 308 clock-names = "clk_xin", "clk_ahb"; 309 no-1-8-v; 310 status = "disabled"; 311 }; 312 313 sdio2: mmc@40101000 { 314 compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a"; 315 reg = <0x40101000 0x1000>; 316 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 318 interrupt-names = "int", "wakeup"; 319 clocks = <&sysctrl R9A06G032_CLK_SDIO1>, <&sysctrl R9A06G032_HCLK_SDIO1>; 320 clock-names = "clk_xin", "clk_ahb"; 321 no-1-8-v; 322 status = "disabled"; 323 }; 324 325 nand_controller: nand-controller@40102000 { 326 compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc"; 327 reg = <0x40102000 0x2000>; 328 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; 330 clock-names = "hclk", "eclk"; 331 power-domains = <&sysctrl>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 status = "disabled"; 335 }; 336 337 dma0: dma-controller@40104000 { 338 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; 339 reg = <0x40104000 0x1000>; 340 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 341 clock-names = "hclk"; 342 clocks = <&sysctrl R9A06G032_HCLK_DMA0>; 343 dma-channels = <8>; 344 dma-requests = <16>; 345 dma-masters = <1>; 346 #dma-cells = <3>; 347 block_size = <0xfff>; 348 data-width = <8>; 349 }; 350 351 dma1: dma-controller@40105000 { 352 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; 353 reg = <0x40105000 0x1000>; 354 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 355 clock-names = "hclk"; 356 clocks = <&sysctrl R9A06G032_HCLK_DMA1>; 357 dma-channels = <8>; 358 dma-requests = <16>; 359 dma-masters = <1>; 360 #dma-cells = <3>; 361 block_size = <0xfff>; 362 data-width = <8>; 363 }; 364 365 gmac1: ethernet@44000000 { 366 compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; 367 reg = <0x44000000 0x2000>; 368 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 371 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 372 clocks = <&sysctrl R9A06G032_HCLK_GMAC0>; 373 clock-names = "stmmaceth"; 374 power-domains = <&sysctrl>; 375 snps,multicast-filter-bins = <256>; 376 snps,perfect-filter-entries = <128>; 377 tx-fifo-depth = <2048>; 378 rx-fifo-depth = <4096>; 379 pcs-handle = <&mii_conv1>; 380 status = "disabled"; 381 }; 382 383 gmac2: ethernet@44002000 { 384 compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; 385 reg = <0x44002000 0x2000>; 386 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 389 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 390 clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; 391 clock-names = "stmmaceth"; 392 power-domains = <&sysctrl>; 393 snps,multicast-filter-bins = <256>; 394 snps,perfect-filter-entries = <128>; 395 tx-fifo-depth = <2048>; 396 rx-fifo-depth = <4096>; 397 status = "disabled"; 398 }; 399 400 eth_miic: eth-miic@44030000 { 401 compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 reg = <0x44030000 0x10000>; 405 clocks = <&sysctrl R9A06G032_CLK_MII_REF>, 406 <&sysctrl R9A06G032_CLK_RGMII_REF>, 407 <&sysctrl R9A06G032_CLK_RMII_REF>, 408 <&sysctrl R9A06G032_HCLK_SWITCH_RG>; 409 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; 410 power-domains = <&sysctrl>; 411 status = "disabled"; 412 413 mii_conv1: mii-conv@1 { 414 reg = <1>; 415 status = "disabled"; 416 }; 417 418 mii_conv2: mii-conv@2 { 419 reg = <2>; 420 status = "disabled"; 421 }; 422 423 mii_conv3: mii-conv@3 { 424 reg = <3>; 425 status = "disabled"; 426 }; 427 428 mii_conv4: mii-conv@4 { 429 reg = <4>; 430 status = "disabled"; 431 }; 432 433 mii_conv5: mii-conv@5 { 434 reg = <5>; 435 status = "disabled"; 436 }; 437 }; 438 439 switch: switch@44050000 { 440 compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; 441 reg = <0x44050000 0x10000>; 442 clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, 443 <&sysctrl R9A06G032_CLK_SWITCH>; 444 clock-names = "hclk", "clk"; 445 power-domains = <&sysctrl>; 446 status = "disabled"; 447 448 ethernet-ports { 449 #address-cells = <1>; 450 #size-cells = <0>; 451 452 switch_port0: port@0 { 453 reg = <0>; 454 pcs-handle = <&mii_conv5>; 455 status = "disabled"; 456 }; 457 458 switch_port1: port@1 { 459 reg = <1>; 460 pcs-handle = <&mii_conv4>; 461 status = "disabled"; 462 }; 463 464 switch_port2: port@2 { 465 reg = <2>; 466 pcs-handle = <&mii_conv3>; 467 status = "disabled"; 468 }; 469 470 switch_port3: port@3 { 471 reg = <3>; 472 pcs-handle = <&mii_conv2>; 473 status = "disabled"; 474 }; 475 476 switch_port4: port@4 { 477 reg = <4>; 478 ethernet = <&gmac2>; 479 label = "cpu"; 480 phy-mode = "internal"; 481 status = "disabled"; 482 fixed-link { 483 speed = <1000>; 484 full-duplex; 485 }; 486 }; 487 }; 488 }; 489 490 gic: interrupt-controller@44101000 { 491 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 492 interrupt-controller; 493 #interrupt-cells = <3>; 494 reg = <0x44101000 0x1000>, /* Distributer */ 495 <0x44102000 0x2000>, /* CPU interface */ 496 <0x44104000 0x2000>, /* Virt interface control */ 497 <0x44106000 0x2000>; /* Virt CPU interface */ 498 interrupts = 499 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 500 }; 501 502 can0: can@52104000 { 503 compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; 504 reg = <0x52104000 0x800>; 505 reg-io-width = <4>; 506 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&sysctrl R9A06G032_HCLK_CAN0>; 508 power-domains = <&sysctrl>; 509 status = "disabled"; 510 }; 511 512 can1: can@52105000 { 513 compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; 514 reg = <0x52105000 0x800>; 515 reg-io-width = <4>; 516 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 517 clocks = <&sysctrl R9A06G032_HCLK_CAN1>; 518 power-domains = <&sysctrl>; 519 status = "disabled"; 520 }; 521 }; 522 523 timer { 524 compatible = "arm,armv7-timer"; 525 interrupt-parent = <&gic>; 526 arm,cpu-registers-not-fw-configured; 527 always-on; 528 interrupts = 529 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 530 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 531 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 532 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 533 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; 534 }; 535 536 usbphy: usb-phy { 537 #phy-cells = <0>; 538 compatible = "usb-nop-xceiv"; 539 status = "disabled"; 540 }; 541}; 542