1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car D3 (R8A77995) SoC 4 * 5 * Copyright (C) 2016 Renesas Electronics Corp. 6 * Copyright (C) 2017 Glider bvba 7 */ 8 9#include <dt-bindings/clock/r8a77995-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/r8a77995-sysc.h> 12 13/ { 14 compatible = "renesas,r8a77995"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 /* 19 * The external audio clocks are configured as 0 Hz fixed frequency 20 * clocks by default. 21 * Boards that provide audio clocks should override them. 22 */ 23 audio_clk_a: audio_clk_a { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <0>; 27 }; 28 29 audio_clk_b: audio_clk_b { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <0>; 33 }; 34 35 /* External CAN clock - to be overridden by boards that provide it */ 36 can_clk: can { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 a53_0: cpu@0 { 47 compatible = "arm,cortex-a53"; 48 reg = <0x0>; 49 device_type = "cpu"; 50 power-domains = <&sysc R8A77995_PD_CA53_CPU0>; 51 next-level-cache = <&L2_CA53>; 52 enable-method = "psci"; 53 }; 54 55 L2_CA53: cache-controller-1 { 56 compatible = "cache"; 57 power-domains = <&sysc R8A77995_PD_CA53_SCU>; 58 cache-unified; 59 cache-level = <2>; 60 }; 61 }; 62 63 extal_clk: extal { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 /* This value must be overridden by the board */ 67 clock-frequency = <0>; 68 bootph-all; 69 }; 70 71 pmu_a53 { 72 compatible = "arm,cortex-a53-pmu"; 73 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 74 }; 75 76 psci { 77 compatible = "arm,psci-1.0", "arm,psci-0.2"; 78 method = "smc"; 79 }; 80 81 scif_clk: scif { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <0>; 85 }; 86 87 soc { 88 compatible = "simple-bus"; 89 interrupt-parent = <&gic>; 90 bootph-all; 91 92 #address-cells = <2>; 93 #size-cells = <2>; 94 ranges; 95 96 rwdt: watchdog@e6020000 { 97 compatible = "renesas,r8a77995-wdt", 98 "renesas,rcar-gen3-wdt"; 99 reg = <0 0xe6020000 0 0x0c>; 100 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 101 clocks = <&cpg CPG_MOD 402>; 102 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 103 resets = <&cpg 402>; 104 status = "disabled"; 105 }; 106 107 gpio0: gpio@e6050000 { 108 compatible = "renesas,gpio-r8a77995", 109 "renesas,rcar-gen3-gpio"; 110 reg = <0 0xe6050000 0 0x50>; 111 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 112 #gpio-cells = <2>; 113 gpio-controller; 114 gpio-ranges = <&pfc 0 0 9>; 115 #interrupt-cells = <2>; 116 interrupt-controller; 117 clocks = <&cpg CPG_MOD 912>; 118 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 119 resets = <&cpg 912>; 120 }; 121 122 gpio1: gpio@e6051000 { 123 compatible = "renesas,gpio-r8a77995", 124 "renesas,rcar-gen3-gpio"; 125 reg = <0 0xe6051000 0 0x50>; 126 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 127 #gpio-cells = <2>; 128 gpio-controller; 129 gpio-ranges = <&pfc 0 32 32>; 130 #interrupt-cells = <2>; 131 interrupt-controller; 132 clocks = <&cpg CPG_MOD 911>; 133 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 134 resets = <&cpg 911>; 135 }; 136 137 gpio2: gpio@e6052000 { 138 compatible = "renesas,gpio-r8a77995", 139 "renesas,rcar-gen3-gpio"; 140 reg = <0 0xe6052000 0 0x50>; 141 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 142 #gpio-cells = <2>; 143 gpio-controller; 144 gpio-ranges = <&pfc 0 64 32>; 145 #interrupt-cells = <2>; 146 interrupt-controller; 147 clocks = <&cpg CPG_MOD 910>; 148 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 149 resets = <&cpg 910>; 150 }; 151 152 gpio3: gpio@e6053000 { 153 compatible = "renesas,gpio-r8a77995", 154 "renesas,rcar-gen3-gpio"; 155 reg = <0 0xe6053000 0 0x50>; 156 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 157 #gpio-cells = <2>; 158 gpio-controller; 159 gpio-ranges = <&pfc 0 96 10>; 160 #interrupt-cells = <2>; 161 interrupt-controller; 162 clocks = <&cpg CPG_MOD 909>; 163 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 164 resets = <&cpg 909>; 165 }; 166 167 gpio4: gpio@e6054000 { 168 compatible = "renesas,gpio-r8a77995", 169 "renesas,rcar-gen3-gpio"; 170 reg = <0 0xe6054000 0 0x50>; 171 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 172 #gpio-cells = <2>; 173 gpio-controller; 174 gpio-ranges = <&pfc 0 128 32>; 175 #interrupt-cells = <2>; 176 interrupt-controller; 177 clocks = <&cpg CPG_MOD 908>; 178 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 179 resets = <&cpg 908>; 180 }; 181 182 gpio5: gpio@e6055000 { 183 compatible = "renesas,gpio-r8a77995", 184 "renesas,rcar-gen3-gpio"; 185 reg = <0 0xe6055000 0 0x50>; 186 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 187 #gpio-cells = <2>; 188 gpio-controller; 189 gpio-ranges = <&pfc 0 160 21>; 190 #interrupt-cells = <2>; 191 interrupt-controller; 192 clocks = <&cpg CPG_MOD 907>; 193 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 194 resets = <&cpg 907>; 195 }; 196 197 gpio6: gpio@e6055400 { 198 compatible = "renesas,gpio-r8a77995", 199 "renesas,rcar-gen3-gpio"; 200 reg = <0 0xe6055400 0 0x50>; 201 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 202 #gpio-cells = <2>; 203 gpio-controller; 204 gpio-ranges = <&pfc 0 192 14>; 205 #interrupt-cells = <2>; 206 interrupt-controller; 207 clocks = <&cpg CPG_MOD 906>; 208 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 209 resets = <&cpg 906>; 210 }; 211 212 pfc: pinctrl@e6060000 { 213 compatible = "renesas,pfc-r8a77995"; 214 reg = <0 0xe6060000 0 0x508>; 215 bootph-all; 216 }; 217 218 cmt0: timer@e60f0000 { 219 compatible = "renesas,r8a77995-cmt0", 220 "renesas,rcar-gen3-cmt0"; 221 reg = <0 0xe60f0000 0 0x1004>; 222 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 224 clocks = <&cpg CPG_MOD 303>; 225 clock-names = "fck"; 226 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 227 resets = <&cpg 303>; 228 status = "disabled"; 229 }; 230 231 cmt1: timer@e6130000 { 232 compatible = "renesas,r8a77995-cmt1", 233 "renesas,rcar-gen3-cmt1"; 234 reg = <0 0xe6130000 0 0x1004>; 235 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cpg CPG_MOD 302>; 244 clock-names = "fck"; 245 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 246 resets = <&cpg 302>; 247 status = "disabled"; 248 }; 249 250 cmt2: timer@e6140000 { 251 compatible = "renesas,r8a77995-cmt1", 252 "renesas,rcar-gen3-cmt1"; 253 reg = <0 0xe6140000 0 0x1004>; 254 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&cpg CPG_MOD 301>; 263 clock-names = "fck"; 264 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 265 resets = <&cpg 301>; 266 status = "disabled"; 267 }; 268 269 cmt3: timer@e6148000 { 270 compatible = "renesas,r8a77995-cmt1", 271 "renesas,rcar-gen3-cmt1"; 272 reg = <0 0xe6148000 0 0x1004>; 273 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&cpg CPG_MOD 300>; 282 clock-names = "fck"; 283 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 284 resets = <&cpg 300>; 285 status = "disabled"; 286 }; 287 288 cpg: clock-controller@e6150000 { 289 compatible = "renesas,r8a77995-cpg-mssr"; 290 reg = <0 0xe6150000 0 0x1000>; 291 clocks = <&extal_clk>; 292 clock-names = "extal"; 293 #clock-cells = <2>; 294 #power-domain-cells = <0>; 295 #reset-cells = <1>; 296 bootph-all; 297 }; 298 299 rst: reset-controller@e6160000 { 300 compatible = "renesas,r8a77995-rst"; 301 reg = <0 0xe6160000 0 0x0200>; 302 bootph-all; 303 }; 304 305 sysc: system-controller@e6180000 { 306 compatible = "renesas,r8a77995-sysc"; 307 reg = <0 0xe6180000 0 0x0400>; 308 #power-domain-cells = <1>; 309 }; 310 311 thermal: thermal@e6190000 { 312 compatible = "renesas,thermal-r8a77995"; 313 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 314 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&cpg CPG_MOD 522>; 318 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 319 resets = <&cpg 522>; 320 #thermal-sensor-cells = <0>; 321 }; 322 323 intc_ex: interrupt-controller@e61c0000 { 324 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; 325 #interrupt-cells = <2>; 326 interrupt-controller; 327 reg = <0 0xe61c0000 0 0x200>; 328 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 334 clocks = <&cpg CPG_MOD 407>; 335 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 336 resets = <&cpg 407>; 337 }; 338 339 tmu0: timer@e61e0000 { 340 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 341 reg = <0 0xe61e0000 0 0x30>; 342 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 345 interrupt-names = "tuni0", "tuni1", "tuni2"; 346 clocks = <&cpg CPG_MOD 125>; 347 clock-names = "fck"; 348 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 349 resets = <&cpg 125>; 350 status = "disabled"; 351 }; 352 353 tmu1: timer@e6fc0000 { 354 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 355 reg = <0 0xe6fc0000 0 0x30>; 356 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 357 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 358 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 360 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 361 clocks = <&cpg CPG_MOD 124>; 362 clock-names = "fck"; 363 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 364 resets = <&cpg 124>; 365 status = "disabled"; 366 }; 367 368 tmu2: timer@e6fd0000 { 369 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 370 reg = <0 0xe6fd0000 0 0x30>; 371 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 375 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 376 clocks = <&cpg CPG_MOD 123>; 377 clock-names = "fck"; 378 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 379 resets = <&cpg 123>; 380 status = "disabled"; 381 }; 382 383 tmu3: timer@e6fe0000 { 384 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 385 reg = <0 0xe6fe0000 0 0x30>; 386 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 389 interrupt-names = "tuni0", "tuni1", "tuni2"; 390 clocks = <&cpg CPG_MOD 122>; 391 clock-names = "fck"; 392 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 393 resets = <&cpg 122>; 394 status = "disabled"; 395 }; 396 397 tmu4: timer@ffc00000 { 398 compatible = "renesas,tmu-r8a77995", "renesas,tmu"; 399 reg = <0 0xffc00000 0 0x30>; 400 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 403 interrupt-names = "tuni0", "tuni1", "tuni2"; 404 clocks = <&cpg CPG_MOD 121>; 405 clock-names = "fck"; 406 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 407 resets = <&cpg 121>; 408 status = "disabled"; 409 }; 410 411 i2c0: i2c@e6500000 { 412 #address-cells = <1>; 413 #size-cells = <0>; 414 compatible = "renesas,i2c-r8a77995", 415 "renesas,rcar-gen3-i2c"; 416 reg = <0 0xe6500000 0 0x40>; 417 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&cpg CPG_MOD 931>; 419 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 420 resets = <&cpg 931>; 421 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 422 <&dmac2 0x91>, <&dmac2 0x90>; 423 dma-names = "tx", "rx", "tx", "rx"; 424 i2c-scl-internal-delay-ns = <6>; 425 status = "disabled"; 426 }; 427 428 i2c1: i2c@e6508000 { 429 #address-cells = <1>; 430 #size-cells = <0>; 431 compatible = "renesas,i2c-r8a77995", 432 "renesas,rcar-gen3-i2c"; 433 reg = <0 0xe6508000 0 0x40>; 434 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&cpg CPG_MOD 930>; 436 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 437 resets = <&cpg 930>; 438 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 439 <&dmac2 0x93>, <&dmac2 0x92>; 440 dma-names = "tx", "rx", "tx", "rx"; 441 i2c-scl-internal-delay-ns = <6>; 442 status = "disabled"; 443 }; 444 445 i2c2: i2c@e6510000 { 446 #address-cells = <1>; 447 #size-cells = <0>; 448 compatible = "renesas,i2c-r8a77995", 449 "renesas,rcar-gen3-i2c"; 450 reg = <0 0xe6510000 0 0x40>; 451 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&cpg CPG_MOD 929>; 453 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 454 resets = <&cpg 929>; 455 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 456 <&dmac2 0x95>, <&dmac2 0x94>; 457 dma-names = "tx", "rx", "tx", "rx"; 458 i2c-scl-internal-delay-ns = <6>; 459 status = "disabled"; 460 }; 461 462 i2c3: i2c@e66d0000 { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 compatible = "renesas,i2c-r8a77995", 466 "renesas,rcar-gen3-i2c"; 467 reg = <0 0xe66d0000 0 0x40>; 468 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&cpg CPG_MOD 928>; 470 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 471 resets = <&cpg 928>; 472 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 473 dma-names = "tx", "rx"; 474 i2c-scl-internal-delay-ns = <6>; 475 status = "disabled"; 476 }; 477 478 hscif0: serial@e6540000 { 479 compatible = "renesas,hscif-r8a77995", 480 "renesas,rcar-gen3-hscif", 481 "renesas,hscif"; 482 reg = <0 0xe6540000 0 0x60>; 483 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&cpg CPG_MOD 520>, 485 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 486 <&scif_clk>; 487 clock-names = "fck", "brg_int", "scif_clk"; 488 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 489 <&dmac2 0x31>, <&dmac2 0x30>; 490 dma-names = "tx", "rx", "tx", "rx"; 491 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 492 resets = <&cpg 520>; 493 status = "disabled"; 494 }; 495 496 hscif3: serial@e66a0000 { 497 compatible = "renesas,hscif-r8a77995", 498 "renesas,rcar-gen3-hscif", 499 "renesas,hscif"; 500 reg = <0 0xe66a0000 0 0x60>; 501 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&cpg CPG_MOD 517>, 503 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 504 <&scif_clk>; 505 clock-names = "fck", "brg_int", "scif_clk"; 506 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 507 dma-names = "tx", "rx"; 508 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 509 resets = <&cpg 517>; 510 status = "disabled"; 511 }; 512 513 hsusb: usb@e6590000 { 514 compatible = "renesas,usbhs-r8a77995", 515 "renesas,rcar-gen3-usbhs"; 516 reg = <0 0xe6590000 0 0x200>; 517 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 519 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 520 <&usb_dmac1 0>, <&usb_dmac1 1>; 521 dma-names = "ch0", "ch1", "ch2", "ch3"; 522 renesas,buswait = <11>; 523 phys = <&usb2_phy0 3>; 524 phy-names = "usb"; 525 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 526 resets = <&cpg 704>, <&cpg 703>; 527 status = "disabled"; 528 }; 529 530 usb_dmac0: dma-controller@e65a0000 { 531 compatible = "renesas,r8a77995-usb-dmac", 532 "renesas,usb-dmac"; 533 reg = <0 0xe65a0000 0 0x100>; 534 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 536 interrupt-names = "ch0", "ch1"; 537 clocks = <&cpg CPG_MOD 330>; 538 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 539 resets = <&cpg 330>; 540 #dma-cells = <1>; 541 dma-channels = <2>; 542 }; 543 544 usb_dmac1: dma-controller@e65b0000 { 545 compatible = "renesas,r8a77995-usb-dmac", 546 "renesas,usb-dmac"; 547 reg = <0 0xe65b0000 0 0x100>; 548 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 550 interrupt-names = "ch0", "ch1"; 551 clocks = <&cpg CPG_MOD 331>; 552 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 553 resets = <&cpg 331>; 554 #dma-cells = <1>; 555 dma-channels = <2>; 556 }; 557 558 arm_cc630p: crypto@e6601000 { 559 compatible = "arm,cryptocell-630p-ree"; 560 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 561 reg = <0x0 0xe6601000 0 0x1000>; 562 clocks = <&cpg CPG_MOD 229>; 563 resets = <&cpg 229>; 564 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 565 }; 566 567 canfd: can@e66c0000 { 568 compatible = "renesas,r8a77995-canfd", 569 "renesas,rcar-gen3-canfd"; 570 reg = <0 0xe66c0000 0 0x8000>; 571 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 573 interrupt-names = "ch_int", "g_int"; 574 clocks = <&cpg CPG_MOD 914>, 575 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 576 <&can_clk>; 577 clock-names = "fck", "canfd", "can_clk"; 578 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 579 assigned-clock-rates = <40000000>; 580 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 581 resets = <&cpg 914>; 582 status = "disabled"; 583 584 channel0 { 585 status = "disabled"; 586 }; 587 588 channel1 { 589 status = "disabled"; 590 }; 591 }; 592 593 dmac0: dma-controller@e6700000 { 594 compatible = "renesas,dmac-r8a77995", 595 "renesas,rcar-dmac"; 596 reg = <0 0xe6700000 0 0x10000>; 597 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 606 interrupt-names = "error", 607 "ch0", "ch1", "ch2", "ch3", 608 "ch4", "ch5", "ch6", "ch7"; 609 clocks = <&cpg CPG_MOD 219>; 610 clock-names = "fck"; 611 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 612 resets = <&cpg 219>; 613 #dma-cells = <1>; 614 dma-channels = <8>; 615 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 616 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 617 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 618 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>; 619 }; 620 621 dmac1: dma-controller@e7300000 { 622 compatible = "renesas,dmac-r8a77995", 623 "renesas,rcar-dmac"; 624 reg = <0 0xe7300000 0 0x10000>; 625 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 634 interrupt-names = "error", 635 "ch0", "ch1", "ch2", "ch3", 636 "ch4", "ch5", "ch6", "ch7"; 637 clocks = <&cpg CPG_MOD 218>; 638 clock-names = "fck"; 639 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 640 resets = <&cpg 218>; 641 #dma-cells = <1>; 642 dma-channels = <8>; 643 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 644 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 645 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 646 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; 647 }; 648 649 dmac2: dma-controller@e7310000 { 650 compatible = "renesas,dmac-r8a77995", 651 "renesas,rcar-dmac"; 652 reg = <0 0xe7310000 0 0x10000>; 653 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 662 interrupt-names = "error", 663 "ch0", "ch1", "ch2", "ch3", 664 "ch4", "ch5", "ch6", "ch7"; 665 clocks = <&cpg CPG_MOD 217>; 666 clock-names = "fck"; 667 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 668 resets = <&cpg 217>; 669 #dma-cells = <1>; 670 dma-channels = <8>; 671 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 672 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 673 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 674 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 675 }; 676 677 ipmmu_ds0: iommu@e6740000 { 678 compatible = "renesas,ipmmu-r8a77995"; 679 reg = <0 0xe6740000 0 0x1000>; 680 renesas,ipmmu-main = <&ipmmu_mm 0>; 681 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 682 #iommu-cells = <1>; 683 }; 684 685 ipmmu_ds1: iommu@e7740000 { 686 compatible = "renesas,ipmmu-r8a77995"; 687 reg = <0 0xe7740000 0 0x1000>; 688 renesas,ipmmu-main = <&ipmmu_mm 1>; 689 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 690 #iommu-cells = <1>; 691 }; 692 693 ipmmu_hc: iommu@e6570000 { 694 compatible = "renesas,ipmmu-r8a77995"; 695 reg = <0 0xe6570000 0 0x1000>; 696 renesas,ipmmu-main = <&ipmmu_mm 2>; 697 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 698 #iommu-cells = <1>; 699 }; 700 701 ipmmu_mm: iommu@e67b0000 { 702 compatible = "renesas,ipmmu-r8a77995"; 703 reg = <0 0xe67b0000 0 0x1000>; 704 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 706 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 707 #iommu-cells = <1>; 708 }; 709 710 ipmmu_mp: iommu@ec670000 { 711 compatible = "renesas,ipmmu-r8a77995"; 712 reg = <0 0xec670000 0 0x1000>; 713 renesas,ipmmu-main = <&ipmmu_mm 4>; 714 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 715 #iommu-cells = <1>; 716 }; 717 718 ipmmu_pv0: iommu@fd800000 { 719 compatible = "renesas,ipmmu-r8a77995"; 720 reg = <0 0xfd800000 0 0x1000>; 721 renesas,ipmmu-main = <&ipmmu_mm 6>; 722 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 723 #iommu-cells = <1>; 724 }; 725 726 ipmmu_rt: iommu@ffc80000 { 727 compatible = "renesas,ipmmu-r8a77995"; 728 reg = <0 0xffc80000 0 0x1000>; 729 renesas,ipmmu-main = <&ipmmu_mm 10>; 730 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 731 #iommu-cells = <1>; 732 }; 733 734 ipmmu_vc0: iommu@fe6b0000 { 735 compatible = "renesas,ipmmu-r8a77995"; 736 reg = <0 0xfe6b0000 0 0x1000>; 737 renesas,ipmmu-main = <&ipmmu_mm 12>; 738 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 739 #iommu-cells = <1>; 740 }; 741 742 ipmmu_vi0: iommu@febd0000 { 743 compatible = "renesas,ipmmu-r8a77995"; 744 reg = <0 0xfebd0000 0 0x1000>; 745 renesas,ipmmu-main = <&ipmmu_mm 14>; 746 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 747 #iommu-cells = <1>; 748 }; 749 750 ipmmu_vp0: iommu@fe990000 { 751 compatible = "renesas,ipmmu-r8a77995"; 752 reg = <0 0xfe990000 0 0x1000>; 753 renesas,ipmmu-main = <&ipmmu_mm 16>; 754 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 755 #iommu-cells = <1>; 756 }; 757 758 avb: ethernet@e6800000 { 759 compatible = "renesas,etheravb-r8a77995", 760 "renesas,etheravb-rcar-gen3"; 761 reg = <0 0xe6800000 0 0x800>; 762 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 787 interrupt-names = "ch0", "ch1", "ch2", "ch3", 788 "ch4", "ch5", "ch6", "ch7", 789 "ch8", "ch9", "ch10", "ch11", 790 "ch12", "ch13", "ch14", "ch15", 791 "ch16", "ch17", "ch18", "ch19", 792 "ch20", "ch21", "ch22", "ch23", 793 "ch24"; 794 clocks = <&cpg CPG_MOD 812>; 795 clock-names = "fck"; 796 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 797 resets = <&cpg 812>; 798 phy-mode = "rgmii"; 799 rx-internal-delay-ps = <1800>; 800 iommus = <&ipmmu_ds0 16>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 status = "disabled"; 804 }; 805 806 can0: can@e6c30000 { 807 compatible = "renesas,can-r8a77995", 808 "renesas,rcar-gen3-can"; 809 reg = <0 0xe6c30000 0 0x1000>; 810 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&cpg CPG_MOD 916>, 812 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 813 <&can_clk>; 814 clock-names = "clkp1", "clkp2", "can_clk"; 815 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 816 assigned-clock-rates = <40000000>; 817 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 818 resets = <&cpg 916>; 819 status = "disabled"; 820 }; 821 822 can1: can@e6c38000 { 823 compatible = "renesas,can-r8a77995", 824 "renesas,rcar-gen3-can"; 825 reg = <0 0xe6c38000 0 0x1000>; 826 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&cpg CPG_MOD 915>, 828 <&cpg CPG_CORE R8A77995_CLK_CANFD>, 829 <&can_clk>; 830 clock-names = "clkp1", "clkp2", "can_clk"; 831 assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; 832 assigned-clock-rates = <40000000>; 833 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 834 resets = <&cpg 915>; 835 status = "disabled"; 836 }; 837 838 pwm0: pwm@e6e30000 { 839 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 840 reg = <0 0xe6e30000 0 0x8>; 841 #pwm-cells = <2>; 842 clocks = <&cpg CPG_MOD 523>; 843 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 844 resets = <&cpg 523>; 845 status = "disabled"; 846 }; 847 848 pwm1: pwm@e6e31000 { 849 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 850 reg = <0 0xe6e31000 0 0x8>; 851 #pwm-cells = <2>; 852 clocks = <&cpg CPG_MOD 523>; 853 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 854 resets = <&cpg 523>; 855 status = "disabled"; 856 }; 857 858 pwm2: pwm@e6e32000 { 859 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 860 reg = <0 0xe6e32000 0 0x8>; 861 #pwm-cells = <2>; 862 clocks = <&cpg CPG_MOD 523>; 863 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 864 resets = <&cpg 523>; 865 status = "disabled"; 866 }; 867 868 pwm3: pwm@e6e33000 { 869 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; 870 reg = <0 0xe6e33000 0 0x8>; 871 #pwm-cells = <2>; 872 clocks = <&cpg CPG_MOD 523>; 873 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 874 resets = <&cpg 523>; 875 status = "disabled"; 876 }; 877 878 scif0: serial@e6e60000 { 879 compatible = "renesas,scif-r8a77995", 880 "renesas,rcar-gen3-scif", "renesas,scif"; 881 reg = <0 0xe6e60000 0 64>; 882 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&cpg CPG_MOD 207>, 884 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 885 <&scif_clk>; 886 clock-names = "fck", "brg_int", "scif_clk"; 887 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 888 <&dmac2 0x51>, <&dmac2 0x50>; 889 dma-names = "tx", "rx", "tx", "rx"; 890 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 891 resets = <&cpg 207>; 892 status = "disabled"; 893 }; 894 895 scif1: serial@e6e68000 { 896 compatible = "renesas,scif-r8a77995", 897 "renesas,rcar-gen3-scif", "renesas,scif"; 898 reg = <0 0xe6e68000 0 64>; 899 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&cpg CPG_MOD 206>, 901 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 902 <&scif_clk>; 903 clock-names = "fck", "brg_int", "scif_clk"; 904 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 905 <&dmac2 0x53>, <&dmac2 0x52>; 906 dma-names = "tx", "rx", "tx", "rx"; 907 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 908 resets = <&cpg 206>; 909 status = "disabled"; 910 }; 911 912 scif2: serial@e6e88000 { 913 compatible = "renesas,scif-r8a77995", 914 "renesas,rcar-gen3-scif", "renesas,scif"; 915 reg = <0 0xe6e88000 0 64>; 916 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 917 clocks = <&cpg CPG_MOD 310>, 918 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 919 <&scif_clk>; 920 clock-names = "fck", "brg_int", "scif_clk"; 921 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 922 <&dmac2 0x13>, <&dmac2 0x12>; 923 dma-names = "tx", "rx", "tx", "rx"; 924 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 925 resets = <&cpg 310>; 926 status = "disabled"; 927 }; 928 929 scif3: serial@e6c50000 { 930 compatible = "renesas,scif-r8a77995", 931 "renesas,rcar-gen3-scif", "renesas,scif"; 932 reg = <0 0xe6c50000 0 64>; 933 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&cpg CPG_MOD 204>, 935 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 936 <&scif_clk>; 937 clock-names = "fck", "brg_int", "scif_clk"; 938 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 939 dma-names = "tx", "rx"; 940 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 941 resets = <&cpg 204>; 942 status = "disabled"; 943 }; 944 945 scif4: serial@e6c40000 { 946 compatible = "renesas,scif-r8a77995", 947 "renesas,rcar-gen3-scif", "renesas,scif"; 948 reg = <0 0xe6c40000 0 64>; 949 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&cpg CPG_MOD 203>, 951 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 952 <&scif_clk>; 953 clock-names = "fck", "brg_int", "scif_clk"; 954 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 955 dma-names = "tx", "rx"; 956 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 957 resets = <&cpg 203>; 958 status = "disabled"; 959 }; 960 961 scif5: serial@e6f30000 { 962 compatible = "renesas,scif-r8a77995", 963 "renesas,rcar-gen3-scif", "renesas,scif"; 964 reg = <0 0xe6f30000 0 64>; 965 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&cpg CPG_MOD 202>, 967 <&cpg CPG_CORE R8A77995_CLK_S3D1C>, 968 <&scif_clk>; 969 clock-names = "fck", "brg_int", "scif_clk"; 970 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 971 <&dmac2 0x5b>, <&dmac2 0x5a>; 972 dma-names = "tx", "rx", "tx", "rx"; 973 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 974 resets = <&cpg 202>; 975 status = "disabled"; 976 }; 977 978 msiof0: spi@e6e90000 { 979 compatible = "renesas,msiof-r8a77995", 980 "renesas,rcar-gen3-msiof"; 981 reg = <0 0xe6e90000 0 0x64>; 982 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&cpg CPG_MOD 211>; 984 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 985 <&dmac2 0x41>, <&dmac2 0x40>; 986 dma-names = "tx", "rx", "tx", "rx"; 987 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 988 resets = <&cpg 211>; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 status = "disabled"; 992 }; 993 994 msiof1: spi@e6ea0000 { 995 compatible = "renesas,msiof-r8a77995", 996 "renesas,rcar-gen3-msiof"; 997 reg = <0 0xe6ea0000 0 0x64>; 998 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&cpg CPG_MOD 210>; 1000 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1001 <&dmac2 0x43>, <&dmac2 0x42>; 1002 dma-names = "tx", "rx", "tx", "rx"; 1003 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1004 resets = <&cpg 210>; 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 status = "disabled"; 1008 }; 1009 1010 msiof2: spi@e6c00000 { 1011 compatible = "renesas,msiof-r8a77995", 1012 "renesas,rcar-gen3-msiof"; 1013 reg = <0 0xe6c00000 0 0x64>; 1014 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&cpg CPG_MOD 209>; 1016 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1017 dma-names = "tx", "rx"; 1018 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1019 resets = <&cpg 209>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 status = "disabled"; 1023 }; 1024 1025 msiof3: spi@e6c10000 { 1026 compatible = "renesas,msiof-r8a77995", 1027 "renesas,rcar-gen3-msiof"; 1028 reg = <0 0xe6c10000 0 0x64>; 1029 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1030 clocks = <&cpg CPG_MOD 208>; 1031 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1032 dma-names = "tx", "rx"; 1033 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1034 resets = <&cpg 208>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 status = "disabled"; 1038 }; 1039 1040 vin4: video@e6ef4000 { 1041 compatible = "renesas,vin-r8a77995"; 1042 reg = <0 0xe6ef4000 0 0x1000>; 1043 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&cpg CPG_MOD 807>; 1045 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1046 resets = <&cpg 807>; 1047 renesas,id = <4>; 1048 status = "disabled"; 1049 }; 1050 1051 rcar_sound: sound@ec500000 { 1052 /* 1053 * #sound-dai-cells is required if simple-card 1054 * 1055 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1056 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1057 */ 1058 /* 1059 * #clock-cells is required for audio_clkout0/1/2/3 1060 * 1061 * clkout : #clock-cells = <0>; <&rcar_sound>; 1062 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1063 */ 1064 compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3"; 1065 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1066 <0 0xec5a0000 0 0x100>, /* ADG */ 1067 <0 0xec540000 0 0x1000>, /* SSIU */ 1068 <0 0xec541000 0 0x280>, /* SSI */ 1069 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1070 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1071 1072 clocks = <&cpg CPG_MOD 1005>, 1073 <&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>, 1074 <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, 1075 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1076 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1077 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1078 <&audio_clk_a>, <&audio_clk_b>, 1079 <&cpg CPG_MOD 922>; 1080 clock-names = "ssi-all", 1081 "ssi.4", "ssi.3", 1082 "src.6", "src.5", 1083 "mix.1", "mix.0", 1084 "ctu.1", "ctu.0", 1085 "dvc.0", "dvc.1", 1086 "clk_a", "clk_b", "clk_i"; 1087 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1088 resets = <&cpg 1005>, 1089 <&cpg 1011>, <&cpg 1012>; 1090 reset-names = "ssi-all", 1091 "ssi.4", "ssi.3"; 1092 status = "disabled"; 1093 1094 rcar_sound,ctu { 1095 ctu00: ctu-0 { }; 1096 ctu01: ctu-1 { }; 1097 ctu02: ctu-2 { }; 1098 ctu03: ctu-3 { }; 1099 ctu10: ctu-4 { }; 1100 ctu11: ctu-5 { }; 1101 ctu12: ctu-6 { }; 1102 ctu13: ctu-7 { }; 1103 }; 1104 1105 rcar_sound,dvc { 1106 dvc0: dvc-0 { 1107 dmas = <&audma0 0xbc>; 1108 dma-names = "tx"; 1109 }; 1110 dvc1: dvc-1 { 1111 dmas = <&audma0 0xbe>; 1112 dma-names = "tx"; 1113 }; 1114 }; 1115 1116 rcar_sound,mix { 1117 mix0: mix-0 { }; 1118 mix1: mix-1 { }; 1119 }; 1120 1121 rcar_sound,src { 1122 src5: src-5 { 1123 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1124 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1125 dma-names = "rx", "tx"; 1126 }; 1127 src6: src-6 { 1128 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1129 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1130 dma-names = "rx", "tx"; 1131 }; 1132 }; 1133 1134 rcar_sound,ssi { 1135 ssi3: ssi-3 { 1136 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1137 dmas = <&audma0 0x07>, <&audma0 0x08>, 1138 <&audma0 0x6f>, <&audma0 0x70>; 1139 dma-names = "rx", "tx", "rxu", "txu"; 1140 }; 1141 ssi4: ssi-4 { 1142 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1143 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1144 <&audma0 0x71>, <&audma0 0x72>; 1145 dma-names = "rx", "tx", "rxu", "txu"; 1146 }; 1147 }; 1148 }; 1149 1150 mlp: mlp@ec520000 { 1151 compatible = "renesas,r8a77995-mlp", 1152 "renesas,rcar-gen3-mlp"; 1153 reg = <0 0xec520000 0 0x800>; 1154 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>; 1156 clocks = <&cpg CPG_MOD 802>; 1157 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1158 resets = <&cpg 802>; 1159 status = "disabled"; 1160 }; 1161 1162 audma0: dma-controller@ec700000 { 1163 compatible = "renesas,dmac-r8a77995", 1164 "renesas,rcar-dmac"; 1165 reg = <0 0xec700000 0 0x10000>; 1166 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1183 interrupt-names = "error", 1184 "ch0", "ch1", "ch2", "ch3", 1185 "ch4", "ch5", "ch6", "ch7", 1186 "ch8", "ch9", "ch10", "ch11", 1187 "ch12", "ch13", "ch14", "ch15"; 1188 clocks = <&cpg CPG_MOD 502>; 1189 clock-names = "fck"; 1190 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1191 resets = <&cpg 502>; 1192 #dma-cells = <1>; 1193 dma-channels = <16>; 1194 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1195 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1196 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1197 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1198 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1199 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1200 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1201 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1202 }; 1203 1204 ohci0: usb@ee080000 { 1205 compatible = "generic-ohci"; 1206 reg = <0 0xee080000 0 0x100>; 1207 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1208 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1209 phys = <&usb2_phy0 1>; 1210 phy-names = "usb"; 1211 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1212 resets = <&cpg 703>, <&cpg 704>; 1213 status = "disabled"; 1214 }; 1215 1216 ehci0: usb@ee080100 { 1217 compatible = "generic-ehci"; 1218 reg = <0 0xee080100 0 0x100>; 1219 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1220 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1221 phys = <&usb2_phy0 2>; 1222 phy-names = "usb"; 1223 companion = <&ohci0>; 1224 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1225 resets = <&cpg 703>, <&cpg 704>; 1226 status = "disabled"; 1227 }; 1228 1229 usb2_phy0: usb-phy@ee080200 { 1230 compatible = "renesas,usb2-phy-r8a77995", 1231 "renesas,rcar-gen3-usb2-phy"; 1232 reg = <0 0xee080200 0 0x700>; 1233 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1235 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1236 resets = <&cpg 703>, <&cpg 704>; 1237 #phy-cells = <1>; 1238 status = "disabled"; 1239 }; 1240 1241 sdhi2: mmc@ee140000 { 1242 compatible = "renesas,sdhi-r8a77995", 1243 "renesas,rcar-gen3-sdhi"; 1244 reg = <0 0xee140000 0 0x2000>; 1245 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1246 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77995_CLK_SD0H>; 1247 clock-names = "core", "clkh"; 1248 max-frequency = <200000000>; 1249 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1250 resets = <&cpg 312>; 1251 iommus = <&ipmmu_ds1 34>; 1252 status = "disabled"; 1253 }; 1254 1255 rpc: spi@ee200000 { 1256 compatible = "renesas,r8a77995-rpc-if", 1257 "renesas,rcar-gen3-rpc-if"; 1258 reg = <0 0xee200000 0 0x200>, 1259 <0 0x08000000 0 0x04000000>, 1260 <0 0xee208000 0 0x100>; 1261 reg-names = "regs", "dirmap", "wbuf"; 1262 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1263 clocks = <&cpg CPG_MOD 917>; 1264 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1265 resets = <&cpg 917>; 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 status = "disabled"; 1269 }; 1270 1271 gic: interrupt-controller@f1010000 { 1272 compatible = "arm,gic-400"; 1273 #interrupt-cells = <3>; 1274 #address-cells = <0>; 1275 interrupt-controller; 1276 reg = <0x0 0xf1010000 0 0x1000>, 1277 <0x0 0xf1020000 0 0x20000>, 1278 <0x0 0xf1040000 0 0x20000>, 1279 <0x0 0xf1060000 0 0x20000>; 1280 interrupts = <GIC_PPI 9 1281 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 1282 clocks = <&cpg CPG_MOD 408>; 1283 clock-names = "clk"; 1284 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1285 resets = <&cpg 408>; 1286 }; 1287 1288 vspbs: vsp@fe960000 { 1289 compatible = "renesas,vsp2"; 1290 reg = <0 0xfe960000 0 0x8000>; 1291 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1292 clocks = <&cpg CPG_MOD 627>; 1293 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1294 resets = <&cpg 627>; 1295 renesas,fcp = <&fcpvb0>; 1296 }; 1297 1298 vspd0: vsp@fea20000 { 1299 compatible = "renesas,vsp2"; 1300 reg = <0 0xfea20000 0 0x5000>; 1301 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1302 clocks = <&cpg CPG_MOD 623>; 1303 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1304 resets = <&cpg 623>; 1305 renesas,fcp = <&fcpvd0>; 1306 }; 1307 1308 vspd1: vsp@fea28000 { 1309 compatible = "renesas,vsp2"; 1310 reg = <0 0xfea28000 0 0x5000>; 1311 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1312 clocks = <&cpg CPG_MOD 622>; 1313 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1314 resets = <&cpg 622>; 1315 renesas,fcp = <&fcpvd1>; 1316 }; 1317 1318 fcpvb0: fcp@fe96f000 { 1319 compatible = "renesas,fcpv"; 1320 reg = <0 0xfe96f000 0 0x200>; 1321 clocks = <&cpg CPG_MOD 607>; 1322 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1323 resets = <&cpg 607>; 1324 iommus = <&ipmmu_vp0 5>; 1325 }; 1326 1327 fcpvd0: fcp@fea27000 { 1328 compatible = "renesas,fcpv"; 1329 reg = <0 0xfea27000 0 0x200>; 1330 clocks = <&cpg CPG_MOD 603>; 1331 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1332 resets = <&cpg 603>; 1333 iommus = <&ipmmu_vi0 8>; 1334 }; 1335 1336 fcpvd1: fcp@fea2f000 { 1337 compatible = "renesas,fcpv"; 1338 reg = <0 0xfea2f000 0 0x200>; 1339 clocks = <&cpg CPG_MOD 602>; 1340 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1341 resets = <&cpg 602>; 1342 iommus = <&ipmmu_vi0 9>; 1343 }; 1344 1345 cmm0: cmm@fea40000 { 1346 compatible = "renesas,r8a77995-cmm", 1347 "renesas,rcar-gen3-cmm"; 1348 reg = <0 0xfea40000 0 0x1000>; 1349 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1350 clocks = <&cpg CPG_MOD 711>; 1351 resets = <&cpg 711>; 1352 }; 1353 1354 cmm1: cmm@fea50000 { 1355 compatible = "renesas,r8a77995-cmm", 1356 "renesas,rcar-gen3-cmm"; 1357 reg = <0 0xfea50000 0 0x1000>; 1358 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1359 clocks = <&cpg CPG_MOD 710>; 1360 resets = <&cpg 710>; 1361 }; 1362 1363 du: display@feb00000 { 1364 compatible = "renesas,du-r8a77995"; 1365 reg = <0 0xfeb00000 0 0x40000>; 1366 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1368 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1369 clock-names = "du.0", "du.1"; 1370 resets = <&cpg 724>; 1371 reset-names = "du.0"; 1372 1373 renesas,cmms = <&cmm0>, <&cmm1>; 1374 renesas,vsps = <&vspd0 0>, <&vspd1 0>; 1375 1376 status = "disabled"; 1377 1378 ports { 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 1382 port@0 { 1383 reg = <0>; 1384 }; 1385 1386 port@1 { 1387 reg = <1>; 1388 du_out_lvds0: endpoint { 1389 remote-endpoint = <&lvds0_in>; 1390 }; 1391 }; 1392 1393 port@2 { 1394 reg = <2>; 1395 du_out_lvds1: endpoint { 1396 remote-endpoint = <&lvds1_in>; 1397 }; 1398 }; 1399 }; 1400 }; 1401 1402 lvds0: lvds-encoder@feb90000 { 1403 compatible = "renesas,r8a77995-lvds"; 1404 reg = <0 0xfeb90000 0 0x20>; 1405 clocks = <&cpg CPG_MOD 727>; 1406 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1407 resets = <&cpg 727>; 1408 status = "disabled"; 1409 1410 renesas,companion = <&lvds1>; 1411 1412 ports { 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 1416 port@0 { 1417 reg = <0>; 1418 lvds0_in: endpoint { 1419 remote-endpoint = <&du_out_lvds0>; 1420 }; 1421 }; 1422 1423 port@1 { 1424 reg = <1>; 1425 }; 1426 }; 1427 }; 1428 1429 lvds1: lvds-encoder@feb90100 { 1430 compatible = "renesas,r8a77995-lvds"; 1431 reg = <0 0xfeb90100 0 0x20>; 1432 clocks = <&cpg CPG_MOD 727>; 1433 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; 1434 resets = <&cpg 726>; 1435 status = "disabled"; 1436 1437 ports { 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 1441 port@0 { 1442 reg = <0>; 1443 lvds1_in: endpoint { 1444 remote-endpoint = <&du_out_lvds1>; 1445 }; 1446 }; 1447 1448 port@1 { 1449 reg = <1>; 1450 }; 1451 }; 1452 }; 1453 1454 prr: chipid@fff00044 { 1455 compatible = "renesas,prr"; 1456 reg = <0 0xfff00044 0 4>; 1457 bootph-all; 1458 }; 1459 }; 1460 1461 thermal-zones { 1462 cpu_thermal: cpu-thermal { 1463 polling-delay-passive = <250>; 1464 polling-delay = <1000>; 1465 thermal-sensors = <&thermal>; 1466 1467 cooling-maps { 1468 }; 1469 1470 trips { 1471 cpu-crit { 1472 temperature = <120000>; 1473 hysteresis = <2000>; 1474 type = "critical"; 1475 }; 1476 }; 1477 }; 1478 }; 1479 1480 timer { 1481 compatible = "arm,armv8-timer"; 1482 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1483 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1484 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1485 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 1486 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; 1487 }; 1488}; 1489