1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M2-N (R8A77930) SoC 4 * 5 * Copyright (C) 2014-2015 Renesas Electronics Corporation 6 */ 7 8#include <dt-bindings/clock/r8a7793-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/power/r8a7793-sysc.h> 12 13/ { 14 compatible = "renesas,r8a7793"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 i2c0 = &i2c0; 20 i2c1 = &i2c1; 21 i2c2 = &i2c2; 22 i2c3 = &i2c3; 23 i2c4 = &i2c4; 24 i2c5 = &i2c5; 25 i2c6 = &i2c6; 26 i2c7 = &i2c7; 27 i2c8 = &i2c8; 28 spi0 = &qspi; 29 }; 30 31 /* 32 * The external audio clocks are configured as 0 Hz fixed frequency 33 * clocks by default. 34 * Boards that provide audio clocks should override them. 35 */ 36 audio_clk_a: audio_clk_a { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 audio_clk_b: audio_clk_b { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 audio_clk_c: audio_clk_c { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <0>; 50 }; 51 52 /* External CAN clock */ 53 can_clk: can { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 /* This value must be overridden by the board. */ 57 clock-frequency = <0>; 58 }; 59 60 cpus { 61 #address-cells = <1>; 62 #size-cells = <0>; 63 64 cpu0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "arm,cortex-a15"; 67 reg = <0>; 68 clock-frequency = <1500000000>; 69 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; 70 power-domains = <&sysc R8A7793_PD_CA15_CPU0>; 71 enable-method = "renesas,apmu"; 72 voltage-tolerance = <1>; /* 1% */ 73 clock-latency = <300000>; /* 300 us */ 74 75 /* kHz - uV - OPPs unknown yet */ 76 operating-points = <1500000 1000000>, 77 <1312500 1000000>, 78 <1125000 1000000>, 79 < 937500 1000000>, 80 < 750000 1000000>, 81 < 375000 1000000>; 82 next-level-cache = <&L2_CA15>; 83 }; 84 85 cpu1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a15"; 88 reg = <1>; 89 clock-frequency = <1500000000>; 90 clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; 91 power-domains = <&sysc R8A7793_PD_CA15_CPU1>; 92 enable-method = "renesas,apmu"; 93 voltage-tolerance = <1>; /* 1% */ 94 clock-latency = <300000>; /* 300 us */ 95 96 /* kHz - uV - OPPs unknown yet */ 97 operating-points = <1500000 1000000>, 98 <1312500 1000000>, 99 <1125000 1000000>, 100 < 937500 1000000>, 101 < 750000 1000000>, 102 < 375000 1000000>; 103 next-level-cache = <&L2_CA15>; 104 }; 105 106 L2_CA15: cache-controller-0 { 107 compatible = "cache"; 108 power-domains = <&sysc R8A7793_PD_CA15_SCU>; 109 cache-unified; 110 cache-level = <2>; 111 }; 112 }; 113 114 /* External root clock */ 115 extal_clk: extal { 116 compatible = "fixed-clock"; 117 #clock-cells = <0>; 118 /* This value must be overridden by the board. */ 119 clock-frequency = <0>; 120 bootph-all; 121 }; 122 123 pmu { 124 compatible = "arm,cortex-a15-pmu"; 125 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 126 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 127 interrupt-affinity = <&cpu0>, <&cpu1>; 128 }; 129 130 /* External SCIF clock */ 131 scif_clk: scif { 132 compatible = "fixed-clock"; 133 #clock-cells = <0>; 134 /* This value must be overridden by the board. */ 135 clock-frequency = <0>; 136 }; 137 138 soc { 139 compatible = "simple-bus"; 140 interrupt-parent = <&gic>; 141 bootph-all; 142 143 #address-cells = <2>; 144 #size-cells = <2>; 145 ranges; 146 147 rwdt: watchdog@e6020000 { 148 compatible = "renesas,r8a7793-wdt", 149 "renesas,rcar-gen2-wdt"; 150 reg = <0 0xe6020000 0 0x0c>; 151 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&cpg CPG_MOD 402>; 153 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 154 resets = <&cpg 402>; 155 status = "disabled"; 156 }; 157 158 gpio0: gpio@e6050000 { 159 compatible = "renesas,gpio-r8a7793", 160 "renesas,rcar-gen2-gpio"; 161 reg = <0 0xe6050000 0 0x50>; 162 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 163 #gpio-cells = <2>; 164 gpio-controller; 165 gpio-ranges = <&pfc 0 0 32>; 166 #interrupt-cells = <2>; 167 interrupt-controller; 168 clocks = <&cpg CPG_MOD 912>; 169 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 170 resets = <&cpg 912>; 171 }; 172 173 gpio1: gpio@e6051000 { 174 compatible = "renesas,gpio-r8a7793", 175 "renesas,rcar-gen2-gpio"; 176 reg = <0 0xe6051000 0 0x50>; 177 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 178 #gpio-cells = <2>; 179 gpio-controller; 180 gpio-ranges = <&pfc 0 32 26>; 181 #interrupt-cells = <2>; 182 interrupt-controller; 183 clocks = <&cpg CPG_MOD 911>; 184 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 185 resets = <&cpg 911>; 186 }; 187 188 gpio2: gpio@e6052000 { 189 compatible = "renesas,gpio-r8a7793", 190 "renesas,rcar-gen2-gpio"; 191 reg = <0 0xe6052000 0 0x50>; 192 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 193 #gpio-cells = <2>; 194 gpio-controller; 195 gpio-ranges = <&pfc 0 64 32>; 196 #interrupt-cells = <2>; 197 interrupt-controller; 198 clocks = <&cpg CPG_MOD 910>; 199 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 200 resets = <&cpg 910>; 201 }; 202 203 gpio3: gpio@e6053000 { 204 compatible = "renesas,gpio-r8a7793", 205 "renesas,rcar-gen2-gpio"; 206 reg = <0 0xe6053000 0 0x50>; 207 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 208 #gpio-cells = <2>; 209 gpio-controller; 210 gpio-ranges = <&pfc 0 96 32>; 211 #interrupt-cells = <2>; 212 interrupt-controller; 213 clocks = <&cpg CPG_MOD 909>; 214 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 215 resets = <&cpg 909>; 216 }; 217 218 gpio4: gpio@e6054000 { 219 compatible = "renesas,gpio-r8a7793", 220 "renesas,rcar-gen2-gpio"; 221 reg = <0 0xe6054000 0 0x50>; 222 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 223 #gpio-cells = <2>; 224 gpio-controller; 225 gpio-ranges = <&pfc 0 128 32>; 226 #interrupt-cells = <2>; 227 interrupt-controller; 228 clocks = <&cpg CPG_MOD 908>; 229 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 230 resets = <&cpg 908>; 231 }; 232 233 gpio5: gpio@e6055000 { 234 compatible = "renesas,gpio-r8a7793", 235 "renesas,rcar-gen2-gpio"; 236 reg = <0 0xe6055000 0 0x50>; 237 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 238 #gpio-cells = <2>; 239 gpio-controller; 240 gpio-ranges = <&pfc 0 160 32>; 241 #interrupt-cells = <2>; 242 interrupt-controller; 243 clocks = <&cpg CPG_MOD 907>; 244 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 245 resets = <&cpg 907>; 246 }; 247 248 gpio6: gpio@e6055400 { 249 compatible = "renesas,gpio-r8a7793", 250 "renesas,rcar-gen2-gpio"; 251 reg = <0 0xe6055400 0 0x50>; 252 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 253 #gpio-cells = <2>; 254 gpio-controller; 255 gpio-ranges = <&pfc 0 192 32>; 256 #interrupt-cells = <2>; 257 interrupt-controller; 258 clocks = <&cpg CPG_MOD 905>; 259 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 260 resets = <&cpg 905>; 261 }; 262 263 gpio7: gpio@e6055800 { 264 compatible = "renesas,gpio-r8a7793", 265 "renesas,rcar-gen2-gpio"; 266 reg = <0 0xe6055800 0 0x50>; 267 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 268 #gpio-cells = <2>; 269 gpio-controller; 270 gpio-ranges = <&pfc 0 224 26>; 271 #interrupt-cells = <2>; 272 interrupt-controller; 273 clocks = <&cpg CPG_MOD 904>; 274 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 275 resets = <&cpg 904>; 276 }; 277 278 pfc: pinctrl@e6060000 { 279 compatible = "renesas,pfc-r8a7793"; 280 reg = <0 0xe6060000 0 0x250>; 281 bootph-all; 282 }; 283 284 /* Special CPG clocks */ 285 cpg: clock-controller@e6150000 { 286 compatible = "renesas,r8a7793-cpg-mssr"; 287 reg = <0 0xe6150000 0 0x1000>; 288 clocks = <&extal_clk>, <&usb_extal_clk>; 289 clock-names = "extal", "usb_extal"; 290 #clock-cells = <2>; 291 #power-domain-cells = <0>; 292 #reset-cells = <1>; 293 bootph-all; 294 }; 295 296 apmu@e6152000 { 297 compatible = "renesas,r8a7793-apmu", "renesas,apmu"; 298 reg = <0 0xe6152000 0 0x188>; 299 cpus = <&cpu0>, <&cpu1>; 300 }; 301 302 rst: reset-controller@e6160000 { 303 compatible = "renesas,r8a7793-rst"; 304 reg = <0 0xe6160000 0 0x0100>; 305 bootph-all; 306 }; 307 308 sysc: system-controller@e6180000 { 309 compatible = "renesas,r8a7793-sysc"; 310 reg = <0 0xe6180000 0 0x0200>; 311 #power-domain-cells = <1>; 312 }; 313 314 irqc0: interrupt-controller@e61c0000 { 315 compatible = "renesas,irqc-r8a7793", "renesas,irqc"; 316 #interrupt-cells = <2>; 317 interrupt-controller; 318 reg = <0 0xe61c0000 0 0x200>; 319 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&cpg CPG_MOD 407>; 330 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 331 resets = <&cpg 407>; 332 }; 333 334 tmu0: timer@e61e0000 { 335 compatible = "renesas,tmu-r8a7793", "renesas,tmu"; 336 reg = <0 0xe61e0000 0 0x30>; 337 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-names = "tuni0", "tuni1", "tuni2"; 341 clocks = <&cpg CPG_MOD 125>; 342 clock-names = "fck"; 343 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 344 resets = <&cpg 125>; 345 status = "disabled"; 346 }; 347 348 tmu1: timer@fff60000 { 349 compatible = "renesas,tmu-r8a7793", "renesas,tmu"; 350 reg = <0 0xfff60000 0 0x30>; 351 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 355 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 356 clocks = <&cpg CPG_MOD 111>; 357 clock-names = "fck"; 358 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 359 resets = <&cpg 111>; 360 status = "disabled"; 361 }; 362 363 tmu2: timer@fff70000 { 364 compatible = "renesas,tmu-r8a7793", "renesas,tmu"; 365 reg = <0 0xfff70000 0 0x30>; 366 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 370 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 371 clocks = <&cpg CPG_MOD 122>; 372 clock-names = "fck"; 373 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 374 resets = <&cpg 122>; 375 status = "disabled"; 376 }; 377 378 tmu3: timer@fff80000 { 379 compatible = "renesas,tmu-r8a7793", "renesas,tmu"; 380 reg = <0 0xfff80000 0 0x30>; 381 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 384 interrupt-names = "tuni0", "tuni1", "tuni2"; 385 clocks = <&cpg CPG_MOD 121>; 386 clock-names = "fck"; 387 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 388 resets = <&cpg 121>; 389 status = "disabled"; 390 }; 391 392 thermal: thermal@e61f0000 { 393 compatible = "renesas,thermal-r8a7793", 394 "renesas,rcar-gen2-thermal", 395 "renesas,rcar-thermal"; 396 reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>; 397 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&cpg CPG_MOD 522>; 399 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 400 resets = <&cpg 522>; 401 #thermal-sensor-cells = <0>; 402 }; 403 404 ipmmu_sy0: iommu@e6280000 { 405 compatible = "renesas,ipmmu-r8a7793", 406 "renesas,ipmmu-vmsa"; 407 reg = <0 0xe6280000 0 0x1000>; 408 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 410 #iommu-cells = <1>; 411 status = "disabled"; 412 }; 413 414 ipmmu_sy1: iommu@e6290000 { 415 compatible = "renesas,ipmmu-r8a7793", 416 "renesas,ipmmu-vmsa"; 417 reg = <0 0xe6290000 0 0x1000>; 418 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 419 #iommu-cells = <1>; 420 status = "disabled"; 421 }; 422 423 ipmmu_ds: iommu@e6740000 { 424 compatible = "renesas,ipmmu-r8a7793", 425 "renesas,ipmmu-vmsa"; 426 reg = <0 0xe6740000 0 0x1000>; 427 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 429 #iommu-cells = <1>; 430 status = "disabled"; 431 }; 432 433 ipmmu_mp: iommu@ec680000 { 434 compatible = "renesas,ipmmu-r8a7793", 435 "renesas,ipmmu-vmsa"; 436 reg = <0 0xec680000 0 0x1000>; 437 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 438 #iommu-cells = <1>; 439 status = "disabled"; 440 }; 441 442 ipmmu_mx: iommu@fe951000 { 443 compatible = "renesas,ipmmu-r8a7793", 444 "renesas,ipmmu-vmsa"; 445 reg = <0 0xfe951000 0 0x1000>; 446 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 448 #iommu-cells = <1>; 449 status = "disabled"; 450 }; 451 452 ipmmu_rt: iommu@ffc80000 { 453 compatible = "renesas,ipmmu-r8a7793", 454 "renesas,ipmmu-vmsa"; 455 reg = <0 0xffc80000 0 0x1000>; 456 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 457 #iommu-cells = <1>; 458 status = "disabled"; 459 }; 460 461 ipmmu_gp: iommu@e62a0000 { 462 compatible = "renesas,ipmmu-r8a7793", 463 "renesas,ipmmu-vmsa"; 464 reg = <0 0xe62a0000 0 0x1000>; 465 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 467 #iommu-cells = <1>; 468 status = "disabled"; 469 }; 470 471 icram0: sram@e63a0000 { 472 compatible = "mmio-sram"; 473 reg = <0 0xe63a0000 0 0x12000>; 474 #address-cells = <1>; 475 #size-cells = <1>; 476 ranges = <0 0 0xe63a0000 0x12000>; 477 }; 478 479 icram1: sram@e63c0000 { 480 compatible = "mmio-sram"; 481 reg = <0 0xe63c0000 0 0x1000>; 482 #address-cells = <1>; 483 #size-cells = <1>; 484 ranges = <0 0 0xe63c0000 0x1000>; 485 486 smp-sram@0 { 487 compatible = "renesas,smp-sram"; 488 reg = <0 0x100>; 489 }; 490 }; 491 492 /* The memory map in the User's Manual maps the cores to 493 * bus numbers 494 */ 495 i2c0: i2c@e6508000 { 496 #address-cells = <1>; 497 #size-cells = <0>; 498 compatible = "renesas,i2c-r8a7793", 499 "renesas,rcar-gen2-i2c"; 500 reg = <0 0xe6508000 0 0x40>; 501 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 502 clocks = <&cpg CPG_MOD 931>; 503 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 504 resets = <&cpg 931>; 505 i2c-scl-internal-delay-ns = <6>; 506 status = "disabled"; 507 }; 508 509 i2c1: i2c@e6518000 { 510 #address-cells = <1>; 511 #size-cells = <0>; 512 compatible = "renesas,i2c-r8a7793", 513 "renesas,rcar-gen2-i2c"; 514 reg = <0 0xe6518000 0 0x40>; 515 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&cpg CPG_MOD 930>; 517 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 518 resets = <&cpg 930>; 519 i2c-scl-internal-delay-ns = <6>; 520 status = "disabled"; 521 }; 522 523 i2c2: i2c@e6530000 { 524 #address-cells = <1>; 525 #size-cells = <0>; 526 compatible = "renesas,i2c-r8a7793", 527 "renesas,rcar-gen2-i2c"; 528 reg = <0 0xe6530000 0 0x40>; 529 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&cpg CPG_MOD 929>; 531 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 532 resets = <&cpg 929>; 533 i2c-scl-internal-delay-ns = <6>; 534 status = "disabled"; 535 }; 536 537 i2c3: i2c@e6540000 { 538 #address-cells = <1>; 539 #size-cells = <0>; 540 compatible = "renesas,i2c-r8a7793", 541 "renesas,rcar-gen2-i2c"; 542 reg = <0 0xe6540000 0 0x40>; 543 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&cpg CPG_MOD 928>; 545 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 546 resets = <&cpg 928>; 547 i2c-scl-internal-delay-ns = <6>; 548 status = "disabled"; 549 }; 550 551 i2c4: i2c@e6520000 { 552 #address-cells = <1>; 553 #size-cells = <0>; 554 compatible = "renesas,i2c-r8a7793", 555 "renesas,rcar-gen2-i2c"; 556 reg = <0 0xe6520000 0 0x40>; 557 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&cpg CPG_MOD 927>; 559 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 560 resets = <&cpg 927>; 561 i2c-scl-internal-delay-ns = <6>; 562 status = "disabled"; 563 }; 564 565 i2c5: i2c@e6528000 { 566 /* doesn't need pinmux */ 567 #address-cells = <1>; 568 #size-cells = <0>; 569 compatible = "renesas,i2c-r8a7793", 570 "renesas,rcar-gen2-i2c"; 571 reg = <0 0xe6528000 0 0x40>; 572 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&cpg CPG_MOD 925>; 574 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 575 resets = <&cpg 925>; 576 i2c-scl-internal-delay-ns = <110>; 577 status = "disabled"; 578 }; 579 580 i2c6: i2c@e60b0000 { 581 /* doesn't need pinmux */ 582 #address-cells = <1>; 583 #size-cells = <0>; 584 compatible = "renesas,iic-r8a7793", 585 "renesas,rcar-gen2-iic", 586 "renesas,rmobile-iic"; 587 reg = <0 0xe60b0000 0 0x425>; 588 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&cpg CPG_MOD 926>; 590 dmas = <&dmac0 0x77>, <&dmac0 0x78>, 591 <&dmac1 0x77>, <&dmac1 0x78>; 592 dma-names = "tx", "rx", "tx", "rx"; 593 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 594 resets = <&cpg 926>; 595 status = "disabled"; 596 }; 597 598 i2c7: i2c@e6500000 { 599 #address-cells = <1>; 600 #size-cells = <0>; 601 compatible = "renesas,iic-r8a7793", 602 "renesas,rcar-gen2-iic", 603 "renesas,rmobile-iic"; 604 reg = <0 0xe6500000 0 0x425>; 605 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&cpg CPG_MOD 318>; 607 dmas = <&dmac0 0x61>, <&dmac0 0x62>, 608 <&dmac1 0x61>, <&dmac1 0x62>; 609 dma-names = "tx", "rx", "tx", "rx"; 610 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 611 resets = <&cpg 318>; 612 status = "disabled"; 613 }; 614 615 i2c8: i2c@e6510000 { 616 #address-cells = <1>; 617 #size-cells = <0>; 618 compatible = "renesas,iic-r8a7793", 619 "renesas,rcar-gen2-iic", 620 "renesas,rmobile-iic"; 621 reg = <0 0xe6510000 0 0x425>; 622 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&cpg CPG_MOD 323>; 624 dmas = <&dmac0 0x65>, <&dmac0 0x66>, 625 <&dmac1 0x65>, <&dmac1 0x66>; 626 dma-names = "tx", "rx", "tx", "rx"; 627 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 628 resets = <&cpg 323>; 629 status = "disabled"; 630 }; 631 632 dmac0: dma-controller@e6700000 { 633 compatible = "renesas,dmac-r8a7793", 634 "renesas,rcar-dmac"; 635 reg = <0 0xe6700000 0 0x20000>; 636 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 652 interrupt-names = "error", 653 "ch0", "ch1", "ch2", "ch3", 654 "ch4", "ch5", "ch6", "ch7", 655 "ch8", "ch9", "ch10", "ch11", 656 "ch12", "ch13", "ch14"; 657 clocks = <&cpg CPG_MOD 219>; 658 clock-names = "fck"; 659 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 660 resets = <&cpg 219>; 661 #dma-cells = <1>; 662 dma-channels = <15>; 663 }; 664 665 dmac1: dma-controller@e6720000 { 666 compatible = "renesas,dmac-r8a7793", 667 "renesas,rcar-dmac"; 668 reg = <0 0xe6720000 0 0x20000>; 669 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 685 interrupt-names = "error", 686 "ch0", "ch1", "ch2", "ch3", 687 "ch4", "ch5", "ch6", "ch7", 688 "ch8", "ch9", "ch10", "ch11", 689 "ch12", "ch13", "ch14"; 690 clocks = <&cpg CPG_MOD 218>; 691 clock-names = "fck"; 692 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 693 resets = <&cpg 218>; 694 #dma-cells = <1>; 695 dma-channels = <15>; 696 }; 697 698 qspi: spi@e6b10000 { 699 compatible = "renesas,qspi-r8a7793", "renesas,qspi"; 700 reg = <0 0xe6b10000 0 0x2c>; 701 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&cpg CPG_MOD 917>; 703 dmas = <&dmac0 0x17>, <&dmac0 0x18>, 704 <&dmac1 0x17>, <&dmac1 0x18>; 705 dma-names = "tx", "rx", "tx", "rx"; 706 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 707 resets = <&cpg 917>; 708 num-cs = <1>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 status = "disabled"; 712 }; 713 714 scifa0: serial@e6c40000 { 715 compatible = "renesas,scifa-r8a7793", 716 "renesas,rcar-gen2-scifa", "renesas,scifa"; 717 reg = <0 0xe6c40000 0 64>; 718 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&cpg CPG_MOD 204>; 720 clock-names = "fck"; 721 dmas = <&dmac0 0x21>, <&dmac0 0x22>, 722 <&dmac1 0x21>, <&dmac1 0x22>; 723 dma-names = "tx", "rx", "tx", "rx"; 724 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 725 resets = <&cpg 204>; 726 status = "disabled"; 727 }; 728 729 scifa1: serial@e6c50000 { 730 compatible = "renesas,scifa-r8a7793", 731 "renesas,rcar-gen2-scifa", "renesas,scifa"; 732 reg = <0 0xe6c50000 0 64>; 733 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&cpg CPG_MOD 203>; 735 clock-names = "fck"; 736 dmas = <&dmac0 0x25>, <&dmac0 0x26>, 737 <&dmac1 0x25>, <&dmac1 0x26>; 738 dma-names = "tx", "rx", "tx", "rx"; 739 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 740 resets = <&cpg 203>; 741 status = "disabled"; 742 }; 743 744 scifa2: serial@e6c60000 { 745 compatible = "renesas,scifa-r8a7793", 746 "renesas,rcar-gen2-scifa", "renesas,scifa"; 747 reg = <0 0xe6c60000 0 64>; 748 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&cpg CPG_MOD 202>; 750 clock-names = "fck"; 751 dmas = <&dmac0 0x27>, <&dmac0 0x28>, 752 <&dmac1 0x27>, <&dmac1 0x28>; 753 dma-names = "tx", "rx", "tx", "rx"; 754 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 755 resets = <&cpg 202>; 756 status = "disabled"; 757 }; 758 759 scifa3: serial@e6c70000 { 760 compatible = "renesas,scifa-r8a7793", 761 "renesas,rcar-gen2-scifa", "renesas,scifa"; 762 reg = <0 0xe6c70000 0 64>; 763 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&cpg CPG_MOD 1106>; 765 clock-names = "fck"; 766 dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, 767 <&dmac1 0x1b>, <&dmac1 0x1c>; 768 dma-names = "tx", "rx", "tx", "rx"; 769 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 770 resets = <&cpg 1106>; 771 status = "disabled"; 772 }; 773 774 scifa4: serial@e6c78000 { 775 compatible = "renesas,scifa-r8a7793", 776 "renesas,rcar-gen2-scifa", "renesas,scifa"; 777 reg = <0 0xe6c78000 0 64>; 778 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&cpg CPG_MOD 1107>; 780 clock-names = "fck"; 781 dmas = <&dmac0 0x1f>, <&dmac0 0x20>, 782 <&dmac1 0x1f>, <&dmac1 0x20>; 783 dma-names = "tx", "rx", "tx", "rx"; 784 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 785 resets = <&cpg 1107>; 786 status = "disabled"; 787 }; 788 789 scifa5: serial@e6c80000 { 790 compatible = "renesas,scifa-r8a7793", 791 "renesas,rcar-gen2-scifa", "renesas,scifa"; 792 reg = <0 0xe6c80000 0 64>; 793 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&cpg CPG_MOD 1108>; 795 clock-names = "fck"; 796 dmas = <&dmac0 0x23>, <&dmac0 0x24>, 797 <&dmac1 0x23>, <&dmac1 0x24>; 798 dma-names = "tx", "rx", "tx", "rx"; 799 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 800 resets = <&cpg 1108>; 801 status = "disabled"; 802 }; 803 804 scifb0: serial@e6c20000 { 805 compatible = "renesas,scifb-r8a7793", 806 "renesas,rcar-gen2-scifb", "renesas,scifb"; 807 reg = <0 0xe6c20000 0 0x100>; 808 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&cpg CPG_MOD 206>; 810 clock-names = "fck"; 811 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, 812 <&dmac1 0x3d>, <&dmac1 0x3e>; 813 dma-names = "tx", "rx", "tx", "rx"; 814 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 815 resets = <&cpg 206>; 816 status = "disabled"; 817 }; 818 819 scifb1: serial@e6c30000 { 820 compatible = "renesas,scifb-r8a7793", 821 "renesas,rcar-gen2-scifb", "renesas,scifb"; 822 reg = <0 0xe6c30000 0 0x100>; 823 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 824 clocks = <&cpg CPG_MOD 207>; 825 clock-names = "fck"; 826 dmas = <&dmac0 0x19>, <&dmac0 0x1a>, 827 <&dmac1 0x19>, <&dmac1 0x1a>; 828 dma-names = "tx", "rx", "tx", "rx"; 829 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 830 resets = <&cpg 207>; 831 status = "disabled"; 832 }; 833 834 scifb2: serial@e6ce0000 { 835 compatible = "renesas,scifb-r8a7793", 836 "renesas,rcar-gen2-scifb", "renesas,scifb"; 837 reg = <0 0xe6ce0000 0 0x100>; 838 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&cpg CPG_MOD 216>; 840 clock-names = "fck"; 841 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, 842 <&dmac1 0x1d>, <&dmac1 0x1e>; 843 dma-names = "tx", "rx", "tx", "rx"; 844 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 845 resets = <&cpg 216>; 846 status = "disabled"; 847 }; 848 849 scif0: serial@e6e60000 { 850 compatible = "renesas,scif-r8a7793", 851 "renesas,rcar-gen2-scif", "renesas,scif"; 852 reg = <0 0xe6e60000 0 64>; 853 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 854 clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 855 <&scif_clk>; 856 clock-names = "fck", "brg_int", "scif_clk"; 857 dmas = <&dmac0 0x29>, <&dmac0 0x2a>, 858 <&dmac1 0x29>, <&dmac1 0x2a>; 859 dma-names = "tx", "rx", "tx", "rx"; 860 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 861 resets = <&cpg 721>; 862 status = "disabled"; 863 }; 864 865 scif1: serial@e6e68000 { 866 compatible = "renesas,scif-r8a7793", 867 "renesas,rcar-gen2-scif", "renesas,scif"; 868 reg = <0 0xe6e68000 0 64>; 869 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 871 <&scif_clk>; 872 clock-names = "fck", "brg_int", "scif_clk"; 873 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, 874 <&dmac1 0x2d>, <&dmac1 0x2e>; 875 dma-names = "tx", "rx", "tx", "rx"; 876 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 877 resets = <&cpg 720>; 878 status = "disabled"; 879 }; 880 881 scif2: serial@e6e58000 { 882 compatible = "renesas,scif-r8a7793", 883 "renesas,rcar-gen2-scif", "renesas,scif"; 884 reg = <0 0xe6e58000 0 64>; 885 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 887 <&scif_clk>; 888 clock-names = "fck", "brg_int", "scif_clk"; 889 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, 890 <&dmac1 0x2b>, <&dmac1 0x2c>; 891 dma-names = "tx", "rx", "tx", "rx"; 892 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 893 resets = <&cpg 719>; 894 status = "disabled"; 895 }; 896 897 scif3: serial@e6ea8000 { 898 compatible = "renesas,scif-r8a7793", 899 "renesas,rcar-gen2-scif", "renesas,scif"; 900 reg = <0 0xe6ea8000 0 64>; 901 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 903 <&scif_clk>; 904 clock-names = "fck", "brg_int", "scif_clk"; 905 dmas = <&dmac0 0x2f>, <&dmac0 0x30>, 906 <&dmac1 0x2f>, <&dmac1 0x30>; 907 dma-names = "tx", "rx", "tx", "rx"; 908 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 909 resets = <&cpg 718>; 910 status = "disabled"; 911 }; 912 913 scif4: serial@e6ee0000 { 914 compatible = "renesas,scif-r8a7793", 915 "renesas,rcar-gen2-scif", "renesas,scif"; 916 reg = <0 0xe6ee0000 0 64>; 917 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 919 <&scif_clk>; 920 clock-names = "fck", "brg_int", "scif_clk"; 921 dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, 922 <&dmac1 0xfb>, <&dmac1 0xfc>; 923 dma-names = "tx", "rx", "tx", "rx"; 924 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 925 resets = <&cpg 715>; 926 status = "disabled"; 927 }; 928 929 scif5: serial@e6ee8000 { 930 compatible = "renesas,scif-r8a7793", 931 "renesas,rcar-gen2-scif", "renesas,scif"; 932 reg = <0 0xe6ee8000 0 64>; 933 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 935 <&scif_clk>; 936 clock-names = "fck", "brg_int", "scif_clk"; 937 dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, 938 <&dmac1 0xfd>, <&dmac1 0xfe>; 939 dma-names = "tx", "rx", "tx", "rx"; 940 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 941 resets = <&cpg 714>; 942 status = "disabled"; 943 }; 944 945 hscif0: serial@e62c0000 { 946 compatible = "renesas,hscif-r8a7793", 947 "renesas,rcar-gen2-hscif", "renesas,hscif"; 948 reg = <0 0xe62c0000 0 96>; 949 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 951 <&scif_clk>; 952 clock-names = "fck", "brg_int", "scif_clk"; 953 dmas = <&dmac0 0x39>, <&dmac0 0x3a>, 954 <&dmac1 0x39>, <&dmac1 0x3a>; 955 dma-names = "tx", "rx", "tx", "rx"; 956 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 957 resets = <&cpg 717>; 958 status = "disabled"; 959 }; 960 961 hscif1: serial@e62c8000 { 962 compatible = "renesas,hscif-r8a7793", 963 "renesas,rcar-gen2-hscif", "renesas,hscif"; 964 reg = <0 0xe62c8000 0 96>; 965 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 967 <&scif_clk>; 968 clock-names = "fck", "brg_int", "scif_clk"; 969 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, 970 <&dmac1 0x4d>, <&dmac1 0x4e>; 971 dma-names = "tx", "rx", "tx", "rx"; 972 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 973 resets = <&cpg 716>; 974 status = "disabled"; 975 }; 976 977 hscif2: serial@e62d0000 { 978 compatible = "renesas,hscif-r8a7793", 979 "renesas,rcar-gen2-hscif", "renesas,hscif"; 980 reg = <0 0xe62d0000 0 96>; 981 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, 983 <&scif_clk>; 984 clock-names = "fck", "brg_int", "scif_clk"; 985 dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, 986 <&dmac1 0x3b>, <&dmac1 0x3c>; 987 dma-names = "tx", "rx", "tx", "rx"; 988 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 989 resets = <&cpg 713>; 990 status = "disabled"; 991 }; 992 993 can0: can@e6e80000 { 994 compatible = "renesas,can-r8a7793", 995 "renesas,rcar-gen2-can"; 996 reg = <0 0xe6e80000 0 0x1000>; 997 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, 999 <&can_clk>; 1000 clock-names = "clkp1", "clkp2", "can_clk"; 1001 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1002 resets = <&cpg 916>; 1003 status = "disabled"; 1004 }; 1005 1006 can1: can@e6e88000 { 1007 compatible = "renesas,can-r8a7793", 1008 "renesas,rcar-gen2-can"; 1009 reg = <0 0xe6e88000 0 0x1000>; 1010 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, 1012 <&can_clk>; 1013 clock-names = "clkp1", "clkp2", "can_clk"; 1014 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1015 resets = <&cpg 915>; 1016 status = "disabled"; 1017 }; 1018 1019 vin0: video@e6ef0000 { 1020 compatible = "renesas,vin-r8a7793", 1021 "renesas,rcar-gen2-vin"; 1022 reg = <0 0xe6ef0000 0 0x1000>; 1023 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1024 clocks = <&cpg CPG_MOD 811>; 1025 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1026 resets = <&cpg 811>; 1027 status = "disabled"; 1028 }; 1029 1030 vin1: video@e6ef1000 { 1031 compatible = "renesas,vin-r8a7793", 1032 "renesas,rcar-gen2-vin"; 1033 reg = <0 0xe6ef1000 0 0x1000>; 1034 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&cpg CPG_MOD 810>; 1036 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1037 resets = <&cpg 810>; 1038 status = "disabled"; 1039 }; 1040 1041 vin2: video@e6ef2000 { 1042 compatible = "renesas,vin-r8a7793", 1043 "renesas,rcar-gen2-vin"; 1044 reg = <0 0xe6ef2000 0 0x1000>; 1045 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1046 clocks = <&cpg CPG_MOD 809>; 1047 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1048 resets = <&cpg 809>; 1049 status = "disabled"; 1050 }; 1051 1052 rcar_sound: sound@ec500000 { 1053 /* 1054 * #sound-dai-cells is required if simple-card 1055 * 1056 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1057 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1058 */ 1059 compatible = "renesas,rcar_sound-r8a7793", 1060 "renesas,rcar_sound-gen2"; 1061 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1062 <0 0xec5a0000 0 0x100>, /* ADG */ 1063 <0 0xec540000 0 0x1000>, /* SSIU */ 1064 <0 0xec541000 0 0x280>, /* SSI */ 1065 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ 1066 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1067 1068 clocks = <&cpg CPG_MOD 1005>, 1069 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1070 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1071 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1072 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1073 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1074 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1075 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1076 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1077 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1078 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1079 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1080 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, 1081 <&cpg CPG_CORE R8A7793_CLK_M2>; 1082 clock-names = "ssi-all", 1083 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1084 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1085 "ssi.1", "ssi.0", 1086 "src.9", "src.8", "src.7", "src.6", 1087 "src.5", "src.4", "src.3", "src.2", 1088 "src.1", "src.0", 1089 "dvc.0", "dvc.1", 1090 "clk_a", "clk_b", "clk_c", "clk_i"; 1091 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1092 resets = <&cpg 1005>, 1093 <&cpg 1006>, <&cpg 1007>, 1094 <&cpg 1008>, <&cpg 1009>, 1095 <&cpg 1010>, <&cpg 1011>, 1096 <&cpg 1012>, <&cpg 1013>, 1097 <&cpg 1014>, <&cpg 1015>; 1098 reset-names = "ssi-all", 1099 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1100 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1101 "ssi.1", "ssi.0"; 1102 1103 status = "disabled"; 1104 1105 rcar_sound,dvc { 1106 dvc0: dvc-0 { 1107 dmas = <&audma1 0xbc>; 1108 dma-names = "tx"; 1109 }; 1110 dvc1: dvc-1 { 1111 dmas = <&audma1 0xbe>; 1112 dma-names = "tx"; 1113 }; 1114 }; 1115 1116 rcar_sound,src { 1117 src0: src-0 { 1118 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1119 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1120 dma-names = "rx", "tx"; 1121 }; 1122 src1: src-1 { 1123 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1124 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1125 dma-names = "rx", "tx"; 1126 }; 1127 src2: src-2 { 1128 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1129 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1130 dma-names = "rx", "tx"; 1131 }; 1132 src3: src-3 { 1133 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1134 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1135 dma-names = "rx", "tx"; 1136 }; 1137 src4: src-4 { 1138 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1139 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1140 dma-names = "rx", "tx"; 1141 }; 1142 src5: src-5 { 1143 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1144 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1145 dma-names = "rx", "tx"; 1146 }; 1147 src6: src-6 { 1148 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1149 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1150 dma-names = "rx", "tx"; 1151 }; 1152 src7: src-7 { 1153 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1154 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1155 dma-names = "rx", "tx"; 1156 }; 1157 src8: src-8 { 1158 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1159 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1160 dma-names = "rx", "tx"; 1161 }; 1162 src9: src-9 { 1163 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1164 dmas = <&audma0 0x97>, <&audma1 0xba>; 1165 dma-names = "rx", "tx"; 1166 }; 1167 }; 1168 1169 rcar_sound,ssi { 1170 ssi0: ssi-0 { 1171 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1172 dmas = <&audma0 0x01>, <&audma1 0x02>, 1173 <&audma0 0x15>, <&audma1 0x16>; 1174 dma-names = "rx", "tx", "rxu", "txu"; 1175 }; 1176 ssi1: ssi-1 { 1177 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1178 dmas = <&audma0 0x03>, <&audma1 0x04>, 1179 <&audma0 0x49>, <&audma1 0x4a>; 1180 dma-names = "rx", "tx", "rxu", "txu"; 1181 }; 1182 ssi2: ssi-2 { 1183 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1184 dmas = <&audma0 0x05>, <&audma1 0x06>, 1185 <&audma0 0x63>, <&audma1 0x64>; 1186 dma-names = "rx", "tx", "rxu", "txu"; 1187 }; 1188 ssi3: ssi-3 { 1189 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1190 dmas = <&audma0 0x07>, <&audma1 0x08>, 1191 <&audma0 0x6f>, <&audma1 0x70>; 1192 dma-names = "rx", "tx", "rxu", "txu"; 1193 }; 1194 ssi4: ssi-4 { 1195 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1196 dmas = <&audma0 0x09>, <&audma1 0x0a>, 1197 <&audma0 0x71>, <&audma1 0x72>; 1198 dma-names = "rx", "tx", "rxu", "txu"; 1199 }; 1200 ssi5: ssi-5 { 1201 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1202 dmas = <&audma0 0x0b>, <&audma1 0x0c>, 1203 <&audma0 0x73>, <&audma1 0x74>; 1204 dma-names = "rx", "tx", "rxu", "txu"; 1205 }; 1206 ssi6: ssi-6 { 1207 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1208 dmas = <&audma0 0x0d>, <&audma1 0x0e>, 1209 <&audma0 0x75>, <&audma1 0x76>; 1210 dma-names = "rx", "tx", "rxu", "txu"; 1211 }; 1212 ssi7: ssi-7 { 1213 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1214 dmas = <&audma0 0x0f>, <&audma1 0x10>, 1215 <&audma0 0x79>, <&audma1 0x7a>; 1216 dma-names = "rx", "tx", "rxu", "txu"; 1217 }; 1218 ssi8: ssi-8 { 1219 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1220 dmas = <&audma0 0x11>, <&audma1 0x12>, 1221 <&audma0 0x7b>, <&audma1 0x7c>; 1222 dma-names = "rx", "tx", "rxu", "txu"; 1223 }; 1224 ssi9: ssi-9 { 1225 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1226 dmas = <&audma0 0x13>, <&audma1 0x14>, 1227 <&audma0 0x7d>, <&audma1 0x7e>; 1228 dma-names = "rx", "tx", "rxu", "txu"; 1229 }; 1230 }; 1231 }; 1232 1233 audma0: dma-controller@ec700000 { 1234 compatible = "renesas,dmac-r8a7793", 1235 "renesas,rcar-dmac"; 1236 reg = <0 0xec700000 0 0x10000>; 1237 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1251 interrupt-names = "error", 1252 "ch0", "ch1", "ch2", "ch3", 1253 "ch4", "ch5", "ch6", "ch7", 1254 "ch8", "ch9", "ch10", "ch11", 1255 "ch12"; 1256 clocks = <&cpg CPG_MOD 502>; 1257 clock-names = "fck"; 1258 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1259 resets = <&cpg 502>; 1260 #dma-cells = <1>; 1261 dma-channels = <13>; 1262 }; 1263 1264 audma1: dma-controller@ec720000 { 1265 compatible = "renesas,dmac-r8a7793", 1266 "renesas,rcar-dmac"; 1267 reg = <0 0xec720000 0 0x10000>; 1268 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 1282 interrupt-names = "error", 1283 "ch0", "ch1", "ch2", "ch3", 1284 "ch4", "ch5", "ch6", "ch7", 1285 "ch8", "ch9", "ch10", "ch11", 1286 "ch12"; 1287 clocks = <&cpg CPG_MOD 501>; 1288 clock-names = "fck"; 1289 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1290 resets = <&cpg 501>; 1291 #dma-cells = <1>; 1292 dma-channels = <13>; 1293 }; 1294 1295 sdhi0: mmc@ee100000 { 1296 compatible = "renesas,sdhi-r8a7793", 1297 "renesas,rcar-gen2-sdhi"; 1298 reg = <0 0xee100000 0 0x328>; 1299 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1300 clocks = <&cpg CPG_MOD 314>; 1301 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, 1302 <&dmac1 0xcd>, <&dmac1 0xce>; 1303 dma-names = "tx", "rx", "tx", "rx"; 1304 max-frequency = <195000000>; 1305 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1306 resets = <&cpg 314>; 1307 status = "disabled"; 1308 }; 1309 1310 sdhi1: mmc@ee140000 { 1311 compatible = "renesas,sdhi-r8a7793", 1312 "renesas,rcar-gen2-sdhi"; 1313 reg = <0 0xee140000 0 0x100>; 1314 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1315 clocks = <&cpg CPG_MOD 312>; 1316 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, 1317 <&dmac1 0xc1>, <&dmac1 0xc2>; 1318 dma-names = "tx", "rx", "tx", "rx"; 1319 max-frequency = <97500000>; 1320 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1321 resets = <&cpg 312>; 1322 status = "disabled"; 1323 }; 1324 1325 sdhi2: mmc@ee160000 { 1326 compatible = "renesas,sdhi-r8a7793", 1327 "renesas,rcar-gen2-sdhi"; 1328 reg = <0 0xee160000 0 0x100>; 1329 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1330 clocks = <&cpg CPG_MOD 311>; 1331 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, 1332 <&dmac1 0xd3>, <&dmac1 0xd4>; 1333 dma-names = "tx", "rx", "tx", "rx"; 1334 max-frequency = <97500000>; 1335 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1336 resets = <&cpg 311>; 1337 status = "disabled"; 1338 }; 1339 1340 mmcif0: mmc@ee200000 { 1341 compatible = "renesas,mmcif-r8a7793", 1342 "renesas,sh-mmcif"; 1343 reg = <0 0xee200000 0 0x80>; 1344 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1345 clocks = <&cpg CPG_MOD 315>; 1346 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, 1347 <&dmac1 0xd1>, <&dmac1 0xd2>; 1348 dma-names = "tx", "rx", "tx", "rx"; 1349 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1350 resets = <&cpg 315>; 1351 status = "disabled"; 1352 max-frequency = <97500000>; 1353 }; 1354 1355 ether: ethernet@ee700000 { 1356 compatible = "renesas,ether-r8a7793", 1357 "renesas,rcar-gen2-ether"; 1358 reg = <0 0xee700000 0 0x400>; 1359 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1360 clocks = <&cpg CPG_MOD 813>; 1361 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1362 resets = <&cpg 813>; 1363 phy-mode = "rmii"; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 status = "disabled"; 1367 }; 1368 1369 gic: interrupt-controller@f1001000 { 1370 compatible = "arm,gic-400"; 1371 #interrupt-cells = <3>; 1372 #address-cells = <0>; 1373 interrupt-controller; 1374 reg = <0 0xf1001000 0 0x1000>, 1375 <0 0xf1002000 0 0x2000>, 1376 <0 0xf1004000 0 0x2000>, 1377 <0 0xf1006000 0 0x2000>; 1378 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1379 clocks = <&cpg CPG_MOD 408>; 1380 clock-names = "clk"; 1381 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1382 resets = <&cpg 408>; 1383 }; 1384 1385 fdp1@fe940000 { 1386 compatible = "renesas,fdp1"; 1387 reg = <0 0xfe940000 0 0x2400>; 1388 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 1389 clocks = <&cpg CPG_MOD 119>; 1390 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1391 resets = <&cpg 119>; 1392 }; 1393 1394 fdp1@fe944000 { 1395 compatible = "renesas,fdp1"; 1396 reg = <0 0xfe944000 0 0x2400>; 1397 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 1398 clocks = <&cpg CPG_MOD 118>; 1399 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1400 resets = <&cpg 118>; 1401 }; 1402 1403 du: display@feb00000 { 1404 compatible = "renesas,du-r8a7793"; 1405 reg = <0 0xfeb00000 0 0x40000>; 1406 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1408 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1409 clock-names = "du.0", "du.1"; 1410 resets = <&cpg 724>; 1411 reset-names = "du.0"; 1412 status = "disabled"; 1413 1414 ports { 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 1418 port@0 { 1419 reg = <0>; 1420 du_out_rgb: endpoint { 1421 }; 1422 }; 1423 port@1 { 1424 reg = <1>; 1425 du_out_lvds0: endpoint { 1426 remote-endpoint = <&lvds0_in>; 1427 }; 1428 }; 1429 }; 1430 }; 1431 1432 lvds0: lvds@feb90000 { 1433 compatible = "renesas,r8a7793-lvds"; 1434 reg = <0 0xfeb90000 0 0x1c>; 1435 clocks = <&cpg CPG_MOD 726>; 1436 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1437 resets = <&cpg 726>; 1438 1439 status = "disabled"; 1440 1441 ports { 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 1445 port@0 { 1446 reg = <0>; 1447 lvds0_in: endpoint { 1448 remote-endpoint = <&du_out_lvds0>; 1449 }; 1450 }; 1451 port@1 { 1452 reg = <1>; 1453 lvds0_out: endpoint { 1454 }; 1455 }; 1456 }; 1457 }; 1458 1459 prr: chipid@ff000044 { 1460 compatible = "renesas,prr"; 1461 reg = <0 0xff000044 0 4>; 1462 bootph-all; 1463 }; 1464 1465 cmt0: timer@ffca0000 { 1466 compatible = "renesas,r8a7793-cmt0", 1467 "renesas,rcar-gen2-cmt0"; 1468 reg = <0 0xffca0000 0 0x1004>; 1469 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1471 clocks = <&cpg CPG_MOD 124>; 1472 clock-names = "fck"; 1473 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1474 resets = <&cpg 124>; 1475 1476 status = "disabled"; 1477 }; 1478 1479 cmt1: timer@e6130000 { 1480 compatible = "renesas,r8a7793-cmt1", 1481 "renesas,rcar-gen2-cmt1"; 1482 reg = <0 0xe6130000 0 0x1004>; 1483 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1491 clocks = <&cpg CPG_MOD 329>; 1492 clock-names = "fck"; 1493 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; 1494 resets = <&cpg 329>; 1495 1496 status = "disabled"; 1497 }; 1498 }; 1499 1500 thermal-zones { 1501 cpu_thermal: cpu-thermal { 1502 polling-delay-passive = <0>; 1503 polling-delay = <0>; 1504 1505 thermal-sensors = <&thermal>; 1506 1507 trips { 1508 cpu-crit { 1509 temperature = <95000>; 1510 hysteresis = <0>; 1511 type = "critical"; 1512 }; 1513 }; 1514 cooling-maps { 1515 }; 1516 }; 1517 }; 1518 1519 timer { 1520 compatible = "arm,armv7-timer"; 1521 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1522 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1523 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1524 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1525 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; 1526 }; 1527 1528 /* External USB clock - can be overridden by the board */ 1529 usb_extal_clk: usb_extal { 1530 compatible = "fixed-clock"; 1531 #clock-cells = <0>; 1532 clock-frequency = <48000000>; 1533 bootph-all; 1534 }; 1535}; 1536