1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
5 * Copyright (c) 2022, Linaro Limited
6 *
7 */
8
9 #include <linux/device.h>
10 #include <linux/interconnect.h>
11 #include <linux/interconnect-provider.h>
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/platform_device.h>
15 #include <linux/property.h>
16 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
17
18 #include "bcm-voter.h"
19 #include "icc-common.h"
20 #include "icc-rpmh.h"
21
22 static struct qcom_icc_node qhm_qspi;
23 static struct qcom_icc_node qhm_qup1;
24 static struct qcom_icc_node xm_sdc4;
25 static struct qcom_icc_node xm_ufs_mem;
26 static struct qcom_icc_node xm_usb3_0;
27 static struct qcom_icc_node qhm_qdss_bam;
28 static struct qcom_icc_node qhm_qup2;
29 static struct qcom_icc_node qxm_crypto;
30 static struct qcom_icc_node qxm_ipa;
31 static struct qcom_icc_node qxm_sp;
32 static struct qcom_icc_node xm_qdss_etr_0;
33 static struct qcom_icc_node xm_qdss_etr_1;
34 static struct qcom_icc_node xm_sdc2;
35 static struct qcom_icc_node qup0_core_master;
36 static struct qcom_icc_node qup1_core_master;
37 static struct qcom_icc_node qup2_core_master;
38 static struct qcom_icc_node qsm_cfg;
39 static struct qcom_icc_node qnm_gemnoc_cnoc;
40 static struct qcom_icc_node qnm_gemnoc_pcie;
41 static struct qcom_icc_node alm_gpu_tcu;
42 static struct qcom_icc_node alm_sys_tcu;
43 static struct qcom_icc_node chm_apps;
44 static struct qcom_icc_node qnm_gpu;
45 static struct qcom_icc_node qnm_lpass_gemnoc;
46 static struct qcom_icc_node qnm_mdsp;
47 static struct qcom_icc_node qnm_mnoc_hf;
48 static struct qcom_icc_node qnm_mnoc_sf;
49 static struct qcom_icc_node qnm_nsp_gemnoc;
50 static struct qcom_icc_node qnm_pcie;
51 static struct qcom_icc_node qnm_snoc_gc;
52 static struct qcom_icc_node qnm_snoc_sf;
53 static struct qcom_icc_node qnm_lpiaon_noc;
54 static struct qcom_icc_node qnm_lpass_lpinoc;
55 static struct qcom_icc_node qxm_lpinoc_dsp_axim;
56 static struct qcom_icc_node llcc_mc;
57 static struct qcom_icc_node qnm_camnoc_hf;
58 static struct qcom_icc_node qnm_camnoc_icp;
59 static struct qcom_icc_node qnm_camnoc_sf;
60 static struct qcom_icc_node qnm_mdp;
61 static struct qcom_icc_node qnm_vapss_hcp;
62 static struct qcom_icc_node qnm_video;
63 static struct qcom_icc_node qnm_video_cv_cpu;
64 static struct qcom_icc_node qnm_video_cvp;
65 static struct qcom_icc_node qnm_video_v_cpu;
66 static struct qcom_icc_node qsm_mnoc_cfg;
67 static struct qcom_icc_node qxm_nsp;
68 static struct qcom_icc_node qsm_pcie_anoc_cfg;
69 static struct qcom_icc_node xm_pcie3_0;
70 static struct qcom_icc_node xm_pcie3_1;
71 static struct qcom_icc_node qhm_gic;
72 static struct qcom_icc_node qnm_aggre1_noc;
73 static struct qcom_icc_node qnm_aggre2_noc;
74 static struct qcom_icc_node xm_gic;
75 static struct qcom_icc_node qns_a1noc_snoc;
76 static struct qcom_icc_node qns_a2noc_snoc;
77 static struct qcom_icc_node qup0_core_slave;
78 static struct qcom_icc_node qup1_core_slave;
79 static struct qcom_icc_node qup2_core_slave;
80 static struct qcom_icc_node qhs_ahb2phy0;
81 static struct qcom_icc_node qhs_ahb2phy1;
82 static struct qcom_icc_node qhs_apss;
83 static struct qcom_icc_node qhs_camera_cfg;
84 static struct qcom_icc_node qhs_clk_ctl;
85 static struct qcom_icc_node qhs_cpr_cx;
86 static struct qcom_icc_node qhs_cpr_mmcx;
87 static struct qcom_icc_node qhs_cpr_mxa;
88 static struct qcom_icc_node qhs_cpr_mxc;
89 static struct qcom_icc_node qhs_cpr_nspcx;
90 static struct qcom_icc_node qhs_crypto0_cfg;
91 static struct qcom_icc_node qhs_cx_rdpm;
92 static struct qcom_icc_node qhs_display_cfg;
93 static struct qcom_icc_node qhs_gpuss_cfg;
94 static struct qcom_icc_node qhs_i2c;
95 static struct qcom_icc_node qhs_imem_cfg;
96 static struct qcom_icc_node qhs_ipa;
97 static struct qcom_icc_node qhs_ipc_router;
98 static struct qcom_icc_node qhs_mss_cfg;
99 static struct qcom_icc_node qhs_mx_rdpm;
100 static struct qcom_icc_node qhs_pcie0_cfg;
101 static struct qcom_icc_node qhs_pcie1_cfg;
102 static struct qcom_icc_node qhs_pdm;
103 static struct qcom_icc_node qhs_pimem_cfg;
104 static struct qcom_icc_node qhs_prng;
105 static struct qcom_icc_node qhs_qdss_cfg;
106 static struct qcom_icc_node qhs_qspi;
107 static struct qcom_icc_node qhs_qup1;
108 static struct qcom_icc_node qhs_qup2;
109 static struct qcom_icc_node qhs_sdc2;
110 static struct qcom_icc_node qhs_sdc4;
111 static struct qcom_icc_node qhs_spss_cfg;
112 static struct qcom_icc_node qhs_tcsr;
113 static struct qcom_icc_node qhs_tlmm;
114 static struct qcom_icc_node qhs_ufs_mem_cfg;
115 static struct qcom_icc_node qhs_usb3_0;
116 static struct qcom_icc_node qhs_venus_cfg;
117 static struct qcom_icc_node qhs_vsense_ctrl_cfg;
118 static struct qcom_icc_node qss_lpass_qtb_cfg;
119 static struct qcom_icc_node qss_mnoc_cfg;
120 static struct qcom_icc_node qss_nsp_qtb_cfg;
121 static struct qcom_icc_node qss_pcie_anoc_cfg;
122 static struct qcom_icc_node xs_qdss_stm;
123 static struct qcom_icc_node xs_sys_tcu_cfg;
124 static struct qcom_icc_node qhs_aoss;
125 static struct qcom_icc_node qhs_tme_cfg;
126 static struct qcom_icc_node qss_cfg;
127 static struct qcom_icc_node qss_ddrss_cfg;
128 static struct qcom_icc_node qxs_boot_imem;
129 static struct qcom_icc_node qxs_imem;
130 static struct qcom_icc_node xs_pcie_0;
131 static struct qcom_icc_node xs_pcie_1;
132 static struct qcom_icc_node qns_gem_noc_cnoc;
133 static struct qcom_icc_node qns_llcc;
134 static struct qcom_icc_node qns_pcie;
135 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc;
136 static struct qcom_icc_node qns_lpass_aggnoc;
137 static struct qcom_icc_node qns_lpi_aon_noc;
138 static struct qcom_icc_node ebi;
139 static struct qcom_icc_node qns_mem_noc_hf;
140 static struct qcom_icc_node qns_mem_noc_sf;
141 static struct qcom_icc_node srvc_mnoc;
142 static struct qcom_icc_node qns_nsp_gemnoc;
143 static struct qcom_icc_node qns_pcie_mem_noc;
144 static struct qcom_icc_node srvc_pcie_aggre_noc;
145 static struct qcom_icc_node qns_gemnoc_gc;
146 static struct qcom_icc_node qns_gemnoc_sf;
147
148 static struct qcom_icc_node qhm_qspi = {
149 .name = "qhm_qspi",
150 .channels = 1,
151 .buswidth = 4,
152 .num_links = 1,
153 .link_nodes = { &qns_a1noc_snoc },
154 };
155
156 static struct qcom_icc_node qhm_qup1 = {
157 .name = "qhm_qup1",
158 .channels = 1,
159 .buswidth = 4,
160 .num_links = 1,
161 .link_nodes = { &qns_a1noc_snoc },
162 };
163
164 static struct qcom_icc_node xm_sdc4 = {
165 .name = "xm_sdc4",
166 .channels = 1,
167 .buswidth = 8,
168 .num_links = 1,
169 .link_nodes = { &qns_a1noc_snoc },
170 };
171
172 static struct qcom_icc_node xm_ufs_mem = {
173 .name = "xm_ufs_mem",
174 .channels = 1,
175 .buswidth = 16,
176 .num_links = 1,
177 .link_nodes = { &qns_a1noc_snoc },
178 };
179
180 static struct qcom_icc_node xm_usb3_0 = {
181 .name = "xm_usb3_0",
182 .channels = 1,
183 .buswidth = 8,
184 .num_links = 1,
185 .link_nodes = { &qns_a1noc_snoc },
186 };
187
188 static struct qcom_icc_node qhm_qdss_bam = {
189 .name = "qhm_qdss_bam",
190 .channels = 1,
191 .buswidth = 4,
192 .num_links = 1,
193 .link_nodes = { &qns_a2noc_snoc },
194 };
195
196 static struct qcom_icc_node qhm_qup2 = {
197 .name = "qhm_qup2",
198 .channels = 1,
199 .buswidth = 4,
200 .num_links = 1,
201 .link_nodes = { &qns_a2noc_snoc },
202 };
203
204 static struct qcom_icc_node qxm_crypto = {
205 .name = "qxm_crypto",
206 .channels = 1,
207 .buswidth = 8,
208 .num_links = 1,
209 .link_nodes = { &qns_a2noc_snoc },
210 };
211
212 static struct qcom_icc_node qxm_ipa = {
213 .name = "qxm_ipa",
214 .channels = 1,
215 .buswidth = 8,
216 .num_links = 1,
217 .link_nodes = { &qns_a2noc_snoc },
218 };
219
220 static struct qcom_icc_node qxm_sp = {
221 .name = "qxm_sp",
222 .channels = 1,
223 .buswidth = 8,
224 .num_links = 1,
225 .link_nodes = { &qns_a2noc_snoc },
226 };
227
228 static struct qcom_icc_node xm_qdss_etr_0 = {
229 .name = "xm_qdss_etr_0",
230 .channels = 1,
231 .buswidth = 8,
232 .num_links = 1,
233 .link_nodes = { &qns_a2noc_snoc },
234 };
235
236 static struct qcom_icc_node xm_qdss_etr_1 = {
237 .name = "xm_qdss_etr_1",
238 .channels = 1,
239 .buswidth = 8,
240 .num_links = 1,
241 .link_nodes = { &qns_a2noc_snoc },
242 };
243
244 static struct qcom_icc_node xm_sdc2 = {
245 .name = "xm_sdc2",
246 .channels = 1,
247 .buswidth = 8,
248 .num_links = 1,
249 .link_nodes = { &qns_a2noc_snoc },
250 };
251
252 static struct qcom_icc_node qup0_core_master = {
253 .name = "qup0_core_master",
254 .channels = 1,
255 .buswidth = 4,
256 .num_links = 1,
257 .link_nodes = { &qup0_core_slave },
258 };
259
260 static struct qcom_icc_node qup1_core_master = {
261 .name = "qup1_core_master",
262 .channels = 1,
263 .buswidth = 4,
264 .num_links = 1,
265 .link_nodes = { &qup1_core_slave },
266 };
267
268 static struct qcom_icc_node qup2_core_master = {
269 .name = "qup2_core_master",
270 .channels = 1,
271 .buswidth = 4,
272 .num_links = 1,
273 .link_nodes = { &qup2_core_slave },
274 };
275
276 static struct qcom_icc_node qsm_cfg = {
277 .name = "qsm_cfg",
278 .channels = 1,
279 .buswidth = 4,
280 .num_links = 44,
281 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
282 &qhs_apss, &qhs_camera_cfg,
283 &qhs_clk_ctl, &qhs_cpr_cx,
284 &qhs_cpr_mmcx, &qhs_cpr_mxa,
285 &qhs_cpr_mxc, &qhs_cpr_nspcx,
286 &qhs_crypto0_cfg, &qhs_cx_rdpm,
287 &qhs_display_cfg, &qhs_gpuss_cfg,
288 &qhs_i2c, &qhs_imem_cfg,
289 &qhs_ipa, &qhs_ipc_router,
290 &qhs_mss_cfg, &qhs_mx_rdpm,
291 &qhs_pcie0_cfg, &qhs_pcie1_cfg,
292 &qhs_pdm, &qhs_pimem_cfg,
293 &qhs_prng, &qhs_qdss_cfg,
294 &qhs_qspi, &qhs_qup1,
295 &qhs_qup2, &qhs_sdc2,
296 &qhs_sdc4, &qhs_spss_cfg,
297 &qhs_tcsr, &qhs_tlmm,
298 &qhs_ufs_mem_cfg, &qhs_usb3_0,
299 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
300 &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
301 &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg,
302 &xs_qdss_stm, &xs_sys_tcu_cfg },
303 };
304
305 static struct qcom_icc_node qnm_gemnoc_cnoc = {
306 .name = "qnm_gemnoc_cnoc",
307 .channels = 1,
308 .buswidth = 16,
309 .num_links = 6,
310 .link_nodes = { &qhs_aoss, &qhs_tme_cfg,
311 &qss_cfg, &qss_ddrss_cfg,
312 &qxs_boot_imem, &qxs_imem },
313 };
314
315 static struct qcom_icc_node qnm_gemnoc_pcie = {
316 .name = "qnm_gemnoc_pcie",
317 .channels = 1,
318 .buswidth = 8,
319 .num_links = 2,
320 .link_nodes = { &xs_pcie_0, &xs_pcie_1 },
321 };
322
323 static struct qcom_icc_node alm_gpu_tcu = {
324 .name = "alm_gpu_tcu",
325 .channels = 1,
326 .buswidth = 8,
327 .num_links = 2,
328 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
329 };
330
331 static struct qcom_icc_node alm_sys_tcu = {
332 .name = "alm_sys_tcu",
333 .channels = 1,
334 .buswidth = 8,
335 .num_links = 2,
336 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
337 };
338
339 static struct qcom_icc_node chm_apps = {
340 .name = "chm_apps",
341 .channels = 3,
342 .buswidth = 32,
343 .num_links = 3,
344 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
345 &qns_pcie },
346 };
347
348 static struct qcom_icc_node qnm_gpu = {
349 .name = "qnm_gpu",
350 .channels = 2,
351 .buswidth = 32,
352 .num_links = 2,
353 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
354 };
355
356 static struct qcom_icc_node qnm_lpass_gemnoc = {
357 .name = "qnm_lpass_gemnoc",
358 .channels = 1,
359 .buswidth = 16,
360 .num_links = 3,
361 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
362 &qns_pcie },
363 };
364
365 static struct qcom_icc_node qnm_mdsp = {
366 .name = "qnm_mdsp",
367 .channels = 1,
368 .buswidth = 16,
369 .num_links = 3,
370 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
371 &qns_pcie },
372 };
373
374 static struct qcom_icc_node qnm_mnoc_hf = {
375 .name = "qnm_mnoc_hf",
376 .channels = 2,
377 .buswidth = 32,
378 .num_links = 2,
379 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
380 };
381
382 static struct qcom_icc_node qnm_mnoc_sf = {
383 .name = "qnm_mnoc_sf",
384 .channels = 2,
385 .buswidth = 32,
386 .num_links = 2,
387 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
388 };
389
390 static struct qcom_icc_node qnm_nsp_gemnoc = {
391 .name = "qnm_nsp_gemnoc",
392 .channels = 2,
393 .buswidth = 32,
394 .num_links = 2,
395 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
396 };
397
398 static struct qcom_icc_node qnm_pcie = {
399 .name = "qnm_pcie",
400 .channels = 1,
401 .buswidth = 16,
402 .num_links = 2,
403 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
404 };
405
406 static struct qcom_icc_node qnm_snoc_gc = {
407 .name = "qnm_snoc_gc",
408 .channels = 1,
409 .buswidth = 8,
410 .num_links = 1,
411 .link_nodes = { &qns_llcc },
412 };
413
414 static struct qcom_icc_node qnm_snoc_sf = {
415 .name = "qnm_snoc_sf",
416 .channels = 1,
417 .buswidth = 16,
418 .num_links = 3,
419 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
420 &qns_pcie },
421 };
422
423 static struct qcom_icc_node qnm_lpiaon_noc = {
424 .name = "qnm_lpiaon_noc",
425 .channels = 1,
426 .buswidth = 16,
427 .num_links = 1,
428 .link_nodes = { &qns_lpass_ag_noc_gemnoc },
429 };
430
431 static struct qcom_icc_node qnm_lpass_lpinoc = {
432 .name = "qnm_lpass_lpinoc",
433 .channels = 1,
434 .buswidth = 16,
435 .num_links = 1,
436 .link_nodes = { &qns_lpass_aggnoc },
437 };
438
439 static struct qcom_icc_node qxm_lpinoc_dsp_axim = {
440 .name = "qxm_lpinoc_dsp_axim",
441 .channels = 1,
442 .buswidth = 16,
443 .num_links = 1,
444 .link_nodes = { &qns_lpi_aon_noc },
445 };
446
447 static struct qcom_icc_node llcc_mc = {
448 .name = "llcc_mc",
449 .channels = 4,
450 .buswidth = 4,
451 .num_links = 1,
452 .link_nodes = { &ebi },
453 };
454
455 static struct qcom_icc_node qnm_camnoc_hf = {
456 .name = "qnm_camnoc_hf",
457 .channels = 2,
458 .buswidth = 32,
459 .num_links = 1,
460 .link_nodes = { &qns_mem_noc_hf },
461 };
462
463 static struct qcom_icc_node qnm_camnoc_icp = {
464 .name = "qnm_camnoc_icp",
465 .channels = 1,
466 .buswidth = 8,
467 .num_links = 1,
468 .link_nodes = { &qns_mem_noc_sf },
469 };
470
471 static struct qcom_icc_node qnm_camnoc_sf = {
472 .name = "qnm_camnoc_sf",
473 .channels = 2,
474 .buswidth = 32,
475 .num_links = 1,
476 .link_nodes = { &qns_mem_noc_sf },
477 };
478
479 static struct qcom_icc_node qnm_mdp = {
480 .name = "qnm_mdp",
481 .channels = 2,
482 .buswidth = 32,
483 .num_links = 1,
484 .link_nodes = { &qns_mem_noc_hf },
485 };
486
487 static struct qcom_icc_node qnm_vapss_hcp = {
488 .name = "qnm_vapss_hcp",
489 .channels = 1,
490 .buswidth = 32,
491 .num_links = 1,
492 .link_nodes = { &qns_mem_noc_sf },
493 };
494
495 static struct qcom_icc_node qnm_video = {
496 .name = "qnm_video",
497 .channels = 2,
498 .buswidth = 32,
499 .num_links = 1,
500 .link_nodes = { &qns_mem_noc_sf },
501 };
502
503 static struct qcom_icc_node qnm_video_cv_cpu = {
504 .name = "qnm_video_cv_cpu",
505 .channels = 1,
506 .buswidth = 8,
507 .num_links = 1,
508 .link_nodes = { &qns_mem_noc_sf },
509 };
510
511 static struct qcom_icc_node qnm_video_cvp = {
512 .name = "qnm_video_cvp",
513 .channels = 1,
514 .buswidth = 32,
515 .num_links = 1,
516 .link_nodes = { &qns_mem_noc_sf },
517 };
518
519 static struct qcom_icc_node qnm_video_v_cpu = {
520 .name = "qnm_video_v_cpu",
521 .channels = 1,
522 .buswidth = 8,
523 .num_links = 1,
524 .link_nodes = { &qns_mem_noc_sf },
525 };
526
527 static struct qcom_icc_node qsm_mnoc_cfg = {
528 .name = "qsm_mnoc_cfg",
529 .channels = 1,
530 .buswidth = 4,
531 .num_links = 1,
532 .link_nodes = { &srvc_mnoc },
533 };
534
535 static struct qcom_icc_node qxm_nsp = {
536 .name = "qxm_nsp",
537 .channels = 2,
538 .buswidth = 32,
539 .num_links = 1,
540 .link_nodes = { &qns_nsp_gemnoc },
541 };
542
543 static struct qcom_icc_node qsm_pcie_anoc_cfg = {
544 .name = "qsm_pcie_anoc_cfg",
545 .channels = 1,
546 .buswidth = 4,
547 .num_links = 1,
548 .link_nodes = { &srvc_pcie_aggre_noc },
549 };
550
551 static struct qcom_icc_node xm_pcie3_0 = {
552 .name = "xm_pcie3_0",
553 .channels = 1,
554 .buswidth = 8,
555 .num_links = 1,
556 .link_nodes = { &qns_pcie_mem_noc },
557 };
558
559 static struct qcom_icc_node xm_pcie3_1 = {
560 .name = "xm_pcie3_1",
561 .channels = 1,
562 .buswidth = 16,
563 .num_links = 1,
564 .link_nodes = { &qns_pcie_mem_noc },
565 };
566
567 static struct qcom_icc_node qhm_gic = {
568 .name = "qhm_gic",
569 .channels = 1,
570 .buswidth = 4,
571 .num_links = 1,
572 .link_nodes = { &qns_gemnoc_sf },
573 };
574
575 static struct qcom_icc_node qnm_aggre1_noc = {
576 .name = "qnm_aggre1_noc",
577 .channels = 1,
578 .buswidth = 16,
579 .num_links = 1,
580 .link_nodes = { &qns_gemnoc_sf },
581 };
582
583 static struct qcom_icc_node qnm_aggre2_noc = {
584 .name = "qnm_aggre2_noc",
585 .channels = 1,
586 .buswidth = 16,
587 .num_links = 1,
588 .link_nodes = { &qns_gemnoc_sf },
589 };
590
591 static struct qcom_icc_node xm_gic = {
592 .name = "xm_gic",
593 .channels = 1,
594 .buswidth = 8,
595 .num_links = 1,
596 .link_nodes = { &qns_gemnoc_gc },
597 };
598
599 static struct qcom_icc_node qns_a1noc_snoc = {
600 .name = "qns_a1noc_snoc",
601 .channels = 1,
602 .buswidth = 16,
603 .num_links = 1,
604 .link_nodes = { &qnm_aggre1_noc },
605 };
606
607 static struct qcom_icc_node qns_a2noc_snoc = {
608 .name = "qns_a2noc_snoc",
609 .channels = 1,
610 .buswidth = 16,
611 .num_links = 1,
612 .link_nodes = { &qnm_aggre2_noc },
613 };
614
615 static struct qcom_icc_node qup0_core_slave = {
616 .name = "qup0_core_slave",
617 .channels = 1,
618 .buswidth = 4,
619 };
620
621 static struct qcom_icc_node qup1_core_slave = {
622 .name = "qup1_core_slave",
623 .channels = 1,
624 .buswidth = 4,
625 };
626
627 static struct qcom_icc_node qup2_core_slave = {
628 .name = "qup2_core_slave",
629 .channels = 1,
630 .buswidth = 4,
631 };
632
633 static struct qcom_icc_node qhs_ahb2phy0 = {
634 .name = "qhs_ahb2phy0",
635 .channels = 1,
636 .buswidth = 4,
637 };
638
639 static struct qcom_icc_node qhs_ahb2phy1 = {
640 .name = "qhs_ahb2phy1",
641 .channels = 1,
642 .buswidth = 4,
643 };
644
645 static struct qcom_icc_node qhs_apss = {
646 .name = "qhs_apss",
647 .channels = 1,
648 .buswidth = 8,
649 };
650
651 static struct qcom_icc_node qhs_camera_cfg = {
652 .name = "qhs_camera_cfg",
653 .channels = 1,
654 .buswidth = 4,
655 };
656
657 static struct qcom_icc_node qhs_clk_ctl = {
658 .name = "qhs_clk_ctl",
659 .channels = 1,
660 .buswidth = 4,
661 };
662
663 static struct qcom_icc_node qhs_cpr_cx = {
664 .name = "qhs_cpr_cx",
665 .channels = 1,
666 .buswidth = 4,
667 };
668
669 static struct qcom_icc_node qhs_cpr_mmcx = {
670 .name = "qhs_cpr_mmcx",
671 .channels = 1,
672 .buswidth = 4,
673 };
674
675 static struct qcom_icc_node qhs_cpr_mxa = {
676 .name = "qhs_cpr_mxa",
677 .channels = 1,
678 .buswidth = 4,
679 };
680
681 static struct qcom_icc_node qhs_cpr_mxc = {
682 .name = "qhs_cpr_mxc",
683 .channels = 1,
684 .buswidth = 4,
685 };
686
687 static struct qcom_icc_node qhs_cpr_nspcx = {
688 .name = "qhs_cpr_nspcx",
689 .channels = 1,
690 .buswidth = 4,
691 };
692
693 static struct qcom_icc_node qhs_crypto0_cfg = {
694 .name = "qhs_crypto0_cfg",
695 .channels = 1,
696 .buswidth = 4,
697 };
698
699 static struct qcom_icc_node qhs_cx_rdpm = {
700 .name = "qhs_cx_rdpm",
701 .channels = 1,
702 .buswidth = 4,
703 };
704
705 static struct qcom_icc_node qhs_display_cfg = {
706 .name = "qhs_display_cfg",
707 .channels = 1,
708 .buswidth = 4,
709 };
710
711 static struct qcom_icc_node qhs_gpuss_cfg = {
712 .name = "qhs_gpuss_cfg",
713 .channels = 1,
714 .buswidth = 8,
715 };
716
717 static struct qcom_icc_node qhs_i2c = {
718 .name = "qhs_i2c",
719 .channels = 1,
720 .buswidth = 4,
721 };
722
723 static struct qcom_icc_node qhs_imem_cfg = {
724 .name = "qhs_imem_cfg",
725 .channels = 1,
726 .buswidth = 4,
727 };
728
729 static struct qcom_icc_node qhs_ipa = {
730 .name = "qhs_ipa",
731 .channels = 1,
732 .buswidth = 4,
733 };
734
735 static struct qcom_icc_node qhs_ipc_router = {
736 .name = "qhs_ipc_router",
737 .channels = 1,
738 .buswidth = 4,
739 };
740
741 static struct qcom_icc_node qhs_mss_cfg = {
742 .name = "qhs_mss_cfg",
743 .channels = 1,
744 .buswidth = 4,
745 };
746
747 static struct qcom_icc_node qhs_mx_rdpm = {
748 .name = "qhs_mx_rdpm",
749 .channels = 1,
750 .buswidth = 4,
751 };
752
753 static struct qcom_icc_node qhs_pcie0_cfg = {
754 .name = "qhs_pcie0_cfg",
755 .channels = 1,
756 .buswidth = 4,
757 };
758
759 static struct qcom_icc_node qhs_pcie1_cfg = {
760 .name = "qhs_pcie1_cfg",
761 .channels = 1,
762 .buswidth = 4,
763 };
764
765 static struct qcom_icc_node qhs_pdm = {
766 .name = "qhs_pdm",
767 .channels = 1,
768 .buswidth = 4,
769 };
770
771 static struct qcom_icc_node qhs_pimem_cfg = {
772 .name = "qhs_pimem_cfg",
773 .channels = 1,
774 .buswidth = 4,
775 };
776
777 static struct qcom_icc_node qhs_prng = {
778 .name = "qhs_prng",
779 .channels = 1,
780 .buswidth = 4,
781 };
782
783 static struct qcom_icc_node qhs_qdss_cfg = {
784 .name = "qhs_qdss_cfg",
785 .channels = 1,
786 .buswidth = 4,
787 };
788
789 static struct qcom_icc_node qhs_qspi = {
790 .name = "qhs_qspi",
791 .channels = 1,
792 .buswidth = 4,
793 };
794
795 static struct qcom_icc_node qhs_qup1 = {
796 .name = "qhs_qup1",
797 .channels = 1,
798 .buswidth = 4,
799 };
800
801 static struct qcom_icc_node qhs_qup2 = {
802 .name = "qhs_qup2",
803 .channels = 1,
804 .buswidth = 4,
805 };
806
807 static struct qcom_icc_node qhs_sdc2 = {
808 .name = "qhs_sdc2",
809 .channels = 1,
810 .buswidth = 4,
811 };
812
813 static struct qcom_icc_node qhs_sdc4 = {
814 .name = "qhs_sdc4",
815 .channels = 1,
816 .buswidth = 4,
817 };
818
819 static struct qcom_icc_node qhs_spss_cfg = {
820 .name = "qhs_spss_cfg",
821 .channels = 1,
822 .buswidth = 4,
823 };
824
825 static struct qcom_icc_node qhs_tcsr = {
826 .name = "qhs_tcsr",
827 .channels = 1,
828 .buswidth = 4,
829 };
830
831 static struct qcom_icc_node qhs_tlmm = {
832 .name = "qhs_tlmm",
833 .channels = 1,
834 .buswidth = 4,
835 };
836
837 static struct qcom_icc_node qhs_ufs_mem_cfg = {
838 .name = "qhs_ufs_mem_cfg",
839 .channels = 1,
840 .buswidth = 4,
841 };
842
843 static struct qcom_icc_node qhs_usb3_0 = {
844 .name = "qhs_usb3_0",
845 .channels = 1,
846 .buswidth = 4,
847 };
848
849 static struct qcom_icc_node qhs_venus_cfg = {
850 .name = "qhs_venus_cfg",
851 .channels = 1,
852 .buswidth = 4,
853 };
854
855 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
856 .name = "qhs_vsense_ctrl_cfg",
857 .channels = 1,
858 .buswidth = 4,
859 };
860
861 static struct qcom_icc_node qss_lpass_qtb_cfg = {
862 .name = "qss_lpass_qtb_cfg",
863 .channels = 1,
864 .buswidth = 4,
865 };
866
867 static struct qcom_icc_node qss_mnoc_cfg = {
868 .name = "qss_mnoc_cfg",
869 .channels = 1,
870 .buswidth = 4,
871 .num_links = 1,
872 .link_nodes = { &qsm_mnoc_cfg },
873 };
874
875 static struct qcom_icc_node qss_nsp_qtb_cfg = {
876 .name = "qss_nsp_qtb_cfg",
877 .channels = 1,
878 .buswidth = 4,
879 };
880
881 static struct qcom_icc_node qss_pcie_anoc_cfg = {
882 .name = "qss_pcie_anoc_cfg",
883 .channels = 1,
884 .buswidth = 4,
885 .num_links = 1,
886 .link_nodes = { &qsm_pcie_anoc_cfg },
887 };
888
889 static struct qcom_icc_node xs_qdss_stm = {
890 .name = "xs_qdss_stm",
891 .channels = 1,
892 .buswidth = 4,
893 };
894
895 static struct qcom_icc_node xs_sys_tcu_cfg = {
896 .name = "xs_sys_tcu_cfg",
897 .channels = 1,
898 .buswidth = 8,
899 };
900
901 static struct qcom_icc_node qhs_aoss = {
902 .name = "qhs_aoss",
903 .channels = 1,
904 .buswidth = 4,
905 };
906
907 static struct qcom_icc_node qhs_tme_cfg = {
908 .name = "qhs_tme_cfg",
909 .channels = 1,
910 .buswidth = 4,
911 };
912
913 static struct qcom_icc_node qss_cfg = {
914 .name = "qss_cfg",
915 .channels = 1,
916 .buswidth = 4,
917 .num_links = 1,
918 .link_nodes = { &qsm_cfg },
919 };
920
921 static struct qcom_icc_node qss_ddrss_cfg = {
922 .name = "qss_ddrss_cfg",
923 .channels = 1,
924 .buswidth = 4,
925 };
926
927 static struct qcom_icc_node qxs_boot_imem = {
928 .name = "qxs_boot_imem",
929 .channels = 1,
930 .buswidth = 8,
931 };
932
933 static struct qcom_icc_node qxs_imem = {
934 .name = "qxs_imem",
935 .channels = 1,
936 .buswidth = 8,
937 };
938
939 static struct qcom_icc_node xs_pcie_0 = {
940 .name = "xs_pcie_0",
941 .channels = 1,
942 .buswidth = 8,
943 };
944
945 static struct qcom_icc_node xs_pcie_1 = {
946 .name = "xs_pcie_1",
947 .channels = 1,
948 .buswidth = 16,
949 };
950
951 static struct qcom_icc_node qns_gem_noc_cnoc = {
952 .name = "qns_gem_noc_cnoc",
953 .channels = 1,
954 .buswidth = 16,
955 .num_links = 1,
956 .link_nodes = { &qnm_gemnoc_cnoc },
957 };
958
959 static struct qcom_icc_node qns_llcc = {
960 .name = "qns_llcc",
961 .channels = 4,
962 .buswidth = 16,
963 .num_links = 1,
964 .link_nodes = { &llcc_mc },
965 };
966
967 static struct qcom_icc_node qns_pcie = {
968 .name = "qns_pcie",
969 .channels = 1,
970 .buswidth = 8,
971 .num_links = 1,
972 .link_nodes = { &qnm_gemnoc_pcie },
973 };
974
975 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = {
976 .name = "qns_lpass_ag_noc_gemnoc",
977 .channels = 1,
978 .buswidth = 16,
979 .num_links = 1,
980 .link_nodes = { &qnm_lpass_gemnoc },
981 };
982
983 static struct qcom_icc_node qns_lpass_aggnoc = {
984 .name = "qns_lpass_aggnoc",
985 .channels = 1,
986 .buswidth = 16,
987 .num_links = 1,
988 .link_nodes = { &qnm_lpiaon_noc },
989 };
990
991 static struct qcom_icc_node qns_lpi_aon_noc = {
992 .name = "qns_lpi_aon_noc",
993 .channels = 1,
994 .buswidth = 16,
995 .num_links = 1,
996 .link_nodes = { &qnm_lpass_lpinoc },
997 };
998
999 static struct qcom_icc_node ebi = {
1000 .name = "ebi",
1001 .channels = 4,
1002 .buswidth = 4,
1003 };
1004
1005 static struct qcom_icc_node qns_mem_noc_hf = {
1006 .name = "qns_mem_noc_hf",
1007 .channels = 2,
1008 .buswidth = 32,
1009 .num_links = 1,
1010 .link_nodes = { &qnm_mnoc_hf },
1011 };
1012
1013 static struct qcom_icc_node qns_mem_noc_sf = {
1014 .name = "qns_mem_noc_sf",
1015 .channels = 2,
1016 .buswidth = 32,
1017 .num_links = 1,
1018 .link_nodes = { &qnm_mnoc_sf },
1019 };
1020
1021 static struct qcom_icc_node srvc_mnoc = {
1022 .name = "srvc_mnoc",
1023 .channels = 1,
1024 .buswidth = 4,
1025 };
1026
1027 static struct qcom_icc_node qns_nsp_gemnoc = {
1028 .name = "qns_nsp_gemnoc",
1029 .channels = 2,
1030 .buswidth = 32,
1031 .num_links = 1,
1032 .link_nodes = { &qnm_nsp_gemnoc },
1033 };
1034
1035 static struct qcom_icc_node qns_pcie_mem_noc = {
1036 .name = "qns_pcie_mem_noc",
1037 .channels = 1,
1038 .buswidth = 16,
1039 .num_links = 1,
1040 .link_nodes = { &qnm_pcie },
1041 };
1042
1043 static struct qcom_icc_node srvc_pcie_aggre_noc = {
1044 .name = "srvc_pcie_aggre_noc",
1045 .channels = 1,
1046 .buswidth = 4,
1047 };
1048
1049 static struct qcom_icc_node qns_gemnoc_gc = {
1050 .name = "qns_gemnoc_gc",
1051 .channels = 1,
1052 .buswidth = 8,
1053 .num_links = 1,
1054 .link_nodes = { &qnm_snoc_gc },
1055 };
1056
1057 static struct qcom_icc_node qns_gemnoc_sf = {
1058 .name = "qns_gemnoc_sf",
1059 .channels = 1,
1060 .buswidth = 16,
1061 .num_links = 1,
1062 .link_nodes = { &qnm_snoc_sf },
1063 };
1064
1065 static struct qcom_icc_bcm bcm_acv = {
1066 .name = "ACV",
1067 .enable_mask = 0x8,
1068 .num_nodes = 1,
1069 .nodes = { &ebi },
1070 };
1071
1072 static struct qcom_icc_bcm bcm_ce0 = {
1073 .name = "CE0",
1074 .num_nodes = 1,
1075 .nodes = { &qxm_crypto },
1076 };
1077
1078 static struct qcom_icc_bcm bcm_cn0 = {
1079 .name = "CN0",
1080 .enable_mask = 0x1,
1081 .keepalive = true,
1082 .num_nodes = 54,
1083 .nodes = { &qsm_cfg, &qhs_ahb2phy0,
1084 &qhs_ahb2phy1, &qhs_apss,
1085 &qhs_camera_cfg, &qhs_clk_ctl,
1086 &qhs_cpr_cx, &qhs_cpr_mmcx,
1087 &qhs_cpr_mxa, &qhs_cpr_mxc,
1088 &qhs_cpr_nspcx, &qhs_crypto0_cfg,
1089 &qhs_cx_rdpm, &qhs_gpuss_cfg,
1090 &qhs_i2c, &qhs_imem_cfg,
1091 &qhs_ipa, &qhs_ipc_router,
1092 &qhs_mss_cfg, &qhs_mx_rdpm,
1093 &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1094 &qhs_pdm, &qhs_pimem_cfg,
1095 &qhs_prng, &qhs_qdss_cfg,
1096 &qhs_qspi, &qhs_qup1,
1097 &qhs_qup2, &qhs_sdc2,
1098 &qhs_sdc4, &qhs_spss_cfg,
1099 &qhs_tcsr, &qhs_tlmm,
1100 &qhs_ufs_mem_cfg, &qhs_usb3_0,
1101 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg,
1102 &qss_lpass_qtb_cfg, &qss_mnoc_cfg,
1103 &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg,
1104 &xs_qdss_stm, &xs_sys_tcu_cfg,
1105 &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1106 &qhs_aoss, &qhs_tme_cfg,
1107 &qss_cfg, &qss_ddrss_cfg,
1108 &qxs_boot_imem, &qxs_imem,
1109 &xs_pcie_0, &xs_pcie_1 },
1110 };
1111
1112 static struct qcom_icc_bcm bcm_cn1 = {
1113 .name = "CN1",
1114 .num_nodes = 1,
1115 .nodes = { &qhs_display_cfg },
1116 };
1117
1118 static struct qcom_icc_bcm bcm_co0 = {
1119 .name = "CO0",
1120 .enable_mask = 0x1,
1121 .num_nodes = 2,
1122 .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1123 };
1124
1125 static struct qcom_icc_bcm bcm_lp0 = {
1126 .name = "LP0",
1127 .num_nodes = 2,
1128 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc },
1129 };
1130
1131 static struct qcom_icc_bcm bcm_mc0 = {
1132 .name = "MC0",
1133 .keepalive = true,
1134 .num_nodes = 1,
1135 .nodes = { &ebi },
1136 };
1137
1138 static struct qcom_icc_bcm bcm_mm0 = {
1139 .name = "MM0",
1140 .num_nodes = 1,
1141 .nodes = { &qns_mem_noc_hf },
1142 };
1143
1144 static struct qcom_icc_bcm bcm_mm1 = {
1145 .name = "MM1",
1146 .enable_mask = 0x1,
1147 .num_nodes = 8,
1148 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
1149 &qnm_camnoc_sf, &qnm_vapss_hcp,
1150 &qnm_video_cv_cpu, &qnm_video_cvp,
1151 &qnm_video_v_cpu, &qns_mem_noc_sf },
1152 };
1153
1154 static struct qcom_icc_bcm bcm_qup0 = {
1155 .name = "QUP0",
1156 .keepalive = true,
1157 .vote_scale = 1,
1158 .num_nodes = 1,
1159 .nodes = { &qup0_core_slave },
1160 };
1161
1162 static struct qcom_icc_bcm bcm_qup1 = {
1163 .name = "QUP1",
1164 .keepalive = true,
1165 .vote_scale = 1,
1166 .num_nodes = 1,
1167 .nodes = { &qup1_core_slave },
1168 };
1169
1170 static struct qcom_icc_bcm bcm_qup2 = {
1171 .name = "QUP2",
1172 .keepalive = true,
1173 .vote_scale = 1,
1174 .num_nodes = 1,
1175 .nodes = { &qup2_core_slave },
1176 };
1177
1178 static struct qcom_icc_bcm bcm_sh0 = {
1179 .name = "SH0",
1180 .keepalive = true,
1181 .num_nodes = 1,
1182 .nodes = { &qns_llcc },
1183 };
1184
1185 static struct qcom_icc_bcm bcm_sh1 = {
1186 .name = "SH1",
1187 .enable_mask = 0x1,
1188 .num_nodes = 13,
1189 .nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1190 &chm_apps, &qnm_gpu,
1191 &qnm_mdsp, &qnm_mnoc_hf,
1192 &qnm_mnoc_sf, &qnm_nsp_gemnoc,
1193 &qnm_pcie, &qnm_snoc_gc,
1194 &qnm_snoc_sf, &qns_gem_noc_cnoc,
1195 &qns_pcie },
1196 };
1197
1198 static struct qcom_icc_bcm bcm_sn0 = {
1199 .name = "SN0",
1200 .keepalive = true,
1201 .num_nodes = 1,
1202 .nodes = { &qns_gemnoc_sf },
1203 };
1204
1205 static struct qcom_icc_bcm bcm_sn1 = {
1206 .name = "SN1",
1207 .enable_mask = 0x1,
1208 .num_nodes = 3,
1209 .nodes = { &qhm_gic, &xm_gic,
1210 &qns_gemnoc_gc },
1211 };
1212
1213 static struct qcom_icc_bcm bcm_sn2 = {
1214 .name = "SN2",
1215 .num_nodes = 1,
1216 .nodes = { &qnm_aggre1_noc },
1217 };
1218
1219 static struct qcom_icc_bcm bcm_sn3 = {
1220 .name = "SN3",
1221 .num_nodes = 1,
1222 .nodes = { &qnm_aggre2_noc },
1223 };
1224
1225 static struct qcom_icc_bcm bcm_sn7 = {
1226 .name = "SN7",
1227 .num_nodes = 1,
1228 .nodes = { &qns_pcie_mem_noc },
1229 };
1230
1231 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1232 };
1233
1234 static struct qcom_icc_node * const aggre1_noc_nodes[] = {
1235 [MASTER_QSPI_0] = &qhm_qspi,
1236 [MASTER_QUP_1] = &qhm_qup1,
1237 [MASTER_SDCC_4] = &xm_sdc4,
1238 [MASTER_UFS_MEM] = &xm_ufs_mem,
1239 [MASTER_USB3_0] = &xm_usb3_0,
1240 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
1241 };
1242
1243 static const struct qcom_icc_desc sm8550_aggre1_noc = {
1244 .nodes = aggre1_noc_nodes,
1245 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
1246 .bcms = aggre1_noc_bcms,
1247 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
1248 };
1249
1250 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
1251 &bcm_ce0,
1252 };
1253
1254 static struct qcom_icc_node * const aggre2_noc_nodes[] = {
1255 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
1256 [MASTER_QUP_2] = &qhm_qup2,
1257 [MASTER_CRYPTO] = &qxm_crypto,
1258 [MASTER_IPA] = &qxm_ipa,
1259 [MASTER_SP] = &qxm_sp,
1260 [MASTER_QDSS_ETR] = &xm_qdss_etr_0,
1261 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
1262 [MASTER_SDCC_2] = &xm_sdc2,
1263 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
1264 };
1265
1266 static const struct qcom_icc_desc sm8550_aggre2_noc = {
1267 .nodes = aggre2_noc_nodes,
1268 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
1269 .bcms = aggre2_noc_bcms,
1270 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
1271 };
1272
1273 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
1274 &bcm_qup0,
1275 &bcm_qup1,
1276 &bcm_qup2,
1277 };
1278
1279 static struct qcom_icc_node * const clk_virt_nodes[] = {
1280 [MASTER_QUP_CORE_0] = &qup0_core_master,
1281 [MASTER_QUP_CORE_1] = &qup1_core_master,
1282 [MASTER_QUP_CORE_2] = &qup2_core_master,
1283 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
1284 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
1285 [SLAVE_QUP_CORE_2] = &qup2_core_slave,
1286 };
1287
1288 static const struct qcom_icc_desc sm8550_clk_virt = {
1289 .nodes = clk_virt_nodes,
1290 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
1291 .bcms = clk_virt_bcms,
1292 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
1293 };
1294
1295 static struct qcom_icc_bcm * const config_noc_bcms[] = {
1296 &bcm_cn0,
1297 &bcm_cn1,
1298 };
1299
1300 static struct qcom_icc_node * const config_noc_nodes[] = {
1301 [MASTER_CNOC_CFG] = &qsm_cfg,
1302 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
1303 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
1304 [SLAVE_APPSS] = &qhs_apss,
1305 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
1306 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
1307 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
1308 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
1309 [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa,
1310 [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc,
1311 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
1312 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
1313 [SLAVE_CX_RDPM] = &qhs_cx_rdpm,
1314 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
1315 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
1316 [SLAVE_I2C] = &qhs_i2c,
1317 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
1318 [SLAVE_IPA_CFG] = &qhs_ipa,
1319 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
1320 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
1321 [SLAVE_MX_RDPM] = &qhs_mx_rdpm,
1322 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
1323 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
1324 [SLAVE_PDM] = &qhs_pdm,
1325 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
1326 [SLAVE_PRNG] = &qhs_prng,
1327 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
1328 [SLAVE_QSPI_0] = &qhs_qspi,
1329 [SLAVE_QUP_1] = &qhs_qup1,
1330 [SLAVE_QUP_2] = &qhs_qup2,
1331 [SLAVE_SDCC_2] = &qhs_sdc2,
1332 [SLAVE_SDCC_4] = &qhs_sdc4,
1333 [SLAVE_SPSS_CFG] = &qhs_spss_cfg,
1334 [SLAVE_TCSR] = &qhs_tcsr,
1335 [SLAVE_TLMM] = &qhs_tlmm,
1336 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
1337 [SLAVE_USB3_0] = &qhs_usb3_0,
1338 [SLAVE_VENUS_CFG] = &qhs_venus_cfg,
1339 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
1340 [SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg,
1341 [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg,
1342 [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg,
1343 [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg,
1344 [SLAVE_QDSS_STM] = &xs_qdss_stm,
1345 [SLAVE_TCU] = &xs_sys_tcu_cfg,
1346 };
1347
1348 static const struct qcom_icc_desc sm8550_config_noc = {
1349 .nodes = config_noc_nodes,
1350 .num_nodes = ARRAY_SIZE(config_noc_nodes),
1351 .bcms = config_noc_bcms,
1352 .num_bcms = ARRAY_SIZE(config_noc_bcms),
1353 };
1354
1355 static struct qcom_icc_bcm * const cnoc_main_bcms[] = {
1356 &bcm_cn0,
1357 };
1358
1359 static struct qcom_icc_node * const cnoc_main_nodes[] = {
1360 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
1361 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
1362 [SLAVE_AOSS] = &qhs_aoss,
1363 [SLAVE_TME_CFG] = &qhs_tme_cfg,
1364 [SLAVE_CNOC_CFG] = &qss_cfg,
1365 [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg,
1366 [SLAVE_BOOT_IMEM] = &qxs_boot_imem,
1367 [SLAVE_IMEM] = &qxs_imem,
1368 [SLAVE_PCIE_0] = &xs_pcie_0,
1369 [SLAVE_PCIE_1] = &xs_pcie_1,
1370 };
1371
1372 static const struct qcom_icc_desc sm8550_cnoc_main = {
1373 .nodes = cnoc_main_nodes,
1374 .num_nodes = ARRAY_SIZE(cnoc_main_nodes),
1375 .bcms = cnoc_main_bcms,
1376 .num_bcms = ARRAY_SIZE(cnoc_main_bcms),
1377 };
1378
1379 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
1380 &bcm_sh0,
1381 &bcm_sh1,
1382 };
1383
1384 static struct qcom_icc_node * const gem_noc_nodes[] = {
1385 [MASTER_GPU_TCU] = &alm_gpu_tcu,
1386 [MASTER_SYS_TCU] = &alm_sys_tcu,
1387 [MASTER_APPSS_PROC] = &chm_apps,
1388 [MASTER_GFX3D] = &qnm_gpu,
1389 [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc,
1390 [MASTER_MSS_PROC] = &qnm_mdsp,
1391 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
1392 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
1393 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc,
1394 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
1395 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
1396 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
1397 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
1398 [SLAVE_LLCC] = &qns_llcc,
1399 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
1400 };
1401
1402 static const struct qcom_icc_desc sm8550_gem_noc = {
1403 .nodes = gem_noc_nodes,
1404 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
1405 .bcms = gem_noc_bcms,
1406 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
1407 };
1408
1409 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = {
1410 };
1411
1412 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = {
1413 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc,
1414 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,
1415 };
1416
1417 static const struct qcom_icc_desc sm8550_lpass_ag_noc = {
1418 .nodes = lpass_ag_noc_nodes,
1419 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
1420 .bcms = lpass_ag_noc_bcms,
1421 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
1422 };
1423
1424 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = {
1425 &bcm_lp0,
1426 };
1427
1428 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = {
1429 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc,
1430 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,
1431 };
1432
1433 static const struct qcom_icc_desc sm8550_lpass_lpiaon_noc = {
1434 .nodes = lpass_lpiaon_noc_nodes,
1435 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes),
1436 .bcms = lpass_lpiaon_noc_bcms,
1437 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),
1438 };
1439
1440 static struct qcom_icc_bcm * const lpass_lpicx_noc_bcms[] = {
1441 };
1442
1443 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = {
1444 [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim,
1445 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,
1446 };
1447
1448 static const struct qcom_icc_desc sm8550_lpass_lpicx_noc = {
1449 .nodes = lpass_lpicx_noc_nodes,
1450 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),
1451 .bcms = lpass_lpicx_noc_bcms,
1452 .num_bcms = ARRAY_SIZE(lpass_lpicx_noc_bcms),
1453 };
1454
1455 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
1456 &bcm_acv,
1457 &bcm_mc0,
1458 };
1459
1460 static struct qcom_icc_node * const mc_virt_nodes[] = {
1461 [MASTER_LLCC] = &llcc_mc,
1462 [SLAVE_EBI1] = &ebi,
1463 };
1464
1465 static const struct qcom_icc_desc sm8550_mc_virt = {
1466 .nodes = mc_virt_nodes,
1467 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
1468 .bcms = mc_virt_bcms,
1469 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
1470 };
1471
1472 static struct qcom_icc_bcm * const mmss_noc_bcms[] = {
1473 &bcm_mm0,
1474 &bcm_mm1,
1475 };
1476
1477 static struct qcom_icc_node * const mmss_noc_nodes[] = {
1478 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
1479 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
1480 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
1481 [MASTER_MDP] = &qnm_mdp,
1482 [MASTER_CDSP_HCP] = &qnm_vapss_hcp,
1483 [MASTER_VIDEO] = &qnm_video,
1484 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu,
1485 [MASTER_VIDEO_PROC] = &qnm_video_cvp,
1486 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
1487 [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg,
1488 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
1489 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
1490 [SLAVE_SERVICE_MNOC] = &srvc_mnoc,
1491 };
1492
1493 static const struct qcom_icc_desc sm8550_mmss_noc = {
1494 .nodes = mmss_noc_nodes,
1495 .num_nodes = ARRAY_SIZE(mmss_noc_nodes),
1496 .bcms = mmss_noc_bcms,
1497 .num_bcms = ARRAY_SIZE(mmss_noc_bcms),
1498 };
1499
1500 static struct qcom_icc_bcm * const nsp_noc_bcms[] = {
1501 &bcm_co0,
1502 };
1503
1504 static struct qcom_icc_node * const nsp_noc_nodes[] = {
1505 [MASTER_CDSP_PROC] = &qxm_nsp,
1506 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
1507 };
1508
1509 static const struct qcom_icc_desc sm8550_nsp_noc = {
1510 .nodes = nsp_noc_nodes,
1511 .num_nodes = ARRAY_SIZE(nsp_noc_nodes),
1512 .bcms = nsp_noc_bcms,
1513 .num_bcms = ARRAY_SIZE(nsp_noc_bcms),
1514 };
1515
1516 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = {
1517 &bcm_sn7,
1518 };
1519
1520 static struct qcom_icc_node * const pcie_anoc_nodes[] = {
1521 [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg,
1522 [MASTER_PCIE_0] = &xm_pcie3_0,
1523 [MASTER_PCIE_1] = &xm_pcie3_1,
1524 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
1525 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,
1526 };
1527
1528 static const struct qcom_icc_desc sm8550_pcie_anoc = {
1529 .nodes = pcie_anoc_nodes,
1530 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
1531 .bcms = pcie_anoc_bcms,
1532 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
1533 };
1534
1535 static struct qcom_icc_bcm * const system_noc_bcms[] = {
1536 &bcm_sn0,
1537 &bcm_sn1,
1538 &bcm_sn2,
1539 &bcm_sn3,
1540 };
1541
1542 static struct qcom_icc_node * const system_noc_nodes[] = {
1543 [MASTER_GIC_AHB] = &qhm_gic,
1544 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
1545 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
1546 [MASTER_GIC] = &xm_gic,
1547 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
1548 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
1549 };
1550
1551 static const struct qcom_icc_desc sm8550_system_noc = {
1552 .nodes = system_noc_nodes,
1553 .num_nodes = ARRAY_SIZE(system_noc_nodes),
1554 .bcms = system_noc_bcms,
1555 .num_bcms = ARRAY_SIZE(system_noc_bcms),
1556 };
1557
1558 static const struct of_device_id qnoc_of_match[] = {
1559 { .compatible = "qcom,sm8550-aggre1-noc",
1560 .data = &sm8550_aggre1_noc},
1561 { .compatible = "qcom,sm8550-aggre2-noc",
1562 .data = &sm8550_aggre2_noc},
1563 { .compatible = "qcom,sm8550-clk-virt",
1564 .data = &sm8550_clk_virt},
1565 { .compatible = "qcom,sm8550-config-noc",
1566 .data = &sm8550_config_noc},
1567 { .compatible = "qcom,sm8550-cnoc-main",
1568 .data = &sm8550_cnoc_main},
1569 { .compatible = "qcom,sm8550-gem-noc",
1570 .data = &sm8550_gem_noc},
1571 { .compatible = "qcom,sm8550-lpass-ag-noc",
1572 .data = &sm8550_lpass_ag_noc},
1573 { .compatible = "qcom,sm8550-lpass-lpiaon-noc",
1574 .data = &sm8550_lpass_lpiaon_noc},
1575 { .compatible = "qcom,sm8550-lpass-lpicx-noc",
1576 .data = &sm8550_lpass_lpicx_noc},
1577 { .compatible = "qcom,sm8550-mc-virt",
1578 .data = &sm8550_mc_virt},
1579 { .compatible = "qcom,sm8550-mmss-noc",
1580 .data = &sm8550_mmss_noc},
1581 { .compatible = "qcom,sm8550-nsp-noc",
1582 .data = &sm8550_nsp_noc},
1583 { .compatible = "qcom,sm8550-pcie-anoc",
1584 .data = &sm8550_pcie_anoc},
1585 { .compatible = "qcom,sm8550-system-noc",
1586 .data = &sm8550_system_noc},
1587 { }
1588 };
1589 MODULE_DEVICE_TABLE(of, qnoc_of_match);
1590
1591 static struct platform_driver qnoc_driver = {
1592 .probe = qcom_icc_rpmh_probe,
1593 .remove = qcom_icc_rpmh_remove,
1594 .driver = {
1595 .name = "qnoc-sm8550",
1596 .of_match_table = qnoc_of_match,
1597 .sync_state = icc_sync_state,
1598 },
1599 };
1600
qnoc_driver_init(void)1601 static int __init qnoc_driver_init(void)
1602 {
1603 return platform_driver_register(&qnoc_driver);
1604 }
1605 core_initcall(qnoc_driver_init);
1606
qnoc_driver_exit(void)1607 static void __exit qnoc_driver_exit(void)
1608 {
1609 platform_driver_unregister(&qnoc_driver);
1610 }
1611 module_exit(qnoc_driver_exit);
1612
1613 MODULE_DESCRIPTION("sm8550 NoC driver");
1614 MODULE_LICENSE("GPL");
1615